Add support for SPARC64 V (and where it already makes sense for other

HAL/Fujitsu) CPUs. For the most part this consists of fleshing out the
MMU and cache handling, it doesn't add pmap optimizations possible with
these CPU, yet, though.
With these changes FreeBSD runs stable on Fujitsu Siemens PRIMEPOWER 250
and likely also other models based on SPARC64 V like 450, 650 and 850.
Thanks go to Michael Moll for providing access to a PRIMEPOWER 250.

14 files changed, 232 insertions, 29 deletions

diff --git a/sys/boot/sparc64/loader/main.c b/sys/boot/sparc64/loader/main.c
index 2afbfee..b3e7908 100644
--- a/sys/boot/sparc64/loader/main.c
+++ b/sys/boot/sparc64/loader/main.c
@@ -451,7 +451,8 @@ dtlb_va_to_pa_sun4u(vm_offset_t va)
 		reg = dtlb_get_data_sun4u(i);
 		wrpr(pstate, pstate, 0);
 		reg >>= TD_PA_SHIFT;
-		if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
+		if (cpu_impl == CPU_IMPL_SPARC64V ||
+		    cpu_impl >= CPU_IMPL_ULTRASPARCIII)
 			return (reg & TD_PA_CH_MASK);
 		return (reg & TD_PA_SF_MASK);
 	}
@@ -474,7 +475,8 @@ itlb_va_to_pa_sun4u(vm_offset_t va)
 		reg = itlb_get_data_sun4u(i);
 		wrpr(pstate, pstate, 0);
 		reg >>= TD_PA_SHIFT;
-		if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
+		if (cpu_impl == CPU_IMPL_SPARC64V ||
+		    cpu_impl >= CPU_IMPL_ULTRASPARCIII)
 			return (reg & TD_PA_CH_MASK);
 		return (reg & TD_PA_SF_MASK);
 	}
@@ -696,6 +698,7 @@ cpu_cpuid_prop_sun4u(void)
 
 	switch (cpu_impl) {
 	case CPU_IMPL_SPARC64:
+	case CPU_IMPL_SPARC64V:
 	case CPU_IMPL_ULTRASPARCI:
 	case CPU_IMPL_ULTRASPARCII:
 	case CPU_IMPL_ULTRASPARCIIi:
@@ -720,6 +723,7 @@ cpu_get_mid_sun4u(void)
 
 	switch (cpu_impl) {
 	case CPU_IMPL_SPARC64:
+	case CPU_IMPL_SPARC64V:
 	case CPU_IMPL_ULTRASPARCI:
 	case CPU_IMPL_ULTRASPARCII:
 	case CPU_IMPL_ULTRASPARCIIi:
diff --git a/sys/conf/files.sparc64 b/sys/conf/files.sparc64
index 63ee2c5..3a0620a 100644
--- a/sys/conf/files.sparc64
+++ b/sys/conf/files.sparc64
@@ -138,3 +138,4 @@ sparc64/sparc64/tsb.c		standard
 sparc64/sparc64/uio_machdep.c	standard
 sparc64/sparc64/upa.c		optional	creator
 sparc64/sparc64/vm_machdep.c	standard
+sparc64/sparc64/zeus.c		standard
diff --git a/sys/sparc64/include/asi.h b/sys/sparc64/include/asi.h
index 90dc3f3..e5769c1 100644
--- a/sys/sparc64/include/asi.h
+++ b/sys/sparc64/include/asi.h
@@ -82,7 +82,10 @@
 #define	ASI_DCACHE_SNOOP_TAG			0x44	/* US-III Cu */
 
 /* Named ASI_DCUCR on US-III, but is mostly identical except for added bits. */
-#define	ASI_LSU_CTL_REG				0x45
+#define	ASI_LSU_CTL_REG				0x45	/* US only */
+
+#define	ASI_MCNTL				0x45	/* SPARC64 only */
+#define		AA_MCNTL			0x08
 
 #define	ASI_DCACHE_DATA				0x46
 #define	ASI_DCACHE_TAG				0x47
@@ -167,6 +170,8 @@
 #define	ASI_ICACHE_PRE_DECODE			0x6e	/* US-I, II */
 #define	ASI_ICACHE_PRE_NEXT_FIELD		0x6f	/* US-I, II */
 
+#define	ASI_FLUSH_L1I				0x67	/* SPARC64 only */
+
 #define	ASI_BLK_AUIP				0x70
 #define	ASI_BLK_AIUS				0x71
 
diff --git a/sys/sparc64/include/cache.h b/sys/sparc64/include/cache.h
index 9c4804b..29bff69 100644
--- a/sys/sparc64/include/cache.h
+++ b/sys/sparc64/include/cache.h
@@ -113,6 +113,10 @@ extern cache_flush_t *cache_flush;
 extern dcache_page_inval_t *dcache_page_inval;
 extern icache_page_inval_t *icache_page_inval;
 
+cache_flush_t zeus_cache_flush;
+dcache_page_inval_t zeus_dcache_page_inval;
+icache_page_inval_t zeus_icache_page_inval;
+
 #endif /* KERNEL */
 
 #endif /* !LOCORE */
diff --git a/sys/sparc64/include/mcntl.h b/sys/sparc64/include/mcntl.h
new file mode 100644
index 0000000..e9483c0
--- /dev/null
+++ b/sys/sparc64/include/mcntl.h
@@ -0,0 +1,62 @@
+/*-
+ * Copyright (c) 2010 Marius Strobl <marius@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_MACHINE_MCNTL_H
+#define	_MACHINE_MCNTL_H
+
+/*
+ * Definitions for the SPARC64 V, VI, VII and VIIIfx Memory Control Register
+ */
+#define	MCNTL_JPS1_TSBP		(1UL << 8)
+
+#define	MCNTL_RMD_SHIFT		12
+#define	MCNTL_RMD_BITS		2
+#define	MCNTL_RMD_MASK							\
+	(((1UL << MCNTL_RMD_BITS) - 1) << MCNTL_RMD_SHIFT)
+#define	MCNTL_RMD_FULL		(0UL << MCNTL_RMD_SHIFT)
+#define	MCNTL_RMD_1024		(2UL << MCNTL_RMD_SHIFT)
+#define	MCNTL_RMD_512		(3UL << MCNTL_RMD_SHIFT)
+
+#define	MCNTL_FW_FDTLB		(1UL << 14)
+#define	MCNTL_FW_FITLB		(1UL << 15)
+#define	MCNTL_NC_CACHE		(1UL << 16)
+
+/* The following bits are valid for the SPARC64 VI, VII and VIIIfx only. */
+#define	MCNTL_MPG_SDTLB		(1UL << 6)
+#define	MCNTL_MPG_SITLB		(1UL << 7)
+
+/* The following bits are valid for the SPARC64 VIIIfx only. */
+#define	MCNTL_HPF_SHIFT		18
+#define	MCNTL_HPF_BITS		2
+#define	MCNTL_HPF_MASK							\
+	(((1UL << MCNTL_HPF_BITS) - 1) << MCNTL_HPF_SHIFT)
+#define	MCNTL_HPF_STRONG	(0UL << MCNTL_HPF_SHIFT)
+#define	MCNTL_HPF_NOT		(1UL << MCNTL_HPF_SHIFT)
+#define	MCNTL_HPF_WEAK		(2UL << MCNTL_HPF_SHIFT)
+
+#endif	/* _MACHINE_MCNTL_H */
diff --git a/sys/sparc64/sparc64/cache.c b/sys/sparc64/sparc64/cache.c
index 8cb8dee..a3c6119 100644
--- a/sys/sparc64/sparc64/cache.c
+++ b/sys/sparc64/sparc64/cache.c
@@ -141,7 +141,12 @@ cache_init(struct pcpu *pcpu)
 	if ((pcpu->pc_cache.dc_size &
 	    ~(1UL << (ffs(pcpu->pc_cache.dc_size) - 1))) != 0)
 		panic("cache_init: D$ size not a power of 2");
-	if (((pcpu->pc_cache.dc_size / pcpu->pc_cache.dc_assoc) /
+	/*
+	 * For CPUs which don't support unaliasing in hardware ensure that
+	 * the data cache doesn't have too many virtual colors.
+	 */
+	if (pcpu->pc_impl != CPU_IMPL_SPARC64V &&
+	    ((pcpu->pc_cache.dc_size / pcpu->pc_cache.dc_assoc) /
 	    PAGE_SIZE) != DCACHE_COLORS)
 		panic("cache_init: too many D$ colors");
 	set = pcpu->pc_cache.ec_size / pcpu->pc_cache.ec_assoc;
@@ -155,12 +160,21 @@ cache_init(struct pcpu *pcpu)
 		icache_page_inval = cheetah_icache_page_inval;
 		tlb_flush_nonlocked = cheetah_tlb_flush_nonlocked;
 		tlb_flush_user = cheetah_tlb_flush_user;
-	} else {
+	} else if (pcpu->pc_impl == CPU_IMPL_SPARC64V) {
+		cache_enable = cheetah_cache_enable;
+		cache_flush = zeus_cache_flush;
+		dcache_page_inval = zeus_dcache_page_inval;
+		icache_page_inval = zeus_icache_page_inval;
+		tlb_flush_nonlocked = cheetah_tlb_flush_nonlocked;
+		tlb_flush_user = cheetah_tlb_flush_user;
+	} else if (pcpu->pc_impl >= CPU_IMPL_ULTRASPARCI &&
+	    pcpu->pc_impl < CPU_IMPL_ULTRASPARCIII) {
 		cache_enable = spitfire_cache_enable;
 		cache_flush = spitfire_cache_flush;
 		dcache_page_inval = spitfire_dcache_page_inval;
 		icache_page_inval = spitfire_icache_page_inval;
 		tlb_flush_nonlocked = spitfire_tlb_flush_nonlocked;
 		tlb_flush_user = spitfire_tlb_flush_user;
-	}
+	} else
+		panic("cache_init: unknown CPU");
 }
diff --git a/sys/sparc64/sparc64/cheetah.c b/sys/sparc64/sparc64/cheetah.c
index 8366187..99d38c9 100644
--- a/sys/sparc64/sparc64/cheetah.c
+++ b/sys/sparc64/sparc64/cheetah.c
@@ -39,11 +39,13 @@ __FBSDID("$FreeBSD$");
 #include <vm/vm.h>
 #include <vm/pmap.h>
 
+#include <machine/asi.h>
 #include <machine/cache.h>
 #include <machine/cpu.h>
 #include <machine/cpufunc.h>
 #include <machine/dcr.h>
 #include <machine/lsu.h>
+#include <machine/mcntl.h>
 #include <machine/smp.h>
 #include <machine/tlb.h>
 #include <machine/ver.h>
@@ -52,7 +54,8 @@ __FBSDID("$FreeBSD$");
 #define	CHEETAH_ICACHE_TAG_LOWER	0x30
 
 /*
- * CPU-specific initialization
+ * CPU-specific initialization - this is used for both the Sun Cheetah and
+ * later as well as the Fujitsu Zeus and later CPUs.
  */
 void
 cheetah_init(u_int cpu_impl)
@@ -75,6 +78,14 @@ cheetah_init(u_int cpu_impl)
 	stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0);
 	membar(Sync);
 
+	if (cpu_impl == CPU_IMPL_SPARC64V) {
+		/* Ensure MCNTL_JPS1_TSBP is 0. */
+		val = ldxa(AA_MCNTL, ASI_MCNTL);
+		val &= ~MCNTL_JPS1_TSBP;
+		stxa(AA_MCNTL, ASI_MCNTL, val);
+		return;
+	}
+
 	/*
 	 * Configure the first large dTLB to hold 4MB pages (e.g. for direct
 	 * mappings) for all three contexts and ensure the second one is set
@@ -207,7 +218,7 @@ cheetah_dcache_page_inval(vm_paddr_t spa)
  * consistency is maintained by hardware.
  */
 void
-cheetah_icache_page_inval(vm_paddr_t pa)
+cheetah_icache_page_inval(vm_paddr_t pa __unused)
 {
 
 }
diff --git a/sys/sparc64/sparc64/identcpu.c b/sys/sparc64/sparc64/identcpu.c
index 0b73151..455aa67 100644
--- a/sys/sparc64/sparc64/identcpu.c
+++ b/sys/sparc64/sparc64/identcpu.c
@@ -41,7 +41,7 @@ cpu_identify(u_long vers, u_int freq, u_int id)
 
 	switch (VER_MANUF(vers)) {
 	case 0x04:
-		manus = "HAL";
+		manus = "HAL/Fujitsu";
 		break;
 	case 0x13:
 	case 0x17:
@@ -57,6 +57,27 @@ cpu_identify(u_long vers, u_int freq, u_int id)
 	case CPU_IMPL_SPARC64:
 		impls = "SPARC64";
 		break;
+	case CPU_IMPL_SPARC64II:
+		impls = "SPARC64-II";
+		break;
+	case CPU_IMPL_SPARC64III:
+		impls = "SPARC64-III";
+		break;
+	case CPU_IMPL_SPARC64IV:
+		impls = "SPARC64-IV";
+		break;
+	case CPU_IMPL_SPARC64V:
+		impls = "SPARC64-V";
+		break;
+	case CPU_IMPL_SPARC64VI:
+		impls = "SPARC64-VI";
+		break;
+	case CPU_IMPL_SPARC64VII:
+		impls = "SPARC64-VII";
+		break;
+	case CPU_IMPL_SPARC64VIIIfx:
+		impls = "SPARC64-VIIIfx";
+		break;
 	case CPU_IMPL_ULTRASPARCI:
 		impls = "UltraSparc-I";
 		break;
@@ -67,7 +88,6 @@ cpu_identify(u_long vers, u_int freq, u_int id)
 		impls = "UltraSparc-IIi";
 		break;
 	case CPU_IMPL_ULTRASPARCIIe:
-		/* V9 Manual says `UltraSparc-e'.  I assume this is wrong. */
 		impls = "UltraSparc-IIe";
 		break;
 	case CPU_IMPL_ULTRASPARCIII:
diff --git a/sys/sparc64/sparc64/machdep.c b/sys/sparc64/sparc64/machdep.c
index c904060..eda2e01 100644
--- a/sys/sparc64/sparc64/machdep.c
+++ b/sys/sparc64/sparc64/machdep.c
@@ -276,6 +276,7 @@ cpu_cpuid_prop(u_int cpu_impl)
 
 	switch (cpu_impl) {
 	case CPU_IMPL_SPARC64:
+	case CPU_IMPL_SPARC64V:
 	case CPU_IMPL_ULTRASPARCI:
 	case CPU_IMPL_ULTRASPARCII:
 	case CPU_IMPL_ULTRASPARCIIi:
@@ -300,6 +301,7 @@ cpu_get_mid(u_int cpu_impl)
 
 	switch (cpu_impl) {
 	case CPU_IMPL_SPARC64:
+	case CPU_IMPL_SPARC64V:
 	case CPU_IMPL_ULTRASPARCI:
 	case CPU_IMPL_ULTRASPARCII:
 	case CPU_IMPL_ULTRASPARCIIi:
@@ -343,7 +345,8 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
 	/*
 	 * Do CPU-specific initialization.
 	 */
-	if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
+	if (cpu_impl == CPU_IMPL_SPARC64V ||
+	    cpu_impl >= CPU_IMPL_ULTRASPARCIII)
 		cheetah_init(cpu_impl);
 
 	/*
@@ -491,6 +494,7 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
 	if (cpu_use_vis) {
 		switch (cpu_impl) {
 		case CPU_IMPL_SPARC64:
+		case CPU_IMPL_SPARC64V:
 		case CPU_IMPL_ULTRASPARCI:
 		case CPU_IMPL_ULTRASPARCII:
 		case CPU_IMPL_ULTRASPARCIIi:
diff --git a/sys/sparc64/sparc64/mp_locore.S b/sys/sparc64/sparc64/mp_locore.S
index bd4fd13..e78b4b9 100644
--- a/sys/sparc64/sparc64/mp_locore.S
+++ b/sys/sparc64/sparc64/mp_locore.S
@@ -200,19 +200,25 @@ ENTRY(mp_startup)
 	srlx	%l1, VER_IMPL_SHIFT, %l1
 	sll	%l1, VER_IMPL_SIZE, %l1
 	srl	%l1, VER_IMPL_SIZE, %l1
+	cmp	%l1, CPU_IMPL_SPARC64V
+	bl	%icc, 4f
+	 nop
+	cmp	%l1, CPU_IMPL_ULTRASPARCI
+	bl	%icc, 2f
+	 nop
 	cmp	%l1, CPU_IMPL_ULTRASPARCIII
 	bl	%icc, 3f
 	 nop
-	mov	CPU_STICKSYNC, %l2
+2:	mov	CPU_STICKSYNC, %l2
 	membar	#StoreLoad
 	stw	%l2, [%l0 + CSA_STATE]
 
-2:	ldx	[%l0 + CSA_STICK], %l2
-	brz	%l2, 2b
+3:	ldx	[%l0 + CSA_STICK], %l2
+	brz	%l2, 3b
 	 nop
 	wr	%l2, 0, %asr24
 
-3:	call	cpu_get_mid
+4:	call	cpu_get_mid
 	 mov	%l1, %o0
 
 	/*
@@ -225,9 +231,9 @@ ENTRY(mp_startup)
 	/*
 	 * Wait till its our turn to bootstrap.
 	 */
-4:	lduw	[%l0 + CSA_MID], %l1
+5:	lduw	[%l0 + CSA_MID], %l1
 	cmp	%l1, %o0
-	bne	%xcc, 4b
+	bne	%xcc, 5b
 	 nop
 
 	add	%l0, CSA_TTES, %l1
@@ -236,7 +242,7 @@ ENTRY(mp_startup)
 	/*
 	 * Map the per-CPU pages.
 	 */
-5:	sllx	%l2, TTE_SHIFT, %l3
+6:	sllx	%l2, TTE_SHIFT, %l3
 	add	%l1, %l3, %l3
 
 	ldx	[%l3 + TTE_VPN], %l4
@@ -251,7 +257,7 @@ ENTRY(mp_startup)
 
 	add	%l2, 1, %l2
 	cmp	%l2, PCPU_PAGES
-	bne	%xcc, 5b
+	bne	%xcc, 6b
 	 nop
 
 	/*
diff --git a/sys/sparc64/sparc64/mp_machdep.c b/sys/sparc64/sparc64/mp_machdep.c
index ce66a4b..4281204 100644
--- a/sys/sparc64/sparc64/mp_machdep.c
+++ b/sys/sparc64/sparc64/mp_machdep.c
@@ -164,7 +164,8 @@ mp_init(u_int cpu_impl)
 	if (cpu_impl == CPU_IMPL_ULTRASPARCIIIi ||
 	    cpu_impl == CPU_IMPL_ULTRASPARCIIIip)
 		isjbus = 1;
-	if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
+	if (cpu_impl == CPU_IMPL_SPARC64V ||
+	    cpu_impl >= CPU_IMPL_ULTRASPARCIII)
 		cpu_ipi_selected = cheetah_ipi_selected;
 	else
 		cpu_ipi_selected = spitfire_ipi_selected;
@@ -315,7 +316,8 @@ ap_start(phandle_t node, u_int mid, u_int cpu_impl)
 		;
 	membar(StoreLoad);
 	csa->csa_tick = rd(tick);
-	if (cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
+	if (cpu_impl == CPU_IMPL_SPARC64V ||
+	    cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
 		while (csa->csa_state != CPU_STICKSYNC)
 			;
 		membar(StoreLoad);
@@ -411,7 +413,8 @@ cpu_mp_bootstrap(struct pcpu *pc)
 	csa = &cpu_start_args;
 
 	/* Do CPU-specific initialization. */
-	if (pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
+	if (pc->pc_impl == CPU_IMPL_SPARC64V ||
+	    pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
 		cheetah_init(pc->pc_impl);
 	/*
 	 * Enable the caches.  Note that his may include applying workarounds.
diff --git a/sys/sparc64/sparc64/pmap.c b/sys/sparc64/sparc64/pmap.c
index 5d69c13..4a2853c 100644
--- a/sys/sparc64/sparc64/pmap.c
+++ b/sys/sparc64/sparc64/pmap.c
@@ -528,7 +528,8 @@ pmap_bootstrap(u_int cpu_impl)
 			tp->tte_data =
 			    ((translations[i].om_tte &
 			    ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
-			    (cpu_impl < CPU_IMPL_ULTRASPARCIII ?
+			    (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
+			    cpu_impl < CPU_IMPL_ULTRASPARCIII ?
 			    (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
 			    (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
 			    (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
@@ -704,16 +705,16 @@ retry:
 		if (va >= VM_MIN_DIRECT_ADDRESS) {
 			tp = NULL;
 			m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
-			(void)vm_page_pa_tryrelock(pm, TLB_DIRECT_TO_PHYS(va), &pa);
+			(void)vm_page_pa_tryrelock(pm, TLB_DIRECT_TO_PHYS(va),
+			    &pa);
 			vm_page_hold(m);
 		} else {
 			tp = tsb_kvtotte(va);
 			if ((tp->tte_data & TD_V) == 0)
 				tp = NULL;
 		}
-	} else {
+	} else
 		tp = tsb_tte_lookup(pm, va);
-	}
 	if (tp != NULL && ((tp->tte_data & TD_SW) ||
 	    (prot & VM_PROT_WRITE) == 0)) {
 		if (vm_page_pa_tryrelock(pm, TTE_GET_PA(tp), &pa))
diff --git a/sys/sparc64/sparc64/tick.c b/sys/sparc64/sparc64/tick.c
index 1a38013..041faa0 100644
--- a/sys/sparc64/sparc64/tick.c
+++ b/sys/sparc64/sparc64/tick.c
@@ -120,7 +120,8 @@ cpu_initclocks(void)
 		 */
 	} else {
 		clock = PCPU_GET(clock);
-		intr_setup(PIL_TICK, PCPU_GET(impl) < CPU_IMPL_ULTRASPARCIII ?
+		intr_setup(PIL_TICK, PCPU_GET(impl) >= CPU_IMPL_ULTRASPARCI &&
+		    PCPU_GET(impl) < CPU_IMPL_ULTRASPARCIII ?
 		    tick_hardclock_bbwar : tick_hardclock, -1, NULL, NULL);
 		set_cputicker(tick_cputicks, clock, 0);
 	}
@@ -325,7 +326,8 @@ void
 tick_clear(u_int cpu_impl)
 {
 
-	if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
+	if (cpu_impl == CPU_IMPL_SPARC64V ||
+	    cpu_impl >= CPU_IMPL_ULTRASPARCIII)
 		wrstick(0, 0);
 	wrpr(tick, 0, 0);
 }
@@ -334,7 +336,8 @@ void
 tick_stop(u_int cpu_impl)
 {
 
-	if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
+	if (cpu_impl == CPU_IMPL_SPARC64V ||
+	    cpu_impl >= CPU_IMPL_ULTRASPARCIII)
 		wrstickcmpr(1L << 63, 0);
 	wrtickcmpr(1L << 63, 0);
 }
diff --git a/sys/sparc64/sparc64/zeus.c b/sys/sparc64/sparc64/zeus.c
new file mode 100644
index 0000000..a3dc4e5
--- /dev/null
+++ b/sys/sparc64/sparc64/zeus.c
@@ -0,0 +1,65 @@
+/*-
+ * Copyright (c) 2010 Marius Strobl <marius@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <machine/asi.h>
+#include <machine/cache.h>
+#include <machine/cpufunc.h>
+
+/*
+ * Flush all lines from the level 1 caches.
+ */
+void
+zeus_cache_flush(void)
+{
+
+	stxa_sync(0, ASI_FLUSH_L1I, 0);
+}
+
+/*
+ * Flush a physical page from the data cache.  Data cache consistency is
+ * maintained by hardware.
+ */
+void
+zeus_dcache_page_inval(vm_paddr_t spa __unused)
+{
+
+}
+
+/*
+ * Flush a physical page from the intsruction cache.  Instruction cache
+ * consistency is maintained by hardware.
+ */
+void
+zeus_icache_page_inval(vm_paddr_t pa __unused)
+{
+
+}