diff options
| author | ian <ian@FreeBSD.org> | 2014-02-23 22:52:48 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2014-02-23 22:52:48 +0000 |
| commit | d45f81d37a377932f62d9668de72ff609ba072dd (patch) | |
| tree | d97eba3c9ad1ba858add069f9eb442eff9de4e72 | |
| parent | 19920f52f7093f9320bea19e012e5517ae02aea5 (diff) | |
| download | FreeBSD-src-d45f81d37a377932f62d9668de72ff609ba072dd.zip FreeBSD-src-d45f81d37a377932f62d9668de72ff609ba072dd.tar.gz | |
If the L2 cache type is PIPT, pass a physical address for a flush.
While this is technically more correct, I don't think it much matters,
because the only thing in the tree that calls cpu_flush_dcache() is md(4)
and I'm > 99% sure it's bogus that it does so; md has no ability to do
anything that can perturb data cache coherency.
| -rw-r--r-- | sys/arm/arm/machdep.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c index 8544dc1..1386210 100644 --- a/sys/arm/arm/machdep.c +++ b/sys/arm/arm/machdep.c @@ -410,7 +410,11 @@ cpu_flush_dcache(void *ptr, size_t len) { cpu_dcache_wb_range((uintptr_t)ptr, len); +#ifdef ARM_L2_PIPT + cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len); +#else cpu_l2cache_wb_range((uintptr_t)ptr, len); +#endif } /* Get current clock frequency for the given cpu id. */ |
