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| author | ian <ian@FreeBSD.org> | 2015-02-23 20:09:05 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2015-02-23 20:09:05 +0000 |
| commit | d8abe6df98c0decd3b7509d6e722e968df5020da (patch) | |
| tree | 33e2044573e7bcc1fe63d3170f2ce2f9256d668d | |
| parent | 45a2a34766ae485750a4e5a76cb0b0d57d32748e (diff) | |
| download | FreeBSD-src-d8abe6df98c0decd3b7509d6e722e968df5020da.zip FreeBSD-src-d8abe6df98c0decd3b7509d6e722e968df5020da.tar.gz | |
There is no reason to do i+dcache writeback and invalidate when changing
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.
Submitted by: Michal Meloun
| -rw-r--r-- | sys/arm/arm/cpufunc_asm_armv7.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 5dcc171..dee9a9a 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -72,11 +72,7 @@ __FBSDID("$FreeBSD$"); #endif ENTRY(armv7_setttb) - stmdb sp!, {r0, lr} - bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ - ldmia sp!, {r0, lr} dsb - orr r0, r0, #PT_ATTR mcr CP15_TTBR0(r0) isb |
