diff options
| author | jhb <jhb@FreeBSD.org> | 2009-03-24 18:10:22 +0000 |
|---|---|---|
| committer | jhb <jhb@FreeBSD.org> | 2009-03-24 18:10:22 +0000 |
| commit | ac5c4c1c38ac2250cf5494d03b2f00b165f14f02 (patch) | |
| tree | 83e2b89a622fb80bb1a4d9d15a9e53de4354c2c0 | |
| parent | 9af3227e1abcc51a349fca5761c5d363da152015 (diff) | |
| download | FreeBSD-src-ac5c4c1c38ac2250cf5494d03b2f00b165f14f02.zip FreeBSD-src-ac5c4c1c38ac2250cf5494d03b2f00b165f14f02.tar.gz | |
Fall back to using configuration type 1 accesses for PCI config requests if
the requested PCI bus falls outside of the bus range given in the ACPI
MCFG table. Several BIOSes seem to not include all of the PCI busses in
systems in their MCFG tables. It maybe that the BIOS is simply buggy and
does support all the busses, but it is more conservative to just fall back
to the old method unless it is certain that memory accesses will work.
| -rw-r--r-- | sys/amd64/pci/pci_cfgreg.c | 2 | ||||
| -rw-r--r-- | sys/i386/pci/pci_cfgreg.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c index 8f757a7..61a2db5 100644 --- a/sys/amd64/pci/pci_cfgreg.c +++ b/sys/amd64/pci/pci_cfgreg.c @@ -119,6 +119,7 @@ pci_docfgregread(int bus, int slot, int func, int reg, int bytes) { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) return (pciereg_cfgread(bus, slot, func, reg, bytes)); else @@ -158,6 +159,7 @@ pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c index 3c41ba7..ecefa17 100644 --- a/sys/i386/pci/pci_cfgreg.c +++ b/sys/i386/pci/pci_cfgreg.c @@ -206,6 +206,7 @@ pci_docfgregread(int bus, int slot, int func, int reg, int bytes) { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) return (pciereg_cfgread(bus, slot, func, reg, bytes)); else @@ -240,6 +241,7 @@ pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else |
