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| author | nyan <nyan@FreeBSD.org> | 2004-03-28 12:06:29 +0000 |
|---|---|---|
| committer | nyan <nyan@FreeBSD.org> | 2004-03-28 12:06:29 +0000 |
| commit | f9ac46b8eb7d3709b65632d9b7e1059a6f09a790 (patch) | |
| tree | 906847151b928804c7843192b53968c396beffb9 | |
| parent | 94b9ebfa4467a679cc9910a005a4609d147a5cec (diff) | |
| download | FreeBSD-src-f9ac46b8eb7d3709b65632d9b7e1059a6f09a790.zip FreeBSD-src-f9ac46b8eb7d3709b65632d9b7e1059a6f09a790.tar.gz | |
MFi386: revision 1.1136.
| -rw-r--r-- | sys/pc98/conf/NOTES | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sys/pc98/conf/NOTES b/sys/pc98/conf/NOTES index 28e154b..f30595d 100644 --- a/sys/pc98/conf/NOTES +++ b/sys/pc98/conf/NOTES @@ -16,7 +16,7 @@ machine pc98 options PC98 # -# We want LINT to cover profiling as well +# We want LINT to cover profiling as well. profile 2 @@ -82,16 +82,16 @@ cpu I686_CPU # aka Pentium Pro(tm) # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct # mapped mode. Default is 2-way set associative mode. # -# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables +# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e., enables # reorder). This option should not be used if you use memory mapped # I/O device(s). # # CPU_DISABLE_CMPXCHG disables the CMPXCHG instruction on > i386 IA32 # machines. VmWare seems to emulate this instruction poorly, causing -# the guest OS to run very slowly. Enabling this with a SMP kernel +# the guest OS to run very slowly. Enabling this with an SMP kernel # will cause the kernel to be unusable. # -# CPU_DISABLE_SSE explicitly prevent I686_CPU from turning on SSE. +# CPU_DISABLE_SSE explicitly prevents I686_CPU from turning on SSE. # # CPU_ENABLE_SSE enables SSE/MMX2 instructions support. This is default # on I686_CPU and above. |
