Add preliminary support for 8168E/8111E PCIe controller.

While I'm here simplify device description string.

Tested by:	Michael Beckmann < michael <> apfel dot de >
MFC after:	5 days

2 files changed, 15 insertions, 2 deletions

diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c
index 9785801..8091506 100644
--- a/sys/dev/re/if_re.c
+++ b/sys/dev/re/if_re.c
@@ -174,8 +174,7 @@ static struct rl_type re_devs[] = {
 	{ RT_VENDORID, RT_DEVICEID_8101E, 0,
 	    "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" },
 	{ RT_VENDORID, RT_DEVICEID_8168, 0,
-	    "RealTek 8168/8168B/8168C/8168CP/8168D/8168DP/"
-	    "8111B/8111C/8111CP/8111DP PCIe Gigabit Ethernet" },
+	    "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" },
 	{ RT_VENDORID, RT_DEVICEID_8169, 0,
 	    "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
 	{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
@@ -220,6 +219,7 @@ static struct rl_hwrev re_hwrevs[] = {
 	{ RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"},
 	{ RL_HWREV_8168D, RL_8169, "8168D/8111D"},
 	{ RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"},
+	{ RL_HWREV_8168E, RL_8169, "8168E/8111E"},
 	{ 0, 0, NULL }
 };
 
@@ -1310,6 +1310,11 @@ re_attach(device_t dev)
 		 */
 		sc->rl_flags |= RL_FLAG_NOJUMBO;
 		break;
+	case RL_HWREV_8168E:
+		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
+		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
+		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO;
+		break;
 	case RL_HWREV_8169_8110SB:
 	case RL_HWREV_8169_8110SBL:
 	case RL_HWREV_8169_8110SC:
@@ -1393,6 +1398,8 @@ re_attach(device_t dev)
 	}
 
 	/* Take PHY out of power down mode. */
+	if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
+		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
 	if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
 		re_gmii_writereg(dev, 1, 0x1f, 0);
 		re_gmii_writereg(dev, 1, 0x0e, 0);
@@ -3135,6 +3142,9 @@ re_setwol(struct rl_softc *sc)
 		v |= RL_CFG5_WOL_LANWAKE;
 	CSR_WRITE_1(sc, RL_CFG5, v);
 
+	if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
+	    (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
+		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
 	/*
 	 * It seems that hardware resets its link speed to 100Mbps in
 	 * power down mode so switching to 100Mbps in driver is not
diff --git a/sys/pci/if_rlreg.h b/sys/pci/if_rlreg.h
index b575289..e8fddc9 100644
--- a/sys/pci/if_rlreg.h
+++ b/sys/pci/if_rlreg.h
@@ -133,6 +133,7 @@
 #define RL_GMEDIASTAT		0x006C	/* 8 bits */
 #define RL_MACDBG		0x006D	/* 8 bits, 8168C SPIN2 only */
 #define RL_GPIO			0x006E	/* 8 bits, 8168C SPIN2 only */
+#define RL_PMCH			0x006F	/* 8 bits */
 #define RL_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
 #define RL_GTXSTART		0x0038	/* 8 bits */
 
@@ -162,6 +163,7 @@
 #define RL_HWREV_8102EL_SPIN1	0x24c00000
 #define RL_HWREV_8168D		0x28000000
 #define RL_HWREV_8168DP		0x28800000
+#define RL_HWREV_8168E		0x2C000000
 #define RL_HWREV_8168_SPIN1	0x30000000
 #define RL_HWREV_8100E		0x30800000
 #define RL_HWREV_8101E		0x34000000
@@ -884,6 +886,7 @@ struct rl_softc {
 	uint32_t		rl_flags;
 #define	RL_FLAG_MSI		0x0001
 #define	RL_FLAG_AUTOPAD		0x0002
+#define	RL_FLAG_PHYWAKE_PM	0x0004
 #define	RL_FLAG_PHYWAKE		0x0008
 #define	RL_FLAG_NOJUMBO		0x0010
 #define	RL_FLAG_PAR		0x0020