- Initial release of bxe(4) to support Broadcom NetXtreme II 10GbE.

  (BCM57710, BCM57711, BCM57711E)

MFC after:	One month

25 files changed, 107849 insertions, 0 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 8f9a7b9..050af02 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -47,6 +47,7 @@ cd(4)		ken	Pre-commit review requested.
 pass(4)		ken	Pre-commit review requested.
 ch(4)		ken	Pre-commit review requested.
 em(4)		jfv	Pre-commit review requested.
+bxe(4)		davidch	Pre-commit review requested.
 tdfx(4)		cokane  Just keep me informed of changes, try not to break it.
 sendmail	gshapiro	Pre-commit review requested.
 etc/mail	gshapiro	Pre-commit review requested.
diff --git a/sys/amd64/conf/GENERIC b/sys/amd64/conf/GENERIC
index 0f259ee..2f68f9e 100644
--- a/sys/amd64/conf/GENERIC
+++ b/sys/amd64/conf/GENERIC
@@ -193,6 +193,7 @@ device		ppi		# Parallel port interface device
 #device		puc
 
 # PCI Ethernet NICs.
+device		bxe		# Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
 device		de		# DEC/Intel DC21x4x (``Tulip'')
 device		em		# Intel PRO/1000 Gigabit Ethernet Family
 device		igb		# Intel PRO/1000 PCIE Server Gigabit Family
diff --git a/sys/boot/forth/loader.conf b/sys/boot/forth/loader.conf
index bfb4ff6..737652a 100644
--- a/sys/boot/forth/loader.conf
+++ b/sys/boot/forth/loader.conf
@@ -268,6 +268,7 @@ if_bge_load="NO"		# Broadcom BCM570x PCI Gigabit Ethernet
 if_bridge_load="NO"		# if_bridge(4) devices
 if_bwi_load="NO"		# Broadcom BCM53xx IEEE 802.11b/g wireness NICs
 if_bwn_load="NO"		# Broadcom BCM43xx IEEE 802.11 wireless NICs
+if_bxe_load="NO"		# Broadcom NetXtreme II 10Gb Ethernet
 if_carp_load="NO"		# carp(4) devices
 if_cas_load="NO"		# Sun Cassini/Cassini+ and NS DP83065 Saturn
 if_cm_load="NO"			# SMC (90c26, 90c56, 90c66)
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index 1ad2d73..cf8064f 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -1900,6 +1900,8 @@ device		xmphy		# XaQti XMAC II
 #	BCM570x family of controllers, including the 3Com 3c996-T,
 #	the Netgear GA302T, the SysKonnect SK-9D21 and SK-9D41, and
 #	the embedded gigE NICs on Dell PowerEdge 2550 servers.
+# bxe:	Broadcom NetXtreme II (BCM57710/57711/57711E) PCIe 10b Ethernet
+#       adapters.
 # bwi:	Broadcom BCM430* and BCM431* family of wireless adapters.
 # bwn:	Broadcom BCM43xx family of wireless adapters.
 # cas:	Sun Cassini/Cassini+ and National Semiconductor DP83065 Saturn
@@ -2078,6 +2080,7 @@ device		wb		# Winbond W89C840F
 device		xl		# 3Com 3c90x (``Boomerang'', ``Cyclone'')
 
 # PCI Ethernet NICs.
+device		bxe		# Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
 device		cxgbe		# Chelsio T4 10GbE PCIe adapter
 device		de		# DEC/Intel DC21x4x (``Tulip'')
 device		em		# Intel Pro/1000 Gigabit Ethernet
diff --git a/sys/conf/files b/sys/conf/files
index 3e083bb..83ec0f1 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -819,6 +819,8 @@ dev/bwi/bwirf.c			optional bwi
 dev/bwi/if_bwi.c		optional bwi
 dev/bwi/if_bwi_pci.c		optional bwi pci
 dev/bwn/if_bwn.c		optional bwn siba_bwn
+dev/bxe/if_bxe.c		optional bxe
+dev/bxe/bxe_link.c		optional bxe
 dev/cardbus/cardbus.c		optional cardbus
 dev/cardbus/cardbus_cis.c	optional cardbus
 dev/cardbus/cardbus_device.c	optional cardbus
diff --git a/sys/conf/options b/sys/conf/options
index 1ea7340..7f92258 100644
--- a/sys/conf/options
+++ b/sys/conf/options
@@ -702,8 +702,13 @@ ED_SIC			opt_ed.h
 BCE_DEBUG		opt_bce.h
 BCE_NVRAM_WRITE_SUPPORT	opt_bce.h
 
+# bxe driver
+BXE_DEBUG		opt_bxe.h
+BXE_NVRAM_WRITE_SUPPORT	opt_bxe.h
+
 SOCKBUF_DEBUG		opt_global.h
 
+
 # options for ubsec driver
 UBSEC_DEBUG		opt_ubsec.h
 UBSEC_RNDTEST		opt_ubsec.h
diff --git a/sys/dev/bxe/bxe_debug.h b/sys/dev/bxe/bxe_debug.h
new file mode 100755
index 0000000..47cabb5
--- /dev/null
+++ b/sys/dev/bxe/bxe_debug.h
@@ -0,0 +1,357 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef _BXE_DEBUG_H
+#define	_BXE_DEBUG_H
+
+extern uint32_t bxe_debug;
+
+/*
+ * Debugging macros and definitions.
+ */
+
+#define	BXE_CP_LOAD		0x00000001
+#define	BXE_CP_SEND		0x00000002
+#define	BXE_CP_RECV		0x00000004
+#define	BXE_CP_INTR		0x00000008
+#define	BXE_CP_UNLOAD		0x00000010
+#define	BXE_CP_RESET		0x00000020
+#define	BXE_CP_IOCTL		0x00000040
+#define	BXE_CP_STATS		0x00000080
+#define	BXE_CP_MISC		0x00000100
+#define	BXE_CP_PHY		0x00000200
+#define	BXE_CP_RAMROD		0x00000400
+#define	BXE_CP_NVRAM		0x00000800
+#define	BXE_CP_REGS		0x00001000
+#define	BXE_CP_ALL		0x00FFFFFF
+#define	BXE_CP_MASK		0x00FFFFFF
+
+#define BXE_LEVEL_FATAL			0x00000000
+#define BXE_LEVEL_WARN			0x01000000
+#define BXE_LEVEL_INFO			0x02000000
+#define BXE_LEVEL_VERBOSE		0x03000000
+#define BXE_LEVEL_EXTREME		0x04000000
+#define BXE_LEVEL_INSANE		0x05000000
+
+#define BXE_LEVEL_MASK			0xFF000000
+
+#define BXE_WARN_LOAD			(BXE_CP_LOAD | BXE_LEVEL_WARN)
+#define BXE_INFO_LOAD			(BXE_CP_LOAD | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_LOAD		(BXE_CP_LOAD | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_LOAD		(BXE_CP_LOAD | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_LOAD			(BXE_CP_LOAD | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_SEND			(BXE_CP_SEND | BXE_LEVEL_WARN)
+#define BXE_INFO_SEND			(BXE_CP_SEND | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_SEND		(BXE_CP_SEND | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_SEND		(BXE_CP_SEND | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_SEND			(BXE_CP_SEND | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_RECV			(BXE_CP_RECV | BXE_LEVEL_WARN)
+#define BXE_INFO_RECV			(BXE_CP_RECV | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_RECV		(BXE_CP_RECV | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_RECV		(BXE_CP_RECV | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_RECV			(BXE_CP_RECV | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_INTR			(BXE_CP_INTR | BXE_LEVEL_WARN)
+#define BXE_INFO_INTR			(BXE_CP_INTR | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_INTR		(BXE_CP_INTR | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_INTR		(BXE_CP_INTR | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_INTR			(BXE_CP_INTR | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_UNLOAD			(BXE_CP_UNLOAD | BXE_LEVEL_WARN)
+#define BXE_INFO_UNLOAD			(BXE_CP_UNLOAD | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_UNLOAD		(BXE_CP_UNLOAD | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_UNLOAD		(BXE_CP_UNLOAD | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_UNLOAD		(BXE_CP_UNLOAD | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_RESET			(BXE_CP_RESET | BXE_LEVEL_WARN)
+#define BXE_INFO_RESET			(BXE_CP_RESET | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_RESET		(BXE_CP_RESET | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_RESET		(BXE_CP_RESET | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_RESET		(BXE_CP_RESET | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_IOCTL			(BXE_CP_IOCTL | BXE_LEVEL_WARN)
+#define BXE_INFO_IOCTL			(BXE_CP_IOCTL | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_IOCTL		(BXE_CP_IOCTL | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_IOCTL		(BXE_CP_IOCTL | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_IOCTL		(BXE_CP_IOCTL | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_STATS			(BXE_CP_STATS | BXE_LEVEL_WARN)
+#define BXE_INFO_STATS			(BXE_CP_STATS | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_STATS		(BXE_CP_STATS | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_STATS		(BXE_CP_STATS | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_STATS		(BXE_CP_STATS | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_MISC			(BXE_CP_MISC | BXE_LEVEL_WARN)
+#define BXE_INFO_MISC			(BXE_CP_MISC | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_MISC		(BXE_CP_MISC | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_MISC		(BXE_CP_MISC | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_MISC			(BXE_CP_MISC | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_PHY			(BXE_CP_PHY | BXE_LEVEL_WARN)
+#define BXE_INFO_PHY			(BXE_CP_PHY | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_PHY			(BXE_CP_PHY | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_PHY			(BXE_CP_PHY | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_PHY			(BXE_CP_PHY | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_RAMROD			(BXE_CP_RAMROD | BXE_LEVEL_WARN)
+#define BXE_INFO_RAMROD			(BXE_CP_RAMROD | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_RAMROD		(BXE_CP_RAMROD | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_RAMROD		(BXE_CP_RAMROD | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_RAMROD		(BXE_CP_RAMROD | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_NVRAM			(BXE_CP_NVRAM | BXE_LEVEL_WARN)
+#define BXE_INFO_NVRAM			(BXE_CP_NVRAM | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_NVRAM		(BXE_CP_NVRAM | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_NVRAM		(BXE_CP_NVRAM | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_NVRAM		(BXE_CP_NVRAM | BXE_LEVEL_INSANE)
+
+#define BXE_WARN_REGS			(BXE_CP_REGS | BXE_LEVEL_WARN)
+#define BXE_INFO_REGS			(BXE_CP_REGS | BXE_LEVEL_INFO)
+#define BXE_VERBOSE_REGS		(BXE_CP_REGS | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME_REGS		(BXE_CP_REGS | BXE_LEVEL_EXTREME)
+#define BXE_INSANE_REGS			(BXE_CP_REGS | BXE_LEVEL_INSANE)
+
+#define BXE_FATAL				(BXE_CP_ALL | BXE_LEVEL_FATAL)
+#define BXE_WARN				(BXE_CP_ALL | BXE_LEVEL_WARN)
+#define BXE_INFO				(BXE_CP_ALL | BXE_LEVEL_INFO)
+#define BXE_VERBOSE				(BXE_CP_ALL | BXE_LEVEL_VERBOSE)
+#define BXE_EXTREME				(BXE_CP_ALL | BXE_LEVEL_EXTREME)
+#define BXE_INSANE				(BXE_CP_ALL | BXE_LEVEL_INSANE)
+
+#define BXE_CODE_PATH(cp)		((cp & BXE_CP_MASK) & bxe_debug)
+#define BXE_MSG_LEVEL(lv)		((lv & BXE_LEVEL_MASK) <= (bxe_debug & BXE_LEVEL_MASK))
+#define BXE_LOG_MSG(m)			(BXE_CODE_PATH(m) && BXE_MSG_LEVEL(m))
+
+
+#ifdef BXE_DEBUG
+
+/* Print a message based on the logging level and code path. */
+#define DBPRINT(sc, level, format, args...)					\
+	do {													\
+		if (BXE_LOG_MSG(level)) {							\
+			device_printf(sc->bxe_dev, format, ## args);	\
+		}													\
+	} while (0)
+
+/* Runs a particular command when debugging is enabled. */
+#define DBRUN(args...)			\
+	do {						\
+		args;					\
+	} while (0)
+
+/* Runs a particular command based on the logging level. */
+#define DBRUNLV(level, args...) \
+	if (BXE_MSG_LEVEL(level)) { \
+		args; 					\
+	}
+
+/* Runs a particular command based on the code path. */
+#define DBRUNCP(cp, args...) 	\
+	if (BXE_CODE_PATH(cp)) { 	\
+		args; 					\
+	}
+
+/* Runs a particular command based on a condition. */
+#define DBRUNIF(cond, args...)	\
+	if (cond) {					\
+		args;					\
+	}
+
+/* Runs a particular command based on the logging level and code path. */
+#define DBRUNMSG(msg, args...)	\
+	if (BXE_LOG_MSG(msg)) {		\
+		args;					\
+	}
+
+/* Announces function entry. */
+#define DBENTER(cond)	\
+	DBPRINT(sc, (cond), "%s(enter:%d)\n", __FUNCTION__, curcpu) \
+
+/* Announces function exit. */
+#define DBEXIT(cond)	\
+	DBPRINT(sc, (cond), "%s(exit:%d)\n", __FUNCTION__, curcpu) \
+
+/* Needed for random() function which is only used in debugging. */
+#include <sys/random.h>
+
+/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
+#define DB_RANDOMFALSE(defects)        (random() > defects)
+#define DB_OR_RANDOMFALSE(defects)  || (random() > defects)
+#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
+
+/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
+#define DB_RANDOMTRUE(defects)         (random() < defects)
+#define DB_OR_RANDOMTRUE(defects)   || (random() < defects)
+#define DB_AND_RANDOMTRUE(defects)  && (random() < defects)
+
+#else
+
+#define DBPRINT(...)
+#define DBRUN(...)
+#define DBRUNLV(...)
+#define DBRUNCP(...)
+#define DBRUNIF(...)
+#define DBRUNMSG(...)
+#define DBENTER(...)
+#define DBENTER_UNLOCKED(...)
+#define DBEXIT(...)
+#define DBEXIT_UNLOCKED(...)
+#define DB_RANDOMFALSE(...)
+#define DB_OR_RANDOMFALSE(...)
+#define DB_AND_RANDOMFALSE(...)
+#define DB_RANDOMTRUE(...)
+#define DB_OR_RANDOMTRUE(...)
+#define DB_AND_RANDOMTRUE(...)
+
+#endif /* BXE_DEBUG */
+
+/* Generic bit decoding for printf("%b"). */
+#define BXE_DWORD_PRINTFB	\
+	"\020"					\
+	"\40b31"				\
+	"\37b30"				\
+	"\36b29"				\
+	"\35b28"				\
+	"\34b27"				\
+	"\33b26"				\
+	"\32b25"				\
+	"\31b24"				\
+	"\30b23"				\
+	"\27b22"				\
+	"\26b21"				\
+	"\25b20"				\
+	"\24b19"				\
+	"\23b18"				\
+	"\22b17"				\
+	"\21b16"				\
+	"\20b15"				\
+	"\17b14"				\
+	"\16b13"				\
+	"\15b12"				\
+	"\14b11"				\
+	"\13b10"				\
+	"\12b9"					\
+	"\11b8"					\
+	"\10b7"					\
+	"\07b6"					\
+	"\06b5"					\
+	"\05b4"					\
+	"\04b3"					\
+	"\03b2"					\
+	"\02b1"					\
+	"\01b0"
+
+/* Supported link settings bit decoding for printf("%b"). */
+#define BXE_SUPPORTED_PRINTFB	\
+	"\020"						\
+	"\040b31"					\
+	"\037b30"					\
+	"\036b29"					\
+	"\035b28"					\
+	"\034b27"					\
+	"\033b26"					\
+	"\032b25"					\
+	"\031b24"					\
+	"\030b23"					\
+	"\027b22"					\
+	"\026b21"					\
+	"\025b20"					\
+	"\024b19"					\
+	"\023b18"					\
+	"\022b17"					\
+	"\02110000BaseT-Full"		\
+	"\0202500BaseX-Full"  		\
+	"\017b14"					\
+	"\016b13"					\
+	"\015b12"					\
+	"\014Pause"					\
+	"\013Asym-Pause" 			\
+	"\012Autoneg"				\
+	"\011Fiber"					\
+	"\010TP"			  		\
+	"\0071000BaseT-Full"  		\
+	"\0061000BaseT-Half"  		\
+	"\005100BaseTX-Full"  		\
+	"\004100BaseTX-Half"  		\
+	"\00310BaseT-Full"			\
+	"\00210BaseT-Half"			\
+	"\001b0"
+
+/* Transmit BD TCP flags bit decoding for printf("%b"). */
+#define BXE_ETH_TX_PARSE_BD_TCP_FLAGS_PRINTFB	\
+	"\020"										\
+	"\10CWR"									\
+	"\07ECE"									\
+	"\06URG"									\
+	"\05ACK"									\
+	"\04PSH"									\
+	"\03RST"									\
+	"\02SYN"									\
+	"\01FIN"
+
+/* Parsing BD global data bit decoding for printf("%b"). */
+#define BXE_ETH_TX_PARSE_BD_GLOBAL_DATA_PRINTFB	\
+	"\020"										\
+	"\10NS"										\
+	"\07LLC_SNAP"								\
+	"\06PSEUDO_CS_WO_LEN"						\
+	"\05CS_ANY"
+
+/* Transmit BD flags bit decoding for printf("%b"). */
+#define BXE_ETH_TX_BD_FLAGS_PRINTFB				\
+	"\020"										\
+	"\10IPv6"									\
+	"\07LSO"									\
+	"\06HDR_POOL" 								\
+	"\05START"									\
+	"\04END"									\
+	"\03TCP_CSUM" 								\
+	"\02IP_CSUM" 								\
+	"\01VLAN"
+
+/* Receive CQE error flags bit decoding for printf("%b"). */
+#define BXE_ETH_FAST_PATH_RX_CQE_ERROR_FLAGS_PRINTFB	\
+	"\020"												\
+	"\10RSRVD"											\
+	"\07RSRVD"											\
+	"\06END_FLAG" 										\
+	"\05START_FLAG"										\
+	"\04L4_BAD_XSUM"									\
+	"\03IP_BAD_XSUM"									\
+	"\02PHY_DECODE_ERR"									\
+	"\01SP"
+
+#endif /* _BXE_DEBUG_H */
diff --git a/sys/dev/bxe/bxe_fw_defs.h b/sys/dev/bxe/bxe_fw_defs.h
new file mode 100755
index 0000000..169fc42
--- /dev/null
+++ b/sys/dev/bxe/bxe_fw_defs.h
@@ -0,0 +1,624 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef _BXE_FW_DEFS_H
+#define _BXE_FW_DEFS_H
+
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
+	(IS_E1H_OFFSET ? 0x7000 : 0x1000)
+#define CSTORM_ASSERT_LIST_OFFSET(idx) \
+	(IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
+	(IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
+	((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
+	0x40) + (index * 0x4)))
+#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
+	(IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
+	((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
+	0x80) + (index * 0x4)))
+#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
+	((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
+#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
+	((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
+	((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
+	((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
+#define CSTORM_FUNCTION_MODE_OFFSET \
+	(IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
+#define CSTORM_HC_BTR_C_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
+#define CSTORM_HC_BTR_U_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
+#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
+	(function * 0x8)))
+#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
+	(function * 0x8)))
+#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
+	(IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
+	(0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
+	(IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
+	(0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
+	(IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
+	(0x241c + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
+	(IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
+	(0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
+	(IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
+	(0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
+	(IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
+	(0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
+	(IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
+	(0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
+#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
+	(function * 0x8)))
+#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
+	(function * 0x8)))
+#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
+	(function * 0x8)))
+#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
+	(function * 0x8)))
+#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
+	(IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
+	(index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
+	(index * 0x4)))
+#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
+	(IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
+	(index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
+	(index * 0x4)))
+#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
+	(IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
+	(index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
+	(index * 0x4)))
+#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
+	(IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
+	(index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
+	(index * 0x4)))
+#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
+	(IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
+	(0x3040 + (port * 0x280) + (cpu_id * 0x28)))
+#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
+	(IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
+	(0x4000 + (port * 0x800) + (cpu_id * 0x80)))
+#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
+	(IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
+	(0x3048 + (port * 0x280) + (cpu_id * 0x28)))
+#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
+	(IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
+	(0x4008 + (port * 0x800) + (cpu_id * 0x80)))
+#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
+#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
+#define CSTORM_STATS_FLAGS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
+	(function * 0x8)))
+#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
+#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
+	(IS_E1H_OFFSET ? 0xa000 : 0x1000)
+#define TSTORM_ASSERT_LIST_OFFSET(idx) \
+	(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
+	(IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
+	: (0x9c0 + (port * 0x120) + (client_id * 0x10)))
+#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
+	(IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
+#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
+	(IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
+#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
+	(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
+	((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
+	0x28) + (index * 0x4)))
+#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
+	((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
+#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
+	((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
+#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
+	(function * 0x8)))
+#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
+	(function * 0x40)))
+#define TSTORM_FUNCTION_MODE_OFFSET \
+	(IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
+#define TSTORM_HC_BTR_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
+	(function * 0x80)))
+#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
+#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
+	(IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
+	: (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
+#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
+	(function * 0x8)))
+#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
+	(function * 0x8)))
+#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
+	(function * 0x8)))
+#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
+	(function * 0x8)))
+#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
+	(function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
+	(function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
+	(function * 0x8)))
+#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
+	(function * 0x8)))
+#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
+	(function * 0x40)))
+#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+	(IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
+	0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
+#define TSTORM_STATS_FLAGS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
+	(function * 0x8)))
+#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
+	(function * 0x8)))
+#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
+#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
+#define USTORM_ASSERT_LIST_INDEX_OFFSET \
+	(IS_E1H_OFFSET ? 0x8000 : 0x1000)
+#define USTORM_ASSERT_LIST_OFFSET(idx) \
+	(IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
+	(IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
+	(0x4010 + (port * 0x360) + (clientId * 0x30)))
+
+#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
+	(IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
+	(0x4028 + (port * 0x360) + (clientId * 0x30)))
+
+#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
+#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
+	(IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
+	0xffffffff)
+#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
+	(function * 0x8)))
+#define USTORM_FUNCTION_MODE_OFFSET \
+	(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
+#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
+	(function * 0x8)))
+#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
+	(function * 0x8)))
+#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
+	(IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
+	(0x4018 + (port * 0x360) + (clientId * 0x30)))
+#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
+	(function * 0x8)))
+#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+	(IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
+	0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
+#define USTORM_RX_PRODS_OFFSET(port, client_id) \
+	(IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
+	: (0x4000 + (port * 0x360) + (client_id * 0x30)))
+#define USTORM_STATS_FLAGS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
+	(function * 0x8)))
+#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
+#define USTORM_TPA_BTR_SIZE 0x1
+#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
+	(IS_E1H_OFFSET ? 0x9000 : 0x1000)
+#define XSTORM_ASSERT_LIST_OFFSET(idx) \
+	(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
+#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
+	(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
+	((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
+	0x28) + (index * 0x4)))
+#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
+	((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
+#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
+	((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
+#define XSTORM_E1HOV_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
+#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
+	(function * 0x8)))
+#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
+	(function * 0x90)))
+#define XSTORM_FUNCTION_MODE_OFFSET \
+	(IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
+#define XSTORM_HC_BTR_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
+	(function * 0x8)))
+#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
+	(function * 0x8)))
+#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+	(IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
+	0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
+#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
+	(function * 0x90)))
+#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
+	(function * 0x10)))
+#define XSTORM_SPQ_PROD_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
+	(function * 0x10)))
+#define XSTORM_STATS_FLAGS_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
+	(function * 0x8)))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
+	(IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
+#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
+	(IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
+	* 0x4)) : (0x1978 + (function * 0x4)))
+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+
+/**
+* This file defines HSI constants for the ETH flow
+*/
+#ifdef _EVEREST_MICROCODE
+#include "microcode_constants.h"
+#include "eth_rx_bd.h"
+#include "eth_tx_bd.h"
+#include "eth_rx_cqe.h"
+#include "eth_rx_sge.h"
+#include "eth_rx_cqe_next_page.h"
+#endif
+
+/* RSS hash types */
+#define DEFAULT_HASH_TYPE 0
+#define IPV4_HASH_TYPE 1
+#define TCP_IPV4_HASH_TYPE 2
+#define IPV6_HASH_TYPE 3
+#define TCP_IPV6_HASH_TYPE 4
+#define VLAN_PRI_HASH_TYPE 5
+#define E1HOV_PRI_HASH_TYPE 6
+#define DSCP_HASH_TYPE 7
+
+
+/* Ethernet Ring parameters */
+#define X_ETH_LOCAL_RING_SIZE 13
+#define FIRST_BD_IN_PKT 0
+#define PARSE_BD_INDEX 1
+#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
+#define U_ETH_NUM_OF_SGES_TO_FETCH 8
+#define U_ETH_MAX_SGES_FOR_PACKET 3
+
+/* Rx ring params */
+#define U_ETH_LOCAL_BD_RING_SIZE 8
+#define U_ETH_LOCAL_SGE_RING_SIZE 10
+#define U_ETH_SGL_SIZE 8
+
+
+#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
+	(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
+
+#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
+#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
+
+#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
+#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
+#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
+
+#define U_ETH_UNDEFINED_Q 0xFF
+
+/* values of command IDs in the ramrod message */
+#define RAMROD_CMD_ID_ETH_PORT_SETUP 80
+#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
+#define RAMROD_CMD_ID_ETH_STAT_QUERY 90
+#define RAMROD_CMD_ID_ETH_UPDATE 100
+#define RAMROD_CMD_ID_ETH_HALT 105
+#define RAMROD_CMD_ID_ETH_SET_MAC 110
+#define RAMROD_CMD_ID_ETH_CFC_DEL 115
+#define RAMROD_CMD_ID_ETH_PORT_DEL 120
+#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
+
+
+/* command values for set mac command */
+#define T_ETH_MAC_COMMAND_SET 0
+#define T_ETH_MAC_COMMAND_INVALIDATE 1
+
+#define T_ETH_INDIRECTION_TABLE_SIZE 128
+
+/*The CRC32 seed, that is used for the hash(reduction) multicast address */
+#define T_ETH_CRC32_HASH_SEED 0x00000000
+
+/* Maximal L2 clients supported */
+#define ETH_MAX_RX_CLIENTS_E1 18
+#define ETH_MAX_RX_CLIENTS_E1H 26
+
+/* Maximal aggregation queues supported */
+#define ETH_MAX_AGGREGATION_QUEUES_E1 32
+#define ETH_MAX_AGGREGATION_QUEUES_E1H 64
+
+/* ETH RSS modes */
+#define ETH_RSS_MODE_DISABLED 0
+#define ETH_RSS_MODE_REGULAR 1
+#define ETH_RSS_MODE_VLAN_PRI 2
+#define ETH_RSS_MODE_E1HOV_PRI 3
+#define ETH_RSS_MODE_IP_DSCP 4
+
+
+/**
+* This file defines HSI constants common to all microcode flows
+*/
+
+/* Connection types */
+#define ETH_CONNECTION_TYPE 0
+#define TOE_CONNECTION_TYPE 1
+#define RDMA_CONNECTION_TYPE 2
+#define ISCSI_CONNECTION_TYPE 3
+#define FCOE_CONNECTION_TYPE 4
+#define RESERVED_CONNECTION_TYPE_0 5
+#define RESERVED_CONNECTION_TYPE_1 6
+#define RESERVED_CONNECTION_TYPE_2 7
+
+
+#define PROTOCOL_STATE_BIT_OFFSET 6
+
+#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+
+/* microcode fixed page page size 4K (chains and ring segments) */
+#define MC_PAGE_SIZE 4096
+
+
+/* Host coalescing constants */
+#define HC_IGU_BC_MODE 0
+#define HC_IGU_NBC_MODE 1
+
+#define HC_REGULAR_SEGMENT 0
+#define HC_DEFAULT_SEGMENT 1
+
+/* index numbers */
+#define HC_USTORM_DEF_SB_NUM_INDICES 8
+#define HC_CSTORM_DEF_SB_NUM_INDICES 8
+#define HC_XSTORM_DEF_SB_NUM_INDICES 4
+#define HC_TSTORM_DEF_SB_NUM_INDICES 4
+#define HC_USTORM_SB_NUM_INDICES 4
+#define HC_CSTORM_SB_NUM_INDICES 4
+
+/* index values - which counter to update */
+
+#define HC_INDEX_U_TOE_RX_CQ_CONS 0
+#define HC_INDEX_U_ETH_RX_CQ_CONS 1
+#define HC_INDEX_U_ETH_RX_BD_CONS 2
+#define HC_INDEX_U_FCOE_EQ_CONS 3
+
+#define HC_INDEX_C_TOE_TX_CQ_CONS 0
+#define HC_INDEX_C_ETH_TX_CQ_CONS 1
+#define HC_INDEX_C_ISCSI_EQ_CONS 2
+
+#define HC_INDEX_DEF_X_SPQ_CONS 0
+
+#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
+#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
+#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
+#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
+#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
+#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
+#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
+
+#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
+#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
+#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
+#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
+
+/* used by the driver to get the SB offset */
+#define USTORM_ID 0
+#define CSTORM_ID 1
+#define XSTORM_ID 2
+#define TSTORM_ID 3
+#define ATTENTION_ID 4
+
+/* max number of slow path commands per port */
+#define MAX_RAMRODS_PER_PORT 8
+
+/* values for RX ETH CQE type field */
+#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
+#define RX_ETH_CQE_TYPE_ETH_RAMROD 1
+
+
+/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
+#define EMULATION_FREQUENCY_FACTOR 1600
+#define FPGA_FREQUENCY_FACTOR 100
+
+#define TIMERS_TICK_SIZE_CHIP (1e-3)
+#define TIMERS_TICK_SIZE_EMUL \
+ ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
+#define TIMERS_TICK_SIZE_FPGA \
+ ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
+
+#define TSEMI_CLK1_RESUL_CHIP (1e-3)
+#define TSEMI_CLK1_RESUL_EMUL \
+ ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define TSEMI_CLK1_RESUL_FPGA \
+ ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
+#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
+#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
+
+#define XSEMI_CLK1_RESUL_CHIP (1e-3)
+#define XSEMI_CLK1_RESUL_EMUL \
+ ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK1_RESUL_FPGA \
+ ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+#define XSEMI_CLK2_RESUL_CHIP (1e-6)
+#define XSEMI_CLK2_RESUL_EMUL \
+ ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK2_RESUL_FPGA \
+ ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
+#define SDM_TIMER_TICK_RESUL_EMUL \
+ ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define SDM_TIMER_TICK_RESUL_FPGA \
+ ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
+#define XSTORM_IP_ID_ROLL_HALF 0x8000
+#define XSTORM_IP_ID_ROLL_ALL 0
+
+#define FW_LOG_LIST_SIZE 50
+
+#define NUM_OF_PROTOCOLS 4
+#define NUM_OF_SAFC_BITS 16
+#define MAX_COS_NUMBER 4
+#define MAX_T_STAT_COUNTER_ID 18
+#define MAX_X_STAT_COUNTER_ID 18
+#define MAX_U_STAT_COUNTER_ID 18
+
+
+#define UNKNOWN_ADDRESS 0
+#define UNICAST_ADDRESS 1
+#define MULTICAST_ADDRESS 2
+#define BROADCAST_ADDRESS 3
+
+#define SINGLE_FUNCTION 0
+#define MULTI_FUNCTION 1
+
+#define IP_V4 0
+#define IP_V6 1
+
+#endif
diff --git a/sys/dev/bxe/bxe_hsi.h b/sys/dev/bxe/bxe_hsi.h
new file mode 100755
index 0000000..dfaa052
--- /dev/null
+++ b/sys/dev/bxe/bxe_hsi.h
@@ -0,0 +1,3179 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+struct license_key {
+	uint32_t reserved[6];
+
+#if defined(__BIG_ENDIAN)
+	uint16_t max_iscsi_init_conn;
+	uint16_t max_iscsi_trgt_conn;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t max_iscsi_trgt_conn;
+	uint16_t max_iscsi_init_conn;
+#endif
+
+	uint32_t reserved_a[6];
+};
+
+#define	PORT_0				0
+#define	PORT_1				1
+#define	PORT_MAX			2
+
+/*
+ * Shared HW configuration
+ */
+struct shared_hw_cfg {					/* NVRAM Offset */
+	/* Up to 16 bytes of NULL-terminated string */
+	uint8_t  part_num[16];				/* 0x104 */
+
+	uint32_t config;				/* 0x114 */
+#define	SHARED_HW_CFG_MDIO_VOLTAGE_MASK			0x00000001
+#define	SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT		0
+#define	SHARED_HW_CFG_MDIO_VOLTAGE_1_2V			0x00000000
+#define	SHARED_HW_CFG_MDIO_VOLTAGE_2_5V			0x00000001
+#define	SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN		0x00000002
+
+#define	SHARED_HW_CFG_PORT_SWAP				0x00000004
+
+#define	SHARED_HW_CFG_BEACON_WOL_EN			0x00000008
+
+#define	SHARED_HW_CFG_MFW_SELECT_MASK			0x00000700
+#define	SHARED_HW_CFG_MFW_SELECT_SHIFT			8
+	/*
+	 * Whatever MFW found in NVM
+	 * (if multiple found, priority order is: NC-SI, UMP, IPMI)
+	 */
+#define	SHARED_HW_CFG_MFW_SELECT_DEFAULT		0x00000000
+#define	SHARED_HW_CFG_MFW_SELECT_NC_SI			0x00000100
+#define	SHARED_HW_CFG_MFW_SELECT_UMP			0x00000200
+#define	SHARED_HW_CFG_MFW_SELECT_IPMI			0x00000300
+	/*
+	 * Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
+	 * (can only be used when an add-in board, not BMC, pulls-down SPIO4).
+	 */
+#define	SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI	0x00000400
+	/*
+	 * Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
+	 * (can only be used when an add-in board, not BMC, pulls-down SPIO4).
+	 */
+#define	SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI		0x00000500
+	/*
+	 * Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
+	 * (can only be used when an add-in board, not BMC, pulls-down SPIO4).
+	 */
+#define	SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP	0x00000600
+
+#define	SHARED_HW_CFG_LED_MODE_MASK			0x000f0000
+#define	SHARED_HW_CFG_LED_MODE_SHIFT			16
+#define	SHARED_HW_CFG_LED_MAC1				0x00000000
+#define	SHARED_HW_CFG_LED_PHY1				0x00010000
+#define	SHARED_HW_CFG_LED_PHY2				0x00020000
+#define	SHARED_HW_CFG_LED_PHY3				0x00030000
+#define	SHARED_HW_CFG_LED_MAC2				0x00040000
+#define	SHARED_HW_CFG_LED_PHY4				0x00050000
+#define	SHARED_HW_CFG_LED_PHY5				0x00060000
+#define	SHARED_HW_CFG_LED_PHY6				0x00070000
+#define	SHARED_HW_CFG_LED_MAC3				0x00080000
+#define	SHARED_HW_CFG_LED_PHY7				0x00090000
+#define	SHARED_HW_CFG_LED_PHY9				0x000a0000
+#define	SHARED_HW_CFG_LED_PHY11				0x000b0000
+#define	SHARED_HW_CFG_LED_MAC4				0x000c0000
+#define	SHARED_HW_CFG_LED_PHY8				0x000d0000
+
+#define	SHARED_HW_CFG_AN_ENABLE_MASK			0x3f000000
+#define	SHARED_HW_CFG_AN_ENABLE_SHIFT			24
+#define	SHARED_HW_CFG_AN_ENABLE_CL37			0x01000000
+#define	SHARED_HW_CFG_AN_ENABLE_CL73			0x02000000
+#define	SHARED_HW_CFG_AN_ENABLE_BAM			0x04000000
+#define	SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION	0x08000000
+#define	SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT	0x10000000
+#define	SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY		0x20000000
+
+	uint32_t config2;				/* 0x118 */
+	/* one time auto detect grace period (in sec) */
+#define	SHARED_HW_CFG_GRACE_PERIOD_MASK			0x000000ff
+#define	SHARED_HW_CFG_GRACE_PERIOD_SHIFT		0
+
+#define	SHARED_HW_CFG_PCIE_GEN2_ENABLED			0x00000100
+
+	/*
+	 * The default value for the core clock is 250MHz and it is
+	 * achieved by setting the clock change to 4.
+	 */
+#define	SHARED_HW_CFG_CLOCK_CHANGE_MASK			0x00000e00
+#define	SHARED_HW_CFG_CLOCK_CHANGE_SHIFT		9
+
+#define	SHARED_HW_CFG_SMBUS_TIMING_100KHZ		0x00000000
+#define	SHARED_HW_CFG_SMBUS_TIMING_400KHZ		0x00001000
+
+#define	SHARED_HW_CFG_HIDE_PORT1			0x00002000
+
+#define	SHARED_HW_CFG_WOL_CAPABLE_DISABLED		0x00000000
+#define	SHARED_HW_CFG_WOL_CAPABLE_ENABLED		0x00004000
+
+	/* Output low when PERST is asserted. */
+#define	SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED	0x00000000
+#define	SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED	0x00008000
+
+#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK	0x00070000
+#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT	16
+#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW		0x00000000
+#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB		0x00010000 /*    0dB */
+#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB	0x00020000 /* -3.5dB */
+#define	SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB	0x00030000 /* -6.0dB */
+
+	/*
+	 * The fan failure mechanism is usually related to the PHY type
+	 * since the power consumption of the board is determined by the PHY.
+	 * Currently, fan is required for most designs with SFX7101, BCM8727
+	 * and BCM8481. If a fan is not required for a board which uses one
+	 * of those PHYs, this field should be set to "Disabled". If a fan is
+	 * required for a different PHY type, this option should be set to
+	 * "Enabled".
+	 * The fan failure indication is expected on
+	 * SPIO5.
+	 */
+#define	SHARED_HW_CFG_FAN_FAILURE_MASK			0x00180000
+#define	SHARED_HW_CFG_FAN_FAILURE_SHIFT			19
+#define	SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE		0x00000000
+#define	SHARED_HW_CFG_FAN_FAILURE_DISABLED		0x00080000
+#define	SHARED_HW_CFG_FAN_FAILURE_ENABLED		0x00100000
+
+	/*  ASPM Power Management support */
+#define	SHARED_HW_CFG_ASPM_SUPPORT_MASK			0x00600000
+#define	SHARED_HW_CFG_ASPM_SUPPORT_SHIFT		21
+#define	SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED	0x00000000
+#define	SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED		0x00200000
+#define	SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED		0x00400000
+#define	SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED	0x00600000
+
+	/*
+	 * The value of PM_TL_IGNORE_REQS (bit0) in PCI register
+	 * tl_control_0 (register 0x2800).
+	 */
+#define	SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED		0x00000000
+#define	SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED		0x00800000
+
+
+	uint32_t power_dissipated;			/* 0x11c */
+#define	SHARED_HW_CFG_POWER_DIS_CMN_MASK		0xff000000
+#define	SHARED_HW_CFG_POWER_DIS_CMN_SHIFT		24
+
+#define	SHARED_HW_CFG_POWER_MGNT_SCALE_MASK		0x00ff0000
+#define	SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT		16
+#define	SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE		0x00000000
+#define	SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT		0x00010000
+#define	SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT		0x00020000
+#define	SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT		0x00030000
+
+	uint32_t ump_nc_si_config;			/* 0x120 */
+#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK		0x00000003
+#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT		0
+#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC		0x00000000
+#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY		0x00000001
+#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII		0x00000000
+#define	SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII		0x00000002
+
+#define	SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK		0x00000f00
+#define	SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT		8
+
+#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK	0x00ff0000
+#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT	16
+#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE	0x00000000
+#define	SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221	0x00010000
+
+	uint32_t board;					/* 0x124 */
+#define	SHARED_HW_CFG_BOARD_REV_MASK			0x00ff0000
+#define	SHARED_HW_CFG_BOARD_REV_SHIFT			16
+
+#define	SHARED_HW_CFG_BOARD_MAJOR_VER_MASK		0x0f000000
+#define	SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT		24
+
+#define	SHARED_HW_CFG_BOARD_MINOR_VER_MASK		0xf0000000
+#define	SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT		28
+
+	uint32_t reserved;				/* 0x128 */
+};
+
+/*
+ * Port HW configuration
+ */
+struct port_hw_cfg {			/* port 0: 0x12c  port 1: 0x2bc */
+	uint32_t pci_id;
+#define	PORT_HW_CFG_PCI_VENDOR_ID_MASK			0xffff0000
+#define	PORT_HW_CFG_PCI_DEVICE_ID_MASK			0x0000ffff
+
+	uint32_t pci_sub_id;
+#define	PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK		0xffff0000
+#define	PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK		0x0000ffff
+
+	uint32_t power_dissipated;
+#define	PORT_HW_CFG_POWER_DIS_D3_MASK			0xff000000
+#define	PORT_HW_CFG_POWER_DIS_D3_SHIFT			24
+#define	PORT_HW_CFG_POWER_DIS_D2_MASK			0x00ff0000
+#define	PORT_HW_CFG_POWER_DIS_D2_SHIFT			16
+#define	PORT_HW_CFG_POWER_DIS_D1_MASK			0x0000ff00
+#define	PORT_HW_CFG_POWER_DIS_D1_SHIFT			8
+#define	PORT_HW_CFG_POWER_DIS_D0_MASK			0x000000ff
+#define	PORT_HW_CFG_POWER_DIS_D0_SHIFT			0
+
+	uint32_t power_consumed;
+#define	PORT_HW_CFG_POWER_CONS_D3_MASK			0xff000000
+#define	PORT_HW_CFG_POWER_CONS_D3_SHIFT			24
+#define	PORT_HW_CFG_POWER_CONS_D2_MASK			0x00ff0000
+#define	PORT_HW_CFG_POWER_CONS_D2_SHIFT			16
+#define	PORT_HW_CFG_POWER_CONS_D1_MASK			0x0000ff00
+#define	PORT_HW_CFG_POWER_CONS_D1_SHIFT			8
+#define	PORT_HW_CFG_POWER_CONS_D0_MASK			0x000000ff
+#define	PORT_HW_CFG_POWER_CONS_D0_SHIFT			0
+
+	uint32_t mac_upper;
+#define	PORT_HW_CFG_UPPERMAC_MASK			0x0000ffff
+#define	PORT_HW_CFG_UPPERMAC_SHIFT			0
+	uint32_t mac_lower;
+
+	uint32_t iscsi_mac_upper;	/* Upper 16 bits are always zeroes */
+	uint32_t iscsi_mac_lower;
+
+	uint32_t rdma_mac_upper;	/* Upper 16 bits are always zeroes */
+	uint32_t rdma_mac_lower;
+
+	uint32_t serdes_config;
+#define	PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK	0x0000ffff
+#define	PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT	0
+
+#define	PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK	0xffff0000
+#define	PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT	16
+
+	uint32_t reserved0[16];				/* 0x158 */
+
+	/*
+	 * 4 times 16 bits for all 4 lanes. In case external PHY is present
+	 * (not direct mode), those values will not take effect on the 4 XGXS
+	 * lanes. For some external PHYs (such as 8706 and 8726) the values
+	 * will be used to configure the external PHY – in those cases, not
+	 * all 4 values are needed.
+	 */
+	uint16_t xgxs_config_rx[4];			/* 0x198 */
+	uint16_t xgxs_config_tx[4];			/* 0x1A0 */
+
+	uint32_t reserved1[64];				/* 0x1A8 */
+
+	uint32_t lane_config;
+#define	PORT_HW_CFG_LANE_SWAP_CFG_MASK			0x0000ffff
+#define	PORT_HW_CFG_LANE_SWAP_CFG_SHIFT			0
+#define	PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK		0x000000ff
+#define	PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT		0
+#define	PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK		0x0000ff00
+#define	PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT		8
+#define	PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK		0x0000c000
+#define	PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT		14
+	/* AN and forced */
+#define	PORT_HW_CFG_LANE_SWAP_CFG_01230123		0x00001b1b
+	/* forced only */
+#define	PORT_HW_CFG_LANE_SWAP_CFG_01233210		0x00001be4
+	/* forced only */
+#define	PORT_HW_CFG_LANE_SWAP_CFG_31203120		0x0000d8d8
+	/* forced only */
+#define	PORT_HW_CFG_LANE_SWAP_CFG_32103210		0x0000e4e4
+
+	uint32_t external_phy_config;
+#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK		0xff000000
+#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT		24
+#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT		0x00000000
+#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482		0x01000000
+#define	PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN	0xff000000
+
+#define	PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK		0x00ff0000
+#define	PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT		16
+
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK		0x0000ff00
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT		8
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT		0x00000000
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071		0x00000100
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072		0x00000200
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073		0x00000300
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705		0x00000400
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706		0x00000500
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726		0x00000600
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481		0x00000700
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101		0x00000800
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727		0x00000900
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC	0x00000a00
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823		0x00000b00
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE		0x0000fd00
+#define	PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN		0x0000ff00
+
+#define	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK		0x000000ff
+#define	PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT		0
+
+	uint32_t speed_capability_mask;
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK		0xffff0000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT		16
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL	0x00010000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF	0x00020000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF	0x00040000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL	0x00080000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_1G		0x00100000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G		0x00200000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_10G		0x00400000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_12G		0x00800000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G		0x01000000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_13G		0x02000000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_15G		0x04000000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_16G		0x08000000
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED	0xf0000000
+
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK		0x0000ffff
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT		0
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL	0x00000001
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF	0x00000002
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF	0x00000004
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL	0x00000008
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_1G		0x00000010
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G		0x00000020
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_10G		0x00000040
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_12G		0x00000080
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G		0x00000100
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_13G		0x00000200
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_15G		0x00000400
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_16G		0x00000800
+#define	PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED	0x0000f000
+
+	/* A place to hold the original MAC address as a backup. */
+	uint32_t backup_mac_upper;			/* 0x2B4 */
+	uint32_t backup_mac_lower;			/* 0x2B8 */
+};
+
+/*
+ * Shared Feature configuration
+ */
+struct shared_feat_cfg {				/* NVRAM Offset */
+	uint32_t config;				/* 0x450 */
+#define	SHARED_FEATURE_BMC_ECHO_MODE_EN			0x00000001
+
+	/*
+	 * Use the values from options 47 and 48 instead of the HW default
+	 * values.
+	 */
+#define	SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED	0x00000000
+#define	SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED	0x00000002
+
+#define	SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO		0x00000000
+#define	SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM		0x00000008
+
+#define	SHARED_FEAT_CFG_NCSI_ID_MASK			0x00000030
+#define	SHARED_FEAT_CFG_NCSI_ID_SHIFT			4
+
+	/*
+	 * Override the OTP back to single function mode. When using GPIO,
+	 * high means only SF, 0 is according to CLP configuration.
+	 */
+#define	SHARED_FEAT_CFG_FORCE_SF_MODE_MASK		0x00000700
+#define	SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT		8
+#define	SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED	0x00000000
+#define	SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF		0x00000100
+#define	SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4		0x00000200
+
+	/*
+	 * The interval in seconds between sending LLDP packets. Set to zero
+	 * to disable the feature.
+	 */
+#define	SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK		0x00FF0000
+#define	SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT	16
+
+	/* The assigned device type ID for LLDP usage. */
+#define	SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK	0xFF000000
+#define	SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT	24
+};
+
+/*
+ * Port Feature configuration
+ */
+struct port_feat_cfg {			/* port 0: 0x454  port 1: 0x4c8 */
+	uint32_t config;
+#define	PORT_FEATURE_BAR1_SIZE_MASK			0x0000000f
+#define	PORT_FEATURE_BAR1_SIZE_SHIFT			0
+#define	PORT_FEATURE_BAR1_SIZE_DISABLED			0x00000000
+#define	PORT_FEATURE_BAR1_SIZE_64K			0x00000001
+#define	PORT_FEATURE_BAR1_SIZE_128K			0x00000002
+#define	PORT_FEATURE_BAR1_SIZE_256K			0x00000003
+#define	PORT_FEATURE_BAR1_SIZE_512K			0x00000004
+#define	PORT_FEATURE_BAR1_SIZE_1M			0x00000005
+#define	PORT_FEATURE_BAR1_SIZE_2M			0x00000006
+#define	PORT_FEATURE_BAR1_SIZE_4M			0x00000007
+#define	PORT_FEATURE_BAR1_SIZE_8M			0x00000008
+#define	PORT_FEATURE_BAR1_SIZE_16M			0x00000009
+#define	PORT_FEATURE_BAR1_SIZE_32M			0x0000000a
+#define	PORT_FEATURE_BAR1_SIZE_64M			0x0000000b
+#define	PORT_FEATURE_BAR1_SIZE_128M			0x0000000c
+#define	PORT_FEATURE_BAR1_SIZE_256M			0x0000000d
+#define	PORT_FEATURE_BAR1_SIZE_512M			0x0000000e
+#define	PORT_FEATURE_BAR1_SIZE_1G			0x0000000f
+#define	PORT_FEATURE_BAR2_SIZE_MASK			0x000000f0
+#define	PORT_FEATURE_BAR2_SIZE_SHIFT			4
+#define	PORT_FEATURE_BAR2_SIZE_DISABLED			0x00000000
+#define	PORT_FEATURE_BAR2_SIZE_64K			0x00000010
+#define	PORT_FEATURE_BAR2_SIZE_128K			0x00000020
+#define	PORT_FEATURE_BAR2_SIZE_256K			0x00000030
+#define	PORT_FEATURE_BAR2_SIZE_512K			0x00000040
+#define	PORT_FEATURE_BAR2_SIZE_1M			0x00000050
+#define	PORT_FEATURE_BAR2_SIZE_2M			0x00000060
+#define	PORT_FEATURE_BAR2_SIZE_4M			0x00000070
+#define	PORT_FEATURE_BAR2_SIZE_8M			0x00000080
+#define	PORT_FEATURE_BAR2_SIZE_16M			0x00000090
+#define	PORT_FEATURE_BAR2_SIZE_32M			0x000000a0
+#define	PORT_FEATURE_BAR2_SIZE_64M			0x000000b0
+#define	PORT_FEATURE_BAR2_SIZE_128M			0x000000c0
+#define	PORT_FEATURE_BAR2_SIZE_256M			0x000000d0
+#define	PORT_FEATURE_BAR2_SIZE_512M			0x000000e0
+#define	PORT_FEATURE_BAR2_SIZE_1G			0x000000f0
+#define	PORT_FEATURE_EN_SIZE_MASK			0x07000000
+#define	PORT_FEATURE_EN_SIZE_SHIFT			24
+#define	PORT_FEATURE_WOL_ENABLED			0x01000000
+#define	PORT_FEATURE_MBA_ENABLED			0x02000000
+#define	PORT_FEATURE_MFW_ENABLED			0x04000000
+
+	/* Advertise expansion ROM even if MBA is disabled. */
+#define	PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED	0x00000000
+#define	PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED		0x08000000
+
+	/* Reserved bits: 28-29 */
+	/*
+	 * Check the optic vendor via i2c against a list of approved modules
+	 * in a separate nvram image.
+	 */
+#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK		0xE0000000
+#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT		29
+#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT	0x00000000
+#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER	0x20000000
+#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG	0x40000000
+#define	PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN	0x60000000
+
+	uint32_t wol_config;
+	/* Default is used when driver sets to "auto" mode. */
+#define	PORT_FEATURE_WOL_DEFAULT_MASK			0x00000003
+#define	PORT_FEATURE_WOL_DEFAULT_SHIFT			0
+#define	PORT_FEATURE_WOL_DEFAULT_DISABLE		0x00000000
+#define	PORT_FEATURE_WOL_DEFAULT_MAGIC			0x00000001
+#define	PORT_FEATURE_WOL_DEFAULT_ACPI			0x00000002
+#define	PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI		0x00000003
+#define	PORT_FEATURE_WOL_RES_PAUSE_CAP			0x00000004
+#define	PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP		0x00000008
+#define	PORT_FEATURE_WOL_ACPI_UPON_MGMT			0x00000010
+
+	uint32_t mba_config;
+#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK		0x00000007
+#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT		0
+#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE		0x00000000
+#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL		0x00000001
+#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP		0x00000002
+#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB		0x00000003
+#define	PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE		0x00000007
+#define	PORT_FEATURE_MBA_RES_PAUSE_CAP			0x00000100
+#define	PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP		0x00000200
+#define	PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE		0x00000400
+#define	PORT_FEATURE_MBA_HOTKEY_CTRL_S			0x00000000
+#define	PORT_FEATURE_MBA_HOTKEY_CTRL_B			0x00000800
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK		0x000ff000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT		12
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED		0x00000000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_2K		0x00001000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_4K		0x00002000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_8K		0x00003000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_16K		0x00004000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_32K		0x00005000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_64K		0x00006000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_128K		0x00007000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_256K		0x00008000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_512K		0x00009000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_1M		0x0000a000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_2M		0x0000b000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_4M		0x0000c000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_8M		0x0000d000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_16M		0x0000e000
+#define	PORT_FEATURE_MBA_EXP_ROM_SIZE_32M		0x0000f000
+#define	PORT_FEATURE_MBA_MSG_TIMEOUT_MASK		0x00f00000
+#define	PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT		20
+#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK		0x03000000
+#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT		24
+#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO		0x00000000
+#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS		0x01000000
+#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H		0x02000000
+#define	PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H		0x03000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_MASK		0x3c000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_SHIFT		26
+#define	PORT_FEATURE_MBA_LINK_SPEED_AUTO		0x00000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_10HD		0x04000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_10FD		0x08000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_100HD		0x0c000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_100FD		0x10000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_1GBPS		0x14000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS		0x18000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4		0x1c000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4		0x20000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR		0x24000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_12GBPS		0x28000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS		0x2c000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_13GBPS		0x30000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_15GBPS		0x34000000
+#define	PORT_FEATURE_MBA_LINK_SPEED_16GBPS		0x38000000
+
+	uint32_t bmc_config;
+#define	PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT		0x00000000
+#define	PORT_FEATURE_BMC_LINK_OVERRIDE_EN		0x00000001
+
+	uint32_t mba_vlan_cfg;
+#define	PORT_FEATURE_MBA_VLAN_TAG_MASK			0x0000ffff
+#define	PORT_FEATURE_MBA_VLAN_TAG_SHIFT			0
+#define	PORT_FEATURE_MBA_VLAN_EN			0x00010000
+
+	uint32_t resource_cfg;
+#define	PORT_FEATURE_RESOURCE_CFG_VALID			0x00000001
+#define	PORT_FEATURE_RESOURCE_CFG_DIAG			0x00000002
+#define	PORT_FEATURE_RESOURCE_CFG_L2			0x00000004
+#define	PORT_FEATURE_RESOURCE_CFG_ISCSI			0x00000008
+#define	PORT_FEATURE_RESOURCE_CFG_RDMA			0x00000010
+
+	uint32_t smbus_config;
+	/* Obsolete */
+#define	PORT_FEATURE_SMBUS_EN				0x00000001
+#define	PORT_FEATURE_SMBUS_ADDR_MASK			0x000000fe
+#define	PORT_FEATURE_SMBUS_ADDR_SHIFT			1
+
+	uint32_t reserved1;
+
+	uint32_t link_config;    /* Used as HW defaults for the driver */
+#define	PORT_FEATURE_CONNECTED_SWITCH_MASK		0x03000000
+#define	PORT_FEATURE_CONNECTED_SWITCH_SHIFT		24
+	/* (forced) low speed switch (< 10G) */
+#define	PORT_FEATURE_CON_SWITCH_1G_SWITCH		0x00000000
+	/* (forced) high speed switch (>= 10G) */
+#define	PORT_FEATURE_CON_SWITCH_10G_SWITCH		0x01000000
+#define	PORT_FEATURE_CON_SWITCH_AUTO_DETECT		0x02000000
+#define	PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT		0x03000000
+
+#define	PORT_FEATURE_LINK_SPEED_MASK			0x000f0000
+#define	PORT_FEATURE_LINK_SPEED_SHIFT			16
+#define	PORT_FEATURE_LINK_SPEED_AUTO			0x00000000
+#define	PORT_FEATURE_LINK_SPEED_10M_FULL		0x00010000
+#define	PORT_FEATURE_LINK_SPEED_10M_HALF		0x00020000
+#define	PORT_FEATURE_LINK_SPEED_100M_HALF		0x00030000
+#define	PORT_FEATURE_LINK_SPEED_100M_FULL		0x00040000
+#define	PORT_FEATURE_LINK_SPEED_1G			0x00050000
+#define	PORT_FEATURE_LINK_SPEED_2_5G			0x00060000
+#define	PORT_FEATURE_LINK_SPEED_10G_CX4			0x00070000
+#define	PORT_FEATURE_LINK_SPEED_10G_KX4			0x00080000
+#define	PORT_FEATURE_LINK_SPEED_10G_KR			0x00090000
+#define	PORT_FEATURE_LINK_SPEED_12G			0x000a0000
+#define	PORT_FEATURE_LINK_SPEED_12_5G			0x000b0000
+#define	PORT_FEATURE_LINK_SPEED_13G			0x000c0000
+#define	PORT_FEATURE_LINK_SPEED_15G			0x000d0000
+#define	PORT_FEATURE_LINK_SPEED_16G			0x000e0000
+
+#define	PORT_FEATURE_FLOW_CONTROL_MASK			0x00000700
+#define	PORT_FEATURE_FLOW_CONTROL_SHIFT			8
+#define	PORT_FEATURE_FLOW_CONTROL_AUTO			0x00000000
+#define	PORT_FEATURE_FLOW_CONTROL_TX			0x00000100
+#define	PORT_FEATURE_FLOW_CONTROL_RX			0x00000200
+#define	PORT_FEATURE_FLOW_CONTROL_BOTH			0x00000300
+#define	PORT_FEATURE_FLOW_CONTROL_NONE			0x00000400
+
+	/*
+	 * The default for MCP link configuration,
+	 * uses the same defines as link_config.
+	 */
+	uint32_t mfw_wol_link_cfg;
+
+	uint32_t reserved[19];
+};
+
+/*
+ * Device Information
+ */
+struct shm_dev_info {						/* size */
+	uint32_t    bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
+
+	struct shared_hw_cfg	shared_hw_config;		/* 40 */
+
+	struct port_hw_cfg	port_hw_config[PORT_MAX];	/* 400*2=800 */
+
+	struct shared_feat_cfg	shared_feature_config; 		/* 4 */
+
+	struct port_feat_cfg	port_feature_config[PORT_MAX];	/* 116*2=232 */
+};
+
+#define	FUNC_0				0
+#define	FUNC_1				1
+#define	FUNC_2				2
+#define	FUNC_3				3
+#define	FUNC_4				4
+#define	FUNC_5				5
+#define	FUNC_6				6
+#define	FUNC_7				7
+#define	E1_FUNC_MAX			2
+#define	E1H_FUNC_MAX			8
+
+#define	VN_0				0
+#define	VN_1				1
+#define	VN_2				2
+#define	VN_3				3
+#define	E1VN_MAX			1
+#define	E1HVN_MAX			4
+
+/*
+ * This value (in milliseconds) determines the frequency of the driver
+ * issuing the PULSE message code.  The firmware monitors this periodic
+ * pulse to determine when to switch to an OS-absent mode.
+ */
+#define	DRV_PULSE_PERIOD_MS		250
+
+/*
+ * This value (in milliseconds) determines how long the driver should
+ * wait for an acknowledgement from the firmware before timing out.  Once
+ * the firmware has timed out, the driver will assume there is no firmware
+ * running and there won't be any firmware-driver synchronization during a
+ * driver reset.
+ */
+#define	FW_ACK_TIME_OUT_MS		5000
+
+#define	FW_ACK_POLL_TIME_MS		1
+
+#define	FW_ACK_NUM_OF_POLL		(FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
+
+/* LED Blink rate that will achieve ~15.9Hz. */
+#define	LED_BLINK_RATE_VAL		480
+
+/*
+ * Driver <-> FW Mailbox
+ */
+struct drv_port_mb {
+	uint32_t link_status;
+	/* Driver should update this field on any link change event. */
+
+#define	LINK_STATUS_LINK_FLAG_MASK			0x00000001
+#define	LINK_STATUS_LINK_UP				0x00000001
+#define	LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001E
+#define	LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE	(0 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_10THD		(1 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_10TFD		(2 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_100TXHD		(3 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_100T4		(4 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_100TXFD		(5 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_1000THD		(6 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(7 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_1000XFD		(7 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_2500THD		(8 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_2500TFD		(9 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_2500XFD		(9 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_10GTFD		(10 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_10GXFD		(10 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_12GTFD		(11 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_12GXFD		(11 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD		(12 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD		(12 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_13GTFD		(13 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_13GXFD		(13 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_15GTFD		(14 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_15GXFD		(14 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_16GTFD		(15 << 1)
+#define	LINK_STATUS_SPEED_AND_DUPLEX_16GXFD		(15 << 1)
+
+#define	LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK		0x00000020
+#define	LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
+
+#define	LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
+#define	LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK	0x00000080
+#define	LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
+
+#define	LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
+#define	LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
+#define	LINK_STATUS_LINK_PARTNER_100T4_CAPABLE		0x00000800
+#define	LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE	0x00001000
+#define	LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE	0x00002000
+#define	LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE		0x00004000
+#define	LINK_STATUS_LINK_PARTNER_10THD_CAPABLE		0x00008000
+
+#define	LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK		0x00010000
+#define	LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00010000
+
+#define	LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK		0x00020000
+#define	LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00020000
+
+#define	LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
+#define	LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0 << 18)
+#define	LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1 << 18)
+#define	LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2 << 18)
+#define	LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3 << 18)
+
+#define	LINK_STATUS_SERDES_LINK				0x00100000
+
+#define	LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE	0x00200000
+#define	LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE	0x00400000
+#define	LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE		0x00800000
+#define	LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE		0x01000000
+#define	LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE	0x02000000
+#define	LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE		0x04000000
+#define	LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE		0x08000000
+#define	LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE		0x10000000
+
+	uint32_t port_stx;
+
+	uint32_t stat_nig_timer;
+
+	/* MCP firmware does not use this field. */
+	uint32_t ext_phy_fw_version;
+};
+
+struct drv_func_mb {
+	uint32_t drv_mb_header;
+#define	DRV_MSG_CODE_MASK				0xffff0000
+#define	DRV_MSG_CODE_LOAD_REQ				0x10000000
+#define	DRV_MSG_CODE_LOAD_DONE				0x11000000
+#define	DRV_MSG_CODE_UNLOAD_REQ_WOL_EN			0x20000000
+#define	DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS			0x20010000
+#define	DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP			0x20020000
+#define	DRV_MSG_CODE_UNLOAD_DONE			0x21000000
+#define	DRV_MSG_CODE_DCC_OK				0x30000000
+#define	DRV_MSG_CODE_DCC_FAILURE			0x31000000
+#define	DRV_MSG_CODE_DIAG_ENTER_REQ			0x50000000
+#define	DRV_MSG_CODE_DIAG_EXIT_REQ			0x60000000
+#define	DRV_MSG_CODE_VALIDATE_KEY			0x70000000
+#define	DRV_MSG_CODE_GET_CURR_KEY			0x80000000
+#define	DRV_MSG_CODE_GET_UPGRADE_KEY			0x81000000
+#define	DRV_MSG_CODE_GET_MANUF_KEY			0x82000000
+#define	DRV_MSG_CODE_LOAD_L2B_PRAM			0x90000000
+	/*
+	 * The optic module verification commands requris bootcode
+	 * v5.0.6 or later.
+	 */
+#define	DRV_MSG_CODE_VRFY_OPT_MDL			0xa0000000
+#define	REQ_BC_VER_4_VRFY_OPT_MDL			0x00050006
+
+#define	BIOS_MSG_CODE_LIC_CHALLENGE			0xff010000
+#define	BIOS_MSG_CODE_LIC_RESPONSE			0xff020000
+#define	BIOS_MSG_CODE_VIRT_MAC_PRIM			0xff030000
+#define	BIOS_MSG_CODE_VIRT_MAC_ISCSI			0xff040000
+
+#define	DRV_MSG_SEQ_NUMBER_MASK				0x0000ffff
+
+	uint32_t drv_mb_param;
+
+	uint32_t fw_mb_header;
+#define	FW_MSG_CODE_MASK				0xffff0000
+#define	FW_MSG_CODE_DRV_LOAD_COMMON			0x10100000
+#define	FW_MSG_CODE_DRV_LOAD_PORT			0x10110000
+#define	FW_MSG_CODE_DRV_LOAD_FUNCTION			0x10120000
+#define	FW_MSG_CODE_DRV_LOAD_REFUSED			0x10200000
+#define	FW_MSG_CODE_DRV_LOAD_DONE			0x11100000
+#define	FW_MSG_CODE_DRV_UNLOAD_COMMON			0x20100000
+#define	FW_MSG_CODE_DRV_UNLOAD_PORT			0x20110000
+#define	FW_MSG_CODE_DRV_UNLOAD_FUNCTION			0x20120000
+#define	FW_MSG_CODE_DRV_UNLOAD_DONE			0x21100000
+#define	FW_MSG_CODE_DCC_DONE				0x30100000
+#define	FW_MSG_CODE_DIAG_ENTER_DONE			0x50100000
+#define	FW_MSG_CODE_DIAG_REFUSE				0x50200000
+#define	FW_MSG_CODE_DIAG_EXIT_DONE			0x60100000
+#define	FW_MSG_CODE_VALIDATE_KEY_SUCCESS		0x70100000
+#define	FW_MSG_CODE_VALIDATE_KEY_FAILURE		0x70200000
+#define	FW_MSG_CODE_GET_KEY_DONE			0x80100000
+#define	FW_MSG_CODE_NO_KEY				0x80f00000
+#define	FW_MSG_CODE_LIC_INFO_NOT_READY			0x80f80000
+#define	FW_MSG_CODE_L2B_PRAM_LOADED			0x90100000
+#define	FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE		0x90210000
+#define	FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE		0x90220000
+#define	FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE		0x90230000
+#define	FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE		0x90240000
+#define	FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS		0xa0100000
+#define	FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG		0xa0200000
+#define	FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED		0xa0300000
+
+#define	FW_MSG_CODE_LIC_CHALLENGE			0xff010000
+#define	FW_MSG_CODE_LIC_RESPONSE			0xff020000
+#define	FW_MSG_CODE_VIRT_MAC_PRIM			0xff030000
+#define	FW_MSG_CODE_VIRT_MAC_ISCSI			0xff040000
+
+#define	FW_MSG_SEQ_NUMBER_MASK				0x0000ffff
+
+	uint32_t fw_mb_param;
+
+	uint32_t drv_pulse_mb;
+#define	DRV_PULSE_SEQ_MASK				0x00007fff
+#define	DRV_PULSE_SYSTEM_TIME_MASK			0xffff0000
+	/*
+	 * The system time is in the format of
+	 * (year-2001)*12*32 + month*32 + day.
+	 */
+#define	DRV_PULSE_ALWAYS_ALIVE				0x00008000
+	/*
+	 * Indicate to the firmware not to go into the
+	 * OS-absent when it is not getting driver pulse.
+	 * This is used for debugging as well for PXE(MBA).
+	 */
+
+	uint32_t mcp_pulse_mb;
+#define	MCP_PULSE_SEQ_MASK				0x00007fff
+#define	MCP_PULSE_ALWAYS_ALIVE				0x00008000
+	/*
+	 * Indicates to the driver not to assert due to lack
+	 * of MCP response.
+	 */
+#define	MCP_EVENT_MASK					0xffff0000
+#define	MCP_EVENT_OTHER_DRIVER_RESET_REQ		0x00010000
+
+	uint32_t iscsi_boot_signature;
+	uint32_t iscsi_boot_block_offset;
+
+	uint32_t drv_status;
+#define	DRV_STATUS_PMF					0x00000001
+
+#define	DRV_STATUS_DCC_EVENT_MASK			0x0000ff00
+#define	DRV_STATUS_DCC_DISABLE_ENABLE_PF		0x00000100
+#define	DRV_STATUS_DCC_BANDWIDTH_ALLOCATION		0x00000200
+#define	DRV_STATUS_DCC_CHANGE_MAC_ADDRESS		0x00000400
+#define	DRV_STATUS_DCC_RESERVED1			0x00000800
+#define	DRV_STATUS_DCC_SET_PROTOCOL			0x00001000
+#define	DRV_STATUS_DCC_SET_PRIORITY			0x00002000
+
+	uint32_t virt_mac_upper;
+#define	VIRT_MAC_SIGN_MASK				0xffff0000
+#define	VIRT_MAC_SIGNATURE				0x564d0000
+	uint32_t virt_mac_lower;
+};
+
+/*
+ * Management firmware state
+ */
+/* Allocate 440 bytes for management firmware. */
+#define	MGMTFW_STATE_WORD_SIZE				110
+
+struct mgmtfw_state {
+	uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
+};
+
+/*
+ * Multi-Function configuration
+ */
+struct shared_mf_cfg {
+	uint32_t clp_mb;
+#define	SHARED_MF_CLP_SET_DEFAULT			0x00000000
+	/* set by CLP */
+#define	SHARED_MF_CLP_EXIT				0x00000001
+	/* set by MCP */
+#define	SHARED_MF_CLP_EXIT_DONE				0x00010000
+};
+
+struct port_mf_cfg {
+	uint32_t dynamic_cfg;			/* device control channel */
+#define	PORT_MF_CFG_E1HOV_TAG_MASK		0x0000ffff
+#define	PORT_MF_CFG_E1HOV_TAG_SHIFT		0
+#define	PORT_MF_CFG_E1HOV_TAG_DEFAULT		PORT_MF_CFG_E1HOV_TAG_MASK
+
+	uint32_t reserved[3];
+};
+
+struct func_mf_cfg {
+	uint32_t config;
+	/* E/R/I/D */
+	/* function 0 of each port cannot be hidden. */
+#define	FUNC_MF_CFG_FUNC_HIDE				0x00000001
+
+#define	FUNC_MF_CFG_PROTOCOL_MASK			0x00000007
+#define	FUNC_MF_CFG_PROTOCOL_ETHERNET			0x00000002
+#define	FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA		0x00000004
+#define	FUNC_MF_CFG_PROTOCOL_ISCSI			0x00000006
+#define	FUNC_MF_CFG_PROTOCOL_DEFAULT					\
+	FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
+
+#define	FUNC_MF_CFG_FUNC_DISABLED			0x00000008
+
+	/* PRI */
+	/* 0 - low priority, 3 - high priority */
+#define	FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK		0x00000300
+#define	FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT		8
+#define	FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT		0x00000000
+
+	/* MINBW, MAXBW */
+	/* value range - 0..100, increments in 100Mbps */
+#define	FUNC_MF_CFG_MIN_BW_MASK				0x00ff0000
+#define	FUNC_MF_CFG_MIN_BW_SHIFT			16
+#define	FUNC_MF_CFG_MIN_BW_DEFAULT			0x00000000
+#define	FUNC_MF_CFG_MAX_BW_MASK				0xff000000
+#define	FUNC_MF_CFG_MAX_BW_SHIFT			24
+#define	FUNC_MF_CFG_MAX_BW_DEFAULT			0x64000000
+
+	uint32_t mac_upper;				/* MAC */
+#define	FUNC_MF_CFG_UPPERMAC_MASK			0x0000ffff
+#define	FUNC_MF_CFG_UPPERMAC_SHIFT			0
+#define	FUNC_MF_CFG_UPPERMAC_DEFAULT		FUNC_MF_CFG_UPPERMAC_MASK
+	uint32_t mac_lower;
+#define	FUNC_MF_CFG_LOWERMAC_DEFAULT			0xffffffff
+
+	uint32_t e1hov_tag;				/* VNI */
+#define	FUNC_MF_CFG_E1HOV_TAG_MASK			0x0000ffff
+#define	FUNC_MF_CFG_E1HOV_TAG_SHIFT			0
+#define	FUNC_MF_CFG_E1HOV_TAG_DEFAULT		FUNC_MF_CFG_E1HOV_TAG_MASK
+
+	uint32_t reserved[2];
+};
+
+struct mf_cfg {
+	struct shared_mf_cfg	shared_mf_config;
+	struct port_mf_cfg	port_mf_config[PORT_MAX];
+	struct func_mf_cfg	func_mf_config[E1H_FUNC_MAX];
+};
+
+/*
+ * Shared Memory Region
+ */
+struct shmem_region {				/*   SharedMem Offset (size) */
+	uint32_t		validity_map[PORT_MAX];	/* 0x0 (4*2 = 0x8) */
+#define	SHR_MEM_FORMAT_REV_ID				('A' << 24)
+#define	SHR_MEM_FORMAT_REV_MASK				0xff000000
+	/* validity bits */
+#define	SHR_MEM_VALIDITY_PCI_CFG			0x00100000
+#define	SHR_MEM_VALIDITY_MB				0x00200000
+#define	SHR_MEM_VALIDITY_DEV_INFO			0x00400000
+#define	SHR_MEM_VALIDITY_RESERVED			0x00000007
+	/* One licensing bit should be set */
+#define	SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK		0x00000038
+#define	SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT	0x00000008
+#define	SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT	0x00000010
+#define	SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT		0x00000020
+	/* Active MFW */
+#define	SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN		0x00000000
+#define	SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI		0x00000040
+#define	SHR_MEM_VALIDITY_ACTIVE_MFW_UMP			0x00000080
+#define	SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI		0x000000c0
+#define	SHR_MEM_VALIDITY_ACTIVE_MFW_NONE		0x000001c0
+#define	SHR_MEM_VALIDITY_ACTIVE_MFW_MASK		0x000001c0
+
+	struct shm_dev_info	dev_info;		/* 0x8     (0x438) */
+
+	struct license_key	drv_lic_key[PORT_MAX];	/* 0x440 (52*2=0x68) */
+
+	/* FW information (for internal FW use) */
+	uint32_t		fw_info_fio_offset;	/* 0x4a8       (0x4) */
+	struct mgmtfw_state	mgmtfw_state;		/* 0x4ac     (0x1b8) */
+
+	struct drv_port_mb	port_mb[PORT_MAX];	/* 0x664 (16*2=0x20) */
+#if !defined(b710) /* BXE_UPSTREAM */
+	struct drv_func_mb	func_mb[E1H_FUNC_MAX];
+#else
+	struct drv_func_mb	func_mb[E1_FUNC_MAX];	/* 0x684 (44*2=0x58) */
+#endif
+
+#if !defined(b710) /* BXE_UPSTREAM */
+	struct mf_cfg		mf_cfg;
+#endif
+};							/* 0x6dc */
+
+struct shmem2_region {
+	uint32_t		size;
+
+	uint32_t		dcc_support;
+#define	SHMEM_DCC_SUPPORT_NONE				0x00000000
+#define	SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV		0x00000001
+#define	SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV	0x00000004
+#define	SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV	0x00000008
+#define	SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV		0x00000040
+#define	SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV		0x00000080
+#define	SHMEM_DCC_SUPPORT_DEFAULT			SHMEM_DCC_SUPPORT_NONE
+};
+
+struct emac_stats {
+	uint32_t	rx_stat_ifhcinoctets;
+	uint32_t	rx_stat_ifhcinbadoctets;
+	uint32_t	rx_stat_etherstatsfragments;
+	uint32_t	rx_stat_ifhcinucastpkts;
+	uint32_t	rx_stat_ifhcinmulticastpkts;
+	uint32_t	rx_stat_ifhcinbroadcastpkts;
+	uint32_t	rx_stat_dot3statsfcserrors;
+	uint32_t	rx_stat_dot3statsalignmenterrors;
+	uint32_t	rx_stat_dot3statscarriersenseerrors;
+	uint32_t	rx_stat_xonpauseframesreceived;
+	uint32_t	rx_stat_xoffpauseframesreceived;
+	uint32_t	rx_stat_maccontrolframesreceived;
+	uint32_t	rx_stat_xoffstateentered;
+	uint32_t	rx_stat_dot3statsframestoolong;
+	uint32_t	rx_stat_etherstatsjabbers;
+	uint32_t	rx_stat_etherstatsundersizepkts;
+	uint32_t	rx_stat_etherstatspkts64octets;
+	uint32_t	rx_stat_etherstatspkts65octetsto127octets;
+	uint32_t	rx_stat_etherstatspkts128octetsto255octets;
+	uint32_t	rx_stat_etherstatspkts256octetsto511octets;
+	uint32_t	rx_stat_etherstatspkts512octetsto1023octets;
+	uint32_t	rx_stat_etherstatspkts1024octetsto1522octets;
+	uint32_t	rx_stat_etherstatspktsover1522octets;
+
+	uint32_t	rx_stat_falsecarriererrors;
+
+	uint32_t	tx_stat_ifhcoutoctets;
+	uint32_t	tx_stat_ifhcoutbadoctets;
+	uint32_t	tx_stat_etherstatscollisions;
+	uint32_t	tx_stat_outxonsent;
+	uint32_t	tx_stat_outxoffsent;
+	uint32_t	tx_stat_flowcontroldone;
+	uint32_t	tx_stat_dot3statssinglecollisionframes;
+	uint32_t	tx_stat_dot3statsmultiplecollisionframes;
+	uint32_t	tx_stat_dot3statsdeferredtransmissions;
+	uint32_t	tx_stat_dot3statsexcessivecollisions;
+	uint32_t	tx_stat_dot3statslatecollisions;
+	uint32_t	tx_stat_ifhcoutucastpkts;
+	uint32_t	tx_stat_ifhcoutmulticastpkts;
+	uint32_t	tx_stat_ifhcoutbroadcastpkts;
+	uint32_t	tx_stat_etherstatspkts64octets;
+	uint32_t	tx_stat_etherstatspkts65octetsto127octets;
+	uint32_t	tx_stat_etherstatspkts128octetsto255octets;
+	uint32_t	tx_stat_etherstatspkts256octetsto511octets;
+	uint32_t	tx_stat_etherstatspkts512octetsto1023octets;
+	uint32_t	tx_stat_etherstatspkts1024octetsto1522octets;
+	uint32_t	tx_stat_etherstatspktsover1522octets;
+	uint32_t	tx_stat_dot3statsinternalmactransmiterrors;
+};
+
+struct bmac_stats {
+	uint32_t	tx_stat_gtpkt_lo;
+	uint32_t	tx_stat_gtpkt_hi;
+	uint32_t	tx_stat_gtxpf_lo;
+	uint32_t	tx_stat_gtxpf_hi;
+	uint32_t	tx_stat_gtfcs_lo;
+	uint32_t	tx_stat_gtfcs_hi;
+	uint32_t	tx_stat_gtmca_lo;
+	uint32_t	tx_stat_gtmca_hi;
+	uint32_t	tx_stat_gtbca_lo;
+	uint32_t	tx_stat_gtbca_hi;
+	uint32_t	tx_stat_gtfrg_lo;
+	uint32_t	tx_stat_gtfrg_hi;
+	uint32_t	tx_stat_gtovr_lo;
+	uint32_t	tx_stat_gtovr_hi;
+	uint32_t	tx_stat_gt64_lo;
+	uint32_t	tx_stat_gt64_hi;
+	uint32_t	tx_stat_gt127_lo;
+	uint32_t	tx_stat_gt127_hi;
+	uint32_t	tx_stat_gt255_lo;
+	uint32_t	tx_stat_gt255_hi;
+	uint32_t	tx_stat_gt511_lo;
+	uint32_t	tx_stat_gt511_hi;
+	uint32_t	tx_stat_gt1023_lo;
+	uint32_t	tx_stat_gt1023_hi;
+	uint32_t	tx_stat_gt1518_lo;
+	uint32_t	tx_stat_gt1518_hi;
+	uint32_t	tx_stat_gt2047_lo;
+	uint32_t	tx_stat_gt2047_hi;
+	uint32_t	tx_stat_gt4095_lo;
+	uint32_t	tx_stat_gt4095_hi;
+	uint32_t	tx_stat_gt9216_lo;
+	uint32_t	tx_stat_gt9216_hi;
+	uint32_t	tx_stat_gt16383_lo;
+	uint32_t	tx_stat_gt16383_hi;
+	uint32_t	tx_stat_gtmax_lo;
+	uint32_t	tx_stat_gtmax_hi;
+	uint32_t	tx_stat_gtufl_lo;
+	uint32_t	tx_stat_gtufl_hi;
+	uint32_t	tx_stat_gterr_lo;
+	uint32_t	tx_stat_gterr_hi;
+	uint32_t	tx_stat_gtbyt_lo;
+	uint32_t	tx_stat_gtbyt_hi;
+
+	uint32_t	rx_stat_gr64_lo;
+	uint32_t	rx_stat_gr64_hi;
+	uint32_t	rx_stat_gr127_lo;
+	uint32_t	rx_stat_gr127_hi;
+	uint32_t	rx_stat_gr255_lo;
+	uint32_t	rx_stat_gr255_hi;
+	uint32_t	rx_stat_gr511_lo;
+	uint32_t	rx_stat_gr511_hi;
+	uint32_t	rx_stat_gr1023_lo;
+	uint32_t	rx_stat_gr1023_hi;
+	uint32_t	rx_stat_gr1518_lo;
+	uint32_t	rx_stat_gr1518_hi;
+	uint32_t	rx_stat_gr2047_lo;
+	uint32_t	rx_stat_gr2047_hi;
+	uint32_t	rx_stat_gr4095_lo;
+	uint32_t	rx_stat_gr4095_hi;
+	uint32_t	rx_stat_gr9216_lo;
+	uint32_t	rx_stat_gr9216_hi;
+	uint32_t	rx_stat_gr16383_lo;
+	uint32_t	rx_stat_gr16383_hi;
+	uint32_t	rx_stat_grmax_lo;
+	uint32_t	rx_stat_grmax_hi;
+	uint32_t	rx_stat_grpkt_lo;
+	uint32_t	rx_stat_grpkt_hi;
+	uint32_t	rx_stat_grfcs_lo;
+	uint32_t	rx_stat_grfcs_hi;
+	uint32_t	rx_stat_grmca_lo;
+	uint32_t	rx_stat_grmca_hi;
+	uint32_t	rx_stat_grbca_lo;
+	uint32_t	rx_stat_grbca_hi;
+	uint32_t	rx_stat_grxcf_lo;
+	uint32_t	rx_stat_grxcf_hi;
+	uint32_t	rx_stat_grxpf_lo;
+	uint32_t	rx_stat_grxpf_hi;
+	uint32_t	rx_stat_grxuo_lo;
+	uint32_t	rx_stat_grxuo_hi;
+	uint32_t	rx_stat_grjbr_lo;
+	uint32_t	rx_stat_grjbr_hi;
+	uint32_t	rx_stat_grovr_lo;
+	uint32_t	rx_stat_grovr_hi;
+	uint32_t	rx_stat_grflr_lo;
+	uint32_t	rx_stat_grflr_hi;
+	uint32_t	rx_stat_grmeg_lo;
+	uint32_t	rx_stat_grmeg_hi;
+	uint32_t	rx_stat_grmeb_lo;
+	uint32_t	rx_stat_grmeb_hi;
+	uint32_t	rx_stat_grbyt_lo;
+	uint32_t	rx_stat_grbyt_hi;
+	uint32_t	rx_stat_grund_lo;
+	uint32_t	rx_stat_grund_hi;
+	uint32_t	rx_stat_grfrg_lo;
+	uint32_t	rx_stat_grfrg_hi;
+	uint32_t	rx_stat_grerb_lo;
+	uint32_t	rx_stat_grerb_hi;
+	uint32_t	rx_stat_grfre_lo;
+	uint32_t	rx_stat_grfre_hi;
+	uint32_t	rx_stat_gripj_lo;
+	uint32_t	rx_stat_gripj_hi;
+};
+
+union mac_stats {
+    struct emac_stats	emac_stats;
+    struct bmac_stats	bmac_stats;
+};
+
+struct mac_stx {
+	/* in_bad_octets */
+	uint32_t	rx_stat_ifhcinbadoctets_hi;
+	uint32_t	rx_stat_ifhcinbadoctets_lo;
+
+	/* out_bad_octets */
+	uint32_t	tx_stat_ifhcoutbadoctets_hi;
+	uint32_t	tx_stat_ifhcoutbadoctets_lo;
+
+	/* crc_receive_errors */
+	uint32_t	rx_stat_dot3statsfcserrors_hi;
+	uint32_t	rx_stat_dot3statsfcserrors_lo;
+	/* alignment_errors */
+	uint32_t	rx_stat_dot3statsalignmenterrors_hi;
+	uint32_t	rx_stat_dot3statsalignmenterrors_lo;
+	/* carrier_sense_errors */
+	uint32_t	rx_stat_dot3statscarriersenseerrors_hi;
+	uint32_t	rx_stat_dot3statscarriersenseerrors_lo;
+	/* false_carrier_detections */
+	uint32_t	rx_stat_falsecarriererrors_hi;
+	uint32_t	rx_stat_falsecarriererrors_lo;
+
+	/* runt_packets_received */
+	uint32_t	rx_stat_etherstatsundersizepkts_hi;
+	uint32_t	rx_stat_etherstatsundersizepkts_lo;
+	/* jabber_packets_received */
+	uint32_t	rx_stat_dot3statsframestoolong_hi;
+	uint32_t	rx_stat_dot3statsframestoolong_lo;
+
+	/* error_runt_packets_received */
+	uint32_t	rx_stat_etherstatsfragments_hi;
+	uint32_t	rx_stat_etherstatsfragments_lo;
+	/* error_jabber_packets_received */
+	uint32_t	rx_stat_etherstatsjabbers_hi;
+	uint32_t	rx_stat_etherstatsjabbers_lo;
+
+	/* control_frames_received */
+	uint32_t	rx_stat_maccontrolframesreceived_hi;
+	uint32_t	rx_stat_maccontrolframesreceived_lo;
+	uint32_t	rx_stat_bmac_xpf_hi;
+	uint32_t	rx_stat_bmac_xpf_lo;
+	uint32_t	rx_stat_bmac_xcf_hi;
+	uint32_t	rx_stat_bmac_xcf_lo;
+
+	/* xoff_state_entered */
+	uint32_t	rx_stat_xoffstateentered_hi;
+	uint32_t	rx_stat_xoffstateentered_lo;
+	/* pause_xon_frames_received */
+	uint32_t	rx_stat_xonpauseframesreceived_hi;
+	uint32_t	rx_stat_xonpauseframesreceived_lo;
+	/* pause_xoff_frames_received */
+	uint32_t	rx_stat_xoffpauseframesreceived_hi;
+	uint32_t	rx_stat_xoffpauseframesreceived_lo;
+	/* pause_xon_frames_transmitted */
+	uint32_t	tx_stat_outxonsent_hi;
+	uint32_t	tx_stat_outxonsent_lo;
+	/* pause_xoff_frames_transmitted */
+	uint32_t	tx_stat_outxoffsent_hi;
+	uint32_t	tx_stat_outxoffsent_lo;
+	/* flow_control_done */
+	uint32_t	tx_stat_flowcontroldone_hi;
+	uint32_t	tx_stat_flowcontroldone_lo;
+
+	/* ether_stats_collisions */
+	uint32_t	tx_stat_etherstatscollisions_hi;
+	uint32_t	tx_stat_etherstatscollisions_lo;
+	/* single_collision_transmit_frames */
+	uint32_t	tx_stat_dot3statssinglecollisionframes_hi;
+	uint32_t	tx_stat_dot3statssinglecollisionframes_lo;
+	/* multiple_collision_transmit_frames */
+	uint32_t	tx_stat_dot3statsmultiplecollisionframes_hi;
+	uint32_t	tx_stat_dot3statsmultiplecollisionframes_lo;
+	/* deferred_transmissions */
+	uint32_t	tx_stat_dot3statsdeferredtransmissions_hi;
+	uint32_t	tx_stat_dot3statsdeferredtransmissions_lo;
+	/* excessive_collision_frames */
+	uint32_t	tx_stat_dot3statsexcessivecollisions_hi;
+	uint32_t	tx_stat_dot3statsexcessivecollisions_lo;
+	/* late_collision_frames */
+	uint32_t	tx_stat_dot3statslatecollisions_hi;
+	uint32_t	tx_stat_dot3statslatecollisions_lo;
+
+	/* frames_transmitted_64_bytes */
+	uint32_t	tx_stat_etherstatspkts64octets_hi;
+	uint32_t	tx_stat_etherstatspkts64octets_lo;
+	/* frames_transmitted_65_127_bytes */
+	uint32_t	tx_stat_etherstatspkts65octetsto127octets_hi;
+	uint32_t	tx_stat_etherstatspkts65octetsto127octets_lo;
+	/* frames_transmitted_128_255_bytes */
+	uint32_t	tx_stat_etherstatspkts128octetsto255octets_hi;
+	uint32_t	tx_stat_etherstatspkts128octetsto255octets_lo;
+	/* frames_transmitted_256_511_bytes */
+	uint32_t	tx_stat_etherstatspkts256octetsto511octets_hi;
+	uint32_t	tx_stat_etherstatspkts256octetsto511octets_lo;
+	/* frames_transmitted_512_1023_bytes */
+	uint32_t	tx_stat_etherstatspkts512octetsto1023octets_hi;
+	uint32_t	tx_stat_etherstatspkts512octetsto1023octets_lo;
+	/* frames_transmitted_1024_1522_bytes */
+	uint32_t	tx_stat_etherstatspkts1024octetsto1522octets_hi;
+	uint32_t	tx_stat_etherstatspkts1024octetsto1522octets_lo;
+	/* frames_transmitted_1523_9022_bytes */
+	uint32_t	tx_stat_etherstatspktsover1522octets_hi;
+	uint32_t	tx_stat_etherstatspktsover1522octets_lo;
+	uint32_t	tx_stat_bmac_2047_hi;
+	uint32_t	tx_stat_bmac_2047_lo;
+	uint32_t	tx_stat_bmac_4095_hi;
+	uint32_t	tx_stat_bmac_4095_lo;
+	uint32_t	tx_stat_bmac_9216_hi;
+	uint32_t	tx_stat_bmac_9216_lo;
+	uint32_t	tx_stat_bmac_16383_hi;
+	uint32_t	tx_stat_bmac_16383_lo;
+
+	/* internal_mac_transmit_errors */
+	uint32_t	tx_stat_dot3statsinternalmactransmiterrors_hi;
+	uint32_t	tx_stat_dot3statsinternalmactransmiterrors_lo;
+
+	/* if_out_discards */
+	uint32_t	tx_stat_bmac_ufl_hi;
+	uint32_t	tx_stat_bmac_ufl_lo;
+};
+
+
+#define	MAC_STX_IDX_MAX			2
+
+struct host_port_stats {
+    uint32_t		host_port_stats_start;
+
+    struct mac_stx	mac_stx[MAC_STX_IDX_MAX];
+
+    uint32_t		brb_drop_hi;
+    uint32_t		brb_drop_lo;
+
+    uint32_t		host_port_stats_end;
+};
+
+struct host_func_stats {
+	uint32_t	host_func_stats_start;
+
+	uint32_t	total_bytes_received_hi;
+	uint32_t	total_bytes_received_lo;
+
+	uint32_t	total_bytes_transmitted_hi;
+	uint32_t	total_bytes_transmitted_lo;
+
+	uint32_t	total_unicast_packets_received_hi;
+	uint32_t	total_unicast_packets_received_lo;
+
+	uint32_t	total_multicast_packets_received_hi;
+	uint32_t	total_multicast_packets_received_lo;
+
+	uint32_t	total_broadcast_packets_received_hi;
+	uint32_t	total_broadcast_packets_received_lo;
+
+	uint32_t	total_unicast_packets_transmitted_hi;
+	uint32_t	total_unicast_packets_transmitted_lo;
+
+	uint32_t	total_multicast_packets_transmitted_hi;
+	uint32_t	total_multicast_packets_transmitted_lo;
+
+	uint32_t	total_broadcast_packets_transmitted_hi;
+	uint32_t	total_broadcast_packets_transmitted_lo;
+
+	uint32_t	valid_bytes_received_hi;
+	uint32_t	valid_bytes_received_lo;
+
+	uint32_t	host_func_stats_end;
+};
+
+#define	BCM_5710_FW_MAJOR_VERSION		5
+#define	BCM_5710_FW_MINOR_VERSION		2
+#define	BCM_5710_FW_REVISION_VERSION		13
+#define	BCM_5710_FW_ENGINEERING_VERSION		0
+#define	BCM_5710_FW_COMPILE_FLAGS		1
+
+/*
+ * Attention bits
+ */
+struct atten_def_status_block {
+	uint32_t	attn_bits;
+	uint32_t	attn_bits_ack;
+	uint8_t		status_block_id;
+	uint8_t		reserved0;
+	uint16_t	attn_bits_index;
+	uint32_t	reserved1;
+};
+
+/*
+ * Common data for all protocols.
+ */
+struct doorbell_hdr {
+	uint8_t		header;
+#define	DOORBELL_HDR_RX			(0x1 << 0)
+#define	DOORBELL_HDR_RX_SHIFT		0
+#define	DOORBELL_HDR_DB_TYPE		(0x1 << 1)
+#define	DOORBELL_HDR_DB_TYPE_SHIFT	1
+#define	DOORBELL_HDR_DPM_SIZE		(0x3 << 2)
+#define	DOORBELL_HDR_DPM_SIZE_SHIFT	2
+#define	DOORBELL_HDR_CONN_TYPE		(0xF << 4)
+#define	DOORBELL_HDR_CONN_TYPE_SHIFT	4
+};
+
+/*
+ * Doorbell message sent to the chip.
+ */
+struct doorbell {
+#if defined(__BIG_ENDIAN)
+	uint16_t	zero_fill2;
+	uint8_t		zero_fill1;
+	struct doorbell_hdr	header;
+#elif defined(__LITTLE_ENDIAN)
+	struct doorbell_hdr	header;
+	uint8_t		zero_fill1;
+	uint16_t	zero_fill2;
+#endif
+};
+
+/*
+ * Doorbell message sent to the chip.
+ */
+struct doorbell_set_prod {
+#if defined(__BIG_ENDIAN)
+	uint16_t	prod;
+	uint8_t		zero_fill1;
+	struct doorbell_hdr	header;
+#elif defined(__LITTLE_ENDIAN)
+	struct doorbell_hdr	header;
+	uint8_t		zero_fill1;
+	uint16_t	prod;
+#endif
+};
+
+/*
+ * IGU driver acknowledgement register.
+ */
+struct igu_ack_register {
+#if defined(__BIG_ENDIAN)
+	uint16_t	sb_id_and_flags;
+#define	IGU_ACK_REGISTER_STATUS_BLOCK_ID	(0x1F << 0)
+#define	IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT	0
+#define	IGU_ACK_REGISTER_STORM_ID		(0x7 << 5)
+#define	IGU_ACK_REGISTER_STORM_ID_SHIFT		5
+#define	IGU_ACK_REGISTER_UPDATE_INDEX		(0x1 << 8)
+#define	IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT	8
+#define	IGU_ACK_REGISTER_INTERRUPT_MODE		(0x3 << 9)
+#define	IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT	9
+#define	IGU_ACK_REGISTER_RESERVED		(0x1F << 11)
+#define	IGU_ACK_REGISTER_RESERVED_SHIFT		11
+	uint16_t	status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	status_block_index;
+	uint16_t	sb_id_and_flags;
+#define	IGU_ACK_REGISTER_STATUS_BLOCK_ID	(0x1F << 0)
+#define	IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT	0
+#define	IGU_ACK_REGISTER_STORM_ID		(0x7 << 5)
+#define	IGU_ACK_REGISTER_STORM_ID_SHIFT		5
+#define	IGU_ACK_REGISTER_UPDATE_INDEX		(0x1 << 8)
+#define	IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT	8
+#define	IGU_ACK_REGISTER_INTERRUPT_MODE		(0x3 << 9)
+#define	IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT	9
+#define	IGU_ACK_REGISTER_RESERVED		(0x1F << 11)
+#define	IGU_ACK_REGISTER_RESERVED_SHIFT		11
+#endif
+};
+
+/*
+ * IGU driver acknowledgement register.
+ */
+struct igu_backward_compatible {
+	uint32_t	sb_id_and_flags;
+#define	IGU_BACKWARD_COMPATIBLE_SB_INDEX		(0xFFFF << 0)
+#define	IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT		0
+#define	IGU_BACKWARD_COMPATIBLE_SB_SELECT		(0x1F << 16)
+#define	IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT		16
+#define	IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS		(0x7 << 21)
+#define	IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT	21
+#define	IGU_BACKWARD_COMPATIBLE_BUPDATE			(0x1 << 24)
+#define	IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT		24
+#define	IGU_BACKWARD_COMPATIBLE_ENABLE_INT		(0x3 << 25)
+#define	IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT	25
+#define	IGU_BACKWARD_COMPATIBLE_RESERVED_0		(0x1F << 27)
+#define	IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT	27
+	uint32_t	reserved_2;
+};
+
+/*
+ * IGU driver acknowledgement register.
+ */
+struct igu_regular {
+	uint32_t	sb_id_and_flags;
+#define	IGU_REGULAR_SB_INDEX			(0xFFFFF << 0)
+#define	IGU_REGULAR_SB_INDEX_SHIFT		0
+#define	IGU_REGULAR_RESERVED0			(0x1 << 20)
+#define	IGU_REGULAR_RESERVED0_SHIFT		20
+#define	IGU_REGULAR_SEGMENT_ACCESS		(0x7 << 21)
+#define	IGU_REGULAR_SEGMENT_ACCESS_SHIFT	21
+#define	IGU_REGULAR_BUPDATE			(0x1 << 24)
+#define	IGU_REGULAR_BUPDATE_SHIFT		24
+#define	IGU_REGULAR_ENABLE_INT			(0x3 << 25)
+#define	IGU_REGULAR_ENABLE_INT_SHIFT		25
+#define	IGU_REGULAR_RESERVED_1			(0x1 << 27)
+#define	IGU_REGULAR_RESERVED_1_SHIFT		27
+#define	IGU_REGULAR_CLEANUP_TYPE		(0x3 << 28)
+#define	IGU_REGULAR_CLEANUP_TYPE_SHIFT		28
+#define	IGU_REGULAR_CLEANUP_SET			(0x1 << 30)
+#define	IGU_REGULAR_CLEANUP_SET_SHIFT		30
+#define	IGU_REGULAR_BCLEANUP			(0x1 << 31)
+#define	IGU_REGULAR_BCLEANUP_SHIFT		31
+	uint32_t	reserved_2;
+};
+
+/*
+ * IGU driver acknowledgement register.
+ */
+union igu_consprod_reg {
+	struct igu_regular	regular;
+	struct igu_backward_compatible	backward_compatible;
+};
+
+/*
+ * Parser parsing flags field.
+ */
+struct parsing_flags {
+	uint16_t	flags;
+#define	PARSING_FLAGS_ETHERNET_ADDRESS_TYPE		(0x1 << 0)
+#define	PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT	0
+#define	PARSING_FLAGS_VLAN				(0x1 << 1)
+#define	PARSING_FLAGS_VLAN_SHIFT			1
+#define	PARSING_FLAGS_EXTRA_VLAN			(0x1 << 2)
+#define	PARSING_FLAGS_EXTRA_VLAN_SHIFT			2
+#define	PARSING_FLAGS_OVER_ETHERNET_PROTOCOL		(0x3 << 3)
+#define	PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT	3
+#define	PARSING_FLAGS_IP_OPTIONS			(0x1 << 5)
+#define	PARSING_FLAGS_IP_OPTIONS_SHIFT			5
+#define	PARSING_FLAGS_FRAGMENTATION_STATUS		(0x1 << 6)
+#define	PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT	6
+#define	PARSING_FLAGS_OVER_IP_PROTOCOL			(0x3 << 7)
+#define	PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT		7
+#define	PARSING_FLAGS_PURE_ACK_INDICATION		(0x1 << 9)
+#define	PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT		9
+#define	PARSING_FLAGS_TCP_OPTIONS_EXIST			(0x1 << 10)
+#define	PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT		10
+#define	PARSING_FLAGS_TIME_STAMP_EXIST_FLAG		(0x1 << 11)
+#define	PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT	11
+#define	PARSING_FLAGS_CONNECTION_MATCH			(0x1 << 12)
+#define	PARSING_FLAGS_CONNECTION_MATCH_SHIFT		12
+#define	PARSING_FLAGS_LLC_SNAP				(0x1 << 13)
+#define	PARSING_FLAGS_LLC_SNAP_SHIFT			13
+#define	PARSING_FLAGS_RESERVED0				(0x3 << 14)
+#define	PARSING_FLAGS_RESERVED0_SHIFT			14
+};
+
+struct regpair {
+	uint32_t	lo;
+	uint32_t	hi;
+};
+
+/*
+ * dmae command structure
+ */
+struct dmae_command {
+	uint32_t	opcode;
+#define	DMAE_COMMAND_SRC			(0x1 << 0)
+#define	DMAE_COMMAND_SRC_SHIFT			0
+#define	DMAE_COMMAND_DST			(0x3 << 1)
+#define	DMAE_COMMAND_DST_SHIFT			1
+#define	DMAE_COMMAND_C_DST			(0x1 << 3)
+#define	DMAE_COMMAND_C_DST_SHIFT		3
+#define	DMAE_COMMAND_C_TYPE_ENABLE		(0x1 << 4)
+#define	DMAE_COMMAND_C_TYPE_ENABLE_SHIFT	4
+#define	DMAE_COMMAND_C_TYPE_CRC_ENABLE		(0x1 << 5)
+#define	DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT	5
+#define	DMAE_COMMAND_C_TYPE_CRC_OFFSET		(0x7 << 6)
+#define	DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT	6
+#define	DMAE_COMMAND_ENDIANITY			(0x3 << 9)
+#define	DMAE_COMMAND_ENDIANITY_SHIFT		9
+#define	DMAE_COMMAND_PORT			(0x1 << 11)
+#define	DMAE_COMMAND_PORT_SHIFT			11
+#define	DMAE_COMMAND_CRC_RESET			(0x1 << 12)
+#define	DMAE_COMMAND_CRC_RESET_SHIFT		12
+#define	DMAE_COMMAND_SRC_RESET			(0x1 << 13)
+#define	DMAE_COMMAND_SRC_RESET_SHIFT		13
+#define	DMAE_COMMAND_DST_RESET			(0x1 << 14)
+#define	DMAE_COMMAND_DST_RESET_SHIFT		14
+#define	DMAE_COMMAND_E1HVN			(0x3 << 15)
+#define	DMAE_COMMAND_E1HVN_SHIFT		15
+#define	DMAE_COMMAND_RESERVED0			(0x7FFF << 17)
+#define	DMAE_COMMAND_RESERVED0_SHIFT		17
+	uint32_t	src_addr_lo;
+	uint32_t	src_addr_hi;
+	uint32_t	dst_addr_lo;
+	uint32_t	dst_addr_hi;
+#if defined(__BIG_ENDIAN)
+	uint16_t	reserved1;
+	uint16_t	len;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	len;
+	uint16_t	reserved1;
+#endif
+	uint32_t	comp_addr_lo;
+	uint32_t	comp_addr_hi;
+	uint32_t	comp_val;
+	uint32_t	crc32;
+	uint32_t	crc32_c;
+#if defined(__BIG_ENDIAN)
+	uint16_t	crc16_c;
+	uint16_t	crc16;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	crc16;
+	uint16_t	crc16_c;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	reserved2;
+	uint16_t	crc_t10;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	crc_t10;
+	uint16_t	reserved2;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	xsum8;
+	uint16_t	xsum16;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	xsum16;
+	uint16_t	xsum8;
+#endif
+};
+
+struct double_regpair {
+	uint32_t	regpair0_lo;
+	uint32_t	regpair0_hi;
+	uint32_t	regpair1_lo;
+	uint32_t	regpair1_hi;
+};
+
+/*
+ * The eth storm context of Ustorm (configuration part).
+ */
+struct ustorm_eth_st_context_config {
+#if defined(__BIG_ENDIAN)
+	uint8_t		flags;
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT	(0x1 << 0)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT	0
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC		(0x1 << 1)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT	1
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA			(0x1 << 2)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT		2
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS		(0x1 << 3)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT	3
+#define	__USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0		(0xF << 4)
+#define	__USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT		4
+	uint8_t		status_block_id;
+	uint8_t		clientId;
+	uint8_t		sb_index_numbers;
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER	(0xF << 0)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT	0
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER		(0xF << 4)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT	4
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		sb_index_numbers;
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER	(0xF << 0)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT	0
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER		(0xF << 4)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT	4
+	uint8_t		clientId;
+	uint8_t		status_block_id;
+	uint8_t		flags;
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT	(0x1 << 0)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT	0
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC		(0x1 << 1)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT	1
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA			(0x1 << 2)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT		2
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS		(0x1 << 3)
+#define	USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT	3
+#define	__USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0		(0xF << 4)
+#define	__USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT		4
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	bd_buff_size;
+	uint8_t		statistics_counter_id;
+	uint8_t		mc_alignment_log_size;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		mc_alignment_log_size;
+	uint8_t		statistics_counter_id;
+	uint16_t	bd_buff_size;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		__local_sge_prod;
+	uint8_t		__local_bd_prod;
+	uint16_t	sge_buff_size;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	sge_buff_size;
+	uint8_t		__local_bd_prod;
+	uint8_t		__local_sge_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__sdm_bd_expected_counter;
+	uint8_t		cstorm_agg_int;
+	uint8_t		__expected_bds_on_ram;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__expected_bds_on_ram;
+	uint8_t		cstorm_agg_int;
+	uint16_t	__sdm_bd_expected_counter;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__ring_data_ram_addr;
+	uint16_t	__hc_cstorm_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__hc_cstorm_ram_addr;
+	uint16_t	__ring_data_ram_addr;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		reserved1;
+	uint8_t		max_sges_for_packet;
+	uint16_t	__bd_ring_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__bd_ring_ram_addr;
+	uint8_t		max_sges_for_packet;
+	uint8_t		reserved1;
+#endif
+	uint32_t	bd_page_base_lo;
+	uint32_t	bd_page_base_hi;
+	uint32_t	sge_page_base_lo;
+	uint32_t	sge_page_base_hi;
+	struct regpair	reserved2;
+};
+
+/*
+ * The eth Rx Buffer Descriptor.
+ */
+struct eth_rx_bd {
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+};
+
+/*
+ * The eth Rx SGE Descriptor.
+ */
+struct eth_rx_sge {
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+};
+
+/*
+ * Local BDs and SGEs rings (in ETH).
+ */
+struct eth_local_rx_rings {
+	struct eth_rx_bd	__local_bd_ring[8];
+	struct eth_rx_sge	__local_sge_ring[10];
+};
+
+/*
+ * The eth storm context of Ustorm.
+ */
+struct ustorm_eth_st_context {
+	struct ustorm_eth_st_context_config	common;
+	struct eth_local_rx_rings		__rings;
+};
+
+/*
+ * The eth storm context of Tstorm.
+ */
+struct tstorm_eth_st_context {
+	uint32_t	__reserved0[28];
+};
+
+/*
+ * The eth aggregative context section of Xstorm.
+ */
+struct xstorm_eth_extra_ag_context_section {
+#if defined(__BIG_ENDIAN)
+	uint8_t		__tcp_agg_vars1;
+	uint8_t		__reserved50;
+	uint16_t	__mss;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__mss;
+	uint8_t		__reserved50;
+	uint8_t		__tcp_agg_vars1;
+#endif
+	uint32_t	__snd_nxt;
+	uint32_t	__tx_wnd;
+	uint32_t	__snd_una;
+	uint32_t	__reserved53;
+#if defined(__BIG_ENDIAN)
+	uint8_t		__agg_val8_th;
+	uint8_t		__agg_val8;
+	uint16_t	__tcp_agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__tcp_agg_vars2;
+	uint8_t		__agg_val8;
+	uint8_t		__agg_val8_th;
+#endif
+	uint32_t	__reserved58;
+	uint32_t	__reserved59;
+	uint32_t	__reserved60;
+	uint32_t	__reserved61;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_val7_th;
+	uint16_t	__agg_val7;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val7;
+	uint16_t	__agg_val7_th;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		__tcp_agg_vars5;
+	uint8_t		__tcp_agg_vars4;
+	uint8_t		__tcp_agg_vars3;
+	uint8_t		__reserved62;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__reserved62;
+	uint8_t		__tcp_agg_vars3;
+	uint8_t		__tcp_agg_vars4;
+	uint8_t		__tcp_agg_vars5;
+#endif
+	uint32_t	__tcp_agg_vars6;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_misc6;
+	uint16_t	__tcp_agg_vars7;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__tcp_agg_vars7;
+	uint16_t	__agg_misc6;
+#endif
+	uint32_t	__agg_val10;
+	uint32_t	__agg_val10_th;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved3;
+	uint8_t		__reserved2;
+	uint8_t		__da_only_cnt;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__da_only_cnt;
+	uint8_t		__reserved2;
+	uint16_t	__reserved3;
+#endif
+};
+
+/*
+ * The eth aggregative context of Xstorm.
+ */
+struct xstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+	uint16_t	agg_val1;
+	uint8_t		__agg_vars1;
+	uint8_t		__state;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__state;
+	uint8_t		__agg_vars1;
+	uint16_t	agg_val1;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		cdu_reserved;
+	uint8_t		__agg_vars4;
+	uint8_t		__agg_vars3;
+	uint8_t		__agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__agg_vars2;
+	uint8_t		__agg_vars3;
+	uint8_t		__agg_vars4;
+	uint8_t		cdu_reserved;
+#endif
+	uint32_t	__bd_prod;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_vars5;
+	uint16_t	__agg_val4_th;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val4_th;
+	uint16_t	__agg_vars5;
+#endif
+	struct xstorm_eth_extra_ag_context_section __extra_section;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_vars7;
+	uint8_t		__agg_val3_th;
+	uint8_t		__agg_vars6;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__agg_vars6;
+	uint8_t		__agg_val3_th;
+	uint16_t	__agg_vars7;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_val11_th;
+	uint16_t	__agg_val11;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val11;
+	uint16_t	__agg_val11_th;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		__reserved1;
+	uint8_t		__agg_val6_th;
+	uint16_t	__agg_val9;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val9;
+	uint8_t		__agg_val6_th;
+	uint8_t		__reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_val2_th;
+	uint16_t	__agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val2;
+	uint16_t	__agg_val2_th;
+#endif
+	uint32_t	__agg_vars8;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_misc0;
+	uint16_t	__agg_val4;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val4;
+	uint16_t	__agg_misc0;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		__agg_val3;
+	uint8_t		__agg_val6;
+	uint8_t		__agg_val5_th;
+	uint8_t		__agg_val5;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__agg_val5;
+	uint8_t		__agg_val5_th;
+	uint8_t		__agg_val6;
+	uint8_t		__agg_val3;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_misc1;
+	uint16_t	__bd_ind_max_val;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__bd_ind_max_val;
+	uint16_t	__agg_misc1;
+#endif
+	uint32_t	__reserved57;
+	uint32_t	__agg_misc4;
+	uint32_t	__agg_misc5;
+};
+
+/*
+ * The eth extra aggregative context section of Tstorm.
+ */
+struct tstorm_eth_extra_ag_context_section {
+	uint32_t	__agg_val1;
+#if defined(__BIG_ENDIAN)
+	uint8_t		__tcp_agg_vars2;
+	uint8_t		__agg_val3;
+	uint16_t	__agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val2;
+	uint8_t		__agg_val3;
+	uint8_t		__tcp_agg_vars2;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_val5;
+	uint8_t		__agg_val6;
+	uint8_t		__tcp_agg_vars3;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__tcp_agg_vars3;
+	uint8_t		__agg_val6;
+	uint16_t	__agg_val5;
+#endif
+	uint32_t	__reserved63;
+	uint32_t	__reserved64;
+	uint32_t	__reserved65;
+	uint32_t	__reserved66;
+	uint32_t	__reserved67;
+	uint32_t	__tcp_agg_vars1;
+	uint32_t	__reserved61;
+	uint32_t	__reserved62;
+	uint32_t	__reserved2;
+};
+
+/*
+ * The eth aggregative context of Tstorm.
+ */
+struct tstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved54;
+	uint8_t		__agg_vars1;
+	uint8_t		__state;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__state;
+	uint8_t		__agg_vars1;
+	uint16_t	__reserved54;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_val4;
+	uint16_t	__agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_vars2;
+	uint16_t	__agg_val4;
+#endif
+	struct tstorm_eth_extra_ag_context_section	__extra_section;
+};
+
+/*
+ * The eth aggregative context of Cstorm.
+ */
+struct cstorm_eth_ag_context {
+	uint32_t	__agg_vars1;
+#if defined(__BIG_ENDIAN)
+	uint8_t		__aux1_th;
+	uint8_t		__aux1_val;
+	uint16_t	__agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_vars2;
+	uint8_t		__aux1_val;
+	uint8_t		__aux1_th;
+#endif
+	uint32_t	__num_of_treated_packet;
+	uint32_t	__last_packet_treated;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved58;
+	uint16_t	__reserved57;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__reserved57;
+	uint16_t	__reserved58;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		__reserved62;
+	uint8_t		__reserved61;
+	uint8_t		__reserved60;
+	uint8_t		__reserved59;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__reserved59;
+	uint8_t		__reserved60;
+	uint8_t		__reserved61;
+	uint8_t		__reserved62;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved64;
+	uint16_t	__reserved63;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__reserved63;
+	uint16_t	__reserved64;
+#endif
+	uint32_t	__reserved65;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_vars3;
+	uint16_t	__rq_inv_cnt;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__rq_inv_cnt;
+	uint16_t	__agg_vars3;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__packet_index_th;
+	uint16_t	__packet_index;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__packet_index;
+	uint16_t	__packet_index_th;
+#endif
+};
+
+/*
+ * The eth aggregative context of Ustorm.
+ */
+struct ustorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+	uint8_t		__aux_counter_flags;
+	uint8_t		__agg_vars2;
+	uint8_t		__agg_vars1;
+	uint8_t		__state;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__state;
+	uint8_t		__agg_vars1;
+	uint8_t		__agg_vars2;
+	uint8_t		__aux_counter_flags;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		cdu_usage;
+	uint8_t		__agg_misc2;
+	uint16_t	__agg_misc1;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_misc1;
+	uint8_t		__agg_misc2;
+	uint8_t		cdu_usage;
+#endif
+	uint32_t	__agg_misc4;
+#if defined(__BIG_ENDIAN)
+	uint8_t		__agg_val3_th;
+	uint8_t		__agg_val3;
+	uint16_t	__agg_misc3;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_misc3;
+	uint8_t		__agg_val3;
+	uint8_t		__agg_val3_th;
+#endif
+	uint32_t	__agg_val1;
+	uint32_t	__agg_misc4_th;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__agg_val2_th;
+	uint16_t	__agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__agg_val2;
+	uint16_t	__agg_val2_th;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved2;
+	uint8_t		__decision_rules;
+	uint8_t		__decision_rule_enable_bits;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__decision_rule_enable_bits;
+	uint8_t		__decision_rules;
+	uint16_t	__reserved2;
+#endif
+};
+
+/*
+ * Timers connection context.
+ */
+struct timers_block_context {
+	uint32_t	__reserved_0;
+	uint32_t	__reserved_1;
+	uint32_t	__reserved_2;
+	uint32_t	flags;
+#define	__TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS	(0x3 << 0)
+#define	__TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
+#define	TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG		(0x1 << 2)
+#define	TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT	2
+#define	__TIMERS_BLOCK_CONTEXT_RESERVED0		(0x1FFFFFFF << 3)
+#define	__TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT		3
+};
+
+/*
+ * Structure for easy accessibility to assembler.
+ */
+struct eth_tx_bd_flags {
+	uint8_t	as_bitfield;
+#define	ETH_TX_BD_FLAGS_VLAN_TAG		(0x1 << 0)
+#define	ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT		0
+#define	ETH_TX_BD_FLAGS_IP_CSUM			(0x1 << 1)
+#define	ETH_TX_BD_FLAGS_IP_CSUM_SHIFT		1
+#define	ETH_TX_BD_FLAGS_L4_CSUM			(0x1 << 2)
+#define	ETH_TX_BD_FLAGS_L4_CSUM_SHIFT		2
+#define	ETH_TX_BD_FLAGS_END_BD			(0x1 << 3)
+#define	ETH_TX_BD_FLAGS_END_BD_SHIFT		3
+#define	ETH_TX_BD_FLAGS_START_BD		(0x1 << 4)
+#define	ETH_TX_BD_FLAGS_START_BD_SHIFT		4
+#define	ETH_TX_BD_FLAGS_HDR_POOL		(0x1 << 5)
+#define	ETH_TX_BD_FLAGS_HDR_POOL_SHIFT		5
+#define	ETH_TX_BD_FLAGS_SW_LSO			(0x1 << 6)
+#define	ETH_TX_BD_FLAGS_SW_LSO_SHIFT		6
+#define	ETH_TX_BD_FLAGS_IPV6			(0x1 << 7)
+#define	ETH_TX_BD_FLAGS_IPV6_SHIFT		7
+};
+
+/*
+ * The eth Tx Buffer Descriptor.
+ */
+struct eth_tx_start_bd {
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+	uint16_t	nbd;
+	uint16_t	nbytes;
+	uint16_t	vlan;
+	struct eth_tx_bd_flags	bd_flags;
+	uint8_t		general_data;
+#define	ETH_TX_START_BD_HDR_NBDS		(0x3F << 0)
+#define	ETH_TX_START_BD_HDR_NBDS_SHIFT		0
+#define	ETH_TX_START_BD_ETH_ADDR_TYPE		(0x3 << 6)
+#define	ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT	6
+};
+
+/*
+ * Tx regular BD structure.
+ */
+struct eth_tx_bd {
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+	uint16_t	total_pkt_bytes;
+	uint16_t	nbytes;
+	uint8_t		reserved[4];
+};
+
+/*
+ * Tx parsing BD structure for ETH,Relevant in START.
+ */
+struct eth_tx_parse_bd {
+	uint8_t		global_data;
+#define	ETH_TX_PARSE_BD_IP_HDR_START_OFFSET		(0xF << 0)
+#define	ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT	0
+#define	ETH_TX_PARSE_BD_UDP_CS_FLG			(0x1 << 4)
+#define	ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT		4
+#define	ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN		(0x1 << 5)
+#define	ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT	5
+#define	ETH_TX_PARSE_BD_LLC_SNAP_EN			(0x1 << 6)
+#define	ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT		6
+#define	ETH_TX_PARSE_BD_NS_FLG				(0x1 << 7)
+#define	ETH_TX_PARSE_BD_NS_FLG_SHIFT			7
+	uint8_t		tcp_flags;
+#define	ETH_TX_PARSE_BD_FIN_FLG				(0x1 << 0)
+#define	ETH_TX_PARSE_BD_FIN_FLG_SHIFT			0
+#define	ETH_TX_PARSE_BD_SYN_FLG				(0x1 << 1)
+#define	ETH_TX_PARSE_BD_SYN_FLG_SHIFT			1
+#define	ETH_TX_PARSE_BD_RST_FLG				(0x1 << 2)
+#define	ETH_TX_PARSE_BD_RST_FLG_SHIFT			2
+#define	ETH_TX_PARSE_BD_PSH_FLG				(0x1 << 3)
+#define	ETH_TX_PARSE_BD_PSH_FLG_SHIFT			3
+#define	ETH_TX_PARSE_BD_ACK_FLG				(0x1 << 4)
+#define	ETH_TX_PARSE_BD_ACK_FLG_SHIFT			4
+#define	ETH_TX_PARSE_BD_URG_FLG				(0x1 << 5)
+#define	ETH_TX_PARSE_BD_URG_FLG_SHIFT			5
+#define	ETH_TX_PARSE_BD_ECE_FLG				(0x1 << 6)
+#define	ETH_TX_PARSE_BD_ECE_FLG_SHIFT			6
+#define	ETH_TX_PARSE_BD_CWR_FLG				(0x1 << 7)
+#define	ETH_TX_PARSE_BD_CWR_FLG_SHIFT			7
+	uint8_t		ip_hlen;
+	uint8_t		reserved;
+	uint16_t	total_hlen;
+	uint16_t	tcp_pseudo_csum;
+	uint16_t	lso_mss;
+	uint16_t	ip_id;
+	uint32_t	tcp_send_seq;
+};
+
+/*
+ * The last BD in the BD memory will hold a pointer to the next BD memory.
+ */
+struct eth_tx_next_bd {
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+	uint8_t		reserved[8];
+};
+
+/*
+ * union for 4 Bd types.
+ */
+union eth_tx_bd_types {
+	struct eth_tx_start_bd	start_bd;
+	struct eth_tx_bd	reg_bd;
+	struct eth_tx_parse_bd	parse_bd;
+	struct eth_tx_next_bd	next_bd;
+};
+
+/*
+ * The eth storm context of Xstorm.
+ */
+struct xstorm_eth_st_context {
+	uint32_t	tx_bd_page_base_lo;
+	uint32_t	tx_bd_page_base_hi;
+#if defined(__BIG_ENDIAN)
+	uint16_t	tx_bd_cons;
+	uint8_t		statistics_data;
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID		(0x7F << 0)
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT	0
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE			(0x1 << 7)
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT		7
+	uint8_t		__local_tx_bd_prod;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__local_tx_bd_prod;
+	uint8_t		statistics_data;
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID		(0x7F << 0)
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT	0
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE			(0x1 << 7)
+#define	XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT		7
+	uint16_t	tx_bd_cons;
+#endif
+	uint32_t	__reserved1;
+	uint32_t	__reserved2;
+#if defined(__BIG_ENDIAN)
+	uint8_t		__ram_cache_index;
+	uint8_t		__double_buffer_client;
+	uint16_t	__pkt_cons;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__pkt_cons;
+	uint8_t		__double_buffer_client;
+	uint8_t		__ram_cache_index;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	__statistics_address;
+	uint16_t	__gso_next;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	__gso_next;
+	uint16_t	__statistics_address;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t		__local_tx_bd_cons;
+	uint8_t		safc_group_num;
+	uint8_t		safc_group_en;
+	uint8_t		__is_eth_conn;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		__is_eth_conn;
+	uint8_t		safc_group_en;
+	uint8_t		safc_group_num;
+	uint8_t		__local_tx_bd_cons;
+#endif
+	union eth_tx_bd_types __bds[13];
+};
+
+/*
+ * The eth storm context of Cstorm.
+ */
+struct cstorm_eth_st_context {
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved0;
+	uint8_t		sb_index_number;
+	uint8_t		status_block_id;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		status_block_id;
+	uint8_t		sb_index_number;
+	uint16_t	__reserved0;
+#endif
+	uint32_t	__reserved1[3];
+};
+
+/*
+ * Ethernet connection context.
+ */
+struct eth_context {
+	struct ustorm_eth_st_context	ustorm_st_context;
+	struct tstorm_eth_st_context	tstorm_st_context;
+	struct xstorm_eth_ag_context	xstorm_ag_context;
+	struct tstorm_eth_ag_context	tstorm_ag_context;
+	struct cstorm_eth_ag_context	cstorm_ag_context;
+	struct ustorm_eth_ag_context	ustorm_ag_context;
+	struct timers_block_context	timers_context;
+	struct xstorm_eth_st_context	xstorm_st_context;
+	struct cstorm_eth_st_context	cstorm_st_context;
+};
+
+/*
+ * Ethernet doorbell
+ */
+struct eth_tx_doorbell {
+#if defined(__BIG_ENDIAN)
+	uint16_t	npackets;
+	uint8_t		params;
+#define	ETH_TX_DOORBELL_NUM_BDS				(0x3F << 0)
+#define	ETH_TX_DOORBELL_NUM_BDS_SHIFT			0
+#define	ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG		(0x1 << 6)
+#define	ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT	6
+#define	ETH_TX_DOORBELL_SPARE				(0x1 << 7)
+#define	ETH_TX_DOORBELL_SPARE_SHIFT			7
+	struct doorbell_hdr hdr;
+#elif defined(__LITTLE_ENDIAN)
+	struct doorbell_hdr hdr;
+	uint8_t		params;
+#define	ETH_TX_DOORBELL_NUM_BDS				(0x3F << 0)
+#define	ETH_TX_DOORBELL_NUM_BDS_SHIFT			0
+#define	ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG		(0x1 << 6)
+#define	ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT	6
+#define	ETH_TX_DOORBELL_SPARE				(0x1 << 7)
+#define	ETH_TX_DOORBELL_SPARE_SHIFT			7
+	uint16_t	npackets;
+#endif
+};
+
+/*
+ * cstorm default status block, generated by ustorm.
+ */
+struct cstorm_def_status_block_u {
+	uint16_t	index_values[HC_USTORM_DEF_SB_NUM_INDICES];
+	uint16_t	status_block_index;
+	uint8_t		func;
+	uint8_t		status_block_id;
+	uint32_t	__flags;
+};
+
+/*
+ * cstorm default status block, generated by cstorm.
+ */
+struct cstorm_def_status_block_c {
+	uint16_t	index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
+	uint16_t	status_block_index;
+	uint8_t		func;
+	uint8_t		status_block_id;
+	uint32_t	__flags;
+};
+
+/*
+ * xstorm status block
+ */
+struct xstorm_def_status_block {
+	uint16_t	index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
+	uint16_t	status_block_index;
+	uint8_t		func;
+	uint8_t		status_block_id;
+	uint32_t	__flags;
+};
+
+/*
+ * tstorm status block
+ */
+struct tstorm_def_status_block {
+	uint16_t	index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
+	uint16_t	status_block_index;
+	uint8_t		func;
+	uint8_t		status_block_id;
+	uint32_t	__flags;
+};
+
+/*
+ * host status block
+ */
+struct host_def_status_block {
+	struct atten_def_status_block	atten_status_block;
+	struct cstorm_def_status_block_u	u_def_status_block;
+	struct cstorm_def_status_block_c	c_def_status_block;
+	struct xstorm_def_status_block	x_def_status_block;
+	struct tstorm_def_status_block	t_def_status_block;
+};
+
+/*
+ * cstorm status block, generated by ustorm.
+ */
+struct cstorm_status_block_u {
+	uint16_t	index_values[HC_USTORM_SB_NUM_INDICES];
+	uint16_t	status_block_index;
+	uint8_t		func;
+	uint8_t		status_block_id;
+	uint32_t	__flags;
+};
+
+/*
+ * cstorm status block, generated by cstorm.
+ */
+struct cstorm_status_block_c {
+	uint16_t	index_values[HC_CSTORM_SB_NUM_INDICES];
+	uint16_t	status_block_index;
+	uint8_t		func;
+	uint8_t		status_block_id;
+	uint32_t	__flags;
+};
+
+/*
+ * host status block
+ */
+struct host_status_block {
+	struct cstorm_status_block_u u_status_block;
+	struct cstorm_status_block_c c_status_block;
+};
+
+/*
+ * The data for RSS setup ramrod.
+ */
+struct eth_client_setup_ramrod_data {
+	uint32_t	client_id;
+	uint8_t		is_rdma;
+	uint8_t		is_fcoe;
+	uint16_t	reserved1;
+};
+
+/*
+ * regular eth FP CQE parameters struct.
+ */
+struct eth_fast_path_rx_cqe {
+	uint8_t		type_error_flags;
+#define	ETH_FAST_PATH_RX_CQE_TYPE			(0x1 << 0)
+#define	ETH_FAST_PATH_RX_CQE_TYPE_SHIFT			0
+#define	ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG		(0x1 << 1)
+#define	ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT	1
+#define	ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG		(0x1 << 2)
+#define	ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT	2
+#define	ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG		(0x1 << 3)
+#define	ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT	3
+#define	ETH_FAST_PATH_RX_CQE_START_FLG			(0x1 << 4)
+#define	ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT		4
+#define	ETH_FAST_PATH_RX_CQE_END_FLG			(0x1 << 5)
+#define	ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT		5
+#define	ETH_FAST_PATH_RX_CQE_RESERVED0			(0x3 << 6)
+#define	ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT		6
+	uint8_t		status_flags;
+#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE		(0x7 << 0)
+#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT	0
+#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG		(0x1 << 3)
+#define	ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT		3
+#define	ETH_FAST_PATH_RX_CQE_BROADCAST_FLG		(0x1 << 4)
+#define	ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT	4
+#define	ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG		(0x1 << 5)
+#define	ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT	5
+#define	ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG	(0x1 << 6)
+#define	ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT	6
+#define	ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG	(0x1 << 7)
+#define	ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT	7
+	uint8_t		placement_offset;
+	uint8_t		queue_index;
+	uint32_t	rss_hash_result;
+	uint16_t	vlan_tag;
+	uint16_t	pkt_len;
+	uint16_t	len_on_bd;
+	struct parsing_flags	pars_flags;
+	uint16_t	sgl[8];
+};
+
+/*
+ * The data for RSS setup ramrod.
+ */
+struct eth_halt_ramrod_data {
+	uint32_t	client_id;
+	uint32_t	reserved0;
+};
+
+
+/*
+ * The data for statistics query ramrod.
+ */
+struct eth_query_ramrod_data {
+#if defined(__BIG_ENDIAN)
+	uint8_t		reserved0;
+	uint8_t		collect_port;
+	uint16_t	drv_counter;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	drv_counter;
+	uint8_t		collect_port;
+	uint8_t		reserved0;
+#endif
+	uint32_t	ctr_id_vector;
+};
+
+/*
+ * Place holder for ramrods protocol specific data.
+ */
+struct ramrod_data {
+	uint32_t	data_lo;
+	uint32_t	data_hi;
+};
+
+/*
+ * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits).
+ */
+union eth_ramrod_data {
+	struct ramrod_data general;
+};
+
+
+/*
+ * Eth Rx Cqe structure- general structure for ramrods.
+ */
+struct common_ramrod_eth_rx_cqe {
+	uint8_t		ramrod_type;
+#define	COMMON_RAMROD_ETH_RX_CQE_TYPE			(0x1 << 0)
+#define	COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT		0
+#define	COMMON_RAMROD_ETH_RX_CQE_ERROR			(0x1 << 1)
+#define	COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT		1
+#define	COMMON_RAMROD_ETH_RX_CQE_RESERVED0		(0x3F << 2)
+#define	COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT	2
+	uint8_t		conn_type;
+	uint16_t	reserved1;
+	uint32_t	conn_and_cmd_data;
+#define	COMMON_RAMROD_ETH_RX_CQE_CID			(0xFFFFFF << 0)
+#define	COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
+#define	COMMON_RAMROD_ETH_RX_CQE_CMD_ID			(0xFF << 24)
+#define	COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT		24
+	struct ramrod_data	protocol_data;
+	uint32_t	reserved2[4];
+};
+
+/*
+ * Rx Last CQE in page (in ETH).
+ */
+struct eth_rx_cqe_next_page {
+	uint32_t	addr_lo;
+	uint32_t	addr_hi;
+	uint32_t	reserved[6];
+};
+
+/*
+ * union for all eth rx cqe types (fix their sizes).
+ */
+union eth_rx_cqe {
+	struct eth_fast_path_rx_cqe	fast_path_cqe;
+	struct common_ramrod_eth_rx_cqe	ramrod_cqe;
+	struct eth_rx_cqe_next_page	next_page_cqe;
+};
+
+/*
+ * Common data for all protocols.
+ */
+struct spe_hdr {
+	uint32_t	conn_and_cmd_data;
+#define	SPE_HDR_CID				(0xFFFFFF << 0)
+#define	SPE_HDR_CID_SHIFT			0
+#define	SPE_HDR_CMD_ID				(0xFF << 24)
+#define	SPE_HDR_CMD_ID_SHIFT			24
+	uint16_t	type;
+#define	SPE_HDR_CONN_TYPE			(0xFF << 0)
+#define	SPE_HDR_CONN_TYPE_SHIFT			0
+#define	SPE_HDR_COMMON_RAMROD			(0xFF << 8)
+#define	SPE_HDR_COMMON_RAMROD_SHIFT		8
+	uint16_t	reserved;
+};
+
+/*
+ * Ethernet slow path element
+ */
+union eth_specific_data {
+	uint8_t		protocol_data[8];
+	struct regpair	mac_config_addr;
+	struct eth_client_setup_ramrod_data	client_setup_ramrod_data;
+	struct eth_halt_ramrod_data	halt_ramrod_data;
+	struct regpair	leading_cqe_addr;
+	struct regpair	update_data_addr;
+	struct eth_query_ramrod_data	query_ramrod_data;
+};
+
+/*
+ * Ethernet slow path element.
+ */
+struct eth_spe {
+	struct spe_hdr hdr;
+	union eth_specific_data data;
+};
+
+/*
+ * Array of 13 bds as appears in the eth xstorm context.
+ */
+struct eth_tx_bds_array {
+	union eth_tx_bd_types bds[13];
+};
+
+/*
+ * Common configuration parameters per function in Tstorm.
+ */
+struct tstorm_eth_function_common_config {
+#if defined(__BIG_ENDIAN)
+	uint8_t		leading_client_id;
+	uint8_t		rss_result_mask;
+	uint16_t	config_flags;
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY	(0x1 << 0)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY	(0x1 << 2)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE		(0x7 << 4)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT	4
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE	(0x1 << 7)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT	7
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM		(0x1 << 8)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT	8
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM		(0x1 << 9)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT	9
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA		(0x1 << 10)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT	10
+#define	__TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0		(0x1F << 11)
+#define	__TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT	11
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	config_flags;
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY	(0x1 << 0)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY	(0x1 << 2)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE		(0x7 << 4)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT	4
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE	(0x1 << 7)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT	7
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM		(0x1 << 8)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT	8
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM		(0x1 << 9)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT	9
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA		(0x1 << 10)
+#define	TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT	10
+#define	__TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0		(0x1F << 11)
+#define	__TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT	11
+	uint8_t		rss_result_mask;
+	uint8_t		leading_client_id;
+#endif
+	uint16_t	vlan_id[2];
+};
+
+/*
+ * RSS idirection table update configuration.
+ */
+struct rss_update_config {
+#if defined(__BIG_ENDIAN)
+	uint16_t	toe_rss_bitmap;
+	uint16_t	flags;
+#define	RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE		(0x1 << 0)
+#define	RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT	0
+#define	RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE		(0x1 << 1)
+#define	RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT	1
+#define	__RSS_UPDATE_CONFIG_RESERVED0			(0x3FFF << 2)
+#define	__RSS_UPDATE_CONFIG_RESERVED0_SHIFT		2
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	flags;
+#define	RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE		(0x1 << 0)
+#define	RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT	0
+#define	RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE		(0x1 << 1)
+#define	RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT	1
+#define	__RSS_UPDATE_CONFIG_RESERVED0			(0x3FFF << 2)
+#define	__RSS_UPDATE_CONFIG_RESERVED0_SHIFT		2
+	uint16_t	toe_rss_bitmap;
+#endif
+	uint32_t	reserved1;
+};
+
+/*
+ * Parameters for eth update ramrod.
+ */
+struct eth_update_ramrod_data {
+	struct tstorm_eth_function_common_config	func_config;
+	uint8_t				indirectionTable[128];
+	struct rss_update_config	rss_config;
+};
+
+/*
+ * MAC filtering configuration command header.
+ */
+struct mac_configuration_hdr {
+	uint8_t		length;
+	uint8_t		offset;
+	uint16_t	client_id;
+	uint32_t	reserved1;
+};
+
+/*
+ * MAC address in list for ramrod.
+ */
+struct tstorm_cam_entry {
+	uint16_t	lsb_mac_addr;
+	uint16_t	middle_mac_addr;
+	uint16_t	msb_mac_addr;
+	uint16_t	flags;
+#define	TSTORM_CAM_ENTRY_PORT_ID		(0x1 << 0)
+#define	TSTORM_CAM_ENTRY_PORT_ID_SHIFT		0
+#define	TSTORM_CAM_ENTRY_RSRVVAL0		(0x7 << 1)
+#define	TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT		1
+#define	TSTORM_CAM_ENTRY_RESERVED0		(0xFFF << 4)
+#define	TSTORM_CAM_ENTRY_RESERVED0_SHIFT	4
+};
+
+/*
+ * MAC filtering: CAM target table entry
+ */
+struct tstorm_cam_target_table_entry {
+	uint8_t		flags;
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST			(0x1 << 0)
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT		0
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL	(0x1 << 1)
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE		(0x1 << 2)
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT		2
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC			(0x1 << 3)
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT		3
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0			(0xF << 4)
+#define	TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT		4
+	uint8_t		reserved1;
+	uint16_t	vlan_id;
+	uint32_t	clients_bit_vector;
+};
+
+/*
+ * MAC address in list for ramrod.
+ */
+struct mac_configuration_entry {
+	struct tstorm_cam_entry	cam_entry;
+	struct tstorm_cam_target_table_entry	target_table_entry;
+};
+
+/*
+ * MAC filtering configuration command.
+ */
+struct mac_configuration_cmd {
+	struct mac_configuration_hdr	hdr;
+	struct mac_configuration_entry	config_table[64];
+};
+
+/*
+ * MAC address in list for ramrod.
+ */
+struct mac_configuration_entry_e1h {
+	uint16_t	lsb_mac_addr;
+	uint16_t	middle_mac_addr;
+	uint16_t	msb_mac_addr;
+	uint16_t	vlan_id;
+	uint16_t	e1hov_id;
+	uint8_t		reserved0;
+	uint8_t		flags;
+#define	MAC_CONFIGURATION_ENTRY_E1H_PORT			(0x1 << 0)
+#define	MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT			0
+#define	MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE			(0x1 << 1)
+#define	MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT		1
+#define	MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC			(0x1 << 2)
+#define	MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT		2
+#define	MAC_CONFIGURATION_ENTRY_E1H_RESERVED1			(0x1F << 3)
+#define	MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT		3
+	uint32_t	clients_bit_vector;
+};
+
+/*
+ * MAC filtering configuration command.
+ */
+struct mac_configuration_cmd_e1h {
+	struct mac_configuration_hdr	hdr;
+	struct mac_configuration_entry_e1h	config_table[32];
+};
+
+/*
+ * Approximate-match multicast filtering for E1H per function in Tstorm.
+ */
+struct tstorm_eth_approximate_match_multicast_filtering {
+	uint32_t	mcast_add_hash_bit_array[8];
+};
+
+/*
+ * Configuration parameters per client in Tstorm.
+ */
+struct tstorm_eth_client_config {
+#if defined(__BIG_ENDIAN)
+	uint8_t		reserved0;
+	uint8_t		statistics_counter_id;
+	uint16_t	mtu;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	mtu;
+	uint8_t		statistics_counter_id;
+	uint8_t		reserved0;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	drop_flags;
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR			(0x1 << 0)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT		0
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR		(0x1 << 1)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT		1
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0			(0x1 << 2)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT		2
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR		(0x1 << 3)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT		3
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED2			(0xFFF << 4)
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT		4
+	uint16_t	config_flags;
+#define	TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE		(0x1 << 0)
+#define	TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT		0
+#define	TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE		(0x1 << 1)
+#define	TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT		1
+#define	TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE		(0x1 << 2)
+#define	TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT	2
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED1			(0x1FFF << 3)
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT		3
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	config_flags;
+#define	TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE		(0x1 << 0)
+#define	TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT		0
+#define	TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE		(0x1 << 1)
+#define	TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT		1
+#define	TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE		(0x1 << 2)
+#define	TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT	2
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED1			(0x1FFF << 3)
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT		3
+	uint16_t	drop_flags;
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR			(0x1 << 0)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT		0
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR		(0x1 << 1)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT		1
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0			(0x1 << 2)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT		2
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR		(0x1 << 3)
+#define	TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT		3
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED2			(0xFFF << 4)
+#define	__TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT		4
+#endif
+};
+
+/*
+ * MAC filtering configuration parameters per port in Tstorm.
+ */
+struct tstorm_eth_mac_filter_config {
+	uint32_t	ucast_drop_all;
+	uint32_t	ucast_accept_all;
+	uint32_t	mcast_drop_all;
+	uint32_t	mcast_accept_all;
+	uint32_t	bcast_drop_all;
+	uint32_t	bcast_accept_all;
+	uint32_t	strict_vlan;
+	uint32_t	vlan_filter[2];
+	uint32_t	reserved;
+};
+
+
+/*
+ * Common flag to indicate existance of TPA.
+ */
+struct tstorm_eth_tpa_exist {
+#if defined(__BIG_ENDIAN)
+	uint16_t	reserved1;
+	uint8_t		reserved0;
+	uint8_t		tpa_exist;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		tpa_exist;
+	uint8_t		reserved0;
+	uint16_t	reserved1;
+#endif
+	uint32_t	reserved2;
+};
+
+/*
+ * rx rings pause data for E1h only.
+ */
+struct ustorm_eth_rx_pause_data_e1h {
+#if defined(__BIG_ENDIAN)
+	uint16_t	bd_thr_low;
+	uint16_t	cqe_thr_low;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	cqe_thr_low;
+	uint16_t	bd_thr_low;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	cos;
+	uint16_t	sge_thr_low;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	sge_thr_low;
+	uint16_t	cos;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	bd_thr_high;
+	uint16_t	cqe_thr_high;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	cqe_thr_high;
+	uint16_t	bd_thr_high;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	reserved0;
+	uint16_t	sge_thr_high;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	sge_thr_high;
+	uint16_t	reserved0;
+#endif
+};
+
+/*
+ * Three RX producers for ETH.
+ */
+struct ustorm_eth_rx_producers {
+#if defined(__BIG_ENDIAN)
+	uint16_t	bd_prod;
+	uint16_t	cqe_prod;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	cqe_prod;
+	uint16_t	bd_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t	reserved;
+	uint16_t	sge_prod;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	sge_prod;
+	uint16_t	reserved;
+#endif
+};
+
+/*
+ * Per-port SAFC demo variables.
+ */
+struct cmng_flags_per_port {
+	uint8_t		con_number[NUM_OF_PROTOCOLS];
+	uint32_t	cmng_enables;
+#define	CMNG_FLAGS_PER_PORT_FAIRNESS_VN			(0x1 << 0)
+#define	CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT		0
+#define	CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN		(0x1 << 1)
+#define	CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT	1
+#define	CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL		(0x1 << 2)
+#define	CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT	2
+#define	CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL	(0x1 << 3)
+#define	CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT	3
+#define	CMNG_FLAGS_PER_PORT_FAIRNESS_COS		(0x1 << 4)
+#define	CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT		4
+#define	__CMNG_FLAGS_PER_PORT_RESERVED0			(0x7FFFFFF << 5)
+#define	__CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT		5
+};
+
+/*
+ * Per-port rate shaping variables.
+ */
+struct rate_shaping_vars_per_port {
+	uint32_t	rs_periodic_timeout;
+	uint32_t	rs_threshold;
+};
+
+/*
+ * Per-port fairness variables.
+ */
+struct fairness_vars_per_port {
+	uint32_t	upper_bound;
+	uint32_t	fair_threshold;
+	uint32_t	fairness_timeout;
+};
+
+/*
+ * Per-port SAFC variables.
+ */
+struct safc_struct_per_port {
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved1;
+	uint8_t		__reserved0;
+	uint8_t		safc_timeout_usec;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		safc_timeout_usec;
+	uint8_t		__reserved0;
+	uint16_t	__reserved1;
+#endif
+	uint16_t	cos_to_pause_mask[NUM_OF_SAFC_BITS];
+};
+
+/*
+ * Per-port congestion management variables.
+ */
+struct cmng_struct_per_port {
+	struct rate_shaping_vars_per_port	rs_vars;
+	struct fairness_vars_per_port	fair_vars;
+	struct safc_struct_per_port	safc_vars;
+	struct cmng_flags_per_port	flags;
+};
+
+/*
+ * Dynamic host coalescing init parameters.
+ */
+struct dynamic_hc_config {
+	uint32_t	threshold[3];
+	uint8_t		shift_per_protocol[HC_USTORM_SB_NUM_INDICES];
+	uint8_t		hc_timeout0[HC_USTORM_SB_NUM_INDICES];
+	uint8_t		hc_timeout1[HC_USTORM_SB_NUM_INDICES];
+	uint8_t		hc_timeout2[HC_USTORM_SB_NUM_INDICES];
+	uint8_t		hc_timeout3[HC_USTORM_SB_NUM_INDICES];
+};
+
+/*
+ * Protocol-common statistics collected by the Xstorm (per client).
+ */
+struct xstorm_per_client_stats {
+	uint32_t	reserved0;
+	uint32_t	unicast_pkts_sent;
+	struct regpair	unicast_bytes_sent;
+	struct regpair	multicast_bytes_sent;
+	uint32_t	multicast_pkts_sent;
+	uint32_t	broadcast_pkts_sent;
+	struct regpair	broadcast_bytes_sent;
+	uint16_t	stats_counter;
+	uint16_t	reserved1;
+	uint32_t	reserved2;
+};
+
+/*
+ * Common statistics collected by the Xstorm (per port).
+ */
+struct xstorm_common_stats {
+	struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
+};
+
+/*
+ * Protocol-common statistics collected by the Tstorm (per port).
+ */
+struct tstorm_per_port_stats {
+	uint32_t	mac_filter_discard;
+	uint32_t	xxoverflow_discard;
+	uint32_t	brb_truncate_discard;
+	uint32_t	mac_discard;
+};
+
+/*
+ * Protocol-common statistics collected by the Tstorm (per client).
+ */
+struct tstorm_per_client_stats {
+	struct regpair	rcv_unicast_bytes;
+	struct regpair	rcv_broadcast_bytes;
+	struct regpair	rcv_multicast_bytes;
+	struct regpair	rcv_error_bytes;
+	uint32_t	checksum_discard;
+	uint32_t	packets_too_big_discard;
+	uint32_t	rcv_unicast_pkts;
+	uint32_t	rcv_broadcast_pkts;
+	uint32_t	rcv_multicast_pkts;
+	uint32_t	no_buff_discard;
+	uint32_t	ttl0_discard;
+	uint16_t	stats_counter;
+	uint16_t	reserved0;
+};
+
+/*
+ * Protocol-common statistics collected by the Tstorm.
+ */
+struct tstorm_common_stats {
+	struct tstorm_per_port_stats	port_statistics;
+	struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
+};
+
+/*
+ * Protocol-common statistics collected by the Ustorm (per client).
+ */
+struct ustorm_per_client_stats {
+	struct regpair	ucast_no_buff_bytes;
+	struct regpair	mcast_no_buff_bytes;
+	struct regpair	bcast_no_buff_bytes;
+	uint32_t	ucast_no_buff_pkts;
+	uint32_t	mcast_no_buff_pkts;
+	uint32_t	bcast_no_buff_pkts;
+	uint16_t	stats_counter;
+	uint16_t	reserved0;
+};
+
+/*
+ * Protocol-common statistics collected by the Ustorm.
+ */
+struct ustorm_common_stats {
+	struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
+};
+
+/*
+ * Eth statistics query structure for the eth_stats_query ramrod.
+ */
+struct eth_stats_query {
+	struct xstorm_common_stats	xstorm_common;
+	struct tstorm_common_stats	tstorm_common;
+	struct ustorm_common_stats	ustorm_common;
+};
+
+/*
+ * Per-vnic fairness variables.
+ */
+struct fairness_vars_per_vn {
+	uint32_t	cos_credit_delta[MAX_COS_NUMBER];
+	uint32_t	protocol_credit_delta[NUM_OF_PROTOCOLS];
+	uint32_t	vn_credit_delta;
+	uint32_t	__reserved0;
+};
+
+/*
+ * FW version stored in the Xstorm RAM.
+ */
+struct fw_version {
+#if defined(__BIG_ENDIAN)
+	uint8_t		engineering;
+	uint8_t		revision;
+	uint8_t		minor;
+	uint8_t		major;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t		major;
+	uint8_t		minor;
+	uint8_t		revision;
+	uint8_t		engineering;
+#endif
+	uint32_t	flags;
+#define	FW_VERSION_OPTIMIZED			(0x1 << 0)
+#define	FW_VERSION_OPTIMIZED_SHIFT		0
+#define	FW_VERSION_BIG_ENDIEN			(0x1 << 1)
+#define	FW_VERSION_BIG_ENDIEN_SHIFT		1
+#define	FW_VERSION_CHIP_VERSION			(0x3 << 2)
+#define	FW_VERSION_CHIP_VERSION_SHIFT		2
+#define	__FW_VERSION_RESERVED			(0xFFFFFFF << 4)
+#define	__FW_VERSION_RESERVED_SHIFT		4
+};
+
+/*
+ * FW version stored in first line of pram.
+ */
+struct pram_fw_version {
+	uint8_t		major;
+	uint8_t		minor;
+	uint8_t		revision;
+	uint8_t		engineering;
+	uint8_t		flags;
+#define	PRAM_FW_VERSION_OPTIMIZED		(0x1 << 0)
+#define	PRAM_FW_VERSION_OPTIMIZED_SHIFT		0
+#define	PRAM_FW_VERSION_STORM_ID		(0x3 << 1)
+#define	PRAM_FW_VERSION_STORM_ID_SHIFT		1
+#define	PRAM_FW_VERSION_BIG_ENDIEN		(0x1 << 3)
+#define	PRAM_FW_VERSION_BIG_ENDIEN_SHIFT	3
+#define	PRAM_FW_VERSION_CHIP_VERSION		(0x3 << 4)
+#define	PRAM_FW_VERSION_CHIP_VERSION_SHIFT	4
+#define	__PRAM_FW_VERSION_RESERVED0		(0x3 << 6)
+#define	__PRAM_FW_VERSION_RESERVED0_SHIFT	6
+};
+
+/*
+ * The send queue element.
+ */
+struct protocol_common_spe {
+	struct spe_hdr	hdr;
+	struct regpair	phy_address;
+};
+
+/*
+ * A single rate shaping counter. can be used as protocol or vnic counter.
+ */
+struct rate_shaping_counter {
+	uint32_t	quota;
+#if defined(__BIG_ENDIAN)
+	uint16_t	__reserved0;
+	uint16_t	rate;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t	rate;
+	uint16_t	__reserved0;
+#endif
+};
+
+/*
+ * Per-vnic rate shaping variables.
+ */
+struct rate_shaping_vars_per_vn {
+	struct rate_shaping_counter	protocol_counters[NUM_OF_PROTOCOLS];
+	struct rate_shaping_counter	vn_counter;
+};
+
+/*
+ * The send queue element.
+ */
+struct slow_path_element {
+	struct spe_hdr	hdr;
+	uint8_t		protocol_data[8];
+};
+
+/*
+ * eth/toe flags that indicate if to query.
+ */
+struct stats_indication_flags {
+	uint32_t	collect_eth;
+	uint32_t	collect_toe;
+};
+
+
diff --git a/sys/dev/bxe/bxe_include.h b/sys/dev/bxe/bxe_include.h
new file mode 100755
index 0000000..79e632b
--- /dev/null
+++ b/sys/dev/bxe/bxe_include.h
@@ -0,0 +1,163 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef _BXE_INCLUDE_H
+#define _BXE_INCLUDE_H
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/endian.h>
+
+#include <machine/bus.h>
+
+/*
+ * Convert FreeBSD byte order to match generated code usage.
+ */
+#if BYTE_ORDER == BIG_ENDIAN
+#define __BIG_ENDIAN 1
+#undef  __LITTLE_ENDIAN
+#else
+#undef  __BIG_ENDIAN
+#define __LITTLE_ENDIAN 1
+#endif
+
+#include "bxe_debug.h"
+#include "bxe_reg.h"
+#include "bxe_fw_defs.h"
+#include "bxe_hsi.h"
+#include "bxe_link.h"
+
+/*
+ * Convenience definitions used in multiple files.
+ */
+#define BXE_PRINTF(fmt, args...)				\
+	do {										\
+		device_printf(sc->bxe_dev, fmt, ##args);\
+	}while(0)
+
+
+#ifdef BXE_DEBUG
+
+#define REG_WR(sc, offset, val)		\
+	bxe_reg_write32(sc, offset, val)
+#define REG_WR8(sc, offset, val)	\
+	bxe_reg_write8(sc, offset, val)
+#define REG_WR16(sc, offset, val)	\
+	bxe_reg_write16(sc, offset, val)
+#define REG_WR32(sc, offset, val)	\
+	bxe_reg_write32(sc, offset, val)
+
+#define REG_RD(sc, offset)			\
+	bxe_reg_read32(sc, offset)
+#define REG_RD8(sc, offset)			\
+	bxe_reg_read8(sc, offset)
+#define REG_RD16(sc, offset)			\
+	bxe_reg_read16(sc, offset)
+#define REG_RD32(sc, offset)			\
+	bxe_reg_read32(sc, offset)
+
+#define REG_RD_IND(sc, offset)		\
+	bxe_reg_rd_ind(sc, offset)
+#define REG_WR_IND(sc, offset, val)	\
+	bxe_reg_wr_ind(sc, offset, val)
+
+#else
+
+#define REG_WR(sc, offset, val)		\
+	bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
+#define REG_WR8(sc, offset, val)	\
+	bus_space_write_1(sc->bxe_btag, sc->bxe_bhandle, offset, val)
+#define REG_WR16(sc, offset, val)	\
+	bus_space_write_2(sc->bxe_btag, sc->bxe_bhandle, offset, val)
+#define REG_WR32(sc, offset, val)		\
+	bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val)
+
+#define REG_RD(sc, offset)			\
+	bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
+#define REG_RD8(sc, offset)			\
+	bus_space_read_1(sc->bxe_btag, sc->bxe_bhandle, offset)
+#define REG_RD16(sc, offset)			\
+	bus_space_read_2(sc->bxe_btag, sc->bxe_bhandle, offset)
+#define REG_RD32(sc, offset)			\
+	bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset)
+
+#define REG_RD_IND(sc, offset)		\
+	bxe_reg_rd_ind(sc, offset)
+#define REG_WR_IND(sc, offset, val)	\
+	bxe_reg_wr_ind(sc, offset, val)
+
+#endif /* BXE_DEBUG */
+
+
+#define REG_RD_DMAE(sc, offset, val, len32)				\
+	do {												\
+		bxe_read_dmae(sc, offset, len32);				\
+		memcpy(val, BXE_SP(sc, wb_data[0]), len32 * 4); \
+	} while (0)
+
+
+#define REG_WR_DMAE(sc, offset, val, len32)				\
+	do { 												\
+		memcpy(BXE_SP(sc, wb_data[0]), val, len32 * 4); \
+		bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), \
+			offset, len32);								\
+	} while (0)
+
+
+#define SHMEM_ADDR(sc, field)	(sc->common.shmem_base + \
+	offsetof(struct shmem_region, field))
+
+#define SHMEM_RD(sc, field) \
+	REG_RD(sc, SHMEM_ADDR(sc, field))
+#define SHMEM_RD16(sc, field) \
+	REG_RD16(sc, SHMEM_ADDR(sc, field))
+
+#define SHMEM_WR(sc, field, val) \
+	REG_WR(sc, SHMEM_ADDR(sc, field), val)
+
+#define SHMEM2_ADDR(sc, field)		(sc->common.shmem2_base + \
+									 offsetof(struct shmem2_region, field))
+#define SHMEM2_RD(sc, field)		REG_RD(sc, SHMEM2_ADDR(sc, field))
+#define SHMEM2_WR(sc, field, val)	REG_WR(sc, SHMEM2_ADDR(sc, field), val)
+
+
+#define EMAC_RD(sc, reg) \
+	REG_RD(sc, emac_base + (uint32_t) reg)
+#define EMAC_WR(sc, reg, val) \
+	REG_WR(sc, emac_base + (uint32_t) reg, val)
+
+#define BMAC_WR(sc, reg, val) \
+	REG_WR(sc, GRCBASE_NIG + bmac_addr + reg, val)
+
+#endif /* _BXE_INCLUDE_H */
diff --git a/sys/dev/bxe/bxe_init.h b/sys/dev/bxe/bxe_init.h
new file mode 100755
index 0000000..f40f316
--- /dev/null
+++ b/sys/dev/bxe/bxe_init.h
@@ -0,0 +1,177 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef BXE_INIT_H
+#define	BXE_INIT_H
+/*
+ * bxe_init.h: Broadcom Everest network driver.
+ * Structures and macros needed during the initialization.
+ */
+
+/* RAM0 size in bytes */
+#define	STORM_INTMEM_SIZE_E1		0x5800
+#define	STORM_INTMEM_SIZE_E1H		0x10000
+#define	STORM_INTMEM_SIZE(sc)		\
+	((CHIP_IS_E1(sc) ? STORM_INTMEM_SIZE_E1 : STORM_INTMEM_SIZE_E1H) / 4)
+
+
+/* Init operation types and structures */
+/* Common for both E1 and E1H */
+#define	OP_RD			0x1 /* read single register */
+#define	OP_WR			0x2 /* write single register */
+#define	OP_IW			0x3 /* write single register using mailbox */
+#define	OP_SW			0x4 /* copy a string to the device */
+#define	OP_SI			0x5 /* copy a string using mailbox */
+#define	OP_ZR			0x6 /* clear memory */
+#define	OP_ZP			0x7 /* unzip then copy with DMAE */
+#define	OP_WR_64		0x8 /* write 64 bit pattern */
+#define	OP_WB			0x9 /* copy a string using DMAE */
+
+/* FPGA and EMUL specific operations */
+#define	OP_WR_EMUL		0xa /* write single register on Emulation */
+#define	OP_WR_FPGA		0xb /* write single register on FPGA */
+#define	OP_WR_ASIC		0xc /* write single register on ASIC */
+
+/* Init stages */
+/* Never reorder stages !!! */
+#define	COMMON_STAGE		0
+#define	PORT0_STAGE		1
+#define	PORT1_STAGE		2
+#define	FUNC0_STAGE		3
+#define	FUNC1_STAGE		4
+#define	FUNC2_STAGE		5
+#define	FUNC3_STAGE		6
+#define	FUNC4_STAGE		7
+#define	FUNC5_STAGE		8
+#define	FUNC6_STAGE		9
+#define	FUNC7_STAGE		10
+#define	STAGE_IDX_MAX		11
+
+#define	STAGE_START		0
+#define	STAGE_END		1
+
+
+/* Indices of blocks */
+#define	PRS_BLOCK		0
+#define	SRCH_BLOCK		1
+#define	TSDM_BLOCK		2
+#define	TCM_BLOCK		3
+#define	BRB1_BLOCK		4
+#define	TSEM_BLOCK		5
+#define	PXPCS_BLOCK		6
+#define	EMAC0_BLOCK		7
+#define	EMAC1_BLOCK		8
+#define	DBU_BLOCK		9
+#define	MISC_BLOCK		10
+#define	DBG_BLOCK		11
+#define	NIG_BLOCK		12
+#define	MCP_BLOCK		13
+#define	UPB_BLOCK		14
+#define	CSDM_BLOCK		15
+#define	USDM_BLOCK		16
+#define	CCM_BLOCK		17
+#define	UCM_BLOCK		18
+#define	USEM_BLOCK		19
+#define	CSEM_BLOCK		20
+#define	XPB_BLOCK		21
+#define	DQ_BLOCK		22
+#define	TIMERS_BLOCK		23
+#define	XSDM_BLOCK		24
+#define	QM_BLOCK		25
+#define	PBF_BLOCK		26
+#define	XCM_BLOCK		27
+#define	XSEM_BLOCK		28
+#define	CDU_BLOCK		29
+#define	DMAE_BLOCK		30
+#define	PXP_BLOCK		31
+#define	CFC_BLOCK		32
+#define	HC_BLOCK		33
+#define	PXP2_BLOCK		34
+#define	MISC_AEU_BLOCK		35
+#define	PGLUE_B_BLOCK		36
+#define	IGU_BLOCK		37
+
+/* Returns the index of start or end of a specific block stage in ops array. */
+#define	BLOCK_OPS_IDX(block, stage, end)	\
+	(2 * (((block) * STAGE_IDX_MAX) + (stage)) + (end))
+
+struct raw_op {
+	uint32_t	op:8;
+	uint32_t	offset:24;
+	uint32_t	raw_data;
+};
+
+struct op_read {
+	uint32_t	op:8;
+	uint32_t	offset:24;
+	uint32_t	pad;
+};
+
+struct op_write {
+	uint32_t	op:8;
+	uint32_t	offset:24;
+	uint32_t	val;
+};
+
+struct op_string_write {
+	uint32_t	op:8;
+	uint32_t	offset:24;
+#ifdef __LITTLE_ENDIAN
+	uint16_t	data_off;
+	uint16_t	data_len;
+#else /* __BIG_ENDIAN */
+	uint16_t	data_len;
+	uint16_t	data_off;
+#endif
+};
+
+struct op_zero {
+	uint32_t	op:8;
+	uint32_t	offset:24;
+	uint32_t	len;
+};
+
+union init_op {
+	struct op_read		read;
+	struct op_write		write;
+	struct op_string_write	str_wr;
+	struct op_zero		zero;
+	struct raw_op		raw;
+};
+
+#include "bxe_init_values_e1.h"
+#include "bxe_init_values_e1h.h"
+
+#endif /* BXE_INIT_H */
+
diff --git a/sys/dev/bxe/bxe_init_values_e1.h b/sys/dev/bxe/bxe_init_values_e1.h
new file mode 100755
index 0000000..ebde6d5
--- /dev/null
+++ b/sys/dev/bxe/bxe_init_values_e1.h
@@ -0,0 +1,30346 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef __BXE_INIT_VALUES_E1_H__
+#define	__BXE_INIT_VALUES_E1_H__
+
+/* bxe_init_values_e1.h: Broadcom NX2 10G network driver.
+ * This array contains the list of operations needed to initialize the chip.
+ *
+ * For each block in the chip there are three init stages:
+ * common - HW used by both ports,
+ * port1 and port2 - initialization for a specific Ethernet port.
+ * When a port is opened or closed, the management CPU tells the driver
+ * whether to init/disable common HW in addition to the port HW.
+ * This way the first port going up will first initializes the common HW,
+ * and the last port going down also resets the common HW
+ *
+ * For each init stage/block there is a list of actions needed in a format:
+ * {operation, register, data}
+ * where:
+ * OP_WR - write a value to the chip.
+ * OP_RD - read a register (usually a clear on read register).
+ * OP_SW - string write, write a section of consecutive addresses to the chip.
+ * OP_SI - copy a string using indirect writes.
+ * OP_ZR - clear a range of memory.
+ * OP_ZP - unzip and copy using DMAE.
+ * OP_WB - string copy using DMAE.
+ *
+ * The #defines mark the stages.
+ *
+ */
+#include "bxe_init.h"
+#include "if_bxe.h"
+
+static struct raw_op init_ops_e1[] = {
+/* #define PRS_COMMON_START        0 */
+	{OP_WR, PRS_REG_INC_VALUE, 0xf},
+	{OP_WR, PRS_REG_EVENT_ID_1, 0x45},
+	{OP_WR, PRS_REG_EVENT_ID_2, 0x84},
+	{OP_WR, PRS_REG_EVENT_ID_3, 0x6},
+	{OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
+	{OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
+	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
+	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
+	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
+	{OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
+	{OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
+	{OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
+	{OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
+	{OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
+	{OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
+	{OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
+	{OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
+	{OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
+/* #define PRS_COMMON_END          1 */
+/* #define TSDM_COMMON_START       44 */
+	{OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
+	{OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
+	{OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
+	{OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2},
+	{OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
+	{OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
+	{OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
+	{OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+	{OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
+/* #define TSDM_COMMON_END         45 */
+/* #define TCM_COMMON_START        66 */
+	{OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
+	{OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
+	{OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
+	{OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
+	{OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
+	{OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
+	{OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
+	{OP_WR, TCM_REG_STORM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_PRS_WEIGHT, 0x5},
+	{OP_WR, TCM_REG_PBF_WEIGHT, 0x6},
+	{OP_WR, TCM_REG_USEM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_CSEM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_CP_WEIGHT, 0x0},
+	{OP_WR, TCM_REG_TSDM_WEIGHT, 0x5},
+	{OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_TM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
+	{OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, TCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, TCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
+	{OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
+	{OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
+	{OP_ZR, TCM_REG_XX_TABLE, 0xa},
+	{OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
+	{OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4},
+	{OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
+	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd},
+	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x7},
+	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x27},
+	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x7},
+	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x27},
+	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x7},
+	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x27},
+	{OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
+	{OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
+	{OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
+	{OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
+	{OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
+	{OP_WR, TCM_REG_TSDM_IFEN, 0x1},
+	{OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
+	{OP_WR, TCM_REG_PRS_IFEN, 0x1},
+	{OP_WR, TCM_REG_PBF_IFEN, 0x1},
+	{OP_WR, TCM_REG_USEM_IFEN, 0x1},
+	{OP_WR, TCM_REG_CSEM_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
+/* #define TCM_COMMON_END          67 */
+/* #define BRB1_COMMON_START       88 */
+	{OP_SW, BRB1_REG_LL_RAM, 0x2000020},
+	{OP_WR, BRB1_REG_SOFT_RESET, 0x1},
+	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
+	{OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
+	{OP_WR, BRB1_REG_SOFT_RESET, 0x0},
+/* #define BRB1_COMMON_END         89 */
+/* #define BRB1_PORT0_START        90 */
+	{OP_WR, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8},
+	{OP_WR, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114},
+	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
+	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
+/* #define BRB1_PORT0_END          91 */
+/* #define BRB1_PORT1_START        92 */
+	{OP_WR, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8},
+	{OP_WR, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114},
+	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
+	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
+/* #define BRB1_PORT1_END          93 */
+/* #define TSEM_COMMON_START       110 */
+	{OP_WB, TSEM_REG_INT_TABLE, 0xd80000},
+	{OP_WR_64, TSEM_REG_INT_TABLE + 0x360, 0x140223},
+	{OP_WB, TSEM_REG_PRAM, 0x45180000},
+	{OP_WR_64, TSEM_REG_PRAM + 0x11460, 0x5d740225},
+	{OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, TSEM_REG_TS_0_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_1_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_2_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_3_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_4_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_5_AS, 0x3},
+	{OP_WR, TSEM_REG_TS_6_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_7_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_8_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_9_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_10_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_11_AS, 0x3},
+	{OP_WR, TSEM_REG_TS_12_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_13_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_14_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_15_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_16_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, TSEM_REG_TS_18_AS, 0x2},
+	{OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, TSEM_REG_THREADS_LIST, 0xff},
+	{OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+	{OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+	{OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+	{OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x23c8, 0x181},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x604, 0x10227},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1e38, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1e30, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x50228},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x8022d},
+/* #define TSEM_COMMON_END         111 */
+/* #define TSEM_PORT0_START        112 */
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x124},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x4920, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1400, 0xa},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1450, 0x6},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1500, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x50235},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1500 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1580, 0x14},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x9c0, 0x48},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x820, 0xe},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x2023a},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2c28, 0x2},
+/* #define TSEM_PORT0_END          113 */
+/* #define TSEM_PORT1_START        114 */
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2348, 0x20},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4490, 0x124},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x4924, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1428, 0xa},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1468, 0x6},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1540, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x1540 + 0x8, 0x5023c},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1540 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x15d0, 0x14},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xae0, 0x48},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x858, 0xe},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20241},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2c30, 0x2},
+/* #define TSEM_PORT1_END          115 */
+/* #define MISC_COMMON_START       220 */
+	{OP_WR, MISC_REG_GRC_TIMEOUT_EN, 0x1},
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
+	{OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
+	{OP_WR, MISC_REG_SPIO, 0xff000000},
+/* #define MISC_COMMON_END         221 */
+/* #define NIG_COMMON_START        264 */
+	{OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
+	{OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
+	{OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
+	{OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
+	{OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
+/* #define NIG_COMMON_END          265 */
+/* #define NIG_PORT0_START         266 */
+	{OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
+	{OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
+	{OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
+	{OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
+	{OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
+	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
+	{OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
+	{OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
+	{OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
+	{OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
+	{OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
+/* #define NIG_PORT0_END           267 */
+/* #define NIG_PORT1_START         268 */
+	{OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
+	{OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
+	{OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
+	{OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
+	{OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
+	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
+	{OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
+	{OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
+	{OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
+	{OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
+	{OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
+/* #define NIG_PORT1_END           269 */
+/* #define UPB_COMMON_START        308 */
+	{OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
+/* #define UPB_COMMON_END          309 */
+/* #define CSDM_COMMON_START       330 */
+	{OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
+	{OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
+	{OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x2},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_4, 0x20},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_5, 0x21},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_6, 0x22},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_7, 0x23},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_8, 0x24},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_9, 0x25},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_10, 0x26},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_11, 0x27},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_12, 0x28},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_13, 0x29},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_14, 0x2a},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_15, 0x2b},
+	{OP_ZR, CSDM_REG_AGG_INT_EVENT_16, 0x56},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_6, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_7, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_8, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_9, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_10, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_11, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_12, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_13, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_14, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_15, 0x1},
+	{OP_ZR, CSDM_REG_AGG_INT_MODE_16, 0x10},
+	{OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+	{OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
+/* #define CSDM_COMMON_END         331 */
+/* #define USDM_COMMON_START       352 */
+	{OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0x365},
+	{OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0x354},
+	{OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0x358},
+	{OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0x375},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
+	{OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
+	{OP_ZR, USDM_REG_AGG_INT_EVENT_2, 0x5e},
+	{OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
+	{OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f},
+	{OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+	{OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
+/* #define USDM_COMMON_END         353 */
+/* #define CCM_COMMON_START        374 */
+	{OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
+	{OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
+	{OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
+	{OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, CCM_REG_STORM_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
+	{OP_WR, CCM_REG_XSEM_WEIGHT, 0x5},
+	{OP_WR, CCM_REG_USEM_WEIGHT, 0x5},
+	{OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_CSDM_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3},
+	{OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
+	{OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
+	{OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
+	{OP_WR, CCM_REG_INV_DONE_Q, 0x1},
+	{OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, CCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, CCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
+	{OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
+	{OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
+	{OP_ZR, CCM_REG_XX_TABLE, 0x12},
+	{OP_SW, CCM_REG_XX_DESCR_TABLE, 0x240243},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
+	{OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
+	{OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
+	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc},
+	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0xc},
+	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2c},
+	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0xc},
+	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x2c},
+	{OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
+	{OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
+	{OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
+	{OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
+	{OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
+	{OP_WR, CCM_REG_CSDM_IFEN, 0x1},
+	{OP_WR, CCM_REG_TSEM_IFEN, 0x1},
+	{OP_WR, CCM_REG_XSEM_IFEN, 0x1},
+	{OP_WR, CCM_REG_USEM_IFEN, 0x1},
+	{OP_WR, CCM_REG_PBF_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
+/* #define CCM_COMMON_END          375 */
+/* #define UCM_COMMON_START        396 */
+	{OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
+	{OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
+	{OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
+	{OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
+	{OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
+	{OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
+	{OP_WR, UCM_REG_STORM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_TSEM_WEIGHT, 0x4},
+	{OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
+	{OP_WR, UCM_REG_XSEM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_DORQ_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_CP_WEIGHT, 0x0},
+	{OP_WR, UCM_REG_USDM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7},
+	{OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_TM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
+	{OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
+	{OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, UCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, UCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
+	{OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
+	{OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
+	{OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
+	{OP_ZR, UCM_REG_XX_TABLE, 0x12},
+	{OP_SW, UCM_REG_XX_DESCR_TABLE, 0x1b0267},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xc},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x9},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
+	{OP_ZR, UCM_REG_N_SM_CTX_LD_4, 0x4},
+	{OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
+	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf},
+	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe},
+	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e},
+	{OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
+	{OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
+	{OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
+	{OP_WR, UCM_REG_USDM_IFEN, 0x1},
+	{OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
+	{OP_WR, UCM_REG_TSEM_IFEN, 0x1},
+	{OP_WR, UCM_REG_CSEM_IFEN, 0x1},
+	{OP_WR, UCM_REG_XSEM_IFEN, 0x1},
+	{OP_WR, UCM_REG_DORQ_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
+/* #define UCM_COMMON_END          397 */
+/* #define USEM_COMMON_START       418 */
+	{OP_WB, USEM_REG_INT_TABLE, 0xda0000},
+	{OP_WR_64, USEM_REG_INT_TABLE + 0x368, 0x130282},
+	{OP_WB, USEM_REG_PRAM, 0x5cbc0000},
+	{OP_WR_64, USEM_REG_PRAM + 0x172f0, 0x51a20284},
+	{OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, USEM_REG_TS_0_AS, 0x0},
+	{OP_WR, USEM_REG_TS_1_AS, 0x1},
+	{OP_WR, USEM_REG_TS_2_AS, 0x4},
+	{OP_WR, USEM_REG_TS_3_AS, 0x0},
+	{OP_WR, USEM_REG_TS_4_AS, 0x1},
+	{OP_WR, USEM_REG_TS_5_AS, 0x3},
+	{OP_WR, USEM_REG_TS_6_AS, 0x0},
+	{OP_WR, USEM_REG_TS_7_AS, 0x1},
+	{OP_WR, USEM_REG_TS_8_AS, 0x4},
+	{OP_WR, USEM_REG_TS_9_AS, 0x0},
+	{OP_WR, USEM_REG_TS_10_AS, 0x1},
+	{OP_WR, USEM_REG_TS_11_AS, 0x3},
+	{OP_WR, USEM_REG_TS_12_AS, 0x0},
+	{OP_WR, USEM_REG_TS_13_AS, 0x1},
+	{OP_WR, USEM_REG_TS_14_AS, 0x4},
+	{OP_WR, USEM_REG_TS_15_AS, 0x0},
+	{OP_WR, USEM_REG_TS_16_AS, 0x4},
+	{OP_WR, USEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, USEM_REG_TS_18_AS, 0x2},
+	{OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, USEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, USEM_REG_THREADS_LIST, 0xffff},
+	{OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+	{OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
+	{OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+	{OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1aa0, 0xc2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1400, 0x40},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5098, 0x4},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5080, 0x5},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x5080 + 0x14, 0x10286},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x2830, 0x20287},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x100289},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x100299},
+/* #define USEM_COMMON_END         419 */
+/* #define USEM_PORT0_START        420 */
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1500, 0xb4},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x1dc8, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4000, 0xd8},
+/* #define USEM_PORT0_END          421 */
+/* #define USEM_PORT1_START        422 */
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x17d0, 0xb4},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x1dcc, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4360, 0xd8},
+/* #define USEM_PORT1_END          423 */
+/* #define CSEM_COMMON_START       440 */
+	{OP_WB, CSEM_REG_INT_TABLE, 0xe00000},
+	{OP_WR_64, CSEM_REG_INT_TABLE + 0x380, 0x1002a9},
+	{OP_WB, CSEM_REG_PRAM, 0x37180000},
+	{OP_WR_64, CSEM_REG_PRAM + 0xdc60, 0x62da02ab},
+	{OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, CSEM_REG_TS_0_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_1_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_2_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_3_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_4_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_5_AS, 0x3},
+	{OP_WR, CSEM_REG_TS_6_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_7_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_8_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_9_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_10_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_11_AS, 0x3},
+	{OP_WR, CSEM_REG_TS_12_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_13_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_14_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_15_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_16_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, CSEM_REG_TS_18_AS, 0x2},
+	{OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
+	{OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x5000, 0x42},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
+	{OP_SW, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802ad},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
+	{OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002b5},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+	{OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002c5},
+/* #define CSEM_COMMON_END         441 */
+/* #define CSEM_PORT0_START        442 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3040, 0xa0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3540, 0x10},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x36c0, 0x30},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4000, 0x200},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x35c0, 0x20},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3840, 0x30},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3000, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x5118, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x2300, 0xe},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
+/* #define CSEM_PORT0_END          443 */
+/* #define CSEM_PORT1_START        444 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x32c0, 0xa0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3580, 0x10},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3780, 0x30},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4800, 0x200},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3640, 0x20},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3900, 0x30},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3020, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x511c, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x2338, 0xe},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
+/* #define CSEM_PORT1_END          445 */
+/* #define XPB_COMMON_START        462 */
+	{OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x28},
+/* #define XPB_COMMON_END          463 */
+/* #define DQ_COMMON_START         484 */
+	{OP_WR, DORQ_REG_MODE_ACT, 0x2},
+	{OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
+	{OP_WR, DORQ_REG_OUTST_REQ, 0x4},
+	{OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
+	{OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
+	{OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
+	{OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
+	{OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
+	{OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
+	{OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
+	{OP_WR, DORQ_REG_AGG_CMD1, 0x80},
+	{OP_WR, DORQ_REG_AGG_CMD2, 0x81},
+	{OP_WR, DORQ_REG_AGG_CMD3, 0x80},
+	{OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
+	{OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
+	{OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
+	{OP_WR, DORQ_REG_REGN, 0x7c1004},
+	{OP_WR, DORQ_REG_IF_EN, 0xf},
+/* #define DQ_COMMON_END           485 */
+/* #define TIMERS_COMMON_START     506 */
+	{OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
+	{OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
+	{OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
+	{OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
+	{OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
+	{OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
+	{OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
+	{OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
+	{OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x1},
+	{OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
+	{OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
+	{OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
+	{OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
+	{OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
+	{OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
+	{OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
+	{OP_WR, TM_REG_EN_TIMERS, 0x1},
+	{OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
+	{OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
+	{OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
+	{OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
+/* #define TIMERS_COMMON_END       507 */
+/* #define TIMERS_PORT0_START      508 */
+	{OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0},
+	{OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0},
+	{OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT0_END        509 */
+/* #define TIMERS_PORT1_START      510 */
+	{OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0},
+	{OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0},
+	{OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT1_END        511 */
+/* #define XSDM_COMMON_START       528 */
+	{OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
+	{OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
+	{OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0x604},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d},
+	{OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52},
+	{OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
+	{OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
+	{OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
+	{OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
+/* #define XSDM_COMMON_END         529 */
+/* #define QM_COMMON_START         550 */
+	{OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
+	{OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
+	{OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
+	{OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
+	{OP_WR, QM_REG_PCIREQAT, 0x2},
+	{OP_WR, QM_REG_CMINITCRD_0, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_1, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_2, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_3, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_4, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_5, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_6, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_7, 0x4},
+	{OP_WR, QM_REG_OUTLDREQ, 0x4},
+	{OP_WR, QM_REG_CTXREG_0, 0x7c},
+	{OP_WR, QM_REG_CTXREG_1, 0x3d},
+	{OP_WR, QM_REG_CTXREG_2, 0x3f},
+	{OP_WR, QM_REG_CTXREG_3, 0x9c},
+	{OP_WR, QM_REG_ENSEC, 0x7},
+	{OP_ZR, QM_REG_QVOQIDX_0, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_5, 0x0},
+	{OP_WR, QM_REG_QVOQIDX_6, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_7, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_8, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_9, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_10, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_11, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_12, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_13, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_14, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_15, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_16, 0x0},
+	{OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
+	{OP_ZR, QM_REG_QVOQIDX_17, 0x4},
+	{OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
+	{OP_ZR, QM_REG_QVOQIDX_21, 0x4},
+	{OP_WR, QM_REG_WRRWEIGHTS_5, 0x1010101},
+	{OP_ZR, QM_REG_QVOQIDX_25, 0x4},
+	{OP_WR, QM_REG_WRRWEIGHTS_6, 0x1010101},
+	{OP_ZR, QM_REG_QVOQIDX_29, 0x3},
+	{OP_WR, QM_REG_QVOQIDX_32, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_33, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_34, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_35, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_36, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_37, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_38, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_39, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_40, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_41, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_42, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_43, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_44, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_45, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_46, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_47, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_48, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
+	{OP_WR, QM_REG_QVOQIDX_49, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_50, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_51, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_52, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_53, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_54, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_55, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_56, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_13, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_57, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_58, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_59, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_60, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_14, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_61, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_62, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_63, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010101},
+	{OP_WR, QM_REG_VOQQMASK_0_LSB, 0xffff003f},
+	{OP_ZR, QM_REG_VOQQMASK_0_MSB, 0x2},
+	{OP_WR, QM_REG_VOQQMASK_1_MSB, 0xffff003f},
+	{OP_WR, QM_REG_VOQQMASK_2_LSB, 0x100},
+	{OP_WR, QM_REG_VOQQMASK_2_MSB, 0x100},
+	{OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
+	{OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc0},
+	{OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc0},
+	{OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e00},
+	{OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e00},
+	{OP_WR, QM_REG_VOQQMASK_6_LSB, 0x4000},
+	{OP_WR, QM_REG_VOQQMASK_6_MSB, 0x4000},
+	{OP_WR, QM_REG_VOQQMASK_7_LSB, 0x8000},
+	{OP_WR, QM_REG_VOQQMASK_7_MSB, 0x8000},
+	{OP_WR, QM_REG_VOQQMASK_8_LSB, 0x2000},
+	{OP_WR, QM_REG_VOQQMASK_8_MSB, 0x2000},
+	{OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x7},
+	{OP_WR, QM_REG_VOQPORT_1, 0x1},
+	{OP_ZR, QM_REG_VOQPORT_2, 0xa},
+	{OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
+	{OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
+	{OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
+	{OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
+	{OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
+	{OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
+	{OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
+	{OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
+	{OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff},
+	{OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff},
+	{OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
+	{OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
+	{OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
+	{OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
+	{OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
+	{OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
+	{OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
+	{OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
+	{OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
+	{OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
+	{OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
+	{OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
+	{OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
+	{OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
+	{OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
+	{OP_WR, QM_REG_ENBYTECRD_LSB, 0x7},
+	{OP_WR, QM_REG_ENBYTECRD_MSB, 0x7},
+	{OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
+	{OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
+	{OP_WR, QM_REG_FUNCNUMSEL_LSB, 0x0},
+	{OP_WR, QM_REG_FUNCNUMSEL_MSB, 0xffffffff},
+	{OP_WR, QM_REG_CMINTEN, 0xff},
+/* #define QM_COMMON_END           551 */
+/* #define PBF_COMMON_START        572 */
+	{OP_WR, PBF_REG_INIT, 0x1},
+	{OP_WR, PBF_REG_INIT_P4, 0x1},
+	{OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
+	{OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
+	{OP_WR, PBF_REG_INIT_P4, 0x0},
+	{OP_WR, PBF_REG_INIT, 0x0},
+	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
+/* #define PBF_COMMON_END          573 */
+/* #define PBF_PORT0_START         574 */
+	{OP_WR, PBF_REG_INIT_P0, 0x1},
+	{OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
+	{OP_WR, PBF_REG_INIT_P0, 0x0},
+	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
+/* #define PBF_PORT0_END           575 */
+/* #define PBF_PORT1_START         576 */
+	{OP_WR, PBF_REG_INIT_P1, 0x1},
+	{OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
+	{OP_WR, PBF_REG_INIT_P1, 0x0},
+	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
+/* #define PBF_PORT1_END           577 */
+/* #define XCM_COMMON_START        594 */
+	{OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
+	{OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
+	{OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
+	{OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
+	{OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
+	{OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
+	{OP_WR, XCM_REG_STORM_WEIGHT, 0x3},
+	{OP_WR, XCM_REG_TSEM_WEIGHT, 0x6},
+	{OP_WR, XCM_REG_CSEM_WEIGHT, 0x3},
+	{OP_WR, XCM_REG_USEM_WEIGHT, 0x3},
+	{OP_WR, XCM_REG_DORQ_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_PBF_WEIGHT, 0x0},
+	{OP_WR, XCM_REG_NIG0_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_CP_WEIGHT, 0x0},
+	{OP_WR, XCM_REG_XSDM_WEIGHT, 0x6},
+	{OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4},
+	{OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_TM_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
+	{OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
+	{OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
+	{OP_WR, XCM_REG_AUX1_Q, 0x2},
+	{OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
+	{OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, XCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, XCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
+	{OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
+	{OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
+	{OP_WR, XCM_REG_XX_MSG_NUM, 0x1f},
+	{OP_ZR, XCM_REG_XX_TABLE, 0x12},
+	{OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f02d5},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
+	{OP_ZR, XCM_REG_N_SM_CTX_LD_4, 0x4},
+	{OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
+	{OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
+	{OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
+	{OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
+	{OP_WR, XCM_REG_XSDM_IFEN, 0x1},
+	{OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
+	{OP_WR, XCM_REG_TSEM_IFEN, 0x1},
+	{OP_WR, XCM_REG_CSEM_IFEN, 0x1},
+	{OP_WR, XCM_REG_USEM_IFEN, 0x1},
+	{OP_WR, XCM_REG_DORQ_IFEN, 0x1},
+	{OP_WR, XCM_REG_PBF_IFEN, 0x1},
+	{OP_WR, XCM_REG_NIG0_IFEN, 0x1},
+	{OP_WR, XCM_REG_NIG1_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
+/* #define XCM_COMMON_END          595 */
+/* #define XCM_PORT0_START         596 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+/* #define XCM_PORT0_END           597 */
+/* #define XCM_PORT1_START         598 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+/* #define XCM_PORT1_END           599 */
+/* #define XSEM_COMMON_START       616 */
+	{OP_WB, XSEM_REG_INT_TABLE, 0xda0000},
+	{OP_WR_64, XSEM_REG_INT_TABLE + 0x368, 0x1302f4},
+	{OP_WB, XSEM_REG_PRAM, 0x71dc0000},
+	{OP_WR_64, XSEM_REG_PRAM + 0x1c770, 0x471202f6},
+	{OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, XSEM_REG_TS_0_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_1_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_2_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_3_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_4_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_5_AS, 0x3},
+	{OP_WR, XSEM_REG_TS_6_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_7_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_8_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_9_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_10_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_11_AS, 0x3},
+	{OP_WR, XSEM_REG_TS_12_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_13_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_14_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_15_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_16_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, XSEM_REG_TS_18_AS, 0x2},
+	{OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
+	{OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
+	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
+	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
+	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
+	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3c40, 0x4},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3c40 + 0x10, 0x202f8},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000, 0x48},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x1000, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3128, 0x8e},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3370, 0x202fa},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3a70, 0x402fc},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3d00, 0x20300},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x1500, 0x20302},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x1500 + 0x8, 0x100},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x1970, 0x0},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x1978, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x1960, 0x20304},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x1f48, 0x20306},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100308},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80318},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80320},
+/* #define XSEM_COMMON_END         617 */
+/* #define XSEM_PORT0_START        618 */
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3a80, 0x14},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3b20, 0x24},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x1400, 0xa},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x1450, 0x6},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3378, 0xd8},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x3a38, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3c58, 0x20328},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3c68, 0x10032a},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x5040, 0x0},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2033a},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
+/* #define XSEM_PORT0_END          619 */
+/* #define XSEM_PORT1_START        620 */
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3ad0, 0x14},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3bb0, 0x24},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x1428, 0xa},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x1468, 0x6},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x36d8, 0xd8},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x3a3c, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3c60, 0x2033c},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3ca8, 0x10033e},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x5044, 0x0},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2034e},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
+/* #define XSEM_PORT1_END          621 */
+/* #define CDU_COMMON_START        638 */
+	{OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
+	{OP_WR, CDU_REG_CDU_DEBUG, 0x264},
+	{OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
+	{OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
+	{OP_WB, CDU_REG_L1TT, 0x2000350},
+	{OP_WB, CDU_REG_MATT, 0x200550},
+	{OP_ZR, CDU_REG_MATT + 0x80, 0x2},
+	{OP_WB, CDU_REG_MATT + 0x88, 0x60570},
+	{OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
+	{OP_WR, CDU_REG_CDU_DEBUG, 0x0},
+/* #define CDU_COMMON_END          639 */
+/* #define DMAE_COMMON_START       660 */
+	{OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
+	{OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
+	{OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
+	{OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x1},
+	{OP_WR, DMAE_REG_PCI_IFEN, 0x1},
+	{OP_WR, DMAE_REG_GRC_IFEN, 0x1},
+/* #define DMAE_COMMON_END         661 */
+/* #define PXP_COMMON_START        682 */
+	{OP_WB, PXP_REG_HST_INBOUND_INT + 0x400, 0x50576},
+	{OP_WB, PXP_REG_HST_INBOUND_INT + 0x420, 0x5057b},
+	{OP_WB, PXP_REG_HST_INBOUND_INT, 0x50580},
+/* #define PXP_COMMON_END          683 */
+/* #define CFC_COMMON_START        704 */
+	{OP_WR, CFC_REG_CONTROL0, 0x10},
+	{OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
+	{OP_WR, CFC_REG_INTERFACES, 0x280000},
+	{OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
+	{OP_WR, CFC_REG_INTERFACES, 0x0},
+/* #define CFC_COMMON_END          705 */
+/* #define HC_COMMON_START         726 */
+	{OP_ZR, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
+/* #define HC_COMMON_END           727 */
+/* #define HC_PORT0_START          728 */
+	{OP_WR, HC_REG_CONFIG_0, 0x1080},
+	{OP_ZR, HC_REG_UC_RAM_ADDR_0, 0x2},
+	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+	{OP_WR, HC_REG_LEADING_EDGE_0, 0xffff},
+	{OP_WR, HC_REG_TRAILING_EDGE_0, 0xffff},
+	{OP_WR, HC_REG_AGG_INT_0, 0x0},
+	{OP_WR, HC_REG_ATTN_IDX, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
+	{OP_WR, HC_REG_VQID_0, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_PORT0_END            729 */
+/* #define HC_PORT1_START          730 */
+	{OP_WR, HC_REG_CONFIG_1, 0x1080},
+	{OP_ZR, HC_REG_UC_RAM_ADDR_1, 0x2},
+	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+	{OP_WR, HC_REG_LEADING_EDGE_1, 0xffff},
+	{OP_WR, HC_REG_TRAILING_EDGE_1, 0xffff},
+	{OP_WR, HC_REG_AGG_INT_1, 0x0},
+	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+	{OP_WR, HC_REG_VQID_1, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_PORT1_END            731 */
+/* #define PXP2_COMMON_START       748 */
+	{OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340},
+	{OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
+	{OP_WR, PXP2_REG_PGL_DEBUG, 0x2},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xffff3330},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0003000},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
+	{OP_ZR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x2},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ25, 0x0},
+	{OP_WR, PXP2_REG_RD_START_INIT, 0x1},
+	{OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
+	{OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
+	{OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
+	{OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
+	{OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
+	{OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
+	{OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
+	{OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
+	{OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
+	{OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
+/* #define PXP2_COMMON_END         749 */
+/* #define MISC_AEU_COMMON_START   770 */
+	{OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
+/* #define MISC_AEU_COMMON_END     771 */
+/* #define MISC_AEU_PORT0_START    772 */
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
+	{OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0},
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
+	{OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14},
+	{OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
+	{OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
+	{OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0x0},
+	{OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
+	{OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
+	{OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0x0},
+	{OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
+	{OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
+	{OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
+/* #define MISC_AEU_PORT0_END      773 */
+/* #define MISC_AEU_PORT1_START    774 */
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
+	{OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0},
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
+	{OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14},
+	{OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
+	{OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
+	{OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0x0},
+	{OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555},
+	{OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555},
+	{OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
+	{OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
+	{OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
+	{OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
+/* #define MISC_AEU_PORT1_END      775 */
+
+};
+
+static const uint16_t init_ops_offsets_e1[] = {
+	0x0000, 0x002e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x002e,
+	0x0050, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0050, 0x008d, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x008d, 0x0092,
+	0x0092, 0x0096, 0x0096, 0x009a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x009a, 0x00d9, 0x00d9, 0x00e7, 0x00e7, 0x00f5, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x00f5, 0x00fc, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x00fc, 0x0101, 0x0101, 0x010c, 0x010c, 0x0117,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0117, 0x0118, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0118, 0x0150, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0150, 0x0174, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0174, 0x01b3, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x01b3, 0x01ee, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x01ee, 0x0231, 0x0231, 0x0234, 0x0234,
+	0x0237, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0237,
+	0x0271, 0x0271, 0x027b, 0x027b, 0x0285, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0285, 0x0286, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0286, 0x0298,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0298, 0x02ad, 0x02ad, 0x02b0, 0x02b0, 0x02b3, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x02b3, 0x02e1, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x02e1, 0x0368, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0368, 0x036f, 0x036f, 0x0373,
+	0x0373, 0x0377, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0377, 0x03b6, 0x03b6, 0x03be, 0x03be, 0x03c6, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x03c6, 0x0417, 0x0417, 0x0429, 0x0429,
+	0x043b, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x043b,
+	0x0445, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0445, 0x044b, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x044b, 0x044e,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x044e, 0x0453, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0453, 0x0454, 0x0454,
+	0x0466, 0x0466, 0x0478, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0478, 0x04e5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x04e5, 0x04e6, 0x04e6, 0x04fa,
+	0x04fa, 0x050e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+};
+
+static const uint32_t init_data_e1[] = {
+	0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
+	0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
+	0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
+	0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
+	0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
+	0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
+	0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
+	0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
+	0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
+	0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
+	0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
+	0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
+	0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
+	0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
+	0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
+	0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
+	0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
+	0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
+	0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
+	0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
+	0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
+	0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
+	0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
+	0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
+	0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
+	0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
+	0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
+	0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
+	0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
+	0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
+	0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
+	0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
+	0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
+	0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
+	0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
+	0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
+	0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
+	0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
+	0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
+	0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
+	0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
+	0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
+	0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
+	0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
+	0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
+	0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
+	0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
+	0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
+	0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
+	0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
+	0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
+	0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
+	0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
+	0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
+	0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
+	0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
+	0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
+	0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
+	0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
+	0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
+	0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
+	0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
+	0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
+	0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
+	0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
+	0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
+	0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
+	0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
+	0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
+	0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
+	0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
+	0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
+	0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
+	0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
+	0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
+	0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
+	0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
+	0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
+	0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
+	0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
+	0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
+	0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
+	0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
+	0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
+	0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
+	0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
+	0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
+	0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
+	0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
+	0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
+	0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
+	0x00000200, 0x00007ff8, 0x00007ff8, 0x0000026f, 0x00001500, 0x00000001,
+	0x00000003, 0x00bebc20, 0x00000003, 0x00bebc20, 0x00000001, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+	0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+	0xffffffff, 0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180,
+	0x00008240, 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600,
+	0x000146c0, 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80,
+	0x00020b40, 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00,
+	0x0002cfc0, 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380,
+	0x00039440, 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800,
+	0x000458c0, 0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700,
+	0x00020a80, 0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00,
+	0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100,
+	0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600,
+	0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00,
+	0x00007ff8, 0x00007ff8, 0x00000174, 0x00001500, 0x00001900, 0x00000000,
+	0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x00007ff8, 0x00007ff8, 0x00000509,
+	0x00003500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00001000,
+	0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300,
+	0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600,
+	0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900,
+	0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00,
+	0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00,
+	0x00007ff8, 0x00007ff8, 0x00000448, 0x00001500, 0x10000000, 0x000028ad,
+	0x00000000, 0x00010001, 0x000d0205, 0xccccccc1, 0xffffffff, 0xffffffff,
+	0x7058103c, 0x00000000, 0x00000000, 0x00000001, 0xcccc0201, 0xcccccccc,
+	0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x000e01b7, 0x011600d6,
+	0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+	0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+	0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, 0x00000000,
+	0x007201bb, 0x012300f3, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+	0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+	0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000,
+	0x00100000, 0x00000000, 0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+	0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
+	0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+	0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+	0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+	0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
+	0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+	0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
+	0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff,
+	0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
+	0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
+	0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+	0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
+	0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+	0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
+	0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+	0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+	0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+	0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
+	0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+	0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
+	0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
+	0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
+	0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+	0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
+	0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x000c0000, 0x000700c0,
+	0x00028130, 0x000b8158, 0x00020210, 0x00010230, 0x000f0240, 0x00010330,
+	0x000c0000, 0x000800c0, 0x00028140, 0x000b8168, 0x00020220, 0x00010240,
+	0x00070250, 0x000202c0, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198,
+	0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100,
+	0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380,
+	0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118,
+	0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc,
+	0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc,
+	0xcccccccc, 0xcccccccc, 0x00002000
+};
+
+static const uint8_t tsem_int_table_data_e1[] = {
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x8c, 0x06, 0x00, 0x00, 0xbc, 0x08, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xd1, 0x02, 0x00, 0x00, 0xd3, 0x02, 0x00, 0x00, 0xd5, 0x02, 0x00, 0x00,
+	0x10, 0x03, 0x00, 0x00, 0x53, 0x01, 0x00, 0x00, 0x54, 0x01, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x5e, 0x15, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xe4, 0x12, 0x00, 0x00, 0x10, 0x13, 0x00, 0x00,
+	0x53, 0x11, 0x00, 0x00, 0xcb, 0x13, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xc1, 0x15, 0x00, 0x00, 0x34, 0x14, 0x00, 0x00,
+	0xf7, 0x13, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x7b, 0x14, 0x00, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xae, 0x1a, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xab, 0x18, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xaf, 0x1a, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xb0, 0x1a, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x0a, 0x19, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xb1, 0x1a, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xdf, 0x21, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x12, 0x20, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x6b, 0x21, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xe0, 0x21, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x13, 0x20, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xcf, 0x1a, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xe1, 0x21, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xd0, 0x1a, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00
+};
+
+static const uint8_t tsem_pram_data_e1[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x06, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x6f, 0x02, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x6f, 0x02, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x9a, 0x05, 0x00, 0x5f,
+	0x50, 0x0c, 0x00, 0x00, 0x26, 0x98, 0x20, 0x83, 0x0c, 0x14, 0x00, 0x00,
+	0x6f, 0xb8, 0x21, 0xb1, 0x0b, 0x20, 0x00, 0x00, 0x19, 0xbc, 0x91, 0x01,
+	0x42, 0x0c, 0x00, 0x00, 0x19, 0x9c, 0x90, 0x01, 0x62, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x40, 0x09, 0x20, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x19, 0xb8, 0x91, 0x01, 0x41, 0x2c, 0x00, 0x00,
+	0x19, 0xcc, 0x90, 0x01, 0x61, 0x2c, 0x00, 0x00, 0x19, 0x07, 0x02, 0x00,
+	0xd0, 0x0c, 0x00, 0x00, 0x00, 0x04, 0x20, 0x0f, 0x00, 0x0c, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x16, 0x00, 0x00, 0x23, 0x38, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0c, 0x19, 0x36, 0x00, 0x00,
+	0x1c, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0xf2, 0x10, 0x0b, 0x00,
+	0x00, 0x34, 0x00, 0x00, 0x21, 0x85, 0x02, 0xa0, 0x80, 0x01, 0x00, 0x00,
+	0x1c, 0x60, 0x68, 0x4c, 0x00, 0x0e, 0x00, 0x00, 0xa3, 0x02, 0x00, 0x00,
+	0x19, 0x12, 0x00, 0x00, 0x23, 0x03, 0xfc, 0xc1, 0x05, 0x00, 0x00, 0x00,
+	0x00, 0x70, 0x04, 0xe2, 0xe0, 0x08, 0x00, 0x00, 0x08, 0x04, 0x08, 0x04,
+	0xff, 0x22, 0x00, 0x00, 0x1e, 0x58, 0x00, 0x02, 0x00, 0x22, 0x00, 0x00,
+	0x1f, 0x78, 0x04, 0xe2, 0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x21, 0x80, 0x04, 0xe2, 0xe0, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x23, 0x00, 0x04, 0xe2,
+	0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x21, 0x00, 0x00,
+	0x23, 0x00, 0x0d, 0x14, 0xe6, 0x0b, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x0d,
+	0xff, 0x03, 0x00, 0x00, 0x19, 0x07, 0x02, 0x00, 0xd0, 0x0c, 0x00, 0x00,
+	0x00, 0x04, 0x20, 0x0f, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06,
+	0x50, 0x2d, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x9c, 0x7f, 0x20, 0x16,
+	0x0c, 0x04, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x72, 0x71, 0xe8, 0x06, 0x87, 0x00, 0x00, 0x00,
+	0x9e, 0x7f, 0x20, 0x16, 0x0c, 0x24, 0x00, 0x00, 0xa0, 0x7f, 0x20, 0x16,
+	0x0c, 0x04, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x6d, 0x80, 0x06, 0x04, 0x00, 0x2f, 0x00, 0x00, 0x6d, 0x00, 0x00, 0x40,
+	0xb0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x4c, 0x00, 0x41, 0x36,
+	0x00, 0x15, 0x00, 0x00, 0x5e, 0x00, 0x42, 0x36, 0x00, 0x15, 0x00, 0x00,
+	0x6f, 0x04, 0x20, 0x57, 0x00, 0x34, 0x00, 0x00, 0x6f, 0xc8, 0x05, 0x00,
+	0x80, 0x21, 0x00, 0x00, 0x6f, 0x70, 0xe6, 0x46, 0x00, 0x34, 0x00, 0x00,
+	0x00, 0xb8, 0x01, 0x00, 0x25, 0x21, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x2d, 0x00, 0x05, 0x00, 0x00, 0x35, 0x00, 0x00, 0x41, 0x00, 0x01, 0x04,
+	0xe6, 0x08, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x0e, 0xff, 0x03, 0x00, 0x00,
+	0x03, 0x6c, 0x20, 0x97, 0x46, 0x20, 0x00, 0x00, 0x70, 0x0b, 0x40, 0x44,
+	0x00, 0x15, 0x00, 0x00, 0x99, 0x0b, 0x60, 0x44, 0x00, 0x15, 0x00, 0x00,
+	0x03, 0x6c, 0x20, 0x97, 0x46, 0x20, 0x00, 0x00, 0x18, 0x62, 0x48, 0x18,
+	0x60, 0x2c, 0x00, 0x00, 0x43, 0x67, 0x2c, 0x80, 0x00, 0x14, 0x00, 0x00,
+	0xf2, 0x98, 0x01, 0x30, 0x07, 0x00, 0x00, 0x00, 0xe7, 0x01, 0xa0, 0x06,
+	0x05, 0x01, 0x00, 0x00, 0x6b, 0x54, 0x70, 0x2e, 0x47, 0x20, 0x00, 0x00,
+	0xd5, 0x06, 0x60, 0x4b, 0x00, 0x15, 0x00, 0x00, 0x67, 0x03, 0xc0, 0x86,
+	0x05, 0x21, 0x00, 0x00, 0x6d, 0x5c, 0x70, 0x26, 0x00, 0x02, 0x00, 0x00,
+	0xd0, 0x06, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x1f, 0xb8, 0x41, 0xe9,
+	0x04, 0x0e, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x80, 0x0f, 0x12, 0x00, 0x00,
+	0x1f, 0x78, 0x00, 0x00, 0xe2, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0xe2, 0x04, 0x00, 0x00,
+	0x00, 0x00, 0xa0, 0x00, 0x00, 0x35, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x21, 0x80, 0xc8, 0x23, 0x24, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x36, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
+	0x00, 0x00, 0xe0, 0x01, 0x50, 0x2d, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x1f, 0xb9, 0x41, 0xc8, 0x04, 0x2e, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x1f, 0x78, 0x00, 0x00,
+	0xe2, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xe2, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x64, 0x00, 0x00, 0x00, 0xe2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x6f, 0x0e, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x6d, 0x0d, 0x06, 0xa0, 0x82, 0x21, 0x00, 0x00, 0x43, 0xb5, 0x05, 0xc0,
+	0x3f, 0x14, 0x00, 0x00, 0x6d, 0xa1, 0x01, 0xa0, 0x07, 0x21, 0x00, 0x00,
+	0x02, 0xbe, 0x09, 0x40, 0x00, 0x14, 0x00, 0x00, 0xee, 0xa4, 0x01, 0xa0,
+	0x07, 0x01, 0x00, 0x00, 0xc0, 0x0d, 0x06, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0xed, 0x10, 0x08, 0xa0, 0x07, 0x01, 0x00, 0x00, 0x6f, 0x07, 0xd0, 0x8e,
+	0x3b, 0x34, 0x00, 0x00, 0xf0, 0xb5, 0x03, 0x00, 0xa2, 0x00, 0x00, 0x00,
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+	0x04, 0x33, 0x00, 0x00, 0x5d, 0x70, 0xd1, 0x00, 0x04, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x5f, 0x78, 0xd9, 0x00,
+	0x04, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x61, 0x80, 0xe1, 0x00, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0xe0, 0x14, 0xf0, 0x05, 0x1b, 0x01, 0x00, 0x00,
+	0xe0, 0xb6, 0x19, 0x46, 0x5b, 0x20, 0x00, 0x00, 0xed, 0xb5, 0x07, 0x36,
+	0x60, 0x0c, 0x00, 0x00, 0xa1, 0x21, 0x60, 0xd4, 0x21, 0x15, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xe0, 0x8d, 0x27, 0x44,
+	0x00, 0x0e, 0x00, 0x00, 0x45, 0x03, 0x2c, 0x0f, 0xe0, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x6b, 0x18, 0xea, 0x00, 0x04, 0x13, 0x00, 0x00, 0xdc, 0x7f, 0xd0, 0x00,
+	0x04, 0x24, 0x00, 0x00, 0x00, 0xac, 0x13, 0x00, 0x00, 0x19, 0x00, 0x00,
+	0xde, 0x7f, 0xd8, 0x00, 0x04, 0x24, 0x00, 0x00, 0xe0, 0x7f, 0xe0, 0x00,
+	0x04, 0x24, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28,
+	0x70, 0x0c, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28, 0x70, 0x0c, 0x00, 0x00,
+	0x06, 0xc2, 0x00, 0x28, 0x04, 0x14, 0x00, 0x00, 0xf0, 0x01, 0x0a, 0x30,
+	0xa2, 0x21, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x6a, 0x22, 0x02, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xdc, 0x41, 0x16, 0x42, 0x00, 0x2e, 0x00, 0x00,
+	0xdc, 0x1d, 0x06, 0x04, 0x00, 0x2e, 0x00, 0x00, 0xdc, 0x1d, 0x26, 0x42,
+	0x00, 0x2e, 0x00, 0x00, 0xdc, 0x19, 0x38, 0x08, 0x00, 0x2e, 0x00, 0x00,
+	0xdc, 0x1d, 0x46, 0x48, 0x00, 0x2e, 0x00, 0x00, 0xef, 0x05, 0x0c, 0x88,
+	0x01, 0x0f, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x40, 0x01, 0x12, 0x00, 0x00,
+	0x5c, 0x01, 0x40, 0x9e, 0x61, 0x21, 0x00, 0x00, 0x77, 0x16, 0x60, 0xf1,
+	0x21, 0x35, 0x00, 0x00, 0x6f, 0x6a, 0xf0, 0x2e, 0x04, 0x23, 0x00, 0x00,
+	0x6f, 0x2f, 0xe0, 0x5e, 0x01, 0x03, 0x00, 0x00, 0x14, 0x11, 0x60, 0xf4,
+	0x21, 0x15, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x19, 0x12, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x26, 0x50, 0x2d, 0x00, 0x00, 0xe8, 0x02, 0x80, 0x2e,
+	0x01, 0x10, 0x00, 0x00, 0x2e, 0x22, 0x17, 0x51, 0x04, 0x39, 0x00, 0x00,
+	0xe8, 0x0a, 0x80, 0xee, 0x00, 0x10, 0x00, 0x00, 0x26, 0xa2, 0x12, 0x51,
+	0x04, 0x39, 0x00, 0x00, 0xe8, 0x06, 0x00, 0x00, 0x00, 0x3a, 0x00, 0x00,
+	0x36, 0x22, 0xfd, 0x50, 0x80, 0x0c, 0x00, 0x00, 0x34, 0x10, 0x60, 0xfe,
+	0x21, 0x15, 0x00, 0x00, 0xe4, 0x01, 0x03, 0xc0, 0x00, 0x34, 0x00, 0x00,
+	0x80, 0xb9, 0x01, 0xa0, 0xa5, 0x01, 0x00, 0x00, 0x00, 0x40, 0xe0, 0x06,
+	0x52, 0x0d, 0x00, 0x00, 0xef, 0x01, 0x00, 0x58, 0xb0, 0x0c, 0x00, 0x00,
+	0xef, 0x05, 0x00, 0x58, 0xb0, 0x2c, 0x00, 0x00, 0xef, 0x09, 0x00, 0x58,
+	0xb0, 0x2c, 0x00, 0x00, 0x05, 0x22, 0x01, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x06, 0x22, 0x01, 0x00, 0x00, 0x15, 0x00, 0x00, 0x06, 0x22, 0x01, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x20, 0x22, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x36, 0x22, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x45, 0x03, 0x8c, 0x26,
+	0x01, 0x14, 0x00, 0x00, 0xf2, 0x98, 0x07, 0x00, 0x07, 0x21, 0x00, 0x00,
+	0xe4, 0x01, 0x03, 0x40, 0x02, 0x34, 0x00, 0x00, 0x80, 0xbd, 0x07, 0xa0,
+	0xa5, 0x21, 0x00, 0x00, 0x16, 0x12, 0x00, 0x00, 0x38, 0x12, 0x00, 0x00,
+	0xc5, 0x06, 0x00, 0x00, 0x08, 0x32, 0x00, 0x00, 0x32, 0xbf, 0x07, 0xc0,
+	0x01, 0x2e, 0x00, 0x00, 0x66, 0x08, 0xf4, 0x00, 0x04, 0x13, 0x00, 0x00,
+	0x19, 0x22, 0x21, 0x00, 0x00, 0x15, 0x00, 0x00, 0x14, 0x23, 0x00, 0x40,
+	0x00, 0x14, 0x00, 0x00, 0x14, 0x8f, 0x07, 0xa0, 0x83, 0x01, 0x00, 0x00,
+	0x00, 0xe0, 0xd0, 0x1e, 0x51, 0x0d, 0x00, 0x00, 0x90, 0x05, 0x00, 0x5f,
+	0x50, 0x0c, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x40, 0x00, 0x34, 0x00, 0x00,
+	0xed, 0x8d, 0x27, 0xa2, 0x8a, 0x21, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x19, 0x22, 0x02, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x00, 0x64, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0xed, 0x8d, 0x17, 0xa1,
+	0x8a, 0x21, 0x00, 0x00, 0x6d, 0xc9, 0xe2, 0xde, 0x00, 0x02, 0x00, 0x00,
+	0xc2, 0x21, 0x60, 0x1d, 0x22, 0x15, 0x00, 0x00, 0xe2, 0x02, 0x20, 0x36,
+	0x00, 0x03, 0x00, 0x00, 0x6d, 0x0e, 0xc1, 0x06, 0x00, 0x23, 0x00, 0x00,
+	0x2f, 0x22, 0x20, 0x00, 0x00, 0x35, 0x00, 0x00, 0xe4, 0x01, 0x03, 0x58,
+	0xb0, 0x2c, 0x00, 0x00, 0x07, 0x03, 0x00, 0x84, 0x01, 0x12, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x10, 0xe4, 0x28, 0x00, 0x00, 0x5f, 0x00, 0x01, 0x00,
+	0x0f, 0x23, 0x00, 0x00, 0x48, 0x02, 0x60, 0x25, 0x22, 0x35, 0x00, 0x00,
+	0x6d, 0x08, 0xe0, 0x06, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06,
+	0x50, 0x2d, 0x00, 0x00, 0x36, 0x22, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x45, 0x03, 0x8c, 0x26, 0x01, 0x14, 0x00, 0x00, 0xf2, 0x98, 0x07, 0x00,
+	0x07, 0x21, 0x00, 0x00, 0xed, 0x65, 0xd0, 0x96, 0x2c, 0x21, 0x00, 0x00,
+	0xee, 0x0d, 0x30, 0x1e, 0x00, 0x23, 0x00, 0x00, 0xe2, 0x02, 0x20, 0x36,
+	0x00, 0x03, 0x00, 0x00, 0xc2, 0x21, 0x60, 0x2f, 0x22, 0x35, 0x00, 0x00,
+	0x66, 0x08, 0xf4, 0x00, 0x04, 0x13, 0x00, 0x00, 0x6d, 0x0e, 0xc1, 0x06,
+	0x00, 0x23, 0x00, 0x00, 0x36, 0x22, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x45, 0x03, 0x2c, 0x0f, 0xe0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x66, 0x08, 0xf0, 0x00,
+	0x04, 0x33, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xe6, 0x99, 0x87, 0x26, 0x60, 0x0c, 0x00, 0x00, 0x32, 0x03, 0x01, 0x5f,
+	0x50, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x46, 0x22, 0x02, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0xdc, 0x05, 0x00, 0x5f, 0x50, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x61, 0x22, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x16, 0x12, 0x00, 0x00, 0x38, 0x12, 0x00, 0x00, 0xc5, 0x06, 0x00, 0x00,
+	0x08, 0x32, 0x00, 0x00, 0x32, 0x27, 0x00, 0x00, 0x18, 0x32, 0x00, 0x00,
+	0x07, 0x0a, 0x00, 0x00, 0x09, 0x32, 0x00, 0x00, 0x53, 0x22, 0x20, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xed, 0x59, 0x30, 0x1e, 0x00, 0x03, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x31, 0x02, 0x34, 0x00, 0x00, 0x6d, 0x52, 0x0c, 0x30,
+	0x8a, 0x01, 0x00, 0x00, 0xdc, 0x05, 0x00, 0x5f, 0x50, 0x2c, 0x00, 0x00,
+	0x16, 0x12, 0x00, 0x60, 0xb1, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x61, 0x22, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0xf7, 0x17, 0x50, 0x4d,
+	0x22, 0x15, 0x00, 0x00, 0x6a, 0x70, 0x91, 0xb6, 0xcc, 0x20, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xef, 0x01, 0x00, 0x40,
+	0x00, 0x34, 0x00, 0x00, 0x80, 0x8d, 0x07, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x6d, 0xbe, 0xd9, 0xde, 0x7b, 0x00, 0x00, 0x00, 0x69, 0xa7, 0x2d, 0x33,
+	0x60, 0x2c, 0x00, 0x00, 0x61, 0x22, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x45, 0x03, 0x8c, 0x26, 0x01, 0x14, 0x00, 0x00, 0xf2, 0x98, 0x07, 0x00,
+	0x07, 0x21, 0x00, 0x00, 0xee, 0x0d, 0x20, 0x2e, 0x00, 0x03, 0x00, 0x00,
+	0x62, 0x03, 0xc0, 0x06, 0x00, 0x23, 0x00, 0x00, 0xc2, 0x21, 0x60, 0x5a,
+	0x22, 0x15, 0x00, 0x00, 0xb2, 0xc8, 0xd2, 0x16, 0x60, 0x0c, 0x00, 0x00,
+	0x66, 0x08, 0xf4, 0x00, 0x04, 0x13, 0x00, 0x00, 0x45, 0x03, 0x2c, 0x0f,
+	0xe0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x66, 0x08, 0xf0, 0x00, 0x04, 0x33, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xe6, 0x99, 0x87, 0x26,
+	0x60, 0x0c, 0x00, 0x00, 0xef, 0x1d, 0xd0, 0x06, 0x00, 0x03, 0x00, 0x00,
+	0xef, 0xa1, 0xf9, 0x1e, 0x20, 0x2c, 0x00, 0x00, 0x6d, 0xbc, 0xc7, 0xd8,
+	0x01, 0x2e, 0x00, 0x00, 0x6d, 0x08, 0x0c, 0xc0, 0x03, 0x2e, 0x00, 0x00,
+	0x00, 0xb4, 0x05, 0xec, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x22, 0x00, 0x00, 0x07, 0x0a, 0x00, 0x80, 0x09, 0x12, 0x00, 0x00,
+	0x80, 0x87, 0x3c, 0x11, 0xe6, 0x2b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00,
+	0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x16, 0x00, 0x00,
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x07, 0x08, 0x0c, 0xc0,
+	0x03, 0x2e, 0x00, 0x00, 0x00, 0x1c, 0x04, 0xec, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x22, 0x00, 0x00, 0x07, 0x00, 0x00, 0xa0,
+	0x02, 0x03, 0x00, 0x00, 0xb4, 0x08, 0x0e, 0x2e, 0x00, 0x0f, 0x00, 0x00,
+	0xb8, 0x05, 0x0c, 0x88, 0x01, 0x2f, 0x00, 0x00, 0x00, 0x58, 0x26, 0x02,
+	0x00, 0x16, 0x00, 0x00, 0x74, 0x10, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0xb4, 0xd0, 0x02, 0x00, 0x00, 0x14, 0x00, 0x00, 0xb4, 0x18, 0x06, 0xa0,
+	0x00, 0x21, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x36, 0x00, 0x00,
+	0x01, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x74, 0xd1, 0x02, 0x00,
+	0x00, 0x34, 0x00, 0x00, 0x74, 0x21, 0x00, 0xa0, 0x00, 0x21, 0x00, 0x00,
+	0x07, 0x0a, 0x00, 0x80, 0x08, 0x32, 0x00, 0x00, 0x01, 0xe0, 0xc6, 0xf9,
+	0x01, 0x0e, 0x00, 0x00, 0x09, 0x00, 0xa0, 0x18, 0x00, 0x03, 0x00, 0x00,
+	0x83, 0x01, 0x30, 0x20, 0x00, 0x23, 0x00, 0x00, 0x72, 0x06, 0x60, 0x82,
+	0x22, 0x35, 0x00, 0x00, 0x00, 0x60, 0x73, 0x30, 0x10, 0x14, 0x00, 0x00,
+	0x03, 0x1f, 0x0c, 0x30, 0x8a, 0x21, 0x00, 0x00, 0xb2, 0xca, 0x4a, 0x1b,
+	0x60, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x08, 0x16, 0x00, 0x00,
+	0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x35, 0xe0, 0xc6, 0xf9,
+	0x01, 0x2e, 0x00, 0x00, 0x00, 0x2c, 0x0f, 0x04, 0x00, 0x36, 0x00, 0x00,
+	0x34, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x36, 0x08, 0x70, 0x03,
+	0x00, 0x22, 0x00, 0x00, 0x39, 0x00, 0x80, 0x03, 0x00, 0x23, 0x00, 0x00,
+	0x00, 0x00, 0x7c, 0x10, 0xe6, 0x0b, 0x00, 0x00, 0x00, 0x89, 0xc6, 0x01,
+	0xff, 0x2b, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00
+};
+
+static const uint8_t usem_int_table_data_e1[] = {
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x27, 0x20, 0x00, 0x00, 0xae, 0x22, 0x00, 0x00, 0xda, 0x23, 0x00, 0x00,
+	0x45, 0x24, 0x00, 0x00, 0xce, 0x1f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x25, 0x08, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xe8, 0x01, 0x00, 0x00, 0xea, 0x01, 0x00, 0x00, 0xec, 0x01, 0x00, 0x00,
+	0xee, 0x01, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x2a, 0x13, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xa9, 0x0d, 0x00, 0x00, 0x2b, 0x13, 0x00, 0x00,
+	0x7c, 0x0d, 0x00, 0x00, 0x25, 0x10, 0x00, 0x00, 0x0a, 0x13, 0x00, 0x00,
+	0x2c, 0x13, 0x00, 0x00, 0xbe, 0x0d, 0x00, 0x00, 0xde, 0x0d, 0x00, 0x00,
+	0xea, 0x0d, 0x00, 0x00, 0x44, 0x12, 0x00, 0x00, 0x0b, 0x0e, 0x00, 0x00,
+	0x35, 0x0e, 0x00, 0x00, 0x16, 0x0e, 0x00, 0x00, 0x2d, 0x13, 0x00, 0x00,
+	0x4d, 0x0e, 0x00, 0x00, 0xf6, 0x0e, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x2e, 0x13, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xe7, 0x10, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x19, 0x11, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x8a, 0x11, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x1b, 0x12, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x3e, 0x27, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x82, 0x27, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xd9, 0x00, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x38, 0x1d, 0x00, 0x00, 0x4a, 0x1e, 0x00, 0x00,
+	0x8c, 0x1f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xd6, 0x00, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x9e, 0x1f, 0x00, 0x00,
+	0x39, 0x1d, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x1b, 0x17, 0x00, 0x00,
+	0x2a, 0x1f, 0x00, 0x00, 0xd3, 0x00, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x1c, 0x17, 0x00, 0x00, 0x2b, 0x1f, 0x00, 0x00,
+	0xaa, 0x1f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00
+};
+
+static const uint8_t usem_pram_data_e1[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x00, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x74, 0x01, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x74, 0x01, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
+	0xff, 0x16, 0x00, 0x00, 0x4f, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
+	0x45, 0x03, 0x0c, 0x00, 0x00, 0x34, 0x00, 0x00, 0x4e, 0x0c, 0x00, 0xa0,
+	0x07, 0x01, 0x00, 0x00, 0x4e, 0x3c, 0x03, 0x00, 0x00, 0x14, 0x00, 0x00,
+	0xce, 0xa4, 0x01, 0xa0, 0x03, 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+	0x80, 0x36, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x4f, 0x04, 0x00, 0xb8, 0x01, 0x2f, 0x00, 0x00, 0xf2, 0x38, 0xb3, 0x86,
+	0x31, 0x20, 0x00, 0x00, 0x01, 0x40, 0x40, 0x00, 0x78, 0x32, 0x00, 0x00,
+	0x01, 0x20, 0x10, 0x00, 0x5c, 0x32, 0x00, 0x00, 0x01, 0x3c, 0xc1, 0xf9,
+	0x01, 0x0e, 0x00, 0x00, 0x0f, 0x38, 0x02, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x11, 0x40, 0x0a, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x13, 0x48, 0x12, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x15, 0x50, 0x1a, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x17, 0x58, 0x22, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x19, 0x60, 0x2a, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x1b, 0x68, 0x32, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x1d, 0x70, 0x3a, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x1f, 0x78, 0x42, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x21, 0x80, 0x4a, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x23, 0x88, 0x52, 0x00,
+	0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x25, 0x90, 0x5a, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x27, 0x98, 0x62, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x29, 0xa0, 0x6a, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x2b, 0xa8, 0x72, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x2d, 0xb0, 0x7a, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x2f, 0xb8, 0x82, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x31, 0xc0, 0x8a, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x33, 0xc8, 0x92, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x35, 0xd0, 0x9a, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x37, 0xd8, 0xa2, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x39, 0xe0, 0xaa, 0x00, 0x00, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x3b, 0xe8, 0xb2, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x3d, 0xf0, 0xba, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0xc2, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x41, 0x00, 0xcb, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x43, 0x08, 0xd3, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x45, 0x10, 0xdb, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x47, 0x18, 0xe3, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x49, 0x20, 0xeb, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x4f, 0x04, 0x00, 0xb8, 0x01, 0x2f, 0x00, 0x00,
+	0x4b, 0x28, 0xf3, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x4d, 0x30, 0xfb, 0x00, 0x00, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x04, 0x00, 0x50, 0x00,
+	0x00, 0x23, 0x00, 0x00, 0x06, 0x00, 0x70, 0x00, 0x00, 0x23, 0x00, 0x00,
+	0x08, 0x00, 0x90, 0x00, 0x00, 0x23, 0x00, 0x00, 0x0a, 0x00, 0xb0, 0x00,
+	0x00, 0x23, 0x00, 0x00, 0x0c, 0x00, 0xd0, 0x00, 0x00, 0x23, 0x00, 0x00,
+	0xe3, 0x1e, 0x60, 0x5a, 0x00, 0x15, 0x00, 0x00, 0x00, 0x9e, 0x80, 0x86,
+	0x00, 0x01, 0x00, 0x00, 0x83, 0x80, 0xf0, 0xde, 0x13, 0x01, 0x00, 0x00,
+	0xce, 0x38, 0x23, 0x0f, 0x60, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00,
+	0x00, 0x16, 0x00, 0x00, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x4e, 0x08, 0x0c, 0xc0, 0x03, 0x0e, 0x00, 0x00, 0x07, 0x08, 0x00, 0x80,
+	0x09, 0x32, 0x00, 0x00, 0x0e, 0xf8, 0x02, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x0f, 0xf8, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x10, 0xf8, 0x0a, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x11, 0xf8, 0x08, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x12, 0xf8, 0x12, 0x00, 0x00, 0x13, 0x00, 0x00, 0x13, 0xf8, 0x10, 0x00,
+	0x00, 0x13, 0x00, 0x00, 0x14, 0xf8, 0x1a, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x15, 0xf8, 0x18, 0x00, 0x00, 0x33, 0x00, 0x00, 0x16, 0xf8, 0x22, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x17, 0xf8, 0x20, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x18, 0xf8, 0x2a, 0x00, 0x00, 0x33, 0x00, 0x00, 0x19, 0xf8, 0x28, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x1a, 0xf8, 0x32, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x1b, 0xf8, 0x30, 0x00, 0x00, 0x13, 0x00, 0x00, 0x1c, 0xf8, 0x3a, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x1d, 0xf8, 0x38, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x1e, 0xf8, 0x42, 0x00, 0x00, 0x13, 0x00, 0x00, 0x1f, 0xf8, 0x40, 0x00,
+	0x00, 0x13, 0x00, 0x00, 0x20, 0xf8, 0x4a, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x21, 0xf8, 0x48, 0x00, 0x00, 0x13, 0x00, 0x00, 0x22, 0xf8, 0x52, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x23, 0xf8, 0x50, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x24, 0xf8, 0x5a, 0x00, 0x00, 0x13, 0x00, 0x00, 0x25, 0xf8, 0x58, 0x00,
+	0x00, 0x13, 0x00, 0x00, 0x26, 0xf8, 0x62, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x27, 0xf8, 0x60, 0x00, 0x00, 0x13, 0x00, 0x00, 0x28, 0xf8, 0x6a, 0x00,
+	0x00, 0x13, 0x00, 0x00, 0x29, 0xf8, 0x68, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x2a, 0xf8, 0x72, 0x00, 0x00, 0x33, 0x00, 0x00, 0x2b, 0xf8, 0x70, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x2c, 0xf8, 0x7a, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x2d, 0xf8, 0x78, 0x00, 0x00, 0x13, 0x00, 0x00, 0x2e, 0xf8, 0x82, 0x00,
+	0x00, 0x13, 0x00, 0x00, 0x2f, 0xf8, 0x80, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x30, 0xf8, 0x8a, 0x00, 0x00, 0x33, 0x00, 0x00, 0x31, 0xf8, 0x88, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x32, 0xf8, 0x92, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x33, 0xf8, 0x90, 0x00, 0x00, 0x13, 0x00, 0x00, 0x34, 0xf8, 0x9a, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x35, 0xf8, 0x98, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x36, 0xf8, 0xa2, 0x00, 0x00, 0x33, 0x00, 0x00, 0x37, 0xf8, 0xa0, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x38, 0xf8, 0xaa, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x39, 0xf8, 0xa8, 0x00, 0x00, 0x33, 0x00, 0x00, 0x3a, 0xf8, 0xb2, 0x00,
+	0x00, 0x13, 0x00, 0x00, 0x3b, 0xf8, 0xb0, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x3c, 0xf8, 0xba, 0x00, 0x00, 0x33, 0x00, 0x00, 0x3d, 0xf8, 0xb8, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x3e, 0xf8, 0xc2, 0x00, 0x00, 0x13, 0x00, 0x00,
+	0x3f, 0xf8, 0xc0, 0x00, 0x00, 0x13, 0x00, 0x00, 0x40, 0xf8, 0xca, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x41, 0xf8, 0xc8, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x42, 0xf8, 0xd2, 0x00, 0x00, 0x13, 0x00, 0x00, 0x43, 0xf8, 0xd0, 0x00,
+	0x00, 0x13, 0x00, 0x00, 0x44, 0xf8, 0xda, 0x00, 0x00, 0x33, 0x00, 0x00,
+	0x45, 0xf8, 0xd8, 0x00, 0x00, 0x33, 0x00, 0x00, 0x46, 0xf8, 0xe2, 0x00,
+	0x00, 0x33, 0x00, 0x00, 0x47, 0xf8, 0xe0, 0x00, 0x00, 0x33, 0x00, 0x00,
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+	0xff, 0x22, 0x00, 0x00, 0x17, 0x20, 0x10, 0x00, 0x5c, 0x12, 0x00, 0x00,
+	0x00, 0x40, 0x2c, 0x00, 0x00, 0x36, 0x00, 0x00, 0x19, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0xe6, 0x28, 0x00, 0x00,
+	0x01, 0xc0, 0x12, 0x02, 0xff, 0x2b, 0x00, 0x00, 0x17, 0x1c, 0xc8, 0xf9,
+	0x01, 0x0e, 0x00, 0x00, 0x1b, 0x2e, 0x20, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x16, 0x5e, 0xb0, 0x01, 0x00, 0x03, 0x00, 0x00, 0x1d, 0x00, 0x80, 0x81,
+	0x01, 0x21, 0x00, 0x00, 0xc5, 0x06, 0x00, 0x41, 0xb1, 0x14, 0x00, 0x00,
+	0x6c, 0xb4, 0x01, 0x00, 0x81, 0x20, 0x00, 0x00, 0x6f, 0xa0, 0x50, 0x00,
+	0x20, 0x13, 0x00, 0x00, 0xc5, 0x9a, 0xda, 0x86, 0xa9, 0x14, 0x00, 0x00,
+	0x6e, 0xb4, 0x01, 0x10, 0x01, 0x00, 0x00, 0x00, 0x6d, 0xb0, 0xd1, 0x06,
+	0x40, 0x2c, 0x00, 0x00, 0x6d, 0x04, 0xd0, 0x06, 0x10, 0x0c, 0x00, 0x00,
+	0x6e, 0xbc, 0xeb, 0x06, 0x00, 0x0c, 0x00, 0x00, 0x6e, 0xb0, 0xe1, 0x06,
+	0x40, 0x2c, 0x00, 0x00, 0x6d, 0xb8, 0x01, 0x40, 0xa0, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x12, 0x2e, 0x03, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x44, 0x40, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x6d, 0x74, 0x03, 0xa0,
+	0x07, 0x21, 0x00, 0x00, 0x46, 0xb4, 0x01, 0x00, 0x00, 0x14, 0x00, 0x00,
+	0x6f, 0x40, 0x06, 0xa0, 0x20, 0x21, 0x00, 0x00, 0xc6, 0x1d, 0x76, 0x04,
+	0x00, 0x14, 0x00, 0x00, 0x5d, 0xb9, 0x01, 0x00, 0x17, 0x01, 0x00, 0x00,
+	0x6f, 0x20, 0xd0, 0x15, 0x0b, 0x14, 0x00, 0x00, 0x6f, 0x74, 0x05, 0x00,
+	0xa0, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x4c, 0x41, 0x36, 0x00, 0x00,
+	0x58, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x58, 0x20, 0x6a, 0x4c,
+	0x00, 0x0e, 0x00, 0x00, 0x6e, 0x00, 0xf0, 0xc6, 0x1b, 0x34, 0x00, 0x00,
+	0x6e, 0x68, 0x01, 0x30, 0xc0, 0x20, 0x00, 0x00, 0x00, 0x60, 0x05, 0xe2,
+	0xe0, 0x08, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, 0xff, 0x22, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x16, 0x00, 0x00, 0x5f, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x5b, 0xb8, 0xc1, 0x05, 0x00, 0x22, 0x00, 0x00,
+	0x5b, 0x68, 0x05, 0xe2, 0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x5f, 0x40, 0x46, 0xe9, 0x01, 0x2e, 0x00, 0x00,
+	0x5d, 0x70, 0x05, 0xe2, 0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x5f, 0x1c, 0x86, 0xf1, 0x03, 0x0e, 0x00, 0x00,
+	0x5f, 0x00, 0x04, 0xe2, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x21, 0x00, 0x00, 0xd3, 0x2d, 0x0d, 0x14, 0xe6, 0x0b, 0x00, 0x00,
+	0x00, 0x2b, 0x00, 0x2c, 0xff, 0x23, 0x00, 0x00, 0xf8, 0x2b, 0x10, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x58, 0x60, 0x01, 0x01, 0x60, 0x2c, 0x00, 0x00,
+	0x08, 0x02, 0x50, 0x6c, 0x00, 0x14, 0x00, 0x00, 0x00, 0xbe, 0x01, 0x10,
+	0xa5, 0x21, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xe9, 0x2d, 0x02, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x4b, 0x80, 0x01, 0x00, 0x78, 0x12, 0x00, 0x00,
+	0xa6, 0x06, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0xa6, 0x3a, 0x01, 0xa0,
+	0x80, 0x21, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00, 0x5c, 0x12, 0x00, 0x00,
+	0xa6, 0xbe, 0x61, 0x80, 0x01, 0x34, 0x00, 0x00, 0xa6, 0x32, 0x01, 0x30,
+	0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x36, 0x00, 0x00,
+	0x4a, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x29, 0x00, 0x80, 0x00,
+	0xe6, 0x08, 0x00, 0x00, 0x02, 0x00, 0x00, 0x94, 0xff, 0x33, 0x00, 0x00,
+	0x4e, 0x04, 0x00, 0x00, 0x09, 0x32, 0x00, 0x00, 0x4b, 0x1c, 0xc8, 0xf9,
+	0x01, 0x0e, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x51, 0x98, 0x0a, 0xc0, 0x03, 0x2e, 0x00, 0x00, 0x8b, 0x05, 0xb0, 0x18,
+	0x30, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x9a, 0x2d, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x0a, 0x07, 0x00, 0x70,
+	0xb0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xd5, 0x2d, 0x41, 0x9a,
+	0x2d, 0x15, 0x00, 0x00, 0x9a, 0x2d, 0x02, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x10, 0xe4, 0x28, 0x00, 0x00, 0x55, 0x00, 0x01, 0x00,
+	0x0f, 0x23, 0x00, 0x00, 0x4d, 0x01, 0x60, 0xf5, 0x2d, 0x15, 0x00, 0x00,
+	0x6d, 0x18, 0xe0, 0x06, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06,
+	0x50, 0x2d, 0x00, 0x00, 0x40, 0x2c, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0xfb, 0x2d, 0x01, 0x04, 0xe6, 0x28, 0x00, 0x00, 0x00, 0x2b, 0x00, 0x2b,
+	0xff, 0x03, 0x00, 0x00, 0xec, 0x1d, 0xd6, 0x0e, 0xc2, 0x00, 0x00, 0x00,
+	0x7a, 0x01, 0x50, 0xfe, 0x2d, 0x15, 0x00, 0x00, 0x6c, 0x06, 0xc0, 0x2e,
+	0x00, 0x03, 0x00, 0x00, 0x7a, 0x01, 0x60, 0xfe, 0x2d, 0x15, 0x00, 0x00,
+	0xec, 0x1d, 0xd6, 0x0e, 0xc2, 0x00, 0x00, 0x00, 0x6c, 0x06, 0xc0, 0x6e,
+	0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x04, 0xe2, 0xe0, 0x28, 0x00, 0x00,
+	0x02, 0x00, 0x01, 0x00, 0xff, 0x03, 0x00, 0x00, 0x8a, 0x28, 0xb2, 0x05,
+	0x60, 0x2c, 0x00, 0x00, 0x5b, 0x00, 0x04, 0xe2, 0xe0, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x21, 0x00, 0x00, 0x00, 0x00, 0x04, 0xe2,
+	0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00,
+	0x00, 0x00, 0x04, 0xe2, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x03, 0x00, 0x00, 0x95, 0x2d, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x10, 0xe4, 0x28, 0x00, 0x00, 0x55, 0x00, 0x01, 0x00,
+	0x0f, 0x23, 0x00, 0x00, 0x4d, 0x01, 0x60, 0x51, 0x2c, 0x15, 0x00, 0x00,
+	0x6d, 0x18, 0xe0, 0x06, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06,
+	0x50, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10, 0xe4, 0x28, 0x00, 0x00,
+	0x55, 0x00, 0x01, 0x00, 0x0f, 0x23, 0x00, 0x00, 0x4d, 0x01, 0x60, 0xc4,
+	0x2c, 0x15, 0x00, 0x00, 0x6d, 0x18, 0xe0, 0x06, 0x00, 0x22, 0x00, 0x00,
+	0x00, 0x00, 0xf0, 0x06, 0x50, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10,
+	0xe4, 0x28, 0x00, 0x00, 0x55, 0x00, 0x01, 0x00, 0x0f, 0x23, 0x00, 0x00,
+	0x4d, 0x01, 0x60, 0xb7, 0x2d, 0x15, 0x00, 0x00, 0x6d, 0x18, 0xe0, 0x06,
+	0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06, 0x50, 0x2d, 0x00, 0x00,
+	0x83, 0x09, 0x00, 0x58, 0xb0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x5d, 0x2e, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x10,
+	0xe6, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x16, 0x00, 0x00, 0x72, 0x10, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0xc5, 0x1d, 0xf6, 0x0e, 0xe0, 0x0c, 0x00, 0x00,
+	0x88, 0x01, 0x20, 0xd7, 0x3b, 0x34, 0x00, 0x00, 0x80, 0xc9, 0x05, 0x00,
+	0xa5, 0x20, 0x00, 0x00, 0x88, 0x09, 0x00, 0x58, 0xb0, 0x0c, 0x00, 0x00,
+	0x88, 0x0d, 0x00, 0x58, 0xb0, 0x2c, 0x00, 0x00, 0x2c, 0x2e, 0x01, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x2c, 0x2e, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x47, 0x2e, 0x01, 0x00, 0x00, 0x15, 0x00, 0x00, 0x88, 0x05, 0x00, 0x58,
+	0xb0, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x52, 0x2e, 0x01, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x74, 0x01, 0x40, 0x2b, 0x2e, 0x35, 0x00, 0x00,
+	0x2b, 0xa8, 0x02, 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x2d, 0xb0, 0x0a, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x2f, 0xb8, 0x12, 0x00,
+	0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x31, 0xc0, 0x1a, 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x33, 0xc8, 0x22, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x35, 0xd0, 0x2a, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x37, 0xd8, 0x32, 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x39, 0xe0, 0x3a, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x3b, 0xe8, 0x42, 0x00,
+	0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x3d, 0xf0, 0x4a, 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0x52, 0x00, 0x20, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x41, 0x00, 0x5b, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x43, 0x08, 0x63, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x1b, 0x68, 0x02, 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x1d, 0x70, 0x0a, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x1f, 0x78, 0x12, 0x00,
+	0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0xa0, 0x00, 0x00, 0x35, 0x00, 0x00, 0x21, 0x80, 0x1a, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x23, 0x88, 0x22, 0x00, 0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x12, 0x11, 0xf2, 0x16, 0x20, 0x2c, 0x00, 0x00,
+	0x6f, 0xfd, 0xf7, 0x0e, 0x10, 0x0c, 0x00, 0x00, 0x89, 0xbc, 0xf3, 0x0e,
+	0xe0, 0x0c, 0x00, 0x00, 0xef, 0xf0, 0x07, 0x00, 0xd0, 0x2c, 0x00, 0x00,
+	0x00, 0x04, 0xe0, 0x06, 0x00, 0x0c, 0x00, 0x00, 0x6e, 0xbc, 0x05, 0x40,
+	0xa0, 0x2c, 0x00, 0x00, 0xef, 0x04, 0xf0, 0x0e, 0x15, 0x0c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xd0, 0x2c, 0x20, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xc2, 0xbc, 0x23, 0x09, 0xe0, 0x0c, 0x00, 0x00,
+	0x92, 0x48, 0x24, 0x09, 0x00, 0x2c, 0x00, 0x00, 0x4d, 0x01, 0x00, 0x00,
+	0x00, 0x15, 0x00, 0x00
+};
+
+static const uint8_t csem_int_table_data_e1[] = {
+	0x24, 0x0f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xb5, 0x0e, 0x00, 0x00, 0xd0, 0x0e, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x08, 0x03, 0x00, 0x00,
+	0x09, 0x03, 0x00, 0x00, 0x21, 0x01, 0x00, 0x00, 0x18, 0x01, 0x00, 0x00,
+	0x0f, 0x01, 0x00, 0x00, 0x06, 0x01, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0xf6, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0x00,
+	0xe4, 0x00, 0x00, 0x00, 0x43, 0x00, 0x00, 0x00, 0xc0, 0x04, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x46, 0x05, 0x00, 0x00,
+	0x48, 0x05, 0x00, 0x00, 0x0b, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x42, 0x0d, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xe3, 0x0c, 0x00, 0x00, 0xce, 0x0c, 0x00, 0x00,
+	0xe6, 0x0c, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xae, 0x10, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xfb, 0x10, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xc9, 0x14, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x12, 0x16, 0x00, 0x00, 0x08, 0x17, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x95, 0x17, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x13, 0x16, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x63, 0x1b, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x6f, 0x1b, 0x00, 0x00
+};
+
+static const uint8_t csem_pram_data_e1[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x02, 0x1f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x09, 0x05, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x09, 0x05, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0xef, 0x01, 0xf0, 0x2e,
+	0x04, 0x23, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x85, 0x7f, 0x40, 0x00, 0x40, 0x06, 0x00, 0x00, 0x98, 0x7f, 0x08, 0x00,
+	0x40, 0x06, 0x00, 0x00, 0x94, 0x7f, 0x18, 0x00, 0x40, 0x26, 0x00, 0x00,
+	0x85, 0x60, 0x02, 0x48, 0xa0, 0x0c, 0x00, 0x00, 0x96, 0x7f, 0x10, 0x00,
+	0x40, 0x26, 0x00, 0x00, 0x92, 0x7f, 0x48, 0x00, 0x40, 0x26, 0x00, 0x00,
+	0x90, 0x7f, 0x50, 0x00, 0x40, 0x06, 0x00, 0x00, 0x8e, 0x7f, 0x58, 0x00,
+	0x40, 0x26, 0x00, 0x00, 0x8c, 0x7f, 0x60, 0x00, 0x40, 0x26, 0x00, 0x00,
+	0x8a, 0x7f, 0x68, 0x00, 0x40, 0x06, 0x00, 0x00, 0x88, 0x7f, 0x70, 0x00,
+	0x40, 0x26, 0x00, 0x00, 0x86, 0x7f, 0x78, 0x00, 0x40, 0x26, 0x00, 0x00,
+	0x89, 0x04, 0x62, 0x17, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x50, 0x48,
+	0x21, 0x14, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0x94, 0x52, 0x3a, 0x0f, 0x04, 0x34, 0x00, 0x00, 0x6f, 0xcf, 0x03, 0x00,
+	0x03, 0x21, 0x00, 0x00, 0x92, 0x60, 0x04, 0x48, 0xa0, 0x0c, 0x00, 0x00,
+	0x00, 0x04, 0x20, 0x89, 0x24, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x89, 0x04, 0x42, 0x1c, 0x00, 0x15, 0x00, 0x00, 0x90, 0x64, 0x02, 0x48,
+	0xa0, 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00, 0x09, 0x24, 0x34, 0x00, 0x00,
+	0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x89, 0x04, 0x42, 0x21, 0x00, 0x35, 0x00, 0x00,
+	0x8e, 0x64, 0x04, 0x48, 0xa0, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0xe0, 0x88,
+	0x23, 0x14, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x89, 0x04, 0x42, 0x26,
+	0x00, 0x15, 0x00, 0x00, 0x8c, 0x58, 0x02, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0x00, 0x10, 0xc0, 0x08, 0x23, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x89, 0x04, 0x42, 0x2b, 0x00, 0x35, 0x00, 0x00, 0x8a, 0x58, 0x04, 0x48,
+	0xa0, 0x2c, 0x00, 0x00, 0x00, 0x14, 0xa0, 0x88, 0x22, 0x14, 0x00, 0x00,
+	0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x89, 0x04, 0x42, 0x30, 0x00, 0x35, 0x00, 0x00,
+	0x88, 0x5c, 0x02, 0x48, 0xa0, 0x2c, 0x00, 0x00, 0x00, 0x18, 0x80, 0x08,
+	0x22, 0x14, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x89, 0x04, 0x42, 0x35,
+	0x00, 0x35, 0x00, 0x00, 0x86, 0x5c, 0x04, 0x48, 0xa0, 0x0c, 0x00, 0x00,
+	0x00, 0x1c, 0x60, 0x88, 0x21, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x89, 0x04, 0x42, 0x3a, 0x00, 0x35, 0x00, 0x00, 0x00, 0x10, 0x04, 0xfa,
+	0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x22, 0x00, 0x00,
+	0x00, 0x00, 0x0c, 0x10, 0xe6, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x12, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x04, 0x00, 0x60, 0x48,
+	0x00, 0x15, 0x00, 0x00, 0x00, 0x20, 0x1b, 0xfe, 0xff, 0x36, 0x00, 0x00,
+	0x73, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x80, 0x42, 0x00, 0xc0,
+	0x03, 0x34, 0x00, 0x00, 0x80, 0x12, 0x00, 0xa0, 0x83, 0x21, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x04, 0x00, 0x60, 0x4e,
+	0x00, 0x15, 0x00, 0x00, 0x00, 0xe0, 0x1a, 0xfe, 0xff, 0x16, 0x00, 0x00,
+	0x73, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x80, 0x42, 0x00, 0x80,
+	0x02, 0x34, 0x00, 0x00, 0x80, 0x12, 0x00, 0xa0, 0x83, 0x21, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x05, 0x00, 0xb0, 0x01,
+	0x00, 0x03, 0x00, 0x00, 0x8b, 0x7f, 0x08, 0x00, 0x40, 0x26, 0x00, 0x00,
+	0x97, 0x7f, 0x28, 0x00, 0x40, 0x26, 0x00, 0x00, 0x87, 0x7f, 0x10, 0x00,
+	0x40, 0x26, 0x00, 0x00, 0x97, 0x2c, 0x02, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x80, 0x18, 0x06, 0xa0, 0x25, 0x21, 0x00, 0x00, 0x95, 0x7f, 0x30, 0x00,
+	0x40, 0x06, 0x00, 0x00, 0x93, 0x7f, 0x38, 0x00, 0x40, 0x26, 0x00, 0x00,
+	0x91, 0x7f, 0x40, 0x00, 0x40, 0x06, 0x00, 0x00, 0x8f, 0x7f, 0x48, 0x00,
+	0x40, 0x26, 0x00, 0x00, 0xa0, 0x7f, 0x50, 0x00, 0x40, 0x06, 0x00, 0x00,
+	0x9e, 0x7f, 0x58, 0x00, 0x40, 0x06, 0x00, 0x00, 0x9c, 0x7f, 0x60, 0x00,
+	0x40, 0x06, 0x00, 0x00, 0x00, 0x00, 0x60, 0xe0, 0x66, 0x34, 0x00, 0x00,
+	0xef, 0xbd, 0x0b, 0x00, 0x8a, 0x20, 0x00, 0x00, 0x89, 0x04, 0x62, 0x63,
+	0x00, 0x15, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x86, 0xbd, 0x29, 0xa2, 0x8a, 0x21, 0x00, 0x00, 0x97, 0x5c, 0x72, 0xe8,
+	0xa1, 0x14, 0x00, 0x00, 0xee, 0xbc, 0x2d, 0x30, 0x03, 0x20, 0x00, 0x00,
+	0x95, 0x2c, 0x04, 0x48, 0xa0, 0x0c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x40,
+	0x00, 0x14, 0x00, 0x00, 0x86, 0xbd, 0x29, 0xa2, 0x8a, 0x21, 0x00, 0x00,
+	0x95, 0x54, 0xe2, 0x0e, 0x62, 0x2c, 0x00, 0x00, 0x89, 0x04, 0x42, 0x68,
+	0x00, 0x15, 0x00, 0x00, 0x93, 0x30, 0x02, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0x00, 0x04, 0x00, 0x80, 0x00, 0x14, 0x00, 0x00, 0x86, 0xbd, 0x29, 0xa2,
+	0x8a, 0x21, 0x00, 0x00, 0x93, 0x4c, 0xe2, 0x0e, 0x62, 0x2c, 0x00, 0x00,
+	0x89, 0x04, 0x42, 0x6d, 0x00, 0x15, 0x00, 0x00, 0x91, 0x30, 0x04, 0x48,
+	0xa0, 0x0c, 0x00, 0x00, 0x00, 0x04, 0x00, 0xc0, 0x00, 0x34, 0x00, 0x00,
+	0x86, 0xbd, 0x29, 0xa2, 0x8a, 0x21, 0x00, 0x00, 0x91, 0x44, 0xe2, 0x0e,
+	0x62, 0x2c, 0x00, 0x00, 0x89, 0x04, 0x42, 0x72, 0x00, 0x35, 0x00, 0x00,
+	0x86, 0x01, 0x00, 0x58, 0xb0, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xa4, 0x00, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00, 0x18, 0xfe,
+	0xff, 0x16, 0x00, 0x00, 0x05, 0x08, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00,
+	0xc2, 0x1e, 0x5a, 0x01, 0xe0, 0x2c, 0x00, 0x00, 0x15, 0x14, 0x32, 0x17,
+	0x00, 0x0c, 0x00, 0x00, 0x99, 0x7f, 0x18, 0x00, 0x40, 0x06, 0x00, 0x00,
+	0x90, 0x7f, 0x20, 0x00, 0x40, 0x26, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x8b, 0x7f, 0x08, 0x00, 0x60, 0x06, 0x00, 0x00,
+	0x19, 0x07, 0x00, 0x70, 0xb0, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc1,
+	0x03, 0x14, 0x00, 0x00, 0x05, 0x54, 0x20, 0x11, 0x8a, 0x20, 0x00, 0x00,
+	0x8c, 0x55, 0x50, 0x00, 0x01, 0x2d, 0x00, 0x00, 0x1a, 0x07, 0x00, 0x70,
+	0xb0, 0x0c, 0x00, 0x00, 0x16, 0x80, 0x50, 0x01, 0x21, 0x2c, 0x00, 0x00,
+	0x0c, 0x56, 0x50, 0x01, 0x01, 0x2d, 0x00, 0x00, 0x05, 0x54, 0x50, 0x00,
+	0x01, 0x0c, 0x00, 0x00, 0x10, 0x07, 0x00, 0x70, 0xb0, 0x0c, 0x00, 0x00,
+	0x14, 0x78, 0x50, 0x01, 0x21, 0x2c, 0x00, 0x00, 0x8c, 0x56, 0x50, 0x01,
+	0x01, 0x0d, 0x00, 0x00, 0x05, 0x54, 0x50, 0x00, 0x01, 0x0c, 0x00, 0x00,
+	0x11, 0x07, 0x00, 0x70, 0xb0, 0x2c, 0x00, 0x00, 0x12, 0x70, 0x50, 0x01,
+	0x21, 0x0c, 0x00, 0x00, 0x0c, 0x57, 0x50, 0x01, 0x01, 0x0d, 0x00, 0x00,
+	0x8d, 0x7f, 0x00, 0x00, 0x60, 0x26, 0x00, 0x00, 0x05, 0x54, 0x50, 0x00,
+	0x01, 0x0c, 0x00, 0x00, 0x89, 0x7f, 0x10, 0x00, 0x60, 0x26, 0x00, 0x00,
+	0x87, 0x7f, 0x18, 0x00, 0x60, 0x26, 0x00, 0x00, 0x05, 0x38, 0x00, 0x40,
+	0xa0, 0x0c, 0x00, 0x00, 0x05, 0x34, 0x00, 0x40, 0xa0, 0x0c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xb3, 0x00, 0x03, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xc6, 0x00, 0x03, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x19, 0x07, 0x00, 0x70, 0xb0, 0x0c, 0x00, 0x00, 0x89, 0x25, 0x96, 0x19,
+	0x61, 0x0c, 0x00, 0x00, 0x1a, 0x07, 0x00, 0x70, 0xb0, 0x0c, 0x00, 0x00,
+	0x09, 0x26, 0xa8, 0x19, 0x61, 0x0c, 0x00, 0x00, 0x10, 0x07, 0x00, 0x70,
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+	0x00, 0x36, 0x00, 0x00, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x81, 0x00, 0x12, 0x80, 0x00, 0x38, 0x00, 0x00, 0x02, 0x01, 0x14, 0x80,
+	0x00, 0x38, 0x00, 0x00, 0x4f, 0x08, 0x00, 0x00, 0x7c, 0x32, 0x00, 0x00,
+	0x4e, 0x18, 0x00, 0x00, 0x3e, 0x32, 0x00, 0x00, 0x4f, 0x38, 0x05, 0xe2,
+	0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x27, 0x00, 0xd0, 0x46, 0x1b, 0x14, 0x00, 0x00, 0x57, 0x40, 0x01, 0x30,
+	0xa0, 0x20, 0x00, 0x00, 0x51, 0x40, 0x05, 0xe2, 0xe0, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x52, 0x58, 0x31, 0xc5,
+	0x15, 0x00, 0x00, 0x00, 0x53, 0x48, 0x05, 0xe2, 0xe0, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x55, 0x00, 0x8c, 0xf1,
+	0x03, 0x2e, 0x00, 0x00, 0x55, 0x00, 0x04, 0xe2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x21, 0x00, 0x00, 0xe8, 0x1a, 0x60, 0xd1,
+	0x1a, 0x35, 0x00, 0x00, 0xef, 0xd0, 0xf2, 0x56, 0x2d, 0x20, 0x00, 0x00,
+	0xca, 0x29, 0xe7, 0x1e, 0x60, 0x2c, 0x00, 0x00, 0x6e, 0x06, 0x00, 0x60,
+	0xb0, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xdb, 0x1a, 0x02, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x6f, 0x0b, 0x0e, 0x2e, 0x00, 0x0f, 0x00, 0x00,
+	0x30, 0x27, 0x20, 0x83, 0xe0, 0x01, 0x00, 0x00, 0x89, 0x17, 0x60, 0xda,
+	0x1a, 0x15, 0x00, 0x00, 0xef, 0x02, 0xfc, 0x0e, 0x2a, 0x00, 0x00, 0x00,
+	0x6e, 0x06, 0xe0, 0x9e, 0x72, 0x01, 0x00, 0x00, 0xe1, 0x1a, 0x00, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x0e, 0x13, 0x00, 0x5f, 0x50, 0x0c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xe1, 0x1a, 0x02, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0xe1, 0x1a, 0x10, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x14, 0x00, 0x33,
+	0x50, 0x2d, 0x00, 0x00, 0x68, 0x1a, 0x10, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0xca, 0x05, 0xa0, 0x1c, 0x10, 0x0c, 0x00, 0x00, 0x00, 0x2c, 0x13, 0x00,
+	0x00, 0x39, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x81, 0xb9, 0xc7, 0x2e, 0xe0, 0x2c, 0x00, 0x00, 0xee, 0xc1, 0xc9, 0x2e,
+	0x06, 0x34, 0x00, 0x00, 0xf0, 0xd9, 0x07, 0x00, 0x22, 0x21, 0x00, 0x00,
+	0xec, 0x72, 0x60, 0x27, 0x10, 0x0c, 0x00, 0x00, 0x6f, 0xbd, 0xc3, 0x16,
+	0x20, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x81, 0x00, 0x02, 0x1b, 0x00, 0x38, 0x00, 0x00, 0x01, 0x01, 0x52, 0x1b,
+	0x00, 0x38, 0x00, 0x00, 0x82, 0x00, 0x04, 0x1b, 0x00, 0x38, 0x00, 0x00,
+	0x02, 0x01, 0x54, 0x1b, 0x00, 0x38, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xec, 0xb4, 0x05, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0xec, 0xb4, 0xd5, 0x0e, 0x24, 0x2c, 0x00, 0x00, 0x6d, 0xb1, 0xd3, 0x0e,
+	0x25, 0x0c, 0x00, 0x00, 0x6f, 0xb5, 0xd3, 0x0e, 0x25, 0x0c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xed, 0xbc, 0x03, 0x48,
+	0xa0, 0x2c, 0x00, 0x00, 0x00, 0x04, 0xe0, 0x26, 0x55, 0x0d, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x85, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xed, 0xb0, 0x05, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0x00, 0x00, 0xe0, 0x26, 0x53, 0x2d, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x10, 0xe4, 0x28, 0x00, 0x00, 0x0a, 0x00, 0x01, 0x00,
+	0x0f, 0x23, 0x00, 0x00, 0xe2, 0x04, 0x60, 0x05, 0x1b, 0x15, 0x00, 0x00,
+	0x6d, 0x08, 0xe0, 0x06, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06,
+	0x50, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0xb0, 0x06, 0x00, 0x80, 0x00, 0x14, 0x00, 0x00, 0x80, 0xbe, 0x07, 0xa0,
+	0xa5, 0x21, 0x00, 0x00, 0xef, 0x05, 0xf0, 0x1e, 0x11, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x21, 0x1b, 0x02, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x37, 0xc0, 0x01, 0x00, 0x78, 0x12, 0x00, 0x00,
+	0x39, 0x00, 0x80, 0x03, 0x00, 0x23, 0x00, 0x00, 0x37, 0x00, 0x04, 0x00,
+	0x5c, 0x12, 0x00, 0x00, 0x39, 0x04, 0x00, 0xc0, 0x04, 0x12, 0x00, 0x00,
+	0x3b, 0x00, 0xc0, 0x03, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00,
+	0x00, 0x16, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x37, 0x04, 0xc0, 0xc1, 0x01, 0x2e, 0x00, 0x00, 0x39, 0x04, 0x00, 0x80,
+	0x04, 0x32, 0x00, 0x00, 0x3a, 0x00, 0xd0, 0x03, 0x00, 0x23, 0x00, 0x00,
+	0x3e, 0x00, 0xf0, 0x03, 0x00, 0x23, 0x00, 0x00, 0x40, 0x00, 0x10, 0x04,
+	0x00, 0x23, 0x00, 0x00, 0x42, 0x00, 0x30, 0x04, 0x00, 0x23, 0x00, 0x00,
+	0x38, 0x08, 0xc0, 0x4b, 0x2b, 0x00, 0x00, 0x00, 0x2c, 0xb0, 0xb0, 0x03,
+	0x60, 0x2c, 0x00, 0x00, 0xc0, 0x16, 0x04, 0x11, 0xe6, 0x08, 0x00, 0x00,
+	0x03, 0x00, 0x00, 0x00, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,
+	0xe6, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00,
+	0x30, 0x07, 0x00, 0x5f, 0x50, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x4c, 0x1b, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0x30, 0x0b, 0x00, 0x00,
+	0x00, 0x34, 0x00, 0x00, 0xf0, 0xed, 0x00, 0xa0, 0xa2, 0x01, 0x00, 0x00,
+	0x3d, 0x00, 0xe0, 0x03, 0x00, 0x03, 0x00, 0x00, 0x3b, 0x04, 0x00, 0x48,
+	0x03, 0x12, 0x00, 0x00, 0x3d, 0x04, 0x00, 0x08, 0x0a, 0x32, 0x00, 0x00,
+	0xb1, 0xc4, 0x02, 0x00, 0x00, 0x14, 0x00, 0x00, 0xbe, 0xe0, 0x20, 0xa0,
+	0x03, 0x21, 0x00, 0x00, 0x30, 0x13, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0xf0, 0xe9, 0x00, 0xa0, 0xa2, 0x21, 0x00, 0x00, 0x37, 0x40, 0x00, 0x00,
+	0x78, 0x12, 0x00, 0x00, 0x37, 0x00, 0x00, 0x00, 0x5c, 0x32, 0x00, 0x00,
+	0x37, 0x04, 0xc0, 0xc1, 0x01, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00,
+	0x00, 0x16, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x3a, 0x04, 0x00, 0x08, 0x0f, 0x12, 0x00, 0x00, 0x37, 0x04, 0x00, 0x88,
+	0x05, 0x12, 0x00, 0x00, 0x39, 0x00, 0xc0, 0x03, 0x00, 0x03, 0x00, 0x00,
+	0x3f, 0x00, 0x00, 0x04, 0x00, 0x23, 0x00, 0x00, 0x41, 0x00, 0x20, 0x04,
+	0x00, 0x03, 0x00, 0x00, 0x3f, 0x1b, 0x21, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x00, 0x00, 0xf0, 0x5e, 0x00, 0x34, 0x00, 0x00, 0x43, 0xbc, 0x07, 0x00,
+	0x8a, 0x21, 0x00, 0x00, 0x02, 0x08, 0x80, 0x03, 0x60, 0x2c, 0x00, 0x00,
+	0x45, 0x1b, 0x20, 0x00, 0x00, 0x35, 0x00, 0x00, 0x0b, 0x04, 0x00, 0x80,
+	0x0e, 0x12, 0x00, 0x00, 0x3a, 0x90, 0x01, 0x00, 0xd8, 0x32, 0x00, 0x00,
+	0x30, 0x23, 0x00, 0x5f, 0x50, 0x2c, 0x00, 0x00, 0x37, 0x04, 0x00, 0x88,
+	0x05, 0x12, 0x00, 0x00, 0x3a, 0x00, 0x00, 0x08, 0x0f, 0x32, 0x00, 0x00,
+	0x45, 0x1b, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0x3a, 0x00, 0x00, 0x00,
+	0xd8, 0x12, 0x00, 0x00, 0x0b, 0x08, 0x00, 0x80, 0x0e, 0x12, 0x00, 0x00,
+	0x00, 0x00, 0x44, 0x10, 0xe6, 0x28, 0x00, 0x00, 0x01, 0xc0, 0x16, 0x02,
+	0xff, 0x0b, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0xe6, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0xef, 0x16, 0x00, 0x03,
+	0x00, 0x03, 0x00, 0x00, 0x0e, 0x63, 0xf0, 0xee, 0x7b, 0x34, 0x00, 0x00,
+	0xf0, 0xbd, 0x07, 0x10, 0xa2, 0x20, 0x00, 0x00, 0x30, 0xbc, 0xc7, 0xd8,
+	0x01, 0x0e, 0x00, 0x00, 0x01, 0x40, 0x40, 0x00, 0x78, 0x32, 0x00, 0x00,
+	0x30, 0x08, 0x0c, 0xc0, 0x03, 0x0e, 0x00, 0x00, 0x00, 0xc0, 0x04, 0xec,
+	0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x22, 0x00, 0x00,
+	0x59, 0x1b, 0x62, 0x57, 0x1b, 0x35, 0x00, 0x00, 0x01, 0x20, 0x10, 0x00,
+	0x5c, 0x32, 0x00, 0x00, 0x00, 0x60, 0x00, 0x20, 0x50, 0x0d, 0x00, 0x00,
+	0x17, 0x00, 0x9c, 0x10, 0xe6, 0x2b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
+	0xff, 0x13, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0xe8, 0x16, 0x00, 0x00,
+	0x57, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0xda, 0x0a, 0x0e, 0x2e,
+	0x00, 0x0f, 0x00, 0x00, 0xa8, 0xa0, 0x52, 0x20, 0x02, 0x14, 0x00, 0x00,
+	0x58, 0x14, 0x08, 0x30, 0x03, 0x21, 0x00, 0x00, 0x32, 0x08, 0x1e, 0x33,
+	0x00, 0x22, 0x00, 0x00, 0x28, 0x17, 0x60, 0x57, 0x1b, 0x15, 0x00, 0x00,
+	0xda, 0x01, 0xac, 0x25, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0xa0, 0x35,
+	0x50, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x0b, 0x00, 0x40, 0x38, 0x00, 0x23, 0x00, 0x00, 0x01, 0x40, 0x00, 0x00,
+	0x78, 0x12, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00, 0x5c, 0x12, 0x00, 0x00,
+	0x80, 0x42, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x80, 0x16, 0x00, 0xa0,
+	0x83, 0x01, 0x00, 0x00, 0x0b, 0x07, 0x00, 0x00, 0x08, 0x32, 0x00, 0x00,
+	0x8b, 0x06, 0x00, 0x80, 0x08, 0x12, 0x00, 0x00, 0x83, 0x00, 0x00, 0x20,
+	0x02, 0x23, 0x00, 0x00, 0x00, 0x7c, 0x43, 0x20, 0x04, 0x14, 0x00, 0x00,
+	0x86, 0x11, 0x08, 0x30, 0x8a, 0x01, 0x00, 0x00, 0x07, 0x00, 0x9c, 0x10,
+	0xe6, 0x0b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0xff, 0x13, 0x00, 0x00,
+	0x83, 0x08, 0x0e, 0x2e, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x64, 0x17, 0x02,
+	0x00, 0x36, 0x00, 0x00, 0x74, 0x10, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x83, 0x0c, 0x02, 0x28, 0x04, 0x34, 0x00, 0x00, 0x83, 0x00, 0x0a, 0x30,
+	0x00, 0x01, 0x00, 0x00, 0x4e, 0x09, 0x60, 0x77, 0x1b, 0x35, 0x00, 0x00,
+	0x74, 0x0d, 0x42, 0x17, 0x00, 0x2c, 0x00, 0x00, 0x2b, 0xaf, 0x3c, 0x18,
+	0x60, 0x0c, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x3c, 0x16, 0x00, 0x00,
+	0x57, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0xda, 0x0a, 0x0e, 0x2e,
+	0x00, 0x0f, 0x00, 0x00, 0x58, 0xa0, 0x22, 0x83, 0xe0, 0x20, 0x00, 0x00,
+	0x28, 0x17, 0x60, 0x7e, 0x1b, 0x35, 0x00, 0x00, 0x31, 0x07, 0xa0, 0x1d,
+	0xc0, 0x21, 0x00, 0x00, 0x5a, 0x07, 0xa0, 0x25, 0x00, 0x03, 0x00, 0x00,
+	0x0b, 0x00, 0x40, 0x38, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00,
+	0x00, 0x36, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x01, 0x40, 0x00, 0x00, 0x78, 0x12, 0x00, 0x00, 0x10, 0x08, 0x0c, 0xc0,
+	0x03, 0x2e, 0x00, 0x00, 0x00, 0x40, 0x04, 0xec, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x22, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00,
+	0x5c, 0x12, 0x00, 0x00, 0x8b, 0x0a, 0x00, 0x80, 0x08, 0x12, 0x00, 0x00,
+	0x05, 0x00, 0x30, 0x08, 0x00, 0x23, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20,
+	0x50, 0x2d, 0x00, 0x00, 0x07, 0x00, 0x9c, 0x10, 0xe6, 0x0b, 0x00, 0x00,
+	0x02, 0x00, 0x00, 0x00, 0xff, 0x13, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00
+};
+
+static const uint8_t xsem_int_table_data_e1[] = {
+	0xe5, 0x1d, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x13, 0x1c, 0x00, 0x00, 0x92, 0x0e, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x98, 0x0b, 0x00, 0x00,
+	0xe2, 0x0b, 0x00, 0x00, 0x04, 0x0c, 0x00, 0x00, 0x71, 0x0e, 0x00, 0x00,
+	0x58, 0x0c, 0x00, 0x00, 0x59, 0x0c, 0x00, 0x00, 0xc4, 0x0c, 0x00, 0x00,
+	0xc5, 0x0c, 0x00, 0x00, 0x24, 0x0d, 0x00, 0x00, 0x5d, 0x0d, 0x00, 0x00,
+	0x5e, 0x0d, 0x00, 0x00, 0x9c, 0x0c, 0x00, 0x00, 0x9d, 0x0c, 0x00, 0x00,
+	0x75, 0x0c, 0x00, 0x00, 0x6a, 0x0e, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x85, 0x04, 0x00, 0x00, 0x87, 0x04, 0x00, 0x00, 0x89, 0x04, 0x00, 0x00,
+	0x8b, 0x04, 0x00, 0x00, 0x2c, 0x03, 0x00, 0x00, 0x2d, 0x03, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x6f, 0x14, 0x00, 0x00, 0xe4, 0x18, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x21, 0x19, 0x00, 0x00,
+	0x24, 0x1b, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xa8, 0x2f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x1b, 0x30, 0x00, 0x00, 0xb5, 0x38, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x26, 0x38, 0x00, 0x00,
+	0xb6, 0x38, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xb7, 0x38, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xb8, 0x38, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xb9, 0x38, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xba, 0x38, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xcd, 0x2e, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x3d, 0x28, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x1a, 0x2a, 0x00, 0x00,
+	0x49, 0x2f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x3e, 0x28, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x78, 0x2f, 0x00, 0x00, 0x79, 0x2f, 0x00, 0x00
+};
+
+static const uint8_t xsem_pram_data_e1[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x04, 0x1f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x48, 0x04, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x48, 0x04, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x0c, 0xc4, 0x00, 0x20,
+	0x00, 0x0f, 0x00, 0x00, 0x86, 0x31, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00,
+	0x1c, 0x24, 0x00, 0xa0, 0x00, 0x01, 0x00, 0x00, 0x42, 0x70, 0x00, 0x00,
+	0x00, 0x34, 0x00, 0x00, 0x8e, 0x5d, 0x00, 0xa0, 0x07, 0x21, 0x00, 0x00,
+	0xc1, 0xcc, 0x02, 0x00, 0x00, 0x14, 0x00, 0x00, 0x89, 0x60, 0x00, 0xa0,
+	0x07, 0x21, 0x00, 0x00, 0x0c, 0xc4, 0x00, 0xb0, 0x02, 0x2f, 0x00, 0x00,
+	0x8e, 0x25, 0x02, 0x00, 0x00, 0x14, 0x00, 0x00, 0x99, 0x28, 0x00, 0xa0,
+	0x00, 0x21, 0x00, 0x00, 0x99, 0xf8, 0x03, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x80, 0x4c, 0x00, 0xa0, 0xa5, 0x21, 0x00, 0x00, 0x11, 0x00, 0x00, 0x01,
+	0x00, 0x23, 0x00, 0x00, 0x0f, 0x00, 0x60, 0x01, 0x00, 0x23, 0x00, 0x00,
+	0x42, 0x30, 0x90, 0x09, 0x2d, 0x14, 0x00, 0x00, 0x9c, 0x5d, 0x02, 0x00,
+	0x07, 0x20, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0x0d, 0x00, 0x40, 0x09, 0x00, 0x03, 0x00, 0x00, 0x89, 0x24, 0x02, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x92, 0x4c, 0x02, 0xa6, 0x03, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0xc0, 0x18, 0x63, 0x14, 0x00, 0x00, 0x8a, 0x44, 0x66, 0x36,
+	0x8a, 0x00, 0x00, 0x00, 0x8c, 0x05, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x98, 0x59, 0x66, 0xa6, 0x80, 0x21, 0x00, 0x00, 0x10, 0x02, 0x23, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x99, 0x0c, 0x14, 0x00, 0x00,
+	0x8f, 0xd8, 0x67, 0x00, 0x8a, 0x01, 0x00, 0x00, 0x97, 0x5c, 0x02, 0x01,
+	0x66, 0x2c, 0x00, 0x00, 0x98, 0xa1, 0x06, 0x58, 0xa0, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x5c, 0x00, 0x04, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x07, 0x02, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x07,
+	0x02, 0x38, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x06, 0x02, 0x38, 0x00, 0x00,
+	0x93, 0x3c, 0x02, 0x00, 0x00, 0x34, 0x00, 0x00, 0x8d, 0x70, 0x00, 0xa0,
+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x06, 0x02, 0x18, 0x00, 0x00,
+	0xb4, 0xd0, 0xc2, 0x08, 0x60, 0x2c, 0x00, 0x00, 0x8d, 0x6c, 0xb4, 0xd1,
+	0x46, 0x34, 0x00, 0x00, 0x8b, 0x24, 0x02, 0x30, 0x00, 0x20, 0x00, 0x00,
+	0x8b, 0xd0, 0xc2, 0x09, 0x27, 0x14, 0x00, 0x00, 0x80, 0x34, 0x02, 0x30,
+	0x25, 0x00, 0x00, 0x00, 0x1c, 0x04, 0xc0, 0x01, 0x10, 0x0c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x39, 0x00, 0x05, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x8b, 0x30, 0xb2, 0x08, 0x20, 0x0c, 0x00, 0x00,
+	0x8b, 0xd0, 0xc2, 0x09, 0x27, 0x14, 0x00, 0x00, 0x80, 0x34, 0x02, 0x30,
+	0x25, 0x00, 0x00, 0x00, 0xb4, 0xd0, 0xc2, 0x41, 0x00, 0x14, 0x00, 0x00,
+	0x8c, 0x70, 0x00, 0x00, 0x03, 0x21, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x32, 0x00, 0x04, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x8d, 0x00, 0x00, 0x48, 0xb0, 0x2c, 0x00, 0x00, 0x96, 0x05, 0x30, 0xc9,
+	0x46, 0x34, 0x00, 0x00, 0x96, 0x4d, 0x12, 0x01, 0x80, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x49, 0x00, 0x01, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x8d, 0x5c, 0x02, 0x00, 0xc0, 0x2c, 0x00, 0x00,
+	0x00, 0x04, 0xf0, 0x08, 0x00, 0x0c, 0x00, 0x00, 0x8a, 0x3c, 0xd2, 0x08,
+	0x25, 0x34, 0x00, 0x00, 0x8a, 0x50, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x8d, 0x30, 0x02, 0x00, 0xc0, 0x2c, 0x00, 0x00, 0x00, 0x04, 0x30, 0x09,
+	0x00, 0x2c, 0x00, 0x00, 0x96, 0x45, 0x26, 0xc9, 0x24, 0x14, 0x00, 0x00,
+	0x89, 0x49, 0x02, 0x00, 0x00, 0x20, 0x00, 0x00, 0x8b, 0x2c, 0x92, 0x58,
+	0x00, 0x34, 0x00, 0x00, 0x8f, 0x44, 0x06, 0x00, 0x03, 0x01, 0x00, 0x00,
+	0x96, 0x01, 0x30, 0x09, 0x00, 0x23, 0x00, 0x00, 0x98, 0x61, 0x06, 0x4b,
+	0x00, 0x14, 0x00, 0x00, 0x0d, 0x70, 0x00, 0x10, 0x03, 0x01, 0x00, 0x00,
+	0x0d, 0x70, 0x00, 0x40, 0xa0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xb8, 0x01, 0x08, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x8c, 0x97, 0x00,
+	0x00, 0x36, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x8a, 0x40, 0xa0, 0x88, 0x22, 0x14, 0x00, 0x00, 0x1c, 0x34, 0x00, 0x30,
+	0x00, 0x00, 0x00, 0x00, 0x1c, 0x30, 0x00, 0x40, 0xa0, 0x0c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xe0, 0x01, 0x07, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x98, 0x05, 0x80, 0x19, 0x10, 0x0c, 0x00, 0x00, 0x98, 0xa1, 0x06, 0x58,
+	0xa0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x24, 0x00, 0x05, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x8a, 0x28, 0x72, 0x09, 0x60, 0x2c, 0x00, 0x00,
+	0x00, 0x00, 0x90, 0x18, 0x50, 0x2d, 0x00, 0x00, 0x94, 0x00, 0x00, 0x48,
+	0xb0, 0x0c, 0x00, 0x00, 0x00, 0x04, 0x60, 0x20, 0x51, 0x0d, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x88, 0x01, 0x01, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x91, 0x05, 0x00, 0x40, 0x01, 0x34, 0x00, 0x00,
+	0x0b, 0x34, 0x06, 0xa0, 0x81, 0x21, 0x00, 0x00, 0x02, 0x2c, 0x10, 0x59,
+	0x00, 0x34, 0x00, 0x00, 0x0c, 0x60, 0x06, 0x00, 0x47, 0x21, 0x00, 0x00,
+	0x89, 0x01, 0x80, 0x19, 0x03, 0x14, 0x00, 0x00, 0x80, 0x2d, 0x06, 0x00,
+	0xa5, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x09, 0x25, 0x14, 0x00, 0x00,
+	0x8d, 0x29, 0x12, 0x30, 0x8a, 0x00, 0x00, 0x00, 0x86, 0x01, 0xb0, 0x18,
+	0x04, 0x14, 0x00, 0x00, 0x80, 0x4d, 0x06, 0x00, 0xa5, 0x01, 0x00, 0x00,
+	0xc2, 0x50, 0x32, 0x59, 0x63, 0x14, 0x00, 0x00, 0x9c, 0x30, 0x06, 0x00,
+	0x07, 0x20, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc9, 0x25, 0x34, 0x00, 0x00,
+	0x8d, 0x60, 0x12, 0x00, 0x8a, 0x20, 0x00, 0x00, 0xc2, 0x50, 0x32, 0xd0,
+	0x25, 0x14, 0x00, 0x00, 0x8d, 0x0c, 0x24, 0x10, 0x07, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0xff, 0xff, 0xff, 0x36, 0x00, 0x00, 0x13, 0x18, 0x00, 0x00,
+	0x00, 0x23, 0x00, 0x00, 0x31, 0x4f, 0x86, 0x49, 0x23, 0x34, 0x00, 0x00,
+	0x8a, 0x35, 0x02, 0x10, 0x02, 0x00, 0x00, 0x00, 0x8a, 0x01, 0x41, 0x20,
+	0x63, 0x34, 0x00, 0x00, 0x80, 0x11, 0x08, 0x10, 0xa5, 0x20, 0x00, 0x00,
+	0x05, 0x35, 0x52, 0x08, 0x25, 0x34, 0x00, 0x00, 0x05, 0x15, 0x12, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x7e, 0x00, 0x01, 0x00, 0x00, 0x15, 0x00, 0x00, 0x8e, 0x20, 0x50, 0x7e,
+	0x00, 0x15, 0x00, 0x00, 0x9b, 0x34, 0xe2, 0x11, 0x25, 0x20, 0x00, 0x00,
+	0x8c, 0x31, 0xb6, 0x98, 0x00, 0x14, 0x00, 0x00, 0x9d, 0x76, 0x08, 0x00,
+	0x03, 0x01, 0x00, 0x00, 0x9d, 0x35, 0xd0, 0x71, 0x00, 0x03, 0x00, 0x00,
+	0x99, 0xf8, 0x33, 0xd8, 0x60, 0x34, 0x00, 0x00, 0x80, 0x4c, 0x06, 0x30,
+	0xa5, 0x00, 0x00, 0x00, 0x9e, 0x31, 0xe6, 0x21, 0x00, 0x02, 0x00, 0x00,
+	0x92, 0x48, 0xe2, 0x11, 0x60, 0x2c, 0x00, 0x00, 0x1d, 0x24, 0x90, 0x73,
+	0x00, 0x0e, 0x00, 0x00, 0x1d, 0x4c, 0xf0, 0x7f, 0x00, 0x2e, 0x00, 0x00,
+	0x13, 0x00, 0x90, 0x50, 0x64, 0x21, 0x00, 0x00, 0x00, 0x04, 0x30, 0x01,
+	0x53, 0x2d, 0x00, 0x00, 0x1d, 0x78, 0x06, 0x00, 0x20, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x40,
+	0xb0, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x36, 0x00, 0x00,
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+	0x00, 0x23, 0x00, 0x00, 0x17, 0x04, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x00, 0x14, 0x09, 0xa0, 0xa5, 0x21, 0x00, 0x00, 0x00, 0x04, 0xd0, 0x69,
+	0xa7, 0x34, 0x00, 0x00, 0xd2, 0x16, 0x1b, 0x30, 0x8a, 0x00, 0x00, 0x00,
+	0x1c, 0x18, 0xb6, 0x00, 0x24, 0x33, 0x00, 0x00, 0x45, 0x6f, 0x48, 0x2c,
+	0x00, 0x22, 0x00, 0x00, 0xc2, 0x10, 0x60, 0x37, 0x38, 0x35, 0x00, 0x00,
+	0xd2, 0x00, 0x90, 0x01, 0x00, 0x23, 0x00, 0x00, 0x0b, 0x2c, 0x00, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x53, 0x48, 0x0b, 0xa2, 0x03, 0x21, 0x00, 0x00,
+	0xef, 0xbd, 0x27, 0x35, 0x60, 0x2c, 0x00, 0x00, 0x52, 0x07, 0x20, 0xb5,
+	0x00, 0x30, 0x00, 0x00, 0x3e, 0x38, 0x1f, 0x5c, 0x04, 0x39, 0x00, 0x00,
+	0x52, 0x0f, 0x20, 0x35, 0x01, 0x10, 0x00, 0x00, 0x3e, 0xb8, 0x21, 0x5c,
+	0x04, 0x39, 0x00, 0x00, 0x52, 0x17, 0x20, 0xb5, 0x01, 0x30, 0x00, 0x00,
+	0x08, 0x00, 0x1f, 0x5c, 0x44, 0x39, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10,
+	0xe4, 0x28, 0x00, 0x00, 0x57, 0x00, 0x01, 0x00, 0x0f, 0x03, 0x00, 0x00,
+	0x21, 0x04, 0x60, 0x43, 0x38, 0x15, 0x00, 0x00, 0x6d, 0x48, 0xed, 0x06,
+	0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06, 0x50, 0x2d, 0x00, 0x00,
+	0x47, 0x38, 0x10, 0x00, 0x00, 0x35, 0x00, 0x00, 0x15, 0xc2, 0x00, 0xc0,
+	0x02, 0x34, 0x00, 0x00, 0xf0, 0x49, 0x0d, 0xa0, 0xa2, 0x01, 0x00, 0x00,
+	0x00, 0x2c, 0x20, 0x35, 0x50, 0x2d, 0x00, 0x00, 0xcc, 0x31, 0x40, 0x48,
+	0x38, 0x15, 0x00, 0x00, 0x15, 0x31, 0x40, 0x49, 0x38, 0x15, 0x00, 0x00,
+	0x1b, 0x00, 0x90, 0x01, 0x00, 0x23, 0x00, 0x00, 0x17, 0x00, 0x80, 0x01,
+	0x00, 0x03, 0x00, 0x00, 0x1c, 0x00, 0xd0, 0x09, 0x00, 0x03, 0x00, 0x00,
+	0xca, 0x00, 0x90, 0x04, 0x00, 0x23, 0x00, 0x00, 0xc6, 0x02, 0x60, 0x5c,
+	0x00, 0x23, 0x00, 0x00, 0x46, 0x0e, 0x80, 0x04, 0x00, 0x03, 0x00, 0x00,
+	0xca, 0x02, 0xa0, 0x34, 0x00, 0x03, 0x00, 0x00, 0xcb, 0x02, 0xb0, 0x74,
+	0x00, 0x23, 0x00, 0x00, 0x00, 0x33, 0x60, 0x54, 0x38, 0x35, 0x00, 0x00,
+	0x46, 0x93, 0x31, 0x2a, 0x28, 0x23, 0x00, 0x00, 0x1b, 0x07, 0xb0, 0x31,
+	0x70, 0x0c, 0x00, 0x00, 0xd6, 0x32, 0x40, 0x55, 0x38, 0x35, 0x00, 0x00,
+	0xff, 0x31, 0x40, 0x56, 0x38, 0x15, 0x00, 0x00, 0x7e, 0x31, 0x10, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x00, 0x04, 0xf0, 0x26, 0x50, 0x2d, 0x00, 0x00,
+	0x83, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0xcc, 0x31, 0x40, 0x5a,
+	0x38, 0x15, 0x00, 0x00, 0xd6, 0x26, 0x02, 0x68, 0xb0, 0x2c, 0x00, 0x00,
+	0xd6, 0x2a, 0x02, 0x68, 0xb0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x71, 0x38, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x72, 0x38, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0x3c, 0x83, 0x00, 0x5f,
+	0x50, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x72, 0x38, 0x02, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0xca, 0x00, 0x90, 0x04, 0x00, 0x23, 0x00, 0x00,
+	0xc6, 0x02, 0x60, 0x5c, 0x00, 0x23, 0x00, 0x00, 0x46, 0x0e, 0x80, 0x04,
+	0x00, 0x03, 0x00, 0x00, 0xca, 0x02, 0xa0, 0x34, 0x00, 0x03, 0x00, 0x00,
+	0x00, 0x33, 0x60, 0x6a, 0x38, 0x15, 0x00, 0x00, 0xcb, 0x02, 0xb0, 0x74,
+	0x00, 0x23, 0x00, 0x00, 0x00, 0x90, 0x61, 0x34, 0x50, 0x2d, 0x00, 0x00,
+	0xd6, 0x32, 0x40, 0x6b, 0x38, 0x15, 0x00, 0x00, 0xff, 0x31, 0x40, 0x6c,
+	0x38, 0x15, 0x00, 0x00, 0x00, 0x0c, 0x12, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x72, 0x38, 0x00, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xa6, 0x7f, 0x00, 0x4b, 0xe4, 0x04, 0x00, 0x00,
+	0xa8, 0x7f, 0x08, 0x4b, 0xe4, 0x04, 0x00, 0x00, 0x26, 0x04, 0xa0, 0x11,
+	0x10, 0x2c, 0x00, 0x00, 0x1a, 0x7d, 0xa0, 0x11, 0x50, 0x2c, 0x00, 0x00,
+	0x1a, 0xa1, 0xf0, 0x09, 0x20, 0x2c, 0x00, 0x00, 0x9f, 0x80, 0xf0, 0x09,
+	0x10, 0x0c, 0x00, 0x00, 0x9f, 0x7c, 0xf0, 0x09, 0x50, 0x2c, 0x00, 0x00,
+	0x9f, 0x40, 0x00, 0x48, 0xb0, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xaf, 0x38, 0x03, 0x00, 0x00, 0x15, 0x00, 0x00, 0x26, 0x3c, 0xf0, 0x11,
+	0x50, 0x2c, 0x00, 0x00, 0x1f, 0x15, 0x00, 0x00, 0xd0, 0x2c, 0x00, 0x00,
+	0x00, 0x04, 0xf0, 0x11, 0x00, 0x2c, 0x00, 0x00, 0x26, 0x68, 0xe4, 0x86,
+	0x00, 0x20, 0x00, 0x00, 0x00, 0xa8, 0x29, 0x00, 0x00, 0x36, 0x00, 0x00,
+	0x1f, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x7d, 0x22, 0xb8,
+	0xe0, 0x14, 0x00, 0x00, 0x1f, 0x99, 0x0f, 0x30, 0x00, 0x20, 0x00, 0x00,
+	0x00, 0x44, 0x14, 0x00, 0x00, 0x36, 0x00, 0x00, 0x6a, 0x08, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x6a, 0x7d, 0x64, 0xb6, 0xb5, 0x20, 0x00, 0x00,
+	0x27, 0x98, 0x00, 0x4b, 0xe4, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x29, 0xa0, 0x08, 0x4b, 0xe4, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xf2,
+	0xe0, 0x08, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0xff, 0x23, 0x00, 0x00,
+	0x00, 0xa8, 0x05, 0xf2, 0xe0, 0x08, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00,
+	0xff, 0x22, 0x00, 0x00, 0x6d, 0x00, 0x01, 0x00, 0x78, 0x12, 0x00, 0x00,
+	0x1a, 0x05, 0x0c, 0x88, 0x01, 0x0f, 0x00, 0x00, 0x6d, 0x00, 0x00, 0x00,
+	0x5c, 0x32, 0x00, 0x00, 0x6d, 0x68, 0xc4, 0xf9, 0x01, 0x2e, 0x00, 0x00,
+	0x6d, 0x00, 0x04, 0xf2, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
+	0xff, 0x01, 0x00, 0x00, 0x00, 0xb8, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0xff, 0x02, 0x00, 0x00, 0x67, 0x58, 0x81, 0xc6,
+	0x15, 0x20, 0x00, 0x00, 0x67, 0x98, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x69, 0x60, 0xb1, 0x86,
+	0x16, 0x00, 0x00, 0x00, 0x69, 0xa0, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x6a, 0x64, 0xc1, 0xc6,
+	0x16, 0x20, 0x00, 0x00, 0x6b, 0xa8, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x6d, 0x70, 0xf1, 0x86,
+	0x17, 0x00, 0x00, 0x00, 0x6d, 0xb0, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x5d, 0x74, 0xe1, 0x06,
+	0x60, 0x2c, 0x00, 0x00, 0x6f, 0xb8, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x31, 0x40, 0xa8,
+	0x38, 0x35, 0x00, 0x00, 0x00, 0x0c, 0x12, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0xc5, 0x05, 0xb0, 0x29, 0x01, 0x34, 0x00, 0x00, 0xc5, 0x6d, 0x0a, 0x30,
+	0x80, 0x21, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x71, 0x00, 0x34, 0x00, 0x00,
+	0xa2, 0x6c, 0x0c, 0x30, 0x8a, 0x21, 0x00, 0x00, 0xa3, 0x92, 0x42, 0x34,
+	0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0xff, 0x31, 0x40, 0xb0, 0x38, 0x35, 0x00, 0x00, 0x00, 0x0c, 0x12, 0x00,
+	0x00, 0x39, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x80, 0x42, 0x00, 0x28, 0x70, 0x0c, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28,
+	0x70, 0x0c, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28, 0x70, 0x0c, 0x00, 0x00,
+	0x80, 0x42, 0x00, 0x28, 0x70, 0x0c, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28,
+	0x70, 0x0c, 0x00, 0x00, 0x44, 0x0a, 0x0e, 0x2e, 0x00, 0x2f, 0x00, 0x00,
+	0xee, 0x7f, 0xc0, 0x4a, 0xe4, 0x24, 0x00, 0x00, 0x44, 0x06, 0x00, 0x80,
+	0x02, 0x14, 0x00, 0x00, 0x00, 0x4a, 0x0d, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x6f, 0xbc, 0x01, 0x00, 0x00, 0x14, 0x00, 0x00, 0x6e, 0x64, 0x10, 0xa0,
+	0x03, 0x01, 0x00, 0x00, 0x1b, 0x6e, 0x08, 0x28, 0x04, 0x34, 0x00, 0x00,
+	0x45, 0x03, 0x0a, 0x30, 0x03, 0x01, 0x00, 0x00, 0x6e, 0x04, 0x00, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x00, 0x48, 0x03, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x00, 0x04, 0xb0, 0xc0, 0x02, 0x34, 0x00, 0x00, 0xd2, 0x4e, 0x11, 0x30,
+	0x8a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x34, 0x00, 0x00,
+	0xd2, 0x12, 0x2d, 0xa0, 0x8a, 0x01, 0x00, 0x00, 0x16, 0x83, 0x00, 0x80,
+	0x00, 0x34, 0x00, 0x00, 0xf0, 0x15, 0x07, 0xa0, 0xa2, 0x01, 0x00, 0x00,
+	0x45, 0x02, 0x50, 0x6c, 0xa7, 0x01, 0x00, 0x00, 0xc4, 0x02, 0x70, 0x01,
+	0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0xc0, 0x01, 0x00, 0x23, 0x00, 0x00,
+	0x9d, 0x00, 0x90, 0x01, 0x00, 0x03, 0x00, 0x00, 0x7e, 0x31, 0x22, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x6f, 0x06, 0xb0, 0x01, 0x00, 0x03, 0x00, 0x00,
+	0x00, 0x04, 0x20, 0x35, 0x52, 0x0d, 0x00, 0x00, 0x83, 0x01, 0x40, 0x99,
+	0x08, 0x03, 0x00, 0x00, 0x83, 0x01, 0x20, 0xad, 0xb4, 0x14, 0x00, 0x00,
+	0x80, 0x69, 0x0c, 0x30, 0xa5, 0x20, 0x00, 0x00, 0xef, 0xa0, 0x02, 0x80,
+	0x05, 0x2f, 0x00, 0x00, 0x94, 0x11, 0xa0, 0x99, 0x66, 0x34, 0x00, 0x00,
+	0x94, 0x55, 0x2c, 0x30, 0x80, 0x20, 0x00, 0x00, 0xef, 0x00, 0x00, 0x00,
+	0x00, 0x34, 0x00, 0x00, 0x80, 0x58, 0x06, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x94, 0x11, 0x50, 0x5c, 0x71, 0x34, 0x00, 0x00, 0x94, 0x59, 0x2a, 0x30,
+	0x80, 0x20, 0x00, 0x00, 0xb6, 0xfe, 0x23, 0x8d, 0x34, 0x14, 0x00, 0x00,
+	0xf0, 0x69, 0x0a, 0x30, 0xa2, 0x20, 0x00, 0x00, 0x94, 0x31, 0x40, 0x24,
+	0x91, 0x14, 0x00, 0x00, 0x94, 0x51, 0x28, 0x30, 0x80, 0x20, 0x00, 0x00,
+	0xbb, 0x01, 0x20, 0x81, 0x04, 0x34, 0x00, 0x00, 0x80, 0x7d, 0x00, 0x30,
+	0xa5, 0x20, 0x00, 0x00, 0x94, 0x51, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00,
+	0x94, 0x8d, 0x1d, 0xa0, 0x80, 0x21, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x09,
+	0x50, 0x2d, 0x00, 0x00, 0x94, 0xa1, 0x40, 0x19, 0x12, 0x0c, 0x00, 0x00,
+	0x42, 0x10, 0x60, 0xe8, 0x38, 0x35, 0x00, 0x00, 0x1a, 0x03, 0x00, 0x70,
+	0xb0, 0x2c, 0x00, 0x00, 0x94, 0x21, 0x40, 0x19, 0x12, 0x2c, 0x00, 0x00,
+	0x96, 0x01, 0x50, 0x59, 0x65, 0x34, 0x00, 0x00, 0x80, 0x2d, 0x0c, 0x30,
+	0xa5, 0x20, 0x00, 0x00, 0x7e, 0x31, 0x20, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0xc5, 0x59, 0x2a, 0x8d, 0xa6, 0x20, 0x00, 0x00, 0x00, 0x04, 0x00, 0xc0,
+	0x01, 0x14, 0x00, 0x00, 0x6f, 0x4a, 0x0d, 0xa2, 0x8a, 0x21, 0x00, 0x00
+};
+
+#endif /*__BXE_INIT_VALUES_E1_H__*/
diff --git a/sys/dev/bxe/bxe_init_values_e1h.h b/sys/dev/bxe/bxe_init_values_e1h.h
new file mode 100755
index 0000000..0a70f7d
--- /dev/null
+++ b/sys/dev/bxe/bxe_init_values_e1h.h
@@ -0,0 +1,39636 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef __BXE_INIT_VALUES_E1H_H__
+#define	__BXE_INIT_VALUES_E1H_H__
+
+/* bxe_init_values_e1h.h: Broadcom NX2 10G network driver.
+ * This array contains the list of operations needed to initialize the chip.
+ *
+ * For each block in the chip there are three init stages:
+ * common - HW used by both ports,
+ * port1 and port2 - initialization for a specific Ethernet port.
+ * When a port is opened or closed, the management CPU tells the driver
+ * whether to init/disable common HW in addition to the port HW.
+ * This way the first port going up will first initializes the common HW,
+ * and the last port going down also resets the common HW
+ *
+ * For each init stage/block there is a list of actions needed in a format:
+ * {operation, register, data}
+ * where:
+ * OP_WR - write a value to the chip.
+ * OP_RD - read a register (usually a clear on read register).
+ * OP_SW - string write, write a section of consecutive addresses to the chip.
+ * OP_SI - copy a string using indirect writes.
+ * OP_ZR - clear a range of memory.
+ * OP_ZP - unzip and copy using DMAE.
+ * OP_WB - string copy using DMAE.
+ *
+ * The #defines mark the stages.
+ *
+ */
+#include "bxe_init.h"
+#include "if_bxe.h"
+
+static struct raw_op init_ops_e1h[] = {
+/* #define PRS_COMMON_START        0 */
+	{OP_WR, PRS_REG_INC_VALUE, 0xf},
+	{OP_WR, PRS_REG_EVENT_ID_1, 0x45},
+	{OP_WR, PRS_REG_EVENT_ID_2, 0x84},
+	{OP_WR, PRS_REG_EVENT_ID_3, 0x6},
+	{OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
+	{OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
+	{OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
+	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
+	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
+	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
+	{OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
+	{OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000},
+	{OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
+	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000},
+	{OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3},
+	{OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
+	{OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
+	{OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
+	{OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
+	{OP_WR, PRS_REG_FCOE_TYPE, 0x8906},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
+	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
+	{OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
+	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
+/* #define PRS_COMMON_END          1 */
+/* #define SRCH_COMMON_START       22 */
+	{OP_WR, SRC_REG_E1HMF_ENABLE, 0x1},
+/* #define SRCH_COMMON_END         23 */
+/* #define TSDM_COMMON_START       44 */
+	{OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
+	{OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
+	{OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
+	{OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_WR, TSDM_REG_AGG_INT_EVENT_0, 0x20},
+	{OP_WR, TSDM_REG_AGG_INT_EVENT_1, 0x0},
+	{OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
+	{OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
+	{OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x1c},
+	{OP_WR, TSDM_REG_AGG_INT_T_0, 0x1},
+	{OP_ZR, TSDM_REG_AGG_INT_T_1, 0x5f},
+	{OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
+/* #define TSDM_COMMON_END         45 */
+/* #define TCM_COMMON_START        66 */
+	{OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
+	{OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
+	{OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
+	{OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
+	{OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
+	{OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
+	{OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
+	{OP_WR, TCM_REG_STORM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_PRS_WEIGHT, 0x5},
+	{OP_WR, TCM_REG_PBF_WEIGHT, 0x6},
+	{OP_WR, TCM_REG_USEM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_CSEM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_CP_WEIGHT, 0x0},
+	{OP_WR, TCM_REG_TSDM_WEIGHT, 0x5},
+	{OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_TM_WEIGHT, 0x2},
+	{OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
+	{OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, TCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, TCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
+	{OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
+	{OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
+	{OP_ZR, TCM_REG_XX_TABLE, 0xa},
+	{OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
+	{OP_WR, TCM_REG_N_SM_CTX_LD_4, 0x1},
+	{OP_ZR, TCM_REG_N_SM_CTX_LD_5, 0x3},
+	{OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
+	{OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
+	{OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
+	{OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
+	{OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
+	{OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
+	{OP_WR, TCM_REG_TSDM_IFEN, 0x1},
+	{OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
+	{OP_WR, TCM_REG_PRS_IFEN, 0x1},
+	{OP_WR, TCM_REG_PBF_IFEN, 0x1},
+	{OP_WR, TCM_REG_USEM_IFEN, 0x1},
+	{OP_WR, TCM_REG_CSEM_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
+/* #define TCM_COMMON_END          67 */
+/* #define TCM_FUNC0_START         72 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd},
+	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x7},
+	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x7},
+	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x7},
+/* #define TCM_FUNC0_END           73 */
+/* #define TCM_FUNC1_START         74 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x27},
+	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x27},
+	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x27},
+/* #define TCM_FUNC1_END           75 */
+/* #define TCM_FUNC2_START         76 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0x1d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x17},
+	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x17},
+	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x17},
+/* #define TCM_FUNC2_END           77 */
+/* #define TCM_FUNC3_START         78 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x3d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x37},
+	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x37},
+	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x37},
+/* #define TCM_FUNC3_END           79 */
+/* #define TCM_FUNC4_START         80 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0x4d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x47},
+	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x47},
+	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x47},
+/* #define TCM_FUNC4_END           81 */
+/* #define TCM_FUNC5_START         82 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x6d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x67},
+	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x67},
+	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x67},
+/* #define TCM_FUNC5_END           83 */
+/* #define TCM_FUNC6_START         84 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0x5d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x57},
+	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x57},
+	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x57},
+/* #define TCM_FUNC6_END           85 */
+/* #define TCM_FUNC7_START         86 */
+	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x7d},
+	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x77},
+	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x77},
+	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x77},
+/* #define TCM_FUNC7_END           87 */
+/* #define BRB1_COMMON_START       88 */
+	{OP_SW, BRB1_REG_LL_RAM, 0x2000020},
+	{OP_WR, BRB1_REG_SOFT_RESET, 0x1},
+	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
+	{OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
+	{OP_WR, BRB1_REG_SOFT_RESET, 0x0},
+/* #define BRB1_COMMON_END         89 */
+/* #define BRB1_PORT0_START        90 */
+	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
+	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
+/* #define BRB1_PORT0_END          91 */
+/* #define BRB1_PORT1_START        92 */
+	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
+	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
+/* #define BRB1_PORT1_END          93 */
+/* #define TSEM_COMMON_START       110 */
+	{OP_WB, TSEM_REG_INT_TABLE, 0xf20000},
+	{OP_WR_64, TSEM_REG_INT_TABLE + 0x3c8, 0x70223},
+	{OP_WB, TSEM_REG_PRAM, 0x5a180000},
+	{OP_WR_64, TSEM_REG_PRAM + 0x16860, 0x52f40225},
+	{OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, TSEM_REG_TS_0_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_1_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_2_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_3_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_4_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_5_AS, 0x3},
+	{OP_WR, TSEM_REG_TS_6_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_7_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_8_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_9_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_10_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_11_AS, 0x3},
+	{OP_WR, TSEM_REG_TS_12_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_13_AS, 0x1},
+	{OP_WR, TSEM_REG_TS_14_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_15_AS, 0x0},
+	{OP_WR, TSEM_REG_TS_16_AS, 0x4},
+	{OP_WR, TSEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, TSEM_REG_TS_18_AS, 0x2},
+	{OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, TSEM_REG_THREADS_LIST, 0xff},
+	{OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+	{OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+	{OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+	{OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
+	{OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x3b3},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x1000 + 0xecc, 0x10227},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x1ed0, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1ed8, 0x6},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e8, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e0, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4040, 0x20228},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x62c0, 0x20022a},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd100, 0x2},
+/* #define TSEM_COMMON_END         111 */
+/* #define TSEM_PORT0_START        112 */
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x124},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3300, 0x14},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x33a0, 0x68},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1c8, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d8, 0x20},
+/* #define TSEM_PORT0_END          113 */
+/* #define TSEM_PORT1_START        114 */
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2490, 0x124},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3350, 0x14},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3540, 0x68},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d0, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd258, 0x20},
+/* #define TSEM_PORT1_END          115 */
+/* #define TSEM_FUNC0_START        116 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2920, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x5024a},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c0, 0x2},
+/* #define TSEM_FUNC0_END          117 */
+/* #define TSEM_FUNC1_START        118 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2924, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3040 + 0x8, 0x5024f},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c8, 0x2},
+/* #define TSEM_FUNC1_END          119 */
+/* #define TSEM_FUNC2_START        120 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2928, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3080 + 0x8, 0x50254},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4010, 0x20259},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d0, 0x2},
+/* #define TSEM_FUNC2_END          121 */
+/* #define TSEM_FUNC3_START        122 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x292c, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x8, 0x5025b},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4018, 0x20260},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d8, 0x2},
+/* #define TSEM_FUNC3_END          123 */
+/* #define TSEM_FUNC4_START        124 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2930, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3100 + 0x8, 0x50262},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4020, 0x20267},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e0, 0x2},
+/* #define TSEM_FUNC4_END          125 */
+/* #define TSEM_FUNC5_START        126 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2934, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3140 + 0x8, 0x50269},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026e},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e8, 0x2},
+/* #define TSEM_FUNC5_END          127 */
+/* #define TSEM_FUNC6_START        128 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2938, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3180 + 0x8, 0x50270},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x32c0, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4030, 0x20275},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f0, 0x2},
+/* #define TSEM_FUNC6_END          129 */
+/* #define TSEM_FUNC7_START        130 */
+	{OP_WR, TSEM_REG_FAST_MEMORY + 0x293c, 0x0},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0, 0x2},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x8, 0x50277},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x1c, 0x9},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x32e0, 0x8},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
+	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4038, 0x2027c},
+	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f8, 0x2},
+/* #define TSEM_FUNC7_END          131 */
+/* #define MISC_COMMON_START       220 */
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
+	{OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
+	{OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
+/* #define MISC_COMMON_END         221 */
+/* #define MISC_FUNC0_START        226 */
+	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC0_END          227 */
+/* #define MISC_FUNC1_START        228 */
+	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC1_END          229 */
+/* #define MISC_FUNC2_START        230 */
+	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC2_END          231 */
+/* #define MISC_FUNC3_START        232 */
+	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC3_END          233 */
+/* #define MISC_FUNC4_START        234 */
+	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC4_END          235 */
+/* #define MISC_FUNC5_START        236 */
+	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC5_END          237 */
+/* #define MISC_FUNC6_START        238 */
+	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
+/* #define MISC_FUNC6_END          239 */
+/* #define MISC_FUNC7_START        240 */
+	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
+/* #define MISC_FUNC7_END          241 */
+/* #define NIG_COMMON_START        264 */
+	{OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
+	{OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
+	{OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
+	{OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
+	{OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
+/* #define NIG_COMMON_END          265 */
+/* #define NIG_PORT0_START         266 */
+	{OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
+	{OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
+	{OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
+	{OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
+	{OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
+	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
+	{OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7},
+	{OP_WR, NIG_REG_LLH0_CLS_TYPE, 0x1},
+	{OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
+	{OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
+	{OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
+	{OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
+	{OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
+/* #define NIG_PORT0_END           267 */
+/* #define NIG_PORT1_START         268 */
+	{OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
+	{OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
+	{OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
+	{OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
+	{OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
+	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
+	{OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_1, 0x7},
+	{OP_WR, NIG_REG_LLH1_CLS_TYPE, 0x1},
+	{OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
+	{OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
+	{OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
+	{OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
+	{OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
+/* #define NIG_PORT1_END           269 */
+/* #define UPB_COMMON_START        308 */
+	{OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
+/* #define UPB_COMMON_END          309 */
+/* #define CSDM_COMMON_START       330 */
+	{OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
+	{OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
+	{OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x2},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_4, 0x20},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_5, 0x21},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_6, 0x22},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_7, 0x23},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_8, 0x24},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_9, 0x25},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_10, 0x26},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_11, 0x27},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_12, 0x28},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_13, 0x29},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_14, 0x2a},
+	{OP_WR, CSDM_REG_AGG_INT_EVENT_15, 0x2b},
+	{OP_ZR, CSDM_REG_AGG_INT_EVENT_16, 0x56},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_6, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_7, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_8, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_9, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_10, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_11, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_12, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_13, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_14, 0x1},
+	{OP_WR, CSDM_REG_AGG_INT_MODE_15, 0x1},
+	{OP_ZR, CSDM_REG_AGG_INT_MODE_16, 0x10},
+	{OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
+/* #define CSDM_COMMON_END         331 */
+/* #define USDM_COMMON_START       352 */
+	{OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0x411},
+	{OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
+	{OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
+	{OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
+	{OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
+	{OP_ZR, USDM_REG_AGG_INT_EVENT_2, 0x2},
+	{OP_WR, USDM_REG_AGG_INT_EVENT_4, 0xa},
+	{OP_WR, USDM_REG_AGG_INT_EVENT_5, 0xf0},
+	{OP_ZR, USDM_REG_AGG_INT_EVENT_6, 0x1f},
+	{OP_WR, USDM_REG_AGG_INT_T_5, 0x1},
+	{OP_ZR, USDM_REG_AGG_INT_T_6, 0x3a},
+	{OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
+	{OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x3},
+	{OP_WR, USDM_REG_AGG_INT_MODE_4, 0x1},
+	{OP_WR, USDM_REG_AGG_INT_MODE_5, 0x1},
+	{OP_ZR, USDM_REG_AGG_INT_MODE_6, 0x1a},
+	{OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
+/* #define USDM_COMMON_END         353 */
+/* #define CCM_COMMON_START        374 */
+	{OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
+	{OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
+	{OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
+	{OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, CCM_REG_STORM_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
+	{OP_WR, CCM_REG_XSEM_WEIGHT, 0x5},
+	{OP_WR, CCM_REG_USEM_WEIGHT, 0x5},
+	{OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_CSDM_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3},
+	{OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2},
+	{OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
+	{OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
+	{OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
+	{OP_WR, CCM_REG_INV_DONE_Q, 0x1},
+	{OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, CCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, CCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
+	{OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
+	{OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
+	{OP_ZR, CCM_REG_XX_TABLE, 0x12},
+	{OP_SW, CCM_REG_XX_DESCR_TABLE, 0x24027e},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
+	{OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
+	{OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
+	{OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
+	{OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
+	{OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
+	{OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
+	{OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
+	{OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
+	{OP_WR, CCM_REG_CSDM_IFEN, 0x1},
+	{OP_WR, CCM_REG_TSEM_IFEN, 0x1},
+	{OP_WR, CCM_REG_XSEM_IFEN, 0x1},
+	{OP_WR, CCM_REG_USEM_IFEN, 0x1},
+	{OP_WR, CCM_REG_PBF_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
+/* #define CCM_COMMON_END          375 */
+/* #define CCM_FUNC0_START         380 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
+	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc},
+	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb},
+	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x7},
+/* #define CCM_FUNC0_END           381 */
+/* #define CCM_FUNC1_START         382 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
+	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b},
+	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x27},
+/* #define CCM_FUNC1_END           383 */
+/* #define CCM_FUNC2_START         384 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
+	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0x1c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0x1b},
+	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x17},
+/* #define CCM_FUNC2_END           385 */
+/* #define CCM_FUNC3_START         386 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
+	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x3c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x3b},
+	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x37},
+/* #define CCM_FUNC3_END           387 */
+/* #define CCM_FUNC4_START         388 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
+	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0x4c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0x4b},
+	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x47},
+/* #define CCM_FUNC4_END           389 */
+/* #define CCM_FUNC5_START         390 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
+	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x6c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x6b},
+	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x67},
+/* #define CCM_FUNC5_END           391 */
+/* #define CCM_FUNC6_START         392 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
+	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0x5c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0x5b},
+	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x57},
+/* #define CCM_FUNC6_END           393 */
+/* #define CCM_FUNC7_START         394 */
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
+	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
+	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x7c},
+	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x7b},
+	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x77},
+/* #define CCM_FUNC7_END           395 */
+/* #define UCM_COMMON_START        396 */
+	{OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
+	{OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
+	{OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
+	{OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
+	{OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
+	{OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
+	{OP_WR, UCM_REG_STORM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_TSEM_WEIGHT, 0x4},
+	{OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
+	{OP_WR, UCM_REG_XSEM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_DORQ_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_CP_WEIGHT, 0x0},
+	{OP_WR, UCM_REG_USDM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7},
+	{OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_TM_WEIGHT, 0x2},
+	{OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
+	{OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
+	{OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, UCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, UCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
+	{OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
+	{OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
+	{OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
+	{OP_ZR, UCM_REG_XX_TABLE, 0x12},
+	{OP_SW, UCM_REG_XX_DESCR_TABLE, 0x1b02a2},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xc},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x9},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
+	{OP_WR, UCM_REG_N_SM_CTX_LD_4, 0xb},
+	{OP_ZR, UCM_REG_N_SM_CTX_LD_5, 0x3},
+	{OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
+	{OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
+	{OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
+	{OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
+	{OP_WR, UCM_REG_USDM_IFEN, 0x1},
+	{OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
+	{OP_WR, UCM_REG_TSEM_IFEN, 0x1},
+	{OP_WR, UCM_REG_CSEM_IFEN, 0x1},
+	{OP_WR, UCM_REG_XSEM_IFEN, 0x1},
+	{OP_WR, UCM_REG_DORQ_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
+/* #define UCM_COMMON_END          397 */
+/* #define UCM_FUNC0_START         402 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf},
+	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe},
+	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC0_END           403 */
+/* #define UCM_FUNC1_START         404 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e},
+	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC1_END           405 */
+/* #define UCM_FUNC2_START         406 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0x1f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0x1e},
+	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC2_END           407 */
+/* #define UCM_FUNC3_START         408 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x3f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x3e},
+	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC3_END           409 */
+/* #define UCM_FUNC4_START         410 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0x4f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0x4e},
+	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC4_END           411 */
+/* #define UCM_FUNC5_START         412 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x6f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x6e},
+	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC5_END           413 */
+/* #define UCM_FUNC6_START         414 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0x5f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0x5e},
+	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define UCM_FUNC6_END           415 */
+/* #define UCM_FUNC7_START         416 */
+	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x7f},
+	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x7e},
+	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
+	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define UCM_FUNC7_END           417 */
+/* #define USEM_COMMON_START       418 */
+	{OP_WB, USEM_REG_INT_TABLE, 0xf60000},
+	{OP_WR_64, USEM_REG_INT_TABLE + 0x3d8, 0x502bd},
+	{OP_WB, USEM_REG_PRAM, 0x8d000000},
+	{OP_WR_64, USEM_REG_PRAM + 0x23400, 0x398002bf},
+	{OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, USEM_REG_TS_0_AS, 0x0},
+	{OP_WR, USEM_REG_TS_1_AS, 0x1},
+	{OP_WR, USEM_REG_TS_2_AS, 0x4},
+	{OP_WR, USEM_REG_TS_3_AS, 0x0},
+	{OP_WR, USEM_REG_TS_4_AS, 0x1},
+	{OP_WR, USEM_REG_TS_5_AS, 0x3},
+	{OP_WR, USEM_REG_TS_6_AS, 0x0},
+	{OP_WR, USEM_REG_TS_7_AS, 0x1},
+	{OP_WR, USEM_REG_TS_8_AS, 0x4},
+	{OP_WR, USEM_REG_TS_9_AS, 0x0},
+	{OP_WR, USEM_REG_TS_10_AS, 0x1},
+	{OP_WR, USEM_REG_TS_11_AS, 0x3},
+	{OP_WR, USEM_REG_TS_12_AS, 0x0},
+	{OP_WR, USEM_REG_TS_13_AS, 0x1},
+	{OP_WR, USEM_REG_TS_14_AS, 0x4},
+	{OP_WR, USEM_REG_TS_15_AS, 0x0},
+	{OP_WR, USEM_REG_TS_16_AS, 0x4},
+	{OP_WR, USEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, USEM_REG_TS_18_AS, 0x2},
+	{OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, USEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, USEM_REG_THREADS_LIST, 0xffff},
+	{OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
+	{OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
+	{OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+	{OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x11480, 0x0},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x11480, 0x1},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2000, 0x102},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x8020, 0xc8},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x8000, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x3da8, 0x4},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x3d80, 0x9},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x3d80 + 0x24, 0x102c1},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4000, 0x4},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x40d0, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x202c2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x74c0, 0x202c4},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xda40, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xe000, 0x800},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x1002c6},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
+	{OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002d6},
+/* #define USEM_COMMON_END         419 */
+/* #define USEM_PORT0_START        420 */
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2450, 0xb4},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad0, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x1a0},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x3db8, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xda88, 0x2},
+/* #define USEM_PORT0_END          421 */
+/* #define USEM_PORT1_START        422 */
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2720, 0xb4},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad8, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0x1a0},
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x3dbc, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xda90, 0x2},
+/* #define USEM_PORT1_END          423 */
+/* #define USEM_FUNC0_START        424 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a30, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd000, 0x6},
+/* #define USEM_FUNC0_END          425 */
+/* #define USEM_FUNC1_START        426 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a34, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd018, 0x6},
+/* #define USEM_FUNC1_END          427 */
+/* #define USEM_FUNC2_START        428 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a38, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd030, 0x6},
+/* #define USEM_FUNC2_END          429 */
+/* #define USEM_FUNC3_START        430 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a3c, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd048, 0x6},
+/* #define USEM_FUNC3_END          431 */
+/* #define USEM_FUNC4_START        432 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a40, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd060, 0x6},
+/* #define USEM_FUNC4_END          433 */
+/* #define USEM_FUNC5_START        434 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a44, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd078, 0x6},
+/* #define USEM_FUNC5_END          435 */
+/* #define USEM_FUNC6_START        436 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a48, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd090, 0x6},
+/* #define USEM_FUNC6_END          437 */
+/* #define USEM_FUNC7_START        438 */
+	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a4c, 0x0},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
+	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd0a8, 0x6},
+/* #define USEM_FUNC7_END          439 */
+/* #define CSEM_COMMON_START       440 */
+	{OP_WB, CSEM_REG_INT_TABLE, 0xe00000},
+	{OP_WR_64, CSEM_REG_INT_TABLE + 0x380, 0x1002e6},
+	{OP_WB, CSEM_REG_PRAM, 0x39280000},
+	{OP_WR_64, CSEM_REG_PRAM + 0xe4a0, 0x61d202e8},
+	{OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, CSEM_REG_TS_0_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_1_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_2_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_3_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_4_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_5_AS, 0x3},
+	{OP_WR, CSEM_REG_TS_6_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_7_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_8_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_9_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_10_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_11_AS, 0x3},
+	{OP_WR, CSEM_REG_TS_12_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_13_AS, 0x1},
+	{OP_WR, CSEM_REG_TS_14_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_15_AS, 0x0},
+	{OP_WR, CSEM_REG_TS_16_AS, 0x4},
+	{OP_WR, CSEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, CSEM_REG_TS_18_AS, 0x2},
+	{OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
+	{OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x11480, 0x1},
+	{OP_WR_EMUL, CSEM_REG_FAST_MEMORY + 0x11480, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x42},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x7000, 0x2},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6700, 0x100},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x9000, 0x400},
+	{OP_SW, CSEM_REG_FAST_MEMORY + 0x6b08, 0x2002ea},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
+	{OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x10030a},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+	{OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x10031a},
+/* #define CSEM_COMMON_END         441 */
+/* #define CSEM_PORT0_START        442 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8100, 0xa0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8600, 0x40},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8c00, 0x3c},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0xb000, 0x200},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8800, 0x80},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8de0, 0x3c},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4040, 0x6},
+/* #define CSEM_PORT0_END          443 */
+/* #define CSEM_PORT1_START        444 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8380, 0xa0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8700, 0x40},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8cf0, 0x3c},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0xb800, 0x200},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8a00, 0x80},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8ed0, 0x3c},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4058, 0x6},
+/* #define CSEM_PORT1_END          445 */
+/* #define CSEM_FUNC0_START        446 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8000, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
+/* #define CSEM_FUNC0_END          447 */
+/* #define CSEM_FUNC1_START        448 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8020, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
+/* #define CSEM_FUNC1_END          449 */
+/* #define CSEM_FUNC2_START        450 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8040, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x61c0, 0x30},
+/* #define CSEM_FUNC2_END          451 */
+/* #define CSEM_FUNC3_START        452 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8060, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6280, 0x30},
+/* #define CSEM_FUNC3_END          453 */
+/* #define CSEM_FUNC4_START        454 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8080, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6340, 0x30},
+/* #define CSEM_FUNC4_END          455 */
+/* #define CSEM_FUNC5_START        456 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x80a0, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6400, 0x30},
+/* #define CSEM_FUNC5_END          457 */
+/* #define CSEM_FUNC6_START        458 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x80c0, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x64c0, 0x30},
+/* #define CSEM_FUNC6_END          459 */
+/* #define CSEM_FUNC7_START        460 */
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x80e0, 0x8},
+	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
+	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6580, 0x30},
+/* #define CSEM_FUNC7_END          461 */
+/* #define XPB_COMMON_START        462 */
+	{OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x28},
+/* #define XPB_COMMON_END          463 */
+/* #define DQ_COMMON_START         484 */
+	{OP_WR, DORQ_REG_MODE_ACT, 0x2},
+	{OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
+	{OP_WR, DORQ_REG_OUTST_REQ, 0x4},
+	{OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
+	{OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
+	{OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
+	{OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
+	{OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
+	{OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
+	{OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
+	{OP_WR, DORQ_REG_AGG_CMD1, 0x80},
+	{OP_WR, DORQ_REG_AGG_CMD2, 0x81},
+	{OP_WR, DORQ_REG_AGG_CMD3, 0x80},
+	{OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
+	{OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
+	{OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
+	{OP_WR, DORQ_REG_REGN, 0x7c1004},
+	{OP_WR, DORQ_REG_IF_EN, 0xf},
+/* #define DQ_COMMON_END           485 */
+/* #define TIMERS_COMMON_START     506 */
+	{OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
+	{OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
+	{OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
+	{OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
+	{OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
+	{OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
+	{OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
+	{OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
+	{OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
+	{OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
+	{OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
+	{OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
+	{OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
+	{OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
+	{OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
+	{OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
+	{OP_WR, TM_REG_EN_TIMERS, 0x1},
+	{OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
+	{OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
+	{OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
+	{OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
+/* #define TIMERS_COMMON_END       507 */
+/* #define TIMERS_PORT0_START      508 */
+	{OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0},
+	{OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0},
+	{OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT0_END        509 */
+/* #define TIMERS_PORT1_START      510 */
+	{OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0},
+	{OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0},
+	{OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
+/* #define TIMERS_PORT1_END        511 */
+/* #define XSDM_COMMON_START       528 */
+	{OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
+	{OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410},
+	{OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0x414},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
+	{OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c},
+	{OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d},
+	{OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52},
+	{OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
+	{OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
+	{OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
+	{OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
+	{OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
+	{OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
+	{OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
+	{OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
+	{OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
+	{OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
+	{OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
+/* #define XSDM_COMMON_END         529 */
+/* #define QM_COMMON_START         550 */
+	{OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
+	{OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
+	{OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
+	{OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
+	{OP_WR, QM_REG_PCIREQAT, 0x2},
+	{OP_WR, QM_REG_CMINITCRD_0, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_1, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_2, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_3, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_4, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_5, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_6, 0x4},
+	{OP_WR, QM_REG_CMINITCRD_7, 0x4},
+	{OP_WR, QM_REG_OUTLDREQ, 0x4},
+	{OP_WR, QM_REG_CTXREG_0, 0x7c},
+	{OP_WR, QM_REG_CTXREG_1, 0x3d},
+	{OP_WR, QM_REG_CTXREG_2, 0x3f},
+	{OP_WR, QM_REG_CTXREG_3, 0x9c},
+	{OP_WR, QM_REG_ENSEC, 0x7},
+	{OP_ZR, QM_REG_QVOQIDX_0, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_5, 0x0},
+	{OP_WR, QM_REG_QVOQIDX_6, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_7, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_8, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_9, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_10, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_11, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_12, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_13, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_14, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_15, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_16, 0x0},
+	{OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
+	{OP_ZR, QM_REG_QVOQIDX_17, 0x4},
+	{OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_21, 0x0},
+	{OP_WR, QM_REG_QVOQIDX_22, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_23, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_24, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_5, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_25, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_26, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_27, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_28, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_6, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_29, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_30, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_31, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_32, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010120},
+	{OP_WR, QM_REG_QVOQIDX_33, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_34, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_35, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_36, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_37, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_38, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_39, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_40, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_41, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_42, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_43, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_44, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_45, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_46, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_47, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_48, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
+	{OP_WR, QM_REG_QVOQIDX_49, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_50, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_51, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_52, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_53, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_54, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_55, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_56, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_13, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_57, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_58, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_59, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_60, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_14, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_61, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_62, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_63, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_64, 0x0},
+	{OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010120},
+	{OP_ZR, QM_REG_QVOQIDX_65, 0x4},
+	{OP_WR, QM_REG_WRRWEIGHTS_16, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_69, 0x0},
+	{OP_WR, QM_REG_QVOQIDX_70, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_71, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_72, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_17, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_73, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_74, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_75, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_76, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_18, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_77, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_78, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_79, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_80, 0x0},
+	{OP_WR, QM_REG_WRRWEIGHTS_19, 0x1010120},
+	{OP_ZR, QM_REG_QVOQIDX_81, 0x4},
+	{OP_WR, QM_REG_WRRWEIGHTS_20, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_85, 0x0},
+	{OP_WR, QM_REG_QVOQIDX_86, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_87, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_88, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_21, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_89, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_90, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_91, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_92, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_22, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_93, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_94, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_95, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_96, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_23, 0x1010120},
+	{OP_WR, QM_REG_QVOQIDX_97, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_98, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_99, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_100, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_24, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_101, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_102, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_103, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_104, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_25, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_105, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_106, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_107, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_108, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_26, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_109, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_110, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_111, 0x7},
+	{OP_WR, QM_REG_QVOQIDX_112, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_27, 0x1010120},
+	{OP_WR, QM_REG_QVOQIDX_113, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_114, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_115, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_116, 0x1},
+	{OP_WR, QM_REG_WRRWEIGHTS_28, 0x1010101},
+	{OP_WR, QM_REG_QVOQIDX_117, 0x1},
+	{OP_WR, QM_REG_QVOQIDX_118, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_119, 0x4},
+	{OP_WR, QM_REG_QVOQIDX_120, 0x2},
+	{OP_WR, QM_REG_WRRWEIGHTS_29, 0x8012004},
+	{OP_WR, QM_REG_QVOQIDX_121, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_122, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_123, 0x5},
+	{OP_WR, QM_REG_QVOQIDX_124, 0x5},
+	{OP_WR, QM_REG_WRRWEIGHTS_30, 0x20081001},
+	{OP_WR, QM_REG_QVOQIDX_125, 0x8},
+	{OP_WR, QM_REG_QVOQIDX_126, 0x6},
+	{OP_WR, QM_REG_QVOQIDX_127, 0x7},
+	{OP_WR, QM_REG_WRRWEIGHTS_31, 0x1010120},
+	{OP_WR, QM_REG_VOQQMASK_0_LSB, 0x3f003f},
+	{OP_WR, QM_REG_VOQQMASK_0_MSB, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f},
+	{OP_WR, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_1_LSB, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_1_MSB, 0x3f003f},
+	{OP_WR, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f},
+	{OP_WR, QM_REG_VOQQMASK_2_LSB, 0x1000100},
+	{OP_WR, QM_REG_VOQQMASK_2_MSB, 0x1000100},
+	{OP_WR, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100},
+	{OP_WR, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100},
+	{OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
+	{OP_WR, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc000c0},
+	{OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc000c0},
+	{OP_WR, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0},
+	{OP_WR, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0},
+	{OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e001e00},
+	{OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e001e00},
+	{OP_WR, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00},
+	{OP_WR, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00},
+	{OP_WR, QM_REG_VOQQMASK_6_LSB, 0x40004000},
+	{OP_WR, QM_REG_VOQQMASK_6_MSB, 0x40004000},
+	{OP_WR, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000},
+	{OP_WR, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000},
+	{OP_WR, QM_REG_VOQQMASK_7_LSB, 0x80008000},
+	{OP_WR, QM_REG_VOQQMASK_7_MSB, 0x80008000},
+	{OP_WR, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000},
+	{OP_WR, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000},
+	{OP_WR, QM_REG_VOQQMASK_8_LSB, 0x20002000},
+	{OP_WR, QM_REG_VOQQMASK_8_MSB, 0x20002000},
+	{OP_WR, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000},
+	{OP_WR, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000},
+	{OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x2},
+	{OP_WR, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_10_LSB, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_10_MSB, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_11_LSB, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_11_MSB, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_VOQPORT_0, 0x0},
+	{OP_WR, QM_REG_VOQPORT_1, 0x1},
+	{OP_ZR, QM_REG_VOQPORT_2, 0xa},
+	{OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
+	{OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
+	{OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
+	{OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
+	{OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
+	{OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
+	{OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
+	{OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
+	{OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff},
+	{OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff},
+	{OP_WR, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff},
+	{OP_WR, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff},
+	{OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
+	{OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
+	{OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
+	{OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
+	{OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
+	{OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
+	{OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
+	{OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
+	{OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
+	{OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
+	{OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
+	{OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
+	{OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
+	{OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
+	{OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
+	{OP_WR, QM_REG_ENBYTECRD_LSB, 0xf000f},
+	{OP_WR, QM_REG_ENBYTECRD_MSB, 0xf000f},
+	{OP_WR, QM_REG_ENBYTECRD_LSB_EXT_A, 0xf000f},
+	{OP_WR, QM_REG_ENBYTECRD_MSB_EXT_A, 0xf000f},
+	{OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
+	{OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
+	{OP_WR, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0},
+	{OP_WR, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff},
+	{OP_WR, QM_REG_PQ2PCIFUNC_0, 0x0},
+	{OP_WR, QM_REG_PQ2PCIFUNC_1, 0x2},
+	{OP_WR, QM_REG_PQ2PCIFUNC_2, 0x1},
+	{OP_WR, QM_REG_PQ2PCIFUNC_3, 0x3},
+	{OP_WR, QM_REG_PQ2PCIFUNC_4, 0x4},
+	{OP_WR, QM_REG_PQ2PCIFUNC_5, 0x6},
+	{OP_WR, QM_REG_PQ2PCIFUNC_6, 0x5},
+	{OP_WR, QM_REG_PQ2PCIFUNC_7, 0x7},
+	{OP_WR, QM_REG_CMINTEN, 0xff},
+/* #define QM_COMMON_END           551 */
+/* #define PBF_COMMON_START        572 */
+	{OP_WR, PBF_REG_INIT, 0x1},
+	{OP_WR, PBF_REG_INIT_P4, 0x1},
+	{OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
+	{OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
+	{OP_WR, PBF_REG_INIT_P4, 0x0},
+	{OP_WR, PBF_REG_INIT, 0x0},
+	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
+/* #define PBF_COMMON_END          573 */
+/* #define PBF_PORT0_START         574 */
+	{OP_WR, PBF_REG_INIT_P0, 0x1},
+	{OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
+	{OP_WR, PBF_REG_INIT_P0, 0x0},
+	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
+/* #define PBF_PORT0_END           575 */
+/* #define PBF_PORT1_START         576 */
+	{OP_WR, PBF_REG_INIT_P1, 0x1},
+	{OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
+	{OP_WR, PBF_REG_INIT_P1, 0x0},
+	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
+/* #define PBF_PORT1_END           577 */
+/* #define XCM_COMMON_START        594 */
+	{OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
+	{OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
+	{OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
+	{OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
+	{OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
+	{OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
+	{OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
+	{OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
+	{OP_WR, XCM_REG_STORM_WEIGHT, 0x3},
+	{OP_WR, XCM_REG_TSEM_WEIGHT, 0x6},
+	{OP_WR, XCM_REG_CSEM_WEIGHT, 0x3},
+	{OP_WR, XCM_REG_USEM_WEIGHT, 0x3},
+	{OP_WR, XCM_REG_DORQ_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_PBF_WEIGHT, 0x0},
+	{OP_WR, XCM_REG_NIG0_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_CP_WEIGHT, 0x0},
+	{OP_WR, XCM_REG_XSDM_WEIGHT, 0x6},
+	{OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4},
+	{OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_TM_WEIGHT, 0x2},
+	{OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
+	{OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
+	{OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
+	{OP_WR, XCM_REG_AUX1_Q, 0x2},
+	{OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
+	{OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
+	{OP_WR, XCM_REG_GR_LD0_PR, 0x1},
+	{OP_WR, XCM_REG_GR_LD1_PR, 0x2},
+	{OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
+	{OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
+	{OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
+	{OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
+	{OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
+	{OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
+	{OP_WR, XCM_REG_XX_MSG_NUM, 0x20},
+	{OP_ZR, XCM_REG_XX_TABLE, 0x12},
+	{OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f032a},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
+	{OP_WR, XCM_REG_N_SM_CTX_LD_4, 0xe},
+	{OP_ZR, XCM_REG_N_SM_CTX_LD_5, 0x3},
+	{OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
+	{OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
+	{OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
+	{OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
+	{OP_WR, XCM_REG_XSDM_IFEN, 0x1},
+	{OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
+	{OP_WR, XCM_REG_TSEM_IFEN, 0x1},
+	{OP_WR, XCM_REG_CSEM_IFEN, 0x1},
+	{OP_WR, XCM_REG_USEM_IFEN, 0x1},
+	{OP_WR, XCM_REG_DORQ_IFEN, 0x1},
+	{OP_WR, XCM_REG_PBF_IFEN, 0x1},
+	{OP_WR, XCM_REG_NIG0_IFEN, 0x1},
+	{OP_WR, XCM_REG_NIG1_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
+	{OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
+	{OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
+/* #define XCM_COMMON_END          595 */
+/* #define XCM_FUNC0_START         600 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC0_END           601 */
+/* #define XCM_FUNC1_START         602 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC1_END           603 */
+/* #define XCM_FUNC2_START         604 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC2_END           605 */
+/* #define XCM_FUNC3_START         606 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC3_END           607 */
+/* #define XCM_FUNC4_START         608 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC4_END           609 */
+/* #define XCM_FUNC5_START         610 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC5_END           611 */
+/* #define XCM_FUNC6_START         612 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
+/* #define XCM_FUNC6_END           613 */
+/* #define XCM_FUNC7_START         614 */
+	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
+	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
+	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
+	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
+	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
+/* #define XCM_FUNC7_END           615 */
+/* #define XSEM_COMMON_START       616 */
+	{OP_WB, XSEM_REG_INT_TABLE, 0xea0000},
+	{OP_WR_64, XSEM_REG_INT_TABLE + 0x3a8, 0xb0349},
+	{OP_WB, XSEM_REG_PRAM, 0x8dc40000},
+	{OP_WR_64, XSEM_REG_PRAM + 0x23710, 0x391e034b},
+	{OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
+	{OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
+	{OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
+	{OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
+	{OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
+	{OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
+	{OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
+	{OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
+	{OP_WR, XSEM_REG_TS_0_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_1_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_2_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_3_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_4_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_5_AS, 0x3},
+	{OP_WR, XSEM_REG_TS_6_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_7_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_8_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_9_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_10_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_11_AS, 0x3},
+	{OP_WR, XSEM_REG_TS_12_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_13_AS, 0x1},
+	{OP_WR, XSEM_REG_TS_14_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_15_AS, 0x0},
+	{OP_WR, XSEM_REG_TS_16_AS, 0x4},
+	{OP_WR, XSEM_REG_TS_17_AS, 0x3},
+	{OP_ZR, XSEM_REG_TS_18_AS, 0x2},
+	{OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
+	{OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
+	{OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
+	{OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
+	{OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
+	{OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
+	{OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
+	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
+	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
+	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
+	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
+	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
+	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
+	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
+	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
+	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x11480, 0x0},
+	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x11480, 0x1},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x29c8, 0x4},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29c8 + 0x10, 0x2034d},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2080, 0x48},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x23d0, 0x2034f},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2498, 0x40351},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x2c50, 0x0},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x2c10, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2c08, 0x20355},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3000, 0x20357},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x100},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x4000, 0x100359},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x8408, 0x20369},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x10036b},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x8037b},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80383},
+/* #define XSEM_COMMON_END         617 */
+/* #define XSEM_PORT0_START        618 */
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xc000, 0xd8},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x24a8, 0x14},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2548, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2548 + 0x88, 0x2038b},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2668, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2668 + 0x88, 0x2038d},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2788, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2788 + 0x88, 0x2038f},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x28a8, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x28a8 + 0x88, 0x20391},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29e0, 0x20393},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x5208, 0x1},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x20395},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd0, 0x2},
+/* #define XSEM_PORT0_END          619 */
+/* #define XSEM_PORT1_START        620 */
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xc360, 0xd8},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x24f8, 0x14},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x25d8, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x25d8 + 0x88, 0x20397},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x26f8, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x26f8 + 0x88, 0x20399},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2818, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2818 + 0x88, 0x2039b},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2938, 0x22},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2938 + 0x88, 0x2039d},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29e8, 0x2039f},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0x520c, 0x1},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x203a1},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd8, 0x2},
+/* #define XSEM_PORT1_END          621 */
+/* #define XSEM_FUNC0_START        622 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c0, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29f0, 0x1003a3},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb000, 0x6},
+/* #define XSEM_FUNC0_END          623 */
+/* #define XSEM_FUNC1_START        624 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c4, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2a30, 0x1003b3},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb018, 0x6},
+/* #define XSEM_FUNC1_END          625 */
+/* #define XSEM_FUNC2_START        626 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c8, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2a70, 0x1003c3},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb030, 0x6},
+/* #define XSEM_FUNC2_END          627 */
+/* #define XSEM_FUNC3_START        628 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6cc, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2ab0, 0x1003d3},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb048, 0x6},
+/* #define XSEM_FUNC3_END          629 */
+/* #define XSEM_FUNC4_START        630 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d0, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2af0, 0x1003e3},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb060, 0x6},
+/* #define XSEM_FUNC4_END          631 */
+/* #define XSEM_FUNC5_START        632 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d4, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2b30, 0x1003f3},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb078, 0x6},
+/* #define XSEM_FUNC5_END          633 */
+/* #define XSEM_FUNC6_START        634 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d8, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2b70, 0x100403},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb090, 0x6},
+/* #define XSEM_FUNC6_END          635 */
+/* #define XSEM_FUNC7_START        636 */
+	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6dc, 0x0},
+	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2bb0, 0x100413},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
+	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb0a8, 0x6},
+/* #define XSEM_FUNC7_END          637 */
+/* #define CDU_COMMON_START        638 */
+	{OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
+	{OP_WR, CDU_REG_MF_MODE, 0x1},
+	{OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
+	{OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
+	{OP_WB, CDU_REG_L1TT, 0x2000423},
+	{OP_WB, CDU_REG_MATT, 0x280623},
+	{OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
+/* #define CDU_COMMON_END          639 */
+/* #define DMAE_COMMON_START       660 */
+	{OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
+	{OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
+	{OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
+	{OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
+	{OP_WR, DMAE_REG_PCI_IFEN, 0x1},
+	{OP_WR, DMAE_REG_GRC_IFEN, 0x1},
+/* #define DMAE_COMMON_END         661 */
+/* #define PXP_COMMON_START        682 */
+	{OP_WB, PXP_REG_HST_INBOUND_INT + 0x400, 0x5064b},
+	{OP_WB, PXP_REG_HST_INBOUND_INT, 0x50650},
+	{OP_WB, PXP_REG_HST_INBOUND_INT + 0x20, 0x50655},
+/* #define PXP_COMMON_END          683 */
+/* #define CFC_COMMON_START        704 */
+	{OP_ZR, CFC_REG_LINK_LIST, 0x100},
+	{OP_WR, CFC_REG_CONTROL0, 0x10},
+	{OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
+	{OP_WR, CFC_REG_INTERFACES, 0x280000},
+	{OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
+	{OP_WR, CFC_REG_INTERFACES, 0x0},
+/* #define CFC_COMMON_END          705 */
+/* #define HC_FUNC0_START          732 */
+	{OP_WR, HC_REG_CONFIG_0, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P0, 0x0},
+	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
+	{OP_WR, HC_REG_VQID_0, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC0_END            733 */
+/* #define HC_FUNC1_START          734 */
+	{OP_WR, HC_REG_CONFIG_1, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P1, 0x1},
+	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+	{OP_WR, HC_REG_VQID_1, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC1_END            735 */
+/* #define HC_FUNC2_START          736 */
+	{OP_WR, HC_REG_CONFIG_0, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P0, 0x2},
+	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
+	{OP_WR, HC_REG_VQID_0, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC2_END            737 */
+/* #define HC_FUNC3_START          738 */
+	{OP_WR, HC_REG_CONFIG_1, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P1, 0x3},
+	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+	{OP_WR, HC_REG_VQID_1, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC3_END            739 */
+/* #define HC_FUNC4_START          740 */
+	{OP_WR, HC_REG_CONFIG_0, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P0, 0x4},
+	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
+	{OP_WR, HC_REG_VQID_0, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC4_END            741 */
+/* #define HC_FUNC5_START          742 */
+	{OP_WR, HC_REG_CONFIG_1, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P1, 0x5},
+	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+	{OP_WR, HC_REG_VQID_1, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC5_END            743 */
+/* #define HC_FUNC6_START          744 */
+	{OP_WR, HC_REG_CONFIG_0, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P0, 0x6},
+	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
+	{OP_WR, HC_REG_VQID_0, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
+	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
+	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+/* #define HC_FUNC6_END            745 */
+/* #define HC_FUNC7_START          746 */
+	{OP_WR, HC_REG_CONFIG_1, 0x1080},
+	{OP_WR, HC_REG_FUNC_NUM_P1, 0x7},
+	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
+	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
+	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
+	{OP_WR, HC_REG_VQID_1, 0x2b5},
+	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
+	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
+	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
+	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
+	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+/* #define HC_FUNC7_END            747 */
+/* #define PXP2_COMMON_START       748 */
+	{OP_WR, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
+	{OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340},
+	{OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
+	{OP_WR, PXP2_REG_RQ_ELT_DISABLE, 0x1},
+	{OP_WR, PXP2_REG_WR_REV_MODE, 0x0},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
+	{OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xff802000},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0005000},
+	{OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xf0001000},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ11, 0x2},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ18, 0x5},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
+	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
+	{OP_WR, PXP2_REG_RD_START_INIT, 0x1},
+	{OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
+	{OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
+	{OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
+	{OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
+	{OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
+	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
+	{OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
+	{OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
+	{OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
+	{OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
+	{OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
+	{OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
+	{OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
+	{OP_WR, PXP2_REG_RQ_ILT_MODE, 0x1},
+	{OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
+/* #define PXP2_COMMON_END         749 */
+/* #define MISC_AEU_COMMON_START   770 */
+	{OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
+	{OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
+	{OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
+	{OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000},
+	{OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
+	{OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
+	{OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000},
+	{OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
+	{OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
+	{OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000},
+	{OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x0},
+	{OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000},
+	{OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014},
+	{OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
+	{OP_WR, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
+	{OP_WR, MISC_REG_AEU_GENERAL_MASK, 0x3},
+/* #define MISC_AEU_COMMON_END     771 */
+/* #define MISC_AEU_PORT0_START    772 */
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff},
+	{OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0},
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
+	{OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000},
+	{OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4},
+/* #define MISC_AEU_PORT0_END      773 */
+/* #define MISC_AEU_PORT1_START    774 */
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff},
+	{OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0},
+	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
+	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
+	{OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000},
+	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3},
+	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000},
+	{OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4},
+/* #define MISC_AEU_PORT1_END      775 */
+
+};
+
+static const uint16_t init_ops_offsets_e1h[] = {
+	0x0000, 0x0031, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0031, 0x0032, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0032,
+	0x0056, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0056, 0x008c, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x008c, 0x0090, 0x0090, 0x0094, 0x0094, 0x0098, 0x0098, 0x009c, 0x009c,
+	0x00a0, 0x00a0, 0x00a4, 0x00a4, 0x00a8, 0x00a8, 0x00ac, 0x00ac, 0x00b1,
+	0x00b1, 0x00b3, 0x00b3, 0x00b5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x00b5, 0x0100, 0x0100, 0x0108, 0x0108, 0x0110, 0x0110,
+	0x0119, 0x0119, 0x0122, 0x0122, 0x012b, 0x012b, 0x0134, 0x0134, 0x013d,
+	0x013d, 0x0146, 0x0146, 0x014f, 0x014f, 0x0158, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0158, 0x015d, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x015d, 0x015e, 0x015e, 0x015f, 0x015f, 0x0160, 0x0160, 0x0161,
+	0x0161, 0x0162, 0x0162, 0x0163, 0x0163, 0x0164, 0x0164, 0x0165, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0165, 0x016a, 0x016a, 0x0177, 0x0177, 0x0184,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0184, 0x0185, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0185, 0x01bc, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x01bc, 0x01e7, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x01e7, 0x0218, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0218, 0x021f, 0x021f, 0x0226, 0x0226, 0x022d, 0x022d,
+	0x0234, 0x0234, 0x023b, 0x023b, 0x0242, 0x0242, 0x0249, 0x0249, 0x0250,
+	0x0250, 0x0288, 0x0000, 0x0000, 0x0000, 0x0000, 0x0288, 0x028c, 0x028c,
+	0x0290, 0x0290, 0x0294, 0x0294, 0x0298, 0x0298, 0x029c, 0x029c, 0x02a0,
+	0x02a0, 0x02a4, 0x02a4, 0x02a8, 0x02a8, 0x02f4, 0x02f4, 0x030b, 0x030b,
+	0x0322, 0x0322, 0x0325, 0x0325, 0x0328, 0x0328, 0x032b, 0x032b, 0x032e,
+	0x032e, 0x0331, 0x0331, 0x0334, 0x0334, 0x0337, 0x0337, 0x033a, 0x033a,
+	0x037a, 0x037a, 0x0381, 0x0381, 0x0388, 0x0388, 0x038c, 0x038c, 0x0390,
+	0x0390, 0x0394, 0x0394, 0x0398, 0x0398, 0x039c, 0x039c, 0x03a0, 0x03a0,
+	0x03a4, 0x03a4, 0x03a8, 0x03a8, 0x03a9, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03a9, 0x03bb,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x03bb, 0x03d0, 0x03d0, 0x03d3, 0x03d3, 0x03d6, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03d6, 0x0403, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0403, 0x0506, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0506, 0x050d, 0x050d, 0x0511,
+	0x0511, 0x0515, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0515, 0x0555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0555, 0x055e, 0x055e,
+	0x0567, 0x0567, 0x0570, 0x0570, 0x0579, 0x0579, 0x0582, 0x0582, 0x058b,
+	0x058b, 0x0594, 0x0594, 0x059d, 0x059d, 0x05f2, 0x05f2, 0x0608, 0x0608,
+	0x061e, 0x061e, 0x0622, 0x0622, 0x0626, 0x0626, 0x062a, 0x062a, 0x062e,
+	0x062e, 0x0632, 0x0632, 0x0636, 0x0636, 0x063a, 0x063a, 0x063e, 0x063e,
+	0x0645, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0645, 0x064b, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x064b, 0x064e,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x064e, 0x0654, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0654, 0x0663, 0x0663, 0x0672, 0x0672, 0x0681,
+	0x0681, 0x0690, 0x0690, 0x069f, 0x069f, 0x06ae, 0x06ae, 0x06bd, 0x06bd,
+	0x06cc, 0x06cc, 0x073d, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x073d, 0x0750, 0x0750, 0x0761,
+	0x0761, 0x0772, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+};
+
+static const uint32_t init_data_e1h[] = {
+	0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
+	0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
+	0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
+	0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
+	0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
+	0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
+	0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
+	0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
+	0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
+	0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
+	0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
+	0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
+	0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
+	0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
+	0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
+	0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
+	0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
+	0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
+	0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
+	0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
+	0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
+	0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
+	0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
+	0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
+	0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
+	0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
+	0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
+	0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
+	0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
+	0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
+	0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
+	0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
+	0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
+	0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
+	0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
+	0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
+	0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
+	0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
+	0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
+	0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
+	0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
+	0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
+	0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
+	0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
+	0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
+	0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
+	0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
+	0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
+	0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
+	0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
+	0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
+	0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
+	0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
+	0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
+	0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
+	0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
+	0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
+	0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
+	0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
+	0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
+	0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
+	0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
+	0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
+	0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
+	0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
+	0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
+	0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
+	0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
+	0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
+	0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
+	0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
+	0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
+	0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
+	0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
+	0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
+	0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
+	0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
+	0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
+	0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
+	0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
+	0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
+	0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
+	0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
+	0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
+	0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
+	0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
+	0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
+	0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
+	0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
+	0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
+	0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
+	0x00000200, 0x00007ff8, 0x00007ff8, 0x00000cdf, 0x00001500, 0x00000001,
+	0x00000001, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000,
+	0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
+	0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
+	0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff,
+	0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000,
+	0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff,
+	0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20,
+	0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003,
+	0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
+	0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240,
+	0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0,
+	0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40,
+	0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0,
+	0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440,
+	0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0,
+	0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80,
+	0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80,
+	0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480,
+	0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980,
+	0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00007ff8,
+	0x00007ff8, 0x0000192a, 0x00003500, 0x00001900, 0x00100000, 0x00000000,
+	0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00007ff8, 0x00007ff8,
+	0x000005c7, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x00001000, 0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280,
+	0x00007300, 0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580,
+	0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880,
+	0x00013900, 0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80,
+	0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80,
+	0x0001ff00, 0x00007ff8, 0x00007ff8, 0x0000112e, 0x00003500, 0x10000000,
+	0x000028ad, 0x00000000, 0x00010001, 0x000d0205, 0xccccccc5, 0xffffffff,
+	0xffffffff, 0x7058103c, 0x00000000, 0x00000000, 0x00000001, 0xcccc0201,
+	0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201,
+	0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201,
+	0xcccccccc, 0xcccc0201, 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+	0x40000000, 0x002625a0, 0x00000000, 0x002625a0, 0x00000000, 0x002625a0,
+	0x00000000, 0x002625a0, 0x00000000, 0x000e0232, 0x011600d6, 0x00100000,
+	0x00000000, 0x002625a0, 0x00000000, 0x002625a0, 0x00000000, 0x002625a0,
+	0x00000000, 0x002625a0, 0x00000000, 0x00720236, 0x012300f3, 0x00100000,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+	0x00000000, 0x0000ffff, 0x00000000, 0xfffffff3, 0x318fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
+	0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
+	0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
+	0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
+	0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
+	0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
+	0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
+	0xcdcdcdcd, 0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
+	0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
+	0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
+	0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
+	0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
+	0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
+	0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
+	0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
+	0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
+	0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
+	0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
+	0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
+	0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
+	0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
+	0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
+	0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
+	0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
+	0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
+	0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
+	0xcdcdcdcd, 0xfffffff3, 0x316fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x302fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
+	0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
+	0xcdcdcdcd, 0xfffffff6, 0x30bfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf314,
+	0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
+	0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
+	0xcdcdcdcd, 0xfffffff7, 0x31cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+	0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff0, 0x307fffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff,
+	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
+	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+	0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x000c0000,
+	0x000700c0, 0x00028130, 0x000b8158, 0x00020210, 0x00010230, 0x000f0240,
+	0x00010330, 0x000c0000, 0x000800c0, 0x00028140, 0x000b8168, 0x00020220,
+	0x00010240, 0x00070250, 0x000202c0, 0x000f0000, 0x000800f0, 0x00028170,
+	0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000,
+	0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298,
+	0x00080380, 0x000b0000, 0x000100b0, 0x000280c0, 0x000580e8, 0x00020140,
+	0x00010160, 0x000e0170, 0x00038250, 0xcccccccc, 0xcccccccc, 0xcccccccc,
+	0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc,
+	0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x04002000
+};
+
+static const uint8_t tsem_int_table_data_e1h[] = {
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x05, 0x11, 0x00, 0x00, 0x3a, 0x13, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x0f, 0x09, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x41, 0x0d, 0x00, 0x00, 0x43, 0x0d, 0x00, 0x00, 0x45, 0x0d, 0x00, 0x00,
+	0x80, 0x0d, 0x00, 0x00, 0xc3, 0x0b, 0x00, 0x00, 0xc4, 0x0b, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xc9, 0x1f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x4b, 0x1d, 0x00, 0x00, 0x77, 0x1d, 0x00, 0x00,
+	0xb7, 0x1b, 0x00, 0x00, 0x34, 0x1e, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x2d, 0x20, 0x00, 0x00, 0x9e, 0x1e, 0x00, 0x00,
+	0x60, 0x1e, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xe5, 0x1e, 0x00, 0x00,
+	0x6b, 0x1f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x20, 0x25, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x1d, 0x23, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x21, 0x25, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x22, 0x25, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x7c, 0x23, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x23, 0x25, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x5f, 0x2c, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x8c, 0x2a, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xeb, 0x2b, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x60, 0x2c, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x8d, 0x2a, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x41, 0x25, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x61, 0x2c, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x42, 0x25, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x65, 0x04, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x5f, 0x04, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x85, 0x01, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x36, 0x08, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x62, 0x04, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00
+};
+
+static const uint8_t tsem_pram_data_e1h[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x16, 0x1f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xdf, 0x0c, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0xdf, 0x0c, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x05, 0x08, 0x00, 0x80,
+	0x0b, 0x2f, 0x00, 0x00, 0x11, 0x14, 0x40, 0x80, 0xe0, 0x2c, 0x00, 0x00,
+	0x17, 0x14, 0x40, 0xc0, 0x00, 0x34, 0x00, 0x00, 0x05, 0x10, 0x06, 0x20,
+	0x07, 0x01, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xc1, 0x11, 0x46, 0x18,
+	0xe0, 0x2c, 0x00, 0x00, 0x84, 0x15, 0x40, 0x18, 0x00, 0x0c, 0x00, 0x00,
+	0x84, 0x11, 0x56, 0x00, 0x60, 0x0c, 0x00, 0x00, 0x00, 0x60, 0x68, 0x00,
+	0x00, 0x16, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x05, 0x10, 0x52, 0x08,
+	0x00, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x16, 0x00, 0x00,
+	0x04, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x85, 0x10, 0x22, 0x0f,
+	0x60, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x00, 0x00, 0x02, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x03, 0x00, 0x00, 0x08, 0x08, 0x00, 0x80, 0x0b, 0x0f, 0x00, 0x00,
+	0x11, 0x20, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x0a, 0x34, 0x02, 0xa0,
+	0x47, 0x21, 0x00, 0x00, 0x17, 0x20, 0xa0, 0xc0, 0x00, 0x34, 0x00, 0x00,
+	0x0b, 0x1c, 0x06, 0x20, 0x07, 0x21, 0x00, 0x00, 0xc1, 0x1d, 0xc6, 0x08,
+	0x23, 0x34, 0x00, 0x00, 0x8a, 0x3d, 0x02, 0x30, 0x07, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x71, 0x00, 0x00, 0x36, 0x00, 0x00, 0x72, 0x08, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x8a, 0x2d, 0xc0, 0x08, 0x23, 0x34, 0x00, 0x00,
+	0x8a, 0x3d, 0x04, 0x30, 0x00, 0x20, 0x00, 0x00, 0x45, 0x03, 0xac, 0x81,
+	0x06, 0x34, 0x00, 0x00, 0x0b, 0x20, 0x00, 0x30, 0x07, 0x20, 0x00, 0x00,
+	0x0d, 0x2d, 0x70, 0xc0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0c,
+	0x19, 0x36, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x10, 0x28, 0x66, 0x4c, 0x00, 0x2e, 0x00, 0x00, 0x0f, 0x40, 0x06, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x16, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x07, 0x20, 0x06, 0x00, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x8c, 0xf1,
+	0x03, 0x0e, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x50, 0x0d, 0x00, 0x00,
+	0x0d, 0x38, 0x06, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x0b, 0x28, 0x46, 0xe7, 0x00, 0x2e, 0x00, 0x00,
+	0x0b, 0x00, 0x06, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x21, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00,
+	0x3b, 0x00, 0x0d, 0x14, 0xe6, 0x0b, 0x00, 0x00, 0x00, 0x37, 0x00, 0x37,
+	0xff, 0x03, 0x00, 0x00, 0x00, 0x44, 0x12, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x68, 0x00,
+	0x00, 0x16, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0xfe, 0xff, 0x16, 0x00, 0x00, 0x0c, 0x08, 0x00, 0x00,
+	0x00, 0x23, 0x00, 0x00, 0x47, 0x88, 0xe0, 0xd8, 0x02, 0x14, 0x00, 0x00,
+	0x0d, 0x40, 0x02, 0x00, 0x07, 0x00, 0x00, 0x00, 0x46, 0x03, 0x0c, 0x09,
+	0x23, 0x14, 0x00, 0x00, 0x8f, 0xc8, 0x03, 0x30, 0x07, 0x20, 0x00, 0x00,
+	0x8f, 0x58, 0xf0, 0x08, 0x10, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x40, 0x4c,
+	0x19, 0x16, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x1f, 0x38, 0x66, 0x4c, 0x00, 0x0e, 0x00, 0x00, 0x9c, 0x7f, 0x00, 0x00,
+	0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x71, 0x00, 0x00, 0x36, 0x00, 0x00,
+	0x72, 0x08, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x1c, 0x34, 0xd0, 0x40,
+	0x00, 0x0c, 0x00, 0x00, 0x0d, 0x34, 0xd0, 0x01, 0x00, 0x14, 0x00, 0x00,
+	0x1c, 0x30, 0x00, 0x00, 0x13, 0x21, 0x00, 0x00, 0x10, 0x70, 0xd0, 0x01,
+	0x00, 0x22, 0x00, 0x00, 0x9c, 0x00, 0xc0, 0xd1, 0x23, 0x01, 0x00, 0x00,
+	0x00, 0x7c, 0x06, 0x00, 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00,
+	0xff, 0x22, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x16, 0x00, 0x00,
+	0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x40, 0x06, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x11, 0x00, 0x8c, 0xf1, 0x03, 0x2e, 0x00, 0x00, 0x1c, 0x74, 0x06, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x11, 0x38, 0x46, 0xe7, 0x00, 0x2e, 0x00, 0x00, 0x11, 0x00, 0x06, 0x00,
+	0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x21, 0x00, 0x00,
+	0xa0, 0x00, 0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x63, 0x00, 0x0d, 0x14,
+	0xe6, 0x2b, 0x00, 0x00, 0x00, 0x15, 0x00, 0x25, 0xff, 0x03, 0x00, 0x00,
+	0x00, 0x80, 0x12, 0x00, 0x00, 0x19, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x16, 0x00, 0x00,
+	0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
+	0xff, 0x16, 0x00, 0x00, 0x10, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
+	0x47, 0x48, 0xe0, 0x58, 0x04, 0x34, 0x00, 0x00, 0x0b, 0x3c, 0x02, 0x00,
+	0x07, 0x20, 0x00, 0x00, 0x8f, 0x40, 0x02, 0x00, 0x0b, 0x14, 0x00, 0x00,
+	0xf2, 0xd8, 0x07, 0xa0, 0x03, 0x21, 0x00, 0x00, 0x00, 0x80, 0x40, 0xd0,
+	0x18, 0x16, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x0c, 0x38, 0x66, 0x4c, 0x00, 0x2e, 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00,
+	0x00, 0x39, 0x00, 0x00, 0x89, 0x7f, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x02, 0x02, 0x18, 0x00, 0x00, 0x09, 0x2c, 0xb0, 0x40,
+	0x00, 0x2c, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x02, 0x18, 0x00, 0x00,
+	0x0b, 0x2c, 0xa0, 0x00, 0x00, 0x14, 0x00, 0x00, 0x09, 0x40, 0x00, 0x00,
+	0x13, 0x21, 0x00, 0x00, 0x45, 0x03, 0x0c, 0x01, 0x04, 0x34, 0x00, 0x00,
+	0x8b, 0x28, 0x00, 0x30, 0x07, 0x20, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
+	0x02, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x16, 0x00, 0x00,
+	0x10, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x02, 0x18, 0x00, 0x00, 0x8b, 0x40, 0x02, 0x00, 0x0c, 0x14, 0x00, 0x00,
+	0xf2, 0xd8, 0x07, 0xa0, 0x03, 0x21, 0x00, 0x00, 0x8b, 0x08, 0xb0, 0x08,
+	0x01, 0x14, 0x00, 0x00, 0x91, 0x3c, 0x02, 0x00, 0x80, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0xb2, 0x10, 0x50, 0x0d, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x07, 0x20, 0x02, 0x00, 0x00, 0x08, 0x00, 0x00,
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+	0x00, 0x15, 0x00, 0x00, 0xed, 0x59, 0x30, 0x1e, 0x00, 0x03, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x31, 0x02, 0x34, 0x00, 0x00, 0x6d, 0x52, 0x0c, 0x30,
+	0x8a, 0x01, 0x00, 0x00, 0xdc, 0x05, 0x00, 0x5f, 0x50, 0x2c, 0x00, 0x00,
+	0x16, 0x12, 0x00, 0x60, 0xb1, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xe1, 0x2c, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0x69, 0x22, 0x50, 0xcd,
+	0x2c, 0x35, 0x00, 0x00, 0x6a, 0x70, 0x91, 0xb6, 0xcc, 0x20, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xef, 0x01, 0x00, 0x40,
+	0x00, 0x34, 0x00, 0x00, 0x80, 0x8d, 0x07, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x6d, 0xbe, 0xd9, 0xde, 0x7b, 0x00, 0x00, 0x00, 0x69, 0xa7, 0x2d, 0x33,
+	0x60, 0x2c, 0x00, 0x00, 0xe1, 0x2c, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x45, 0x03, 0x8c, 0x26, 0x01, 0x14, 0x00, 0x00, 0xf2, 0x98, 0x07, 0x00,
+	0x07, 0x21, 0x00, 0x00, 0xee, 0x0d, 0x20, 0x2e, 0x00, 0x03, 0x00, 0x00,
+	0x62, 0x03, 0xc0, 0x06, 0x00, 0x23, 0x00, 0x00, 0x42, 0x2c, 0x60, 0xda,
+	0x2c, 0x15, 0x00, 0x00, 0xb2, 0xc8, 0xd2, 0x16, 0x60, 0x0c, 0x00, 0x00,
+	0x66, 0x08, 0xf4, 0x00, 0x04, 0x13, 0x00, 0x00, 0x45, 0x03, 0x2c, 0x0f,
+	0xe0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x66, 0x08, 0xf1, 0x00, 0x04, 0x13, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xe6, 0x99, 0x87, 0x26,
+	0x60, 0x0c, 0x00, 0x00, 0xef, 0x1d, 0xd0, 0x06, 0x00, 0x03, 0x00, 0x00,
+	0xef, 0xa1, 0xf9, 0x1e, 0x20, 0x2c, 0x00, 0x00, 0x6d, 0xbc, 0xc7, 0xd8,
+	0x01, 0x2e, 0x00, 0x00, 0x6d, 0x08, 0x0c, 0xc0, 0x03, 0x2e, 0x00, 0x00,
+	0x00, 0xb4, 0x05, 0xec, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x22, 0x00, 0x00, 0x07, 0x0a, 0x00, 0x80, 0x09, 0x12, 0x00, 0x00,
+	0x80, 0x87, 0x3c, 0x11, 0xe6, 0x2b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00,
+	0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x16, 0x00, 0x00,
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x07, 0x08, 0x0c, 0xc0,
+	0x03, 0x2e, 0x00, 0x00, 0x00, 0x1c, 0x04, 0xec, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x22, 0x00, 0x00, 0x07, 0x00, 0x00, 0xa0,
+	0x02, 0x03, 0x00, 0x00, 0xb4, 0x08, 0x0e, 0x2e, 0x00, 0x0f, 0x00, 0x00,
+	0xb4, 0x08, 0x1e, 0xa0, 0x00, 0x0e, 0x00, 0x00, 0xb8, 0x05, 0x0c, 0x88,
+	0x01, 0x2f, 0x00, 0x00, 0x00, 0x60, 0x31, 0x02, 0x00, 0x36, 0x00, 0x00,
+	0x74, 0x10, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0xb4, 0xd0, 0x02, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0xb4, 0x18, 0x06, 0xa0, 0x00, 0x21, 0x00, 0x00,
+	0x00, 0x40, 0x00, 0x20, 0x00, 0x36, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x74, 0xd1, 0x02, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x74, 0x21, 0x00, 0xa0, 0x00, 0x21, 0x00, 0x00, 0x07, 0x0a, 0x00, 0x80,
+	0x08, 0x32, 0x00, 0x00, 0x01, 0xe0, 0xc6, 0xf9, 0x01, 0x0e, 0x00, 0x00,
+	0x09, 0x00, 0xa0, 0x18, 0x00, 0x03, 0x00, 0x00, 0x83, 0x01, 0x30, 0x20,
+	0x00, 0x23, 0x00, 0x00, 0xeb, 0x10, 0x60, 0x03, 0x2d, 0x15, 0x00, 0x00,
+	0x00, 0x60, 0x73, 0x30, 0x10, 0x14, 0x00, 0x00, 0x03, 0x1f, 0x0c, 0x30,
+	0x8a, 0x21, 0x00, 0x00, 0xb2, 0xca, 0x4a, 0x1b, 0x60, 0x2c, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x50, 0x08, 0x16, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x35, 0xe0, 0xc6, 0xf9, 0x01, 0x2e, 0x00, 0x00,
+	0x00, 0x2c, 0x0f, 0x04, 0x00, 0x36, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x36, 0x08, 0x70, 0x03, 0x00, 0x22, 0x00, 0x00,
+	0x39, 0x00, 0x80, 0x03, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x10,
+	0xe6, 0x0b, 0x00, 0x00, 0x00, 0x89, 0xc6, 0x01, 0xff, 0x2b, 0x00, 0x00
+};
+
+static const uint8_t usem_int_table_data_e1h[] = {
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x0e, 0x38, 0x00, 0x00, 0xaa, 0x3a, 0x00, 0x00, 0xd8, 0x3b, 0x00, 0x00,
+	0x41, 0x3c, 0x00, 0x00, 0xb3, 0x37, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xd8, 0x17, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xe7, 0x1f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x9e, 0x19, 0x00, 0x00, 0xa0, 0x19, 0x00, 0x00, 0xa2, 0x19, 0x00, 0x00,
+	0xa4, 0x19, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xfb, 0x2a, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x73, 0x25, 0x00, 0x00, 0xfc, 0x2a, 0x00, 0x00,
+	0x44, 0x25, 0x00, 0x00, 0xf5, 0x27, 0x00, 0x00, 0xdb, 0x2a, 0x00, 0x00,
+	0xfd, 0x2a, 0x00, 0x00, 0x88, 0x25, 0x00, 0x00, 0xac, 0x25, 0x00, 0x00,
+	0xb8, 0x25, 0x00, 0x00, 0x14, 0x2a, 0x00, 0x00, 0xd9, 0x25, 0x00, 0x00,
+	0x03, 0x26, 0x00, 0x00, 0xe4, 0x25, 0x00, 0x00, 0xfe, 0x2a, 0x00, 0x00,
+	0x1b, 0x26, 0x00, 0x00, 0xc4, 0x26, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xff, 0x2a, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xb7, 0x28, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xe9, 0x28, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xd0, 0x27, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x5a, 0x29, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xeb, 0x29, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x4a, 0x3f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x8e, 0x3f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xaf, 0x17, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x17, 0x35, 0x00, 0x00, 0x2e, 0x36, 0x00, 0x00,
+	0x71, 0x37, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xac, 0x17, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x83, 0x37, 0x00, 0x00,
+	0x18, 0x35, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf4, 0x2e, 0x00, 0x00,
+	0x0e, 0x37, 0x00, 0x00, 0xa9, 0x17, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf5, 0x2e, 0x00, 0x00, 0x0f, 0x37, 0x00, 0x00,
+	0x8f, 0x37, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x17, 0x03, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xff, 0x0c, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xed, 0x02, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x7f, 0x12, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xb2, 0x13, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf9, 0x14, 0x00, 0x00
+};
+
+static const uint8_t usem_pram_data_e1h[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x10, 0x1f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x2a, 0x19, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x2a, 0x19, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x42, 0x08, 0x00, 0x80, 0x0b, 0x2f, 0x00, 0x00,
+	0x11, 0x08, 0xb1, 0xcb, 0x2e, 0x14, 0x00, 0x00, 0x46, 0x0c, 0x03, 0x30,
+	0x47, 0x20, 0x00, 0x00, 0x17, 0x08, 0x61, 0xc4, 0x00, 0x34, 0x00, 0x00,
+	0x3c, 0x00, 0x07, 0x20, 0x07, 0x01, 0x00, 0x00, 0xc1, 0x01, 0xb7, 0xcb,
+	0x2e, 0x34, 0x00, 0x00, 0xc6, 0x0d, 0x05, 0x30, 0x07, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x71, 0x00, 0x00, 0x36, 0x00, 0x00, 0x72, 0x08, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0xc6, 0xf1, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0xc6, 0xf9, 0x02, 0xa0, 0x00, 0x01, 0x00, 0x00, 0x45, 0x03, 0x4c, 0x00,
+	0x01, 0x34, 0x00, 0x00, 0x3c, 0x08, 0x01, 0x30, 0x07, 0x20, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x0c, 0x4d, 0x16, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x3e, 0xf1, 0x00, 0x44, 0x01, 0x20, 0x00, 0x00,
+	0x44, 0x18, 0x67, 0x4c, 0x00, 0x2e, 0x00, 0x00, 0x43, 0x10, 0x07, 0x00,
+	0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x16, 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x40, 0x08, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x8c, 0xf1,
+	0x03, 0x0e, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 0x50, 0x2d, 0x00, 0x00,
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+	0x5d, 0xbc, 0x43, 0xe9, 0x04, 0x0e, 0x00, 0x00, 0x5d, 0x70, 0x01, 0x00,
+	0xe2, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xe2, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x6e, 0x00, 0x00, 0x00,
+	0xe2, 0x25, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x59, 0x60, 0x03, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x5b, 0x68, 0x0b, 0x00, 0x00, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x08, 0x0a, 0x00, 0x60,
+	0xb0, 0x0c, 0x00, 0x00, 0x08, 0x06, 0x00, 0x60, 0xb0, 0x0c, 0x00, 0x00,
+	0x88, 0x09, 0x00, 0x58, 0xb0, 0x0c, 0x00, 0x00, 0x0c, 0x46, 0x01, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x0c, 0x46, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x0d, 0x46, 0x01, 0x00, 0x00, 0x15, 0x00, 0x00, 0x8b, 0x09, 0x00, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x8b, 0xb9, 0x01, 0xa0, 0x81, 0x21, 0x00, 0x00,
+	0x6e, 0x2c, 0xc6, 0xd8, 0x01, 0x0e, 0x00, 0x00, 0x17, 0x40, 0x00, 0x00,
+	0x78, 0x32, 0x00, 0x00, 0x6e, 0x18, 0x0c, 0xc0, 0x03, 0x0e, 0x00, 0x00,
+	0x00, 0xb8, 0x05, 0xec, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x22, 0x00, 0x00, 0x17, 0x20, 0x10, 0x00, 0x5c, 0x12, 0x00, 0x00,
+	0x00, 0x40, 0x2c, 0x00, 0x00, 0x36, 0x00, 0x00, 0x19, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0xe6, 0x28, 0x00, 0x00,
+	0x01, 0xc0, 0x12, 0x02, 0xff, 0x2b, 0x00, 0x00, 0x17, 0x1c, 0xc8, 0xf9,
+	0x01, 0x0e, 0x00, 0x00, 0x3d, 0x46, 0x20, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x16, 0x5e, 0xb0, 0x01, 0x00, 0x03, 0x00, 0x00, 0x1d, 0x00, 0x80, 0x81,
+	0x01, 0x21, 0x00, 0x00, 0xc5, 0x06, 0x00, 0x41, 0xb1, 0x14, 0x00, 0x00,
+	0x6c, 0xb4, 0x01, 0x00, 0x81, 0x20, 0x00, 0x00, 0x6f, 0xa0, 0x51, 0x00,
+	0x20, 0x33, 0x00, 0x00, 0xc5, 0x9a, 0xda, 0x86, 0xa9, 0x14, 0x00, 0x00,
+	0x6e, 0xb4, 0x01, 0x10, 0x01, 0x00, 0x00, 0x00, 0x6d, 0xb0, 0xd1, 0x06,
+	0x40, 0x2c, 0x00, 0x00, 0x6d, 0x04, 0xd0, 0x06, 0x10, 0x0c, 0x00, 0x00,
+	0x6e, 0xbc, 0xeb, 0x06, 0x00, 0x0c, 0x00, 0x00, 0x6e, 0xb0, 0xe1, 0x06,
+	0x40, 0x2c, 0x00, 0x00, 0x6d, 0xb8, 0x01, 0x40, 0xa0, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x34, 0x46, 0x03, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x44, 0x40, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x6d, 0x74, 0x03, 0xa0,
+	0x07, 0x21, 0x00, 0x00, 0x46, 0xb4, 0x01, 0x00, 0x00, 0x14, 0x00, 0x00,
+	0x6f, 0x70, 0x01, 0xa0, 0x20, 0x01, 0x00, 0x00, 0xc6, 0x1d, 0x76, 0x04,
+	0x00, 0x14, 0x00, 0x00, 0x5d, 0xb9, 0x01, 0x00, 0x17, 0x01, 0x00, 0x00,
+	0x6f, 0x20, 0xd0, 0x15, 0x0b, 0x14, 0x00, 0x00, 0x6f, 0x74, 0x05, 0x00,
+	0xa0, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x4c, 0x41, 0x36, 0x00, 0x00,
+	0x58, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x58, 0x20, 0x6a, 0x4c,
+	0x00, 0x0e, 0x00, 0x00, 0x6e, 0x00, 0xf0, 0xc6, 0x1b, 0x34, 0x00, 0x00,
+	0x6e, 0x68, 0x01, 0x30, 0xc0, 0x20, 0x00, 0x00, 0x00, 0x60, 0x05, 0xe2,
+	0xe0, 0x08, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, 0xff, 0x22, 0x00, 0x00,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x16, 0x00, 0x00, 0x5f, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x90, 0x19, 0x0e, 0xa2, 0x00, 0x2f, 0x00, 0x00,
+	0x6e, 0xb8, 0xb1, 0x05, 0x60, 0x2c, 0x00, 0x00, 0x5b, 0x68, 0x05, 0xe2,
+	0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x5f, 0x40, 0x46, 0xe9, 0x01, 0x2e, 0x00, 0x00, 0x5d, 0x70, 0x05, 0xe2,
+	0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x5f, 0x1c, 0x86, 0xf1, 0x03, 0x0e, 0x00, 0x00, 0x5f, 0x00, 0x04, 0xe2,
+	0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x21, 0x00, 0x00,
+	0xf5, 0x45, 0x0d, 0x14, 0xe6, 0x0b, 0x00, 0x00, 0x00, 0x2b, 0x00, 0x2c,
+	0xff, 0x23, 0x00, 0x00, 0x18, 0x44, 0x10, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x58, 0x60, 0x01, 0x01, 0x60, 0x2c, 0x00, 0x00, 0x08, 0x02, 0x50, 0x6c,
+	0x00, 0x14, 0x00, 0x00, 0x00, 0xbe, 0x01, 0x10, 0xa5, 0x21, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x0b, 0x46, 0x02, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x4b, 0x80, 0x01, 0x00, 0x78, 0x12, 0x00, 0x00, 0xa6, 0x06, 0x00, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0xa6, 0x3a, 0x01, 0xa0, 0x80, 0x21, 0x00, 0x00,
+	0x4b, 0x00, 0x00, 0x00, 0x5c, 0x12, 0x00, 0x00, 0xa6, 0xbe, 0x61, 0x80,
+	0x01, 0x34, 0x00, 0x00, 0xa6, 0x32, 0x01, 0x30, 0x02, 0x20, 0x00, 0x00,
+	0x00, 0x00, 0x14, 0x00, 0x00, 0x36, 0x00, 0x00, 0x4a, 0x00, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x29, 0x00, 0x80, 0x00, 0xe6, 0x08, 0x00, 0x00,
+	0x02, 0x00, 0x00, 0x94, 0xff, 0x33, 0x00, 0x00, 0x4e, 0x04, 0x00, 0x00,
+	0x09, 0x32, 0x00, 0x00, 0x4b, 0x1c, 0xc8, 0xf9, 0x01, 0x0e, 0x00, 0x00,
+	0x00, 0x00, 0xa0, 0x00, 0x00, 0x35, 0x00, 0x00, 0x51, 0x98, 0x0a, 0xc0,
+	0x03, 0x2e, 0x00, 0x00, 0x8b, 0x05, 0xb0, 0x18, 0x30, 0x2c, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0xbb, 0x45, 0x00, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x0a, 0x07, 0x00, 0x70, 0xb0, 0x2c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xf7, 0x45, 0x41, 0xbb, 0x45, 0x15, 0x00, 0x00,
+	0xbb, 0x45, 0x02, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80,
+	0xe4, 0x28, 0x00, 0x00, 0x55, 0x00, 0x01, 0x00, 0x0f, 0x23, 0x00, 0x00,
+	0x03, 0x19, 0x60, 0x17, 0x46, 0x35, 0x00, 0x00, 0x6d, 0x18, 0xe0, 0x06,
+	0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06, 0x50, 0x2d, 0x00, 0x00,
+	0x60, 0x44, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x1d, 0x46, 0x01, 0x04,
+	0xe6, 0x28, 0x00, 0x00, 0x00, 0x2b, 0x00, 0x2b, 0xff, 0x03, 0x00, 0x00,
+	0xec, 0x1d, 0xd6, 0x0e, 0xc2, 0x00, 0x00, 0x00, 0x30, 0x19, 0x50, 0x20,
+	0x46, 0x15, 0x00, 0x00, 0x6c, 0x06, 0xc0, 0x2e, 0x00, 0x03, 0x00, 0x00,
+	0x30, 0x19, 0x60, 0x20, 0x46, 0x15, 0x00, 0x00, 0xec, 0x1d, 0xd6, 0x0e,
+	0xc2, 0x00, 0x00, 0x00, 0x6c, 0x06, 0xc0, 0x6e, 0x00, 0x23, 0x00, 0x00,
+	0x00, 0x00, 0x04, 0xe2, 0xe0, 0x28, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00,
+	0xff, 0x03, 0x00, 0x00, 0x8a, 0x28, 0xb2, 0x05, 0x60, 0x2c, 0x00, 0x00,
+	0x5b, 0x00, 0x04, 0xe2, 0xe0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x21, 0x00, 0x00, 0x00, 0x00, 0x04, 0xe2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x04, 0xe2,
+	0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00,
+	0xb6, 0x45, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80,
+	0xe4, 0x28, 0x00, 0x00, 0x55, 0x00, 0x01, 0x00, 0x0f, 0x23, 0x00, 0x00,
+	0x03, 0x19, 0x60, 0x71, 0x44, 0x15, 0x00, 0x00, 0x6d, 0x18, 0xe0, 0x06,
+	0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06, 0x50, 0x2d, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x80, 0xe4, 0x28, 0x00, 0x00, 0x55, 0x00, 0x01, 0x00,
+	0x0f, 0x23, 0x00, 0x00, 0x03, 0x19, 0x60, 0xe4, 0x44, 0x15, 0x00, 0x00,
+	0x6d, 0x18, 0xe0, 0x06, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x06,
+	0x50, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0xe4, 0x28, 0x00, 0x00,
+	0x55, 0x00, 0x01, 0x00, 0x0f, 0x23, 0x00, 0x00, 0x03, 0x19, 0x60, 0xd8,
+	0x45, 0x35, 0x00, 0x00, 0x6d, 0x18, 0xe0, 0x06, 0x00, 0x22, 0x00, 0x00,
+	0x00, 0x00, 0xf0, 0x06, 0x50, 0x2d, 0x00, 0x00, 0x83, 0x09, 0x00, 0x58,
+	0xb0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x7f, 0x46, 0x01, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x10, 0xe6, 0x0b, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x16, 0x00, 0x00, 0x72, 0x10, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0xc5, 0x1d, 0xf6, 0x0e, 0xe0, 0x0c, 0x00, 0x00, 0x88, 0x01, 0x20, 0xd7,
+	0x3b, 0x34, 0x00, 0x00, 0x80, 0xc9, 0x05, 0x00, 0xa5, 0x20, 0x00, 0x00,
+	0x88, 0x09, 0x00, 0x58, 0xb0, 0x0c, 0x00, 0x00, 0x88, 0x0d, 0x00, 0x58,
+	0xb0, 0x2c, 0x00, 0x00, 0x4e, 0x46, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x4e, 0x46, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00, 0x69, 0x46, 0x01, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x88, 0x05, 0x00, 0x58, 0xb0, 0x0c, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x74, 0x46, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x2a, 0x19, 0x40, 0x4d, 0x46, 0x35, 0x00, 0x00, 0x2b, 0xa8, 0x02, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x2d, 0xb0, 0x0a, 0x00, 0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x2f, 0xb8, 0x12, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x31, 0xc0, 0x1a, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x33, 0xc8, 0x22, 0x00, 0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x35, 0xd0, 0x2a, 0x00, 0x20, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x37, 0xd8, 0x32, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x39, 0xe0, 0x3a, 0x00, 0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x3b, 0xe8, 0x42, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x3d, 0xf0, 0x4a, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x3f, 0xf8, 0x52, 0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x41, 0x00, 0x5b, 0x00, 0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x43, 0x08, 0x63, 0x00, 0x20, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x1b, 0x68, 0x02, 0x00,
+	0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x1d, 0x70, 0x0a, 0x00, 0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x1f, 0x78, 0x12, 0x00, 0x20, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0x21, 0x80, 0x1a, 0x00, 0x20, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x23, 0x88, 0x22, 0x00,
+	0x20, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+	0x12, 0x11, 0xf2, 0x16, 0x20, 0x2c, 0x00, 0x00, 0x6f, 0xfd, 0xf7, 0x0e,
+	0x10, 0x0c, 0x00, 0x00, 0x89, 0xbc, 0xf3, 0x0e, 0xe0, 0x0c, 0x00, 0x00,
+	0xef, 0xf0, 0x07, 0x00, 0xd0, 0x2c, 0x00, 0x00, 0x00, 0x04, 0xe0, 0x06,
+	0x00, 0x0c, 0x00, 0x00, 0x6e, 0xbc, 0x05, 0x40, 0xa0, 0x2c, 0x00, 0x00,
+	0xef, 0x04, 0xf0, 0x0e, 0x15, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xf0, 0x44, 0x20, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0xc2, 0xbc, 0x23, 0x09, 0xe0, 0x0c, 0x00, 0x00, 0x92, 0x48, 0x24, 0x09,
+	0x00, 0x2c, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00
+};
+
+static const uint8_t csem_int_table_data_e1h[] = {
+	0x09, 0x10, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x97, 0x0f, 0x00, 0x00, 0xb3, 0x0f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xc6, 0x03, 0x00, 0x00,
+	0xc7, 0x03, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, 0xbe, 0x01, 0x00, 0x00,
+	0xb5, 0x01, 0x00, 0x00, 0xac, 0x01, 0x00, 0x00, 0xef, 0x00, 0x00, 0x00,
+	0xa5, 0x01, 0x00, 0x00, 0x9c, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00,
+	0x8a, 0x01, 0x00, 0x00, 0xe9, 0x00, 0x00, 0x00, 0x7e, 0x05, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x04, 0x06, 0x00, 0x00,
+	0x06, 0x06, 0x00, 0x00, 0xc9, 0x03, 0x00, 0x00, 0xca, 0x03, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x21, 0x0e, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xc2, 0x0d, 0x00, 0x00, 0xad, 0x0d, 0x00, 0x00,
+	0xc5, 0x0d, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x98, 0x11, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xe6, 0x11, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xbb, 0x15, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x05, 0x17, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x8f, 0x18, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x06, 0x17, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x6a, 0x1c, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x76, 0x1c, 0x00, 0x00
+};
+
+static const uint8_t csem_pram_data_e1h[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x12, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xc7, 0x05, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0xc7, 0x05, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0xef, 0x01, 0xf0, 0x2e,
+	0x04, 0x23, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x84, 0x7f, 0x40, 0x00, 0x40, 0x07, 0x00, 0x00, 0x8d, 0x7f, 0x08, 0x00,
+	0x40, 0x07, 0x00, 0x00, 0x87, 0x7f, 0x18, 0x00, 0x40, 0x27, 0x00, 0x00,
+	0x84, 0x34, 0x02, 0x48, 0xa0, 0x0c, 0x00, 0x00, 0x8b, 0x7f, 0x10, 0x00,
+	0x40, 0x07, 0x00, 0x00, 0x97, 0x7f, 0x50, 0x00, 0x40, 0x07, 0x00, 0x00,
+	0x95, 0x7f, 0x58, 0x00, 0x40, 0x07, 0x00, 0x00, 0x93, 0x7f, 0x60, 0x00,
+	0x40, 0x27, 0x00, 0x00, 0x91, 0x7f, 0x68, 0x00, 0x40, 0x27, 0x00, 0x00,
+	0x8f, 0x7f, 0x70, 0x00, 0x40, 0x27, 0x00, 0x00, 0x85, 0x7f, 0x48, 0x00,
+	0x40, 0x07, 0x00, 0x00, 0x88, 0x7f, 0x78, 0x00, 0x40, 0x27, 0x00, 0x00,
+	0x47, 0x05, 0x62, 0x17, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x40, 0x08,
+	0x21, 0x14, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0x87, 0x1e, 0x3a, 0x0f, 0x04, 0x34, 0x00, 0x00, 0x6f, 0xcf, 0x03, 0x00,
+	0x03, 0x21, 0x00, 0x00, 0x85, 0x34, 0x04, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0x00, 0x04, 0x50, 0x48, 0x21, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x47, 0x05, 0x42, 0x1c, 0x00, 0x15, 0x00, 0x00, 0x97, 0x38, 0x02, 0x48,
+	0xa0, 0x2c, 0x00, 0x00, 0x00, 0x08, 0x70, 0xc9, 0x25, 0x34, 0x00, 0x00,
+	0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x21, 0x00, 0x35, 0x00, 0x00,
+	0x95, 0x38, 0x04, 0x48, 0xa0, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0x50, 0x49,
+	0x25, 0x14, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x26,
+	0x00, 0x15, 0x00, 0x00, 0x93, 0x2c, 0x02, 0x48, 0xa0, 0x0c, 0x00, 0x00,
+	0x00, 0x10, 0x30, 0xc9, 0x24, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x47, 0x05, 0x42, 0x2b, 0x00, 0x35, 0x00, 0x00, 0x91, 0x2c, 0x04, 0x48,
+	0xa0, 0x2c, 0x00, 0x00, 0x00, 0x14, 0x10, 0x49, 0x24, 0x14, 0x00, 0x00,
+	0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x30, 0x00, 0x35, 0x00, 0x00,
+	0x8f, 0x30, 0x02, 0x48, 0xa0, 0x0c, 0x00, 0x00, 0x00, 0x18, 0xf0, 0xc8,
+	0x23, 0x14, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x35,
+	0x00, 0x35, 0x00, 0x00, 0x88, 0x30, 0x04, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0x00, 0x1c, 0x80, 0x08, 0x22, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x47, 0x05, 0x42, 0x3a, 0x00, 0x35, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x84, 0x7f, 0x40, 0x00, 0x40, 0x07, 0x00, 0x00,
+	0x8d, 0x7f, 0x08, 0x00, 0x40, 0x07, 0x00, 0x00, 0x87, 0x7f, 0x18, 0x00,
+	0x40, 0x27, 0x00, 0x00, 0x84, 0x34, 0x02, 0x00, 0x00, 0x14, 0x00, 0x00,
+	0x80, 0xbc, 0x07, 0xa0, 0x25, 0x21, 0x00, 0x00, 0x8b, 0x7f, 0x10, 0x00,
+	0x40, 0x07, 0x00, 0x00, 0x97, 0x7f, 0x50, 0x00, 0x40, 0x07, 0x00, 0x00,
+	0x95, 0x7f, 0x58, 0x00, 0x40, 0x07, 0x00, 0x00, 0x93, 0x7f, 0x60, 0x00,
+	0x40, 0x27, 0x00, 0x00, 0x91, 0x7f, 0x68, 0x00, 0x40, 0x27, 0x00, 0x00,
+	0x8f, 0x7f, 0x70, 0x00, 0x40, 0x27, 0x00, 0x00, 0x85, 0x7f, 0x48, 0x00,
+	0x40, 0x07, 0x00, 0x00, 0x88, 0x7f, 0x78, 0x00, 0x40, 0x27, 0x00, 0x00,
+	0x00, 0x40, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0xef, 0xbe, 0x09, 0xa2,
+	0x8a, 0x01, 0x00, 0x00, 0x47, 0x05, 0x62, 0x4e, 0x00, 0x15, 0x00, 0x00,
+	0x84, 0x10, 0x72, 0xe8, 0xa1, 0x14, 0x00, 0x00, 0xee, 0xbc, 0x2d, 0x30,
+	0x03, 0x20, 0x00, 0x00, 0xf3, 0x40, 0x30, 0x0f, 0x10, 0x0c, 0x00, 0x00,
+	0x85, 0x34, 0x04, 0x48, 0xa0, 0x2c, 0x00, 0x00, 0x00, 0x04, 0x50, 0x48,
+	0x21, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x53,
+	0x00, 0x35, 0x00, 0x00, 0x97, 0x38, 0x02, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0x00, 0x08, 0x70, 0xc9, 0x25, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x47, 0x05, 0x42, 0x58, 0x00, 0x15, 0x00, 0x00, 0x95, 0x38, 0x04, 0x48,
+	0xa0, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0x50, 0x49, 0x25, 0x14, 0x00, 0x00,
+	0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x5d, 0x00, 0x15, 0x00, 0x00,
+	0x93, 0x2c, 0x02, 0x48, 0xa0, 0x0c, 0x00, 0x00, 0x00, 0x10, 0x30, 0xc9,
+	0x24, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x62,
+	0x00, 0x15, 0x00, 0x00, 0x91, 0x2c, 0x04, 0x48, 0xa0, 0x2c, 0x00, 0x00,
+	0x00, 0x14, 0x10, 0x49, 0x24, 0x14, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32,
+	0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x47, 0x05, 0x42, 0x67, 0x00, 0x15, 0x00, 0x00, 0x8f, 0x30, 0x02, 0x48,
+	0xa0, 0x0c, 0x00, 0x00, 0x00, 0x18, 0xf0, 0xc8, 0x23, 0x14, 0x00, 0x00,
+	0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x6c, 0x00, 0x35, 0x00, 0x00,
+	0x88, 0x30, 0x04, 0x48, 0xa0, 0x2c, 0x00, 0x00, 0x00, 0x1c, 0x80, 0x08,
+	0x22, 0x34, 0x00, 0x00, 0x6f, 0xba, 0x23, 0x32, 0x8a, 0x00, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x47, 0x05, 0x42, 0x71,
+	0x00, 0x35, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x84, 0x7f, 0x40, 0x00, 0x40, 0x07, 0x00, 0x00, 0x8d, 0x7f, 0x08, 0x00,
+	0x40, 0x07, 0x00, 0x00, 0x87, 0x7f, 0x18, 0x00, 0x40, 0x27, 0x00, 0x00,
+	0x84, 0x34, 0x02, 0x00, 0x00, 0x14, 0x00, 0x00, 0x80, 0xbc, 0x07, 0xa0,
+	0x25, 0x21, 0x00, 0x00, 0x8b, 0x7f, 0x10, 0x00, 0x40, 0x07, 0x00, 0x00,
+	0x97, 0x7f, 0x50, 0x00, 0x40, 0x07, 0x00, 0x00, 0x95, 0x7f, 0x58, 0x00,
+	0x40, 0x07, 0x00, 0x00, 0x93, 0x7f, 0x60, 0x00, 0x40, 0x27, 0x00, 0x00,
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+	0x32, 0x08, 0x1e, 0x33, 0x00, 0x22, 0x00, 0x00, 0x22, 0x18, 0x60, 0x5d,
+	0x1c, 0x35, 0x00, 0x00, 0xda, 0x01, 0xac, 0x25, 0x00, 0x02, 0x00, 0x00,
+	0x00, 0x04, 0xa0, 0x35, 0x50, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x0b, 0x00, 0x40, 0x38, 0x00, 0x23, 0x00, 0x00,
+	0x01, 0x40, 0x00, 0x00, 0x78, 0x12, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00,
+	0x5c, 0x12, 0x00, 0x00, 0x80, 0x42, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x80, 0x16, 0x00, 0xa0, 0x83, 0x01, 0x00, 0x00, 0x0b, 0x07, 0x00, 0x00,
+	0x08, 0x32, 0x00, 0x00, 0x8b, 0x06, 0x00, 0x80, 0x08, 0x12, 0x00, 0x00,
+	0x83, 0x00, 0x00, 0x20, 0x02, 0x23, 0x00, 0x00, 0x00, 0x7c, 0x43, 0x20,
+	0x04, 0x14, 0x00, 0x00, 0x86, 0x11, 0x08, 0x30, 0x8a, 0x01, 0x00, 0x00,
+	0x07, 0x00, 0x9c, 0x10, 0xe6, 0x0b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
+	0xff, 0x13, 0x00, 0x00, 0x83, 0x08, 0x0e, 0x2e, 0x00, 0x2f, 0x00, 0x00,
+	0x83, 0x08, 0x1e, 0xa0, 0x00, 0x2e, 0x00, 0x00, 0x00, 0x84, 0x35, 0x02,
+	0x00, 0x16, 0x00, 0x00, 0x74, 0x10, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x83, 0x0c, 0x02, 0x28, 0x04, 0x34, 0x00, 0x00, 0x83, 0x00, 0x0a, 0x30,
+	0x00, 0x01, 0x00, 0x00, 0x15, 0x0a, 0x60, 0x7f, 0x1c, 0x15, 0x00, 0x00,
+	0x74, 0x0d, 0x42, 0x17, 0x00, 0x2c, 0x00, 0x00, 0x2b, 0xaf, 0x3c, 0x18,
+	0x60, 0x0c, 0x00, 0x00, 0xda, 0x0a, 0x0e, 0x2e, 0x00, 0x0f, 0x00, 0x00,
+	0x00, 0x1c, 0x00, 0x00, 0x3c, 0x16, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00,
+	0x00, 0x02, 0x00, 0x00, 0xda, 0x0a, 0x1e, 0xa0, 0x00, 0x0e, 0x00, 0x00,
+	0x58, 0xa0, 0x22, 0x83, 0xe0, 0x20, 0x00, 0x00, 0x22, 0x18, 0x60, 0x87,
+	0x1c, 0x15, 0x00, 0x00, 0x31, 0x07, 0xa0, 0x1d, 0xc0, 0x21, 0x00, 0x00,
+	0x5a, 0x07, 0xa0, 0x25, 0x00, 0x03, 0x00, 0x00, 0x0b, 0x00, 0x40, 0x38,
+	0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x36, 0x00, 0x00,
+	0x10, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x40, 0x00, 0x00,
+	0x78, 0x12, 0x00, 0x00, 0x10, 0x08, 0x0c, 0xc0, 0x03, 0x2e, 0x00, 0x00,
+	0x00, 0x40, 0x04, 0xec, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x22, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00, 0x5c, 0x12, 0x00, 0x00,
+	0x8b, 0x0a, 0x00, 0x80, 0x08, 0x12, 0x00, 0x00, 0x05, 0x00, 0x30, 0x08,
+	0x00, 0x23, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x50, 0x2d, 0x00, 0x00,
+	0x07, 0x00, 0x9c, 0x10, 0xe6, 0x0b, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
+	0xff, 0x13, 0x00, 0x00
+};
+
+static const uint8_t xsem_int_table_data_e1h[] = {
+	0x3e, 0x2b, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x53, 0x29, 0x00, 0x00, 0x8a, 0x1b, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x88, 0x18, 0x00, 0x00,
+	0xd2, 0x18, 0x00, 0x00, 0xf4, 0x18, 0x00, 0x00, 0x69, 0x1b, 0x00, 0x00,
+	0x4a, 0x19, 0x00, 0x00, 0x4b, 0x19, 0x00, 0x00, 0xb6, 0x19, 0x00, 0x00,
+	0xb7, 0x19, 0x00, 0x00, 0x17, 0x1a, 0x00, 0x00, 0x50, 0x1a, 0x00, 0x00,
+	0x51, 0x1a, 0x00, 0x00, 0x8e, 0x19, 0x00, 0x00, 0x8f, 0x19, 0x00, 0x00,
+	0x67, 0x19, 0x00, 0x00, 0x62, 0x1b, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x6b, 0x11, 0x00, 0x00, 0x6d, 0x11, 0x00, 0x00, 0x6f, 0x11, 0x00, 0x00,
+	0x71, 0x11, 0x00, 0x00, 0x12, 0x10, 0x00, 0x00, 0x13, 0x10, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x73, 0x21, 0x00, 0x00, 0xeb, 0x25, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x2a, 0x26, 0x00, 0x00,
+	0x63, 0x28, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x51, 0x3d, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xda, 0x3d, 0x00, 0x00, 0xa7, 0x46, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0x18, 0x46, 0x00, 0x00,
+	0xa8, 0x46, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xa9, 0x46, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xaa, 0x46, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xab, 0x46, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xac, 0x46, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x70, 0x3c, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xb5, 0x35, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xbd, 0x37, 0x00, 0x00,
+	0xf0, 0x3c, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xb6, 0x35, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x20, 0x3d, 0x00, 0x00, 0x21, 0x3d, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xa4, 0x01, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0x91, 0x02, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00,
+	0xf8, 0x7f, 0x00, 0x00, 0x0f, 0x02, 0x00, 0x00, 0xf8, 0x7f, 0x00, 0x00
+};
+
+static const uint8_t xsem_pram_data_e1h[] = {
+	0x05, 0x02, 0x0d, 0x00, 0x14, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x2e, 0x11, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x2e, 0x11, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x61, 0x08, 0x00, 0x80,
+	0x0b, 0x0f, 0x00, 0x00, 0x11, 0x84, 0x01, 0x00, 0x00, 0x34, 0x00, 0x00,
+	0x66, 0x7c, 0x03, 0xa0, 0x47, 0x01, 0x00, 0x00, 0x17, 0x84, 0x61, 0xc6,
+	0x00, 0x34, 0x00, 0x00, 0x62, 0x78, 0x07, 0x20, 0x07, 0x21, 0x00, 0x00,
+	0xc1, 0x79, 0x07, 0x0d, 0x34, 0x34, 0x00, 0x00, 0xe6, 0x8d, 0x03, 0x30,
+	0x07, 0x00, 0x00, 0x00, 0x45, 0x03, 0x0c, 0x0d, 0x34, 0x34, 0x00, 0x00,
+	0x5e, 0x8c, 0x05, 0x30, 0x07, 0x20, 0x00, 0x00, 0xe6, 0x89, 0xf1, 0xc4,
+	0x13, 0x34, 0x00, 0x00, 0xe6, 0x85, 0x01, 0x30, 0x00, 0x20, 0x00, 0x00,
+	0x00, 0x00, 0x71, 0x00, 0x00, 0x36, 0x00, 0x00, 0x72, 0x08, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x5e, 0x24, 0xe0, 0x84, 0x13, 0x34, 0x00, 0x00,
+	0xde, 0x88, 0x01, 0x30, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x0c,
+	0x31, 0x36, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+	0x5f, 0x79, 0x03, 0x06, 0x00, 0x02, 0x00, 0x00, 0x64, 0x98, 0x67, 0x4c,
+	0x00, 0x2e, 0x00, 0x00, 0x63, 0x90, 0x07, 0x00, 0x00, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00,
+	0x00, 0x16, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x61, 0x88, 0x07, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x50, 0x00, 0x8c, 0xf1, 0x03, 0x2e, 0x00, 0x00,
+	0x5f, 0x80, 0x07, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x50, 0x98, 0x47, 0xe7, 0x00, 0x0e, 0x00, 0x00,
+	0x50, 0x00, 0x06, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x21, 0x00, 0x00, 0xd1, 0x00, 0x00, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0x26, 0x00, 0x0d, 0x14, 0xe6, 0x0b, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30,
+	0xff, 0x03, 0x00, 0x00, 0x00, 0x44, 0x13, 0x00, 0x00, 0x19, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x51, 0x00, 0x00, 0x05,
+	0x00, 0x23, 0x00, 0x00, 0xd1, 0x35, 0x27, 0x05, 0x00, 0x22, 0x00, 0x00,
+	0x5e, 0x08, 0x00, 0x80, 0x0b, 0x0f, 0x00, 0x00, 0x11, 0x78, 0x01, 0x00,
+	0x00, 0x34, 0x00, 0x00, 0x5e, 0x4c, 0x01, 0xa0, 0x47, 0x01, 0x00, 0x00,
+	0x5e, 0x0c, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0xde, 0x51, 0x01, 0xa0,
+	0x82, 0x21, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x42, 0x32, 0x00, 0x00,
+	0x51, 0x0c, 0x00, 0x00, 0x16, 0x12, 0x00, 0x00, 0x51, 0x14, 0x00, 0x40,
+	0x17, 0x12, 0x00, 0x00, 0x50, 0x08, 0x00, 0xc0, 0x0b, 0x2e, 0x00, 0x00,
+	0x51, 0x78, 0x27, 0xe5, 0x00, 0x2e, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00,
+	0x00, 0x19, 0x00, 0x00, 0x51, 0x00, 0x00, 0xc0, 0x0e, 0x12, 0x00, 0x00,
+	0x55, 0x00, 0x60, 0x05, 0x00, 0x03, 0x00, 0x00, 0x57, 0x00, 0x80, 0x05,
+	0x00, 0x03, 0x00, 0x00, 0x59, 0x00, 0xa0, 0x05, 0x00, 0x03, 0x00, 0x00,
+	0x5b, 0x00, 0xc0, 0x05, 0x00, 0x23, 0x00, 0x00, 0x5d, 0x00, 0xf0, 0x1e,
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+	0xd6, 0x2a, 0x02, 0x68, 0xb0, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x63, 0x46, 0x01, 0x00, 0x00, 0x35, 0x00, 0x00,
+	0x64, 0x46, 0x01, 0x00, 0x00, 0x15, 0x00, 0x00, 0x3c, 0x83, 0x00, 0x5f,
+	0x50, 0x2c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x64, 0x46, 0x02, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0xca, 0x00, 0x90, 0x04, 0x00, 0x23, 0x00, 0x00,
+	0xc6, 0x02, 0x60, 0x5c, 0x00, 0x23, 0x00, 0x00, 0x46, 0x0e, 0x80, 0x04,
+	0x00, 0x03, 0x00, 0x00, 0xca, 0x02, 0xa0, 0x34, 0x00, 0x03, 0x00, 0x00,
+	0xf3, 0x40, 0x60, 0x5c, 0x46, 0x35, 0x00, 0x00, 0xcb, 0x02, 0xb0, 0x74,
+	0x00, 0x23, 0x00, 0x00, 0x00, 0x90, 0x61, 0x34, 0x50, 0x2d, 0x00, 0x00,
+	0xb9, 0x40, 0x40, 0x5d, 0x46, 0x15, 0x00, 0x00, 0xbf, 0x3f, 0x40, 0x5e,
+	0x46, 0x35, 0x00, 0x00, 0x00, 0x0c, 0x12, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00, 0x64, 0x46, 0x00, 0x00,
+	0x00, 0x35, 0x00, 0x00, 0xa6, 0x7f, 0x00, 0x6b, 0xe4, 0x05, 0x00, 0x00,
+	0xa8, 0x7f, 0x08, 0x6b, 0xe4, 0x05, 0x00, 0x00, 0x26, 0x04, 0xa0, 0x11,
+	0x10, 0x2c, 0x00, 0x00, 0x1a, 0x7d, 0xa0, 0x11, 0x50, 0x2c, 0x00, 0x00,
+	0x1a, 0xa1, 0xf0, 0x09, 0x20, 0x2c, 0x00, 0x00, 0x9f, 0x80, 0xf0, 0x09,
+	0x10, 0x0c, 0x00, 0x00, 0x9f, 0x7c, 0xf0, 0x09, 0x50, 0x2c, 0x00, 0x00,
+	0x9f, 0x40, 0x00, 0x48, 0xb0, 0x0c, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xa1, 0x46, 0x03, 0x00, 0x00, 0x35, 0x00, 0x00, 0x26, 0x3c, 0xf0, 0x11,
+	0x50, 0x2c, 0x00, 0x00, 0x1f, 0x15, 0x00, 0x00, 0xd0, 0x2c, 0x00, 0x00,
+	0x00, 0x04, 0xf0, 0x11, 0x00, 0x2c, 0x00, 0x00, 0x26, 0x68, 0xe4, 0x86,
+	0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x36, 0x00, 0x00,
+	0x1f, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x7d, 0x22, 0xb8,
+	0xe0, 0x14, 0x00, 0x00, 0x1f, 0x99, 0x0f, 0x30, 0x00, 0x20, 0x00, 0x00,
+	0x00, 0x44, 0x14, 0x00, 0x00, 0x36, 0x00, 0x00, 0x6a, 0x08, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x00, 0x6a, 0x7d, 0x64, 0xb6, 0xb5, 0x20, 0x00, 0x00,
+	0x27, 0x98, 0x00, 0x6b, 0xe4, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x00, 0x29, 0xa0, 0x08, 0x6b, 0xe4, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xf2,
+	0xe0, 0x08, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0xff, 0x23, 0x00, 0x00,
+	0x00, 0xa8, 0x05, 0xf2, 0xe0, 0x08, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00,
+	0xff, 0x22, 0x00, 0x00, 0x6d, 0x00, 0x01, 0x00, 0x78, 0x12, 0x00, 0x00,
+	0x1a, 0x05, 0x0c, 0x88, 0x01, 0x0f, 0x00, 0x00, 0x6d, 0x00, 0x00, 0x00,
+	0x5c, 0x32, 0x00, 0x00, 0x6d, 0x68, 0xc4, 0xf9, 0x01, 0x2e, 0x00, 0x00,
+	0x6d, 0x00, 0x04, 0xf2, 0xe0, 0x28, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
+	0xff, 0x01, 0x00, 0x00, 0x00, 0xb8, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0xff, 0x02, 0x00, 0x00, 0x67, 0x58, 0x81, 0xc6,
+	0x15, 0x20, 0x00, 0x00, 0x67, 0x98, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x69, 0x60, 0xb1, 0x86,
+	0x16, 0x00, 0x00, 0x00, 0x69, 0xa0, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x6a, 0x64, 0xc1, 0xc6,
+	0x16, 0x20, 0x00, 0x00, 0x6b, 0xa8, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x6d, 0x70, 0xf1, 0x86,
+	0x17, 0x00, 0x00, 0x00, 0x6d, 0xb0, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x5d, 0x74, 0xe1, 0x06,
+	0x60, 0x2c, 0x00, 0x00, 0x6f, 0xb8, 0x05, 0xf2, 0xe0, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xbf, 0x3f, 0x40, 0x9a,
+	0x46, 0x15, 0x00, 0x00, 0x00, 0x0c, 0x12, 0x00, 0x00, 0x39, 0x00, 0x00,
+	0xc5, 0x05, 0xb0, 0x29, 0x01, 0x34, 0x00, 0x00, 0xc5, 0x6d, 0x0a, 0x30,
+	0x80, 0x21, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x71, 0x00, 0x34, 0x00, 0x00,
+	0xa2, 0x6c, 0x0c, 0x30, 0x8a, 0x21, 0x00, 0x00, 0xa3, 0x92, 0x42, 0x34,
+	0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0xbf, 0x3f, 0x40, 0xa2, 0x46, 0x35, 0x00, 0x00, 0x00, 0x0c, 0x12, 0x00,
+	0x00, 0x39, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x15, 0x00, 0x00,
+	0x80, 0x42, 0x00, 0x28, 0x70, 0x0c, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28,
+	0x70, 0x0c, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28, 0x70, 0x0c, 0x00, 0x00,
+	0x80, 0x42, 0x00, 0x28, 0x70, 0x0c, 0x00, 0x00, 0x80, 0x42, 0x00, 0x28,
+	0x70, 0x0c, 0x00, 0x00, 0xee, 0x7f, 0xc0, 0x6a, 0xe4, 0x25, 0x00, 0x00,
+	0x44, 0x0a, 0x0e, 0x2e, 0x00, 0x2f, 0x00, 0x00, 0x44, 0x06, 0x00, 0x80,
+	0x02, 0x14, 0x00, 0x00, 0x00, 0x4a, 0x0d, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x6f, 0xbc, 0x01, 0x00, 0x00, 0x14, 0x00, 0x00, 0x6e, 0x64, 0x10, 0xa0,
+	0x03, 0x01, 0x00, 0x00, 0x1b, 0x6e, 0x08, 0x28, 0x04, 0x34, 0x00, 0x00,
+	0x45, 0x03, 0x0a, 0x30, 0x03, 0x01, 0x00, 0x00, 0x6e, 0x04, 0x00, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x00, 0x48, 0x03, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x00, 0x04, 0xb0, 0xc0, 0x02, 0x34, 0x00, 0x00, 0xd2, 0x4e, 0x11, 0x30,
+	0x8a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x34, 0x00, 0x00,
+	0xd2, 0x12, 0x2d, 0xa0, 0x8a, 0x01, 0x00, 0x00, 0x16, 0x83, 0x00, 0x80,
+	0x00, 0x34, 0x00, 0x00, 0xf0, 0x15, 0x07, 0xa0, 0xa2, 0x01, 0x00, 0x00,
+	0x45, 0x02, 0x50, 0x6c, 0xa7, 0x01, 0x00, 0x00, 0xc4, 0x02, 0x70, 0x01,
+	0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0xc0, 0x01, 0x00, 0x23, 0x00, 0x00,
+	0x9d, 0x00, 0x90, 0x01, 0x00, 0x03, 0x00, 0x00, 0x3d, 0x3f, 0x22, 0x00,
+	0x00, 0x15, 0x00, 0x00, 0x6f, 0x06, 0xb0, 0x01, 0x00, 0x03, 0x00, 0x00,
+	0x00, 0x04, 0x20, 0x35, 0x52, 0x0d, 0x00, 0x00, 0x03, 0x08, 0x53, 0x2c,
+	0xe4, 0x33, 0x00, 0x00, 0x94, 0x89, 0xa0, 0xb1, 0xb4, 0x21, 0x00, 0x00,
+	0x83, 0x01, 0xa0, 0x99, 0x66, 0x14, 0x00, 0x00, 0x80, 0x55, 0x0c, 0x30,
+	0xa5, 0x20, 0x00, 0x00, 0xef, 0xa0, 0x02, 0x80, 0x05, 0x2f, 0x00, 0x00,
+	0x94, 0x11, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x94, 0x59, 0x26, 0xa0,
+	0x80, 0x01, 0x00, 0x00, 0xef, 0x00, 0x50, 0x5c, 0x71, 0x34, 0x00, 0x00,
+	0x80, 0x58, 0x0a, 0x30, 0xa5, 0x00, 0x00, 0x00, 0x94, 0x11, 0x20, 0x8d,
+	0x34, 0x34, 0x00, 0x00, 0x94, 0x69, 0x2a, 0x30, 0x80, 0x20, 0x00, 0x00,
+	0xb6, 0xfe, 0x43, 0x24, 0x91, 0x14, 0x00, 0x00, 0xf0, 0x51, 0x08, 0x30,
+	0xa2, 0x20, 0x00, 0x00, 0x94, 0x31, 0x20, 0x81, 0x04, 0x14, 0x00, 0x00,
+	0x94, 0x7d, 0x20, 0x30, 0x80, 0x20, 0x00, 0x00, 0xbb, 0x01, 0x00, 0x00,
+	0x00, 0x34, 0x00, 0x00, 0x80, 0x8d, 0x0d, 0xa0, 0xa5, 0x21, 0x00, 0x00,
+	0x94, 0x51, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x94, 0x69, 0x12, 0xa0,
+	0x80, 0x21, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f, 0x00, 0x00,
+	0x94, 0xa1, 0x40, 0x19, 0x12, 0x0c, 0x00, 0x00, 0x3f, 0x1d, 0x60, 0xdb,
+	0x46, 0x15, 0x00, 0x00, 0x1a, 0x03, 0x00, 0x70, 0xb0, 0x2c, 0x00, 0x00,
+	0x94, 0x21, 0x40, 0x19, 0x12, 0x2c, 0x00, 0x00, 0x96, 0x01, 0x50, 0x59,
+	0x65, 0x34, 0x00, 0x00, 0x80, 0x2d, 0x0c, 0x30, 0xa5, 0x20, 0x00, 0x00,
+	0x3d, 0x3f, 0x20, 0x00, 0x00, 0x35, 0x00, 0x00, 0xc5, 0x59, 0x2a, 0x8d,
+	0xa6, 0x20, 0x00, 0x00, 0x00, 0x04, 0x00, 0xc0, 0x01, 0x14, 0x00, 0x00,
+	0x6f, 0x4a, 0x0d, 0xa2, 0x8a, 0x21, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x3f, 0x00, 0x00
+};
+
+#endif /*__BXE_INIT_VALUES_E1H_H__*/
diff --git a/sys/dev/bxe/bxe_link.c b/sys/dev/bxe/bxe_link.c
new file mode 100755
index 0000000..6ee29a8
--- /dev/null
+++ b/sys/dev/bxe/bxe_link.c
@@ -0,0 +1,6162 @@
+/*-
+ * Copyright (c) 2007-2010 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_bxe.h"
+#include "bxe_include.h"
+#include "if_bxe.h"
+
+void bxe_write_dmae(struct bxe_softc *, bus_addr_t, uint32_t, uint32_t);
+void bxe_read_dmae(struct bxe_softc *, uint32_t, uint32_t);
+int bxe_set_gpio(struct bxe_softc *, int, uint32_t, uint8_t);
+int bxe_get_gpio(struct bxe_softc *, int, uint8_t);
+int bxe_set_spio(struct bxe_softc *, int, uint32_t);
+int bxe_set_gpio_int(struct bxe_softc *, int, uint32_t, uint8_t);
+int bxe_fw_command(struct bxe_softc *, uint32_t);
+
+#ifdef BXE_DEBUG
+extern uint32_t
+bxe_reg_read32	(struct bxe_softc *, bus_size_t);
+extern void
+bxe_reg_write32	(struct bxe_softc *, bus_size_t, uint32_t);
+#endif
+
+#undef msleep
+#define msleep(m) DELAY(m * 1000)
+
+#define	EMAC_RX_MODE_KEEP_MAC_CONTROL	(1L<<3)
+#define	EMAC_RX_MODE_KEEP_VLAN_TAG		(1L<<10)
+#define	MDIO_PMA_REG_8481_LED1_MASK		0xa82c
+#define	MDIO_PMA_REG_8481_LED2_MASK		0xa82f
+#define	MDIO_PMA_REG_8481_LED3_MASK		0xa832
+/*
+ * [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
+ * logic for interrupts must be used. Enable per bit of interrupt of
+ * ~latch_status.latch_status.
+ */
+#define	NIG_REG_LATCH_BC_0					0x16210
+/*
+ * [RW 27] Latch for each interrupt from Unicore.b[0]
+ * status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
+ * b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
+ * b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
+ * b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
+ * b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
+ * b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
+ * b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
+ * b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
+ * b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
+ * b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
+ * b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
+ * b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs
+ */
+#define	NIG_REG_LATCH_STATUS_0					0x18000
+
+#define	ETH_HLEN			14
+#define	ETH_OVREHEAD			(ETH_HLEN + 8)/* 8 for CRC + VLAN*/
+#define	ETH_MIN_PACKET_SIZE		60
+#define	ETH_MAX_PACKET_SIZE		1500
+#define	ETH_MAX_JUMBO_PACKET_SIZE	9600
+#define	MDIO_ACCESS_TIMEOUT		1000
+#define	BMAC_CONTROL_RX_ENABLE		2
+
+struct bxe_image_header {
+	uint32_t	magic;
+#define	FILE_MAGIC			0x669955aa
+	uint32_t	version;
+#define	FORMAT_VERSION_2		0x2
+	uint32_t	type;
+#define	IMAGE_HDR_TYPE_BCM8073		0x33373038
+#define	IMAGE_HDR_TYPE_BCM8726		0x36323738
+#define	IMAGE_HDR_TYPE_BCM8727		0x37323738
+#define	IMAGE_HDR_TYPE_BCM8481		0x31383438
+#define	IMAGE_HDR_TYPE_SFX7101		0x68706673
+	uint32_t	image_info;
+	uint32_t	byte_cnt;
+};
+
+/*
+ * Shortcut definitions
+ */
+
+#define	NIG_LATCH_BC_ENABLE_MI_INT		0
+
+#define	NIG_STATUS_EMAC0_MI_INT			\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
+#define	NIG_STATUS_XGXS0_LINK10G		\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
+#define	NIG_STATUS_XGXS0_LINK_STATUS		\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
+#define	NIG_STATUS_XGXS0_LINK_STATUS_SIZE	\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
+#define	NIG_STATUS_SERDES0_LINK_STATUS		\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
+#define	NIG_MASK_MI_INT				\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
+#define	NIG_MASK_XGXS0_LINK10G			\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
+#define	NIG_MASK_XGXS0_LINK_STATUS		\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
+#define	NIG_MASK_SERDES0_LINK_STATUS		\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
+
+#define	MDIO_AN_CL73_OR_37_COMPLETE					\
+	(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |		\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
+
+#define	XGXS_RESET_BITS							\
+	(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |		\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |		\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
+
+#define	SERDES_RESET_BITS						\
+	(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |		\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
+
+#define	AUTONEG_CL37		SHARED_HW_CFG_AN_ENABLE_CL37
+#define	AUTONEG_CL73		SHARED_HW_CFG_AN_ENABLE_CL73
+#define	AUTONEG_BAM 		SHARED_HW_CFG_AN_ENABLE_BAM
+#define	AUTONEG_PARALLEL	SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
+#define	AUTONEG_SGMII_FIBER_AUTODET	\
+	SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
+#define	AUTONEG_REMOTE_PHY  	SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
+
+#define	GP_STATUS_PAUSE_RSOLUTION_TXSIDE	\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
+#define	GP_STATUS_PAUSE_RSOLUTION_RXSIDE	\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
+#define	GP_STATUS_SPEED_MASK		\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
+#define	GP_STATUS_10M		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
+#define	GP_STATUS_100M		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
+#define	GP_STATUS_1G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
+#define	GP_STATUS_2_5G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
+#define	GP_STATUS_5G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
+#define	GP_STATUS_6G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
+#define	GP_STATUS_10G_HIG	\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
+#define	GP_STATUS_10G_CX4	\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
+#define	GP_STATUS_12G_HIG	\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
+#define	GP_STATUS_12_5G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
+#define	GP_STATUS_13G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
+#define	GP_STATUS_15G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
+#define	GP_STATUS_16G		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
+#define	GP_STATUS_1G_KX		MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
+#define	GP_STATUS_10G_KX4	\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
+
+#define	LINK_10THD  		LINK_STATUS_SPEED_AND_DUPLEX_10THD
+#define	LINK_10TFD  		LINK_STATUS_SPEED_AND_DUPLEX_10TFD
+#define	LINK_100TXHD		LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
+#define	LINK_100T4  		LINK_STATUS_SPEED_AND_DUPLEX_100T4
+#define	LINK_100TXFD		LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
+#define	LINK_1000THD		LINK_STATUS_SPEED_AND_DUPLEX_1000THD
+#define	LINK_1000TFD		LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
+#define	LINK_1000XFD		LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
+#define	LINK_2500THD		LINK_STATUS_SPEED_AND_DUPLEX_2500THD
+#define	LINK_2500TFD		LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
+#define	LINK_2500XFD		LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
+#define	LINK_10GTFD 		LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
+#define	LINK_10GXFD 		LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
+#define	LINK_12GTFD 		LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
+#define	LINK_12GXFD 		LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
+#define	LINK_12_5GTFD		LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
+#define	LINK_12_5GXFD		LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
+#define	LINK_13GTFD 		LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
+#define	LINK_13GXFD 		LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
+#define	LINK_15GTFD 		LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
+#define	LINK_15GXFD 		LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
+#define	LINK_16GTFD 		LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
+#define	LINK_16GXFD 		LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
+
+#define	PHY_XGXS_FLAG				0x1
+#define	PHY_SGMII_FLAG				0x2
+#define	PHY_SERDES_FLAG				0x4
+
+#define	SFP_EEPROM_CON_TYPE_ADDR		0x2
+#define	SFP_EEPROM_CON_TYPE_VAL_LC		0x7
+#define	SFP_EEPROM_CON_TYPE_VAL_COPPER		0x21
+
+#define	SFP_EEPROM_COMP_CODE_ADDR		0x3
+#define	SFP_EEPROM_COMP_CODE_SR_MASK		(1 << 4)
+#define	SFP_EEPROM_COMP_CODE_LR_MASK		(1 << 5)
+#define	SFP_EEPROM_COMP_CODE_LRM_MASK		(1 << 6)
+
+#define	SFP_EEPROM_FC_TX_TECH_ADDR		0x8
+#define	SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE	0x4
+#define	SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE	0x8
+
+#define	SFP_EEPROM_OPTIONS_ADDR 		0x40
+#define	SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK	0x1
+#define	SFP_EEPROM_OPTIONS_SIZE 		2
+
+#define	EDC_MODE_LINEAR				0x0022
+#define	EDC_MODE_LIMITING			0x0044
+#define	EDC_MODE_PASSIVE_DAC			0x0055
+
+/*
+ * 8073 Download definitions.
+ */
+/* spi Parameters.*/
+#define	SPI_CTRL_1_L	0xC000
+#define	SPI_CTRL_1_H	0xC002
+#define	SPI_CTRL_2_L	0xC400
+#define	SPI_CTRL_2_H	0xC402
+#define	SPI_TXFIFO	0xD000
+#define	SPI_RXFIFO	0xD400
+
+/* Input Command Messages.*/
+/*
+ * Write CPU/SPI Control Regs, followed by Count And
+ * CPU/SPI Controller Reg add/data pairs.
+ */
+#define	WR_CPU_CTRL_REGS	0x11
+/*
+ * Read CPU/SPI Control Regs, followed by Count and
+ * CPU/SPI Controller Register Add.
+ */
+#define	RD_CPU_CTRL_REGS	0xEE
+/*
+ * Write CPU/SPI Control Regs Continously, followed by
+ * Count and CPU/SPI Controller Reg addr and data's.
+ */
+#define	WR_CPU_CTRL_FIFO	0x66
+/* Output Command Messages.*/
+#define	DONE			0x4321
+
+/* SPI Controller Commands (known As messages).*/
+#define	MSGTYPE_HWR		0x40
+#define	MSGTYPE_HRD		0x80
+#define	WRSR_OPCODE		0x01
+#define	WR_OPCODE		0x02
+#define	RD_OPCODE		0x03
+#define	WRDI_OPCODE		0x04
+#define	RDSR_OPCODE		0x05
+#define	WREN_OPCODE		0x06
+#define	WR_BLOCK_SIZE		0x40 /* Maximum 64 Bytes Writes.*/
+
+#define	BUF_SIZE_BCM		0x4000 /* Code Size is 16k bytes.*/
+#define	UPGRADE_TIMEOUT_BCM	1000
+
+/*
+ * INTERFACE
+ */
+#define	CL45_WR_OVER_CL22(_sc, _port, _phy_addr, _bank, _addr, _val)	\
+	bxe_cl45_write(_sc, _port, 0, _phy_addr, DEFAULT_PHY_DEV_ADDR,	\
+	(_bank + (_addr & 0xf)), _val)
+
+#define	CL45_RD_OVER_CL22(_sc, _port, _phy_addr, _bank, _addr, _val)	\
+	bxe_cl45_read(_sc, _port, 0, _phy_addr, DEFAULT_PHY_DEV_ADDR,	\
+	(_bank + (_addr & 0xf)), _val)
+
+static void
+bxe_set_serdes_access(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t emac_base;
+
+	sc = params->sc;
+	emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+	/* Set Clause 22 */
+	REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + params->port * 0x10, 1);
+	REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
+	DELAY(500);
+	REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
+	DELAY(500);
+	 /* Set Clause 45 */
+	REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + params->port * 0x10, 0);
+}
+
+static void
+bxe_set_phy_mdio(struct link_params *params, uint8_t phy_flags)
+{
+	struct bxe_softc *sc;
+
+	sc = params->sc;
+	if (phy_flags & PHY_XGXS_FLAG) {
+		REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0);
+		REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18,
+		    DEFAULT_PHY_DEV_ADDR);
+	} else {
+		bxe_set_serdes_access(params);
+
+		REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + params->port * 0x10,
+		    DEFAULT_PHY_DEV_ADDR);
+	}
+}
+
+static uint32_t
+bxe_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
+{
+	uint32_t val;
+
+	val = REG_RD(sc, reg);
+	val |= bits;
+	REG_WR(sc, reg, val);
+	return (val);
+}
+
+static uint32_t
+bxe_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
+{
+	uint32_t val;
+
+	val = REG_RD(sc, reg);
+	val &= ~bits;
+	REG_WR(sc, reg, val);
+	return (val);
+}
+
+static void
+bxe_emac_init(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t emac_base, val;
+	uint16_t timeout;
+	uint8_t port;
+
+	/* reset and unreset the emac core */
+	sc = params->sc;
+	port = params->port;
+	emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+	    (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
+	DELAY(5);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+	    (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
+
+	/* Init emac - use read-modify-write. */
+	/* self clear reset */
+	val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
+	EMAC_WR(sc, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
+
+	timeout = 200;
+	do {
+		val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
+		DBPRINT(sc, BXE_VERBOSE_PHY, "EMAC reset reg is %u\n", val);
+		if (!timeout) {
+			DBPRINT(sc, BXE_VERBOSE_PHY, "EMAC timeout!\n");
+			return;
+		}
+		timeout--;
+	} while (val & EMAC_MODE_RESET);
+
+	/* Set mac address. */
+	val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+	EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH, val);
+
+	val = ((params->mac_addr[2] << 24) | (params->mac_addr[3] << 16) |
+	    (params->mac_addr[4] << 8) | params->mac_addr[5]);
+	EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + 4, val);
+}
+
+static uint8_t
+bxe_emac_enable(struct link_params *params, struct link_vars *vars, uint8_t lb)
+{
+	struct bxe_softc *sc;
+	uint32_t emac_base, ser_lane, val;
+	uint8_t port;
+
+	sc = params->sc;
+	DBPRINT(sc, BXE_VERBOSE_PHY, "enabling EMAC\n");
+
+	port = params->port;
+	emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+	/* enable emac and not bmac */
+	REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
+
+	if (vars->phy_flags & PHY_XGXS_FLAG) {
+		ser_lane = ((params->lane_config &
+		    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+		    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+		DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS\n");
+		/* select the master lanes (out of 0-3) */
+		REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
+		/* select XGXS */
+		REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
+
+	} else { /* SerDes */
+		DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes\n");
+		/* select SerDes */
+		REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
+	}
+
+	bxe_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE, EMAC_RX_MODE_RESET);
+	bxe_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET);
+
+	/* pause enable/disable */
+	bxe_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
+	    EMAC_RX_MODE_FLOW_EN);
+	if (vars->flow_ctrl & FLOW_CTRL_RX)
+		bxe_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
+		    EMAC_RX_MODE_FLOW_EN);
+
+	bxe_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+	    (EMAC_TX_MODE_EXT_PAUSE_EN | EMAC_TX_MODE_FLOW_EN));
+	if (vars->flow_ctrl & FLOW_CTRL_TX)
+		bxe_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+		    (EMAC_TX_MODE_EXT_PAUSE_EN | EMAC_TX_MODE_FLOW_EN));
+
+	/* KEEP_VLAN_TAG, promiscuous */
+	val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
+	val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
+
+	EMAC_WR(sc, EMAC_REG_EMAC_RX_MODE, val);
+
+	/* Set Loopback */
+	val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
+	if (lb)
+		val |= 0x810;
+	else
+		val &= ~0x810;
+	EMAC_WR(sc, EMAC_REG_EMAC_MODE, val);
+
+	/* enable emac */
+	REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1);
+
+	/* Enable emac for jumbo packets. */
+	EMAC_WR(sc, EMAC_REG_EMAC_RX_MTU_SIZE, (EMAC_RX_MTU_SIZE_JUMBO_ENA |
+	    (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
+
+	/* strip CRC */
+	REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
+
+	/* Disable the NIG in/out to the bmac. */
+	REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0);
+	REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0);
+	REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0);
+
+	/* Enable the NIG in/out to the emac. */
+	REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
+	val = 0;
+	if (vars->flow_ctrl & FLOW_CTRL_TX)
+		val = 1;
+
+	REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
+	REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
+
+	REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
+
+	vars->mac_type = MAC_TYPE_EMAC;
+	return (0);
+}
+
+static uint8_t
+bxe_bmac1_enable(struct link_params *params, struct link_vars *vars,
+    uint8_t is_lb)
+{
+	struct bxe_softc *sc;
+	uint32_t bmac_addr, wb_data[2], val;
+	uint8_t port;
+
+	sc = params->sc;
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Enabling BigMAC1\n");
+
+	port = params->port;
+	bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
+	    NIG_REG_INGRESS_BMAC0_MEM;
+
+	/* XGXS control */
+	wb_data[0] = 0x3c;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, wb_data,
+	    2);
+
+	/* tx MAC SA */
+	wb_data[0] = ((params->mac_addr[2] << 24) |
+	    (params->mac_addr[3] << 16) | (params->mac_addr[4] << 8) |
+	    params->mac_addr[5]);
+	wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
+
+	/* tx control */
+	val = 0xc0;
+	if (vars->flow_ctrl & FLOW_CTRL_TX)
+		val |= 0x800000;
+	wb_data[0] = val;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
+
+	/* mac control */
+	val = 0x3;
+	if (is_lb) {
+		val |= 0x4;
+		DBPRINT(sc, BXE_VERBOSE_PHY, "enable bmac loopback\n");
+	}
+	wb_data[0] = val;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
+
+	/* set rx mtu */
+	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
+
+	/* rx control set to don't strip crc */
+	val = 0x14;
+	if (vars->flow_ctrl & FLOW_CTRL_RX)
+		val |= 0x20;
+
+	wb_data[0] = val;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
+
+	/* set tx mtu */
+	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
+			wb_data, 2);
+
+	/* set cnt max size */
+	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
+
+	/* configure safc */
+	wb_data[0] = 0x1000200;
+	wb_data[1] = 0;
+	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, wb_data,
+	    2);
+
+	return (0);
+}
+
+static uint8_t
+bxe_bmac_enable(struct link_params *params, struct link_vars *vars,
+    uint8_t is_lb)
+{
+	struct bxe_softc *sc;
+	uint32_t val;
+	uint8_t rc, port;
+
+	sc = params->sc;
+	port = params->port;
+
+	/* reset and unreset the BigMac */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+	    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+	msleep(1);
+
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+	    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+	/* enable access for bmac registers */
+	REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
+
+	rc = bxe_bmac1_enable(params, vars, is_lb);
+
+	REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1);
+	REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0);
+	REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
+	val = 0;
+	if (vars->flow_ctrl & FLOW_CTRL_TX)
+		val = 1;
+	REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
+	REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0);
+	REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0);
+	REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0);
+	REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1);
+	REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1);
+
+	vars->mac_type = MAC_TYPE_BMAC;
+	return (rc);
+}
+
+static void
+bxe_phy_deassert(struct link_params *params, uint8_t phy_flags)
+{
+	struct bxe_softc *sc;
+	uint32_t val;
+
+	sc = params->sc;
+	if (phy_flags & PHY_XGXS_FLAG) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "bxe_phy_deassert:XGXS\n");
+		val = XGXS_RESET_BITS;
+
+	} else { /* SerDes */
+		DBPRINT(sc, BXE_VERBOSE_PHY, "bxe_phy_deassert:SerDes\n");
+		val = SERDES_RESET_BITS;
+	}
+
+	val = val << (params->port * 16);
+
+	/* reset and unreset the SerDes/XGXS */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
+	DELAY(500);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
+	bxe_set_phy_mdio(params, phy_flags);
+}
+
+void
+bxe_link_status_update(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint8_t link_10g, port;
+
+	sc = params->sc;
+	port = params->port;
+
+	if (params->switch_cfg == SWITCH_CFG_1G)
+		vars->phy_flags = PHY_SERDES_FLAG;
+	else
+		vars->phy_flags = PHY_XGXS_FLAG;
+	vars->link_status = REG_RD(sc, params->shmem_base +
+	    offsetof(struct shmem_region, port_mb[port].link_status));
+
+	vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
+
+	if (vars->link_up) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "phy link up\n");
+
+		vars->phy_link_up = 1;
+		vars->duplex = DUPLEX_FULL;
+		switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
+		case LINK_10THD:
+			vars->duplex = DUPLEX_HALF;
+			/* FALLTHROUGH */
+		case LINK_10TFD:
+			vars->line_speed = SPEED_10;
+			break;
+		case LINK_100TXHD:
+			vars->duplex = DUPLEX_HALF;
+			/* FALLTHROUGH */
+		case LINK_100T4:
+		case LINK_100TXFD:
+			vars->line_speed = SPEED_100;
+			break;
+		case LINK_1000THD:
+			vars->duplex = DUPLEX_HALF;
+			/* FALLTHROUGH */
+		case LINK_1000TFD:
+			vars->line_speed = SPEED_1000;
+			break;
+		case LINK_2500THD:
+			vars->duplex = DUPLEX_HALF;
+			/* FALLTHROUGH */
+		case LINK_2500TFD:
+			vars->line_speed = SPEED_2500;
+			break;
+		case LINK_10GTFD:
+			vars->line_speed = SPEED_10000;
+			break;
+		case LINK_12GTFD:
+			vars->line_speed = SPEED_12000;
+			break;
+		case LINK_12_5GTFD:
+			vars->line_speed = SPEED_12500;
+			break;
+		case LINK_13GTFD:
+			vars->line_speed = SPEED_13000;
+			break;
+		case LINK_15GTFD:
+			vars->line_speed = SPEED_15000;
+			break;
+		case LINK_16GTFD:
+			vars->line_speed = SPEED_16000;
+			break;
+		default:
+			break;
+		}
+
+		if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
+			vars->flow_ctrl |= FLOW_CTRL_TX;
+		else
+			vars->flow_ctrl &= ~FLOW_CTRL_TX;
+
+		if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
+			vars->flow_ctrl |= FLOW_CTRL_RX;
+		else
+			vars->flow_ctrl &= ~FLOW_CTRL_RX;
+
+		if (vars->phy_flags & PHY_XGXS_FLAG) {
+			if (vars->line_speed &&
+			    ((vars->line_speed == SPEED_10) ||
+			    (vars->line_speed == SPEED_100))) {
+				vars->phy_flags |= PHY_SGMII_FLAG;
+			} else
+				vars->phy_flags &= ~PHY_SGMII_FLAG;
+		}
+
+		/* Anything 10 and over uses the bmac. */
+		link_10g = ((vars->line_speed == SPEED_10000) ||
+		    (vars->line_speed == SPEED_12000) ||
+		    (vars->line_speed == SPEED_12500) ||
+		    (vars->line_speed == SPEED_13000) ||
+		    (vars->line_speed == SPEED_15000) ||
+		    (vars->line_speed == SPEED_16000));
+		if (link_10g)
+			vars->mac_type = MAC_TYPE_BMAC;
+		else
+			vars->mac_type = MAC_TYPE_EMAC;
+
+	} else {
+		/* link down */
+		DBPRINT(sc, BXE_VERBOSE_PHY, "phy link down\n");
+
+		vars->phy_link_up = 0;
+
+		vars->line_speed = 0;
+		vars->duplex = DUPLEX_FULL;
+		vars->flow_ctrl = FLOW_CTRL_NONE;
+
+		/* Indicate no mac active. */
+		vars->mac_type = MAC_TYPE_NONE;
+	}
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "link_status 0x%x phy_link_up %x\n",
+	    vars->link_status, vars->phy_link_up);
+	DBPRINT(sc, BXE_VERBOSE_PHY, "line_speed %x duplex %x flow_ctrl 0x%x\n",
+	    vars->line_speed, vars->duplex, vars->flow_ctrl);
+}
+
+static void
+bxe_update_mng(struct link_params *params, uint32_t link_status)
+{
+	struct bxe_softc *sc;
+
+	sc = params->sc;
+	REG_WR(sc, params->shmem_base + offsetof(struct shmem_region,
+	    port_mb[params->port].link_status), link_status);
+}
+
+static void
+bxe_bmac_rx_disable(struct bxe_softc *sc, uint32_t chip_id, uint8_t port)
+{
+	uint32_t bmac_addr, wb_data[2];
+	uint32_t nig_bmac_enable;
+
+	bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
+	    NIG_REG_INGRESS_BMAC0_MEM;
+	nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
+
+	/* Only if the bmac is out of reset */
+	if (REG_RD(sc, MISC_REG_RESET_REG_2) &
+	    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
+		REG_RD_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
+		    wb_data, 2);
+		wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
+		REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
+		    wb_data, 2);
+
+		msleep(1);
+	}
+}
+
+static uint8_t
+bxe_pbf_update(struct link_params *params, uint32_t flow_ctrl,
+    uint32_t line_speed)
+{
+	struct bxe_softc *sc;
+	uint32_t count, crd, init_crd;
+	uint32_t thresh;
+	uint8_t port;
+
+	sc = params->sc;
+	port = params->port;
+
+	/* Disable port. */
+	REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1);
+
+	/* Wait for init credit. */
+	init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
+	crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
+	DBPRINT(sc, BXE_VERBOSE_PHY, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
+
+	count = 1000;
+	while ((init_crd != crd) && count) {
+		msleep(5);
+
+		crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
+		count--;
+	}
+	crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
+	if (init_crd != crd) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "BUG! init_crd 0x%x != crd 0x%x\n",
+		    init_crd, crd);
+		return (-EINVAL);
+	}
+
+	if (flow_ctrl & FLOW_CTRL_RX || line_speed == SPEED_10 ||
+	    line_speed == SPEED_100 || line_speed == SPEED_1000 ||
+	    line_speed == SPEED_2500) {
+		REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
+		/* Update threshold. */
+		REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
+		/* Update init credit. */
+		init_crd = 778; 	/* (800-18-4) */
+	} else {
+		thresh = (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD) / 16;
+		REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
+		/* Update threshold. */
+		REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
+		/* Update init credit. */
+		switch (line_speed) {
+		case SPEED_10000:
+			init_crd = thresh + 553 - 22;
+			break;
+		case SPEED_12000:
+			init_crd = thresh + 664 - 22;
+			break;
+		case SPEED_13000:
+			init_crd = thresh + 742 - 22;
+			break;
+		case SPEED_16000:
+			init_crd = thresh + 778 - 22;
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Invalid line_speed 0x%x\n", line_speed);
+			return (-EINVAL);
+		}
+	}
+	REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
+	DBPRINT(sc, BXE_VERBOSE_PHY, "PBF updated to speed %d credit %d\n",
+	    line_speed, init_crd);
+
+	/* Probe the credit changes. */
+	REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
+	msleep(5);
+	REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0);
+
+	/* Enable port. */
+	REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0);
+	return (0);
+}
+
+static uint32_t
+bxe_get_emac_base(struct bxe_softc *sc, uint32_t ext_phy_type, uint8_t port)
+{
+	uint32_t emac_base;
+
+	switch (ext_phy_type) {
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+		/* All MDC/MDIO is directed through single EMAC. */
+		if (REG_RD(sc, NIG_REG_PORT_SWAP))
+			emac_base = GRCBASE_EMAC0;
+		else
+			emac_base = GRCBASE_EMAC1;
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+		emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
+		break;
+	default:
+		emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+		break;
+	}
+	return (emac_base);
+}
+
+uint8_t
+bxe_cl45_write(struct bxe_softc *sc, uint8_t port, uint32_t ext_phy_type,
+    uint8_t phy_addr, uint8_t devad, uint16_t reg, uint16_t val)
+{
+	uint32_t mdio_ctrl, saved_mode, tmp;
+	uint8_t i, rc;
+
+	rc = 0;
+	mdio_ctrl = bxe_get_emac_base(sc, ext_phy_type, port);
+
+	/*
+	 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
+	 * (a value of 49==0x31) and make sure that the AUTO poll is off.
+	 */
+
+	saved_mode = REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+	tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
+	    EMAC_MDIO_MODE_CLOCK_CNT);
+	tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
+	    (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
+	REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
+	REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+	DELAY(40);
+
+	/* address */
+
+	tmp = ((phy_addr << 21) | (devad << 16) | reg |
+	    EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
+	REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
+
+	for (i = 0; i < 50; i++) {
+		DELAY(10);
+
+		tmp = REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
+		if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
+			DELAY(5);
+			break;
+		}
+	}
+	if (tmp & EMAC_MDIO_COMM_START_BUSY) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "write phy register failed\n");
+		rc = -EINVAL;
+	} else {
+		/* data */
+		tmp = ((phy_addr << 21) | (devad << 16) | val |
+		    EMAC_MDIO_COMM_COMMAND_WRITE_45 |
+		    EMAC_MDIO_COMM_START_BUSY);
+		REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
+
+		for (i = 0; i < 50; i++) {
+			DELAY(10);
+
+			tmp = REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
+			if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
+				DELAY(5);
+				break;
+			}
+		}
+		if (tmp & EMAC_MDIO_COMM_START_BUSY) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "write phy register failed\n");
+			rc = -EINVAL;
+		}
+	}
+
+	/* Restore the saved mode. */
+	REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
+
+	return (rc);
+}
+
+uint8_t
+bxe_cl45_read(struct bxe_softc *sc, uint8_t port, uint32_t ext_phy_type,
+    uint8_t phy_addr, uint8_t devad, uint16_t reg, uint16_t *ret_val)
+{
+	uint32_t mdio_ctrl, saved_mode, val;
+	uint16_t i;
+	uint8_t rc;
+
+	rc = 0;
+	mdio_ctrl = bxe_get_emac_base(sc, ext_phy_type, port);
+
+	/*
+	 * set clause 45 mode, slow down the MDIO clock to 2.5MHz
+	 * (a value of 49==0x31) and make sure that the AUTO poll is off.
+	 */
+	saved_mode = REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+	val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
+	    EMAC_MDIO_MODE_CLOCK_CNT));
+	val |= (EMAC_MDIO_MODE_CLAUSE_45 |
+	    (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
+	REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
+	REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
+	DELAY(40);
+
+	/* address */
+	val = ((phy_addr << 21) | (devad << 16) | reg |
+	    EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
+	REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
+
+	for (i = 0; i < 50; i++) {
+		DELAY(10);
+
+		val = REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
+		if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
+			DELAY(5);
+			break;
+		}
+	}
+	if (val & EMAC_MDIO_COMM_START_BUSY) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "read phy register failed\n");
+
+		*ret_val = 0;
+		rc = -EINVAL;
+	} else {
+		/* data */
+		val = ((phy_addr << 21) | (devad << 16) |
+		    EMAC_MDIO_COMM_COMMAND_READ_45 | EMAC_MDIO_COMM_START_BUSY);
+		REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
+
+		for (i = 0; i < 50; i++) {
+			DELAY(10);
+
+			val = REG_RD(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
+			if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
+				*ret_val = (uint16_t)(val &
+				    EMAC_MDIO_COMM_DATA);
+				break;
+			}
+		}
+		if (val & EMAC_MDIO_COMM_START_BUSY) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "read phy register failed\n");
+
+			*ret_val = 0;
+			rc = -EINVAL;
+		}
+	}
+
+	/* Restore the saved mode. */
+	REG_WR(sc, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
+
+	return (rc);
+}
+
+static void
+bxe_set_aer_mmd(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ser_lane;
+	uint16_t offset;
+
+	sc = params->sc;
+	ser_lane = ((params->lane_config &
+	    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+	    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+	offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
+	    (params->phy_addr + ser_lane) : 0;
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_AER_BLOCK, MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
+}
+
+static void
+bxe_set_master_ln(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t new_master_ln, ser_lane;
+
+	sc = params->sc;
+	ser_lane = ((params->lane_config &
+	    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+	    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+	/* Set the master_ln for AN. */
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_XGXS_BLOCK2, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+	    &new_master_ln);
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_XGXS_BLOCK2 , MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+	    (new_master_ln | ser_lane));
+}
+
+static uint8_t
+bxe_reset_unicore(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t mii_control;
+	uint16_t i;
+
+	sc = params->sc;
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+	    &mii_control);
+
+	/* Reset the unicore. */
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+	    (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
+	if (params->switch_cfg == SWITCH_CFG_1G)
+		bxe_set_serdes_access(params);
+
+	/* Wait for the reset to self clear. */
+	for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
+		DELAY(5);
+
+		/* The reset erased the previous bank value. */
+		CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+		    &mii_control);
+
+		if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
+			DELAY(5);
+			return (0);
+		}
+	}
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "BUG! XGXS is still in reset!\n");
+	return (-EINVAL);
+}
+
+static void
+bxe_set_swap_lanes(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t ser_lane, rx_lane_swap, tx_lane_swap;
+
+	sc = params->sc;
+	/*
+	 * Each two bits represents a lane number:
+	 *  No swap is 0123 => 0x1b no need to enable the swap.
+	 */
+
+	ser_lane = ((params->lane_config &
+	    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+	    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+	rx_lane_swap = ((params->lane_config &
+	    PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
+	    PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
+	tx_lane_swap = ((params->lane_config &
+	    PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
+	    PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
+
+	if (rx_lane_swap != 0x1b) {
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_XGXS_BLOCK2, MDIO_XGXS_BLOCK2_RX_LN_SWAP,
+		    (rx_lane_swap | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
+		    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
+	} else {
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_XGXS_BLOCK2, MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
+	}
+
+	if (tx_lane_swap != 0x1b) {
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_XGXS_BLOCK2, MDIO_XGXS_BLOCK2_TX_LN_SWAP,
+		    (tx_lane_swap | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
+	} else {
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_XGXS_BLOCK2, MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
+	}
+}
+
+static void
+bxe_set_parallel_detection(struct link_params *params, uint8_t phy_flags)
+{
+	struct bxe_softc *sc;
+	uint16_t control2;
+
+	sc = params->sc;
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+	    &control2);
+	if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
+		control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
+	else
+		control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
+	DBPRINT(sc, 1, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
+	    params->speed_cap_mask, control2);
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+	    control2);
+
+	if ((phy_flags & PHY_XGXS_FLAG) && (params->speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
+		DBPRINT(sc, BXE_INFO, "XGXS\n");
+
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_10G_PARALLEL_DETECT,
+		    MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
+		    MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
+
+		CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_10G_PARALLEL_DETECT,
+		    MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, &control2);
+
+		control2 |=
+		    MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
+
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_10G_PARALLEL_DETECT,
+		    MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, control2);
+
+		/* Disable parallel detection of HiG. */
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_XGXS_BLOCK2,
+		    MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
+		    MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
+		    MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
+	}
+}
+
+static void
+bxe_set_autoneg(struct link_params *params, struct link_vars *vars,
+    uint8_t enable_cl73)
+{
+	struct bxe_softc *sc;
+	uint16_t reg_val;
+
+	sc = params->sc;
+	/* CL37 Autoneg */
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
+
+	/* CL37 Autoneg Enabled */
+	if (vars->line_speed == SPEED_AUTO_NEG)
+		reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
+	else /* CL37 Autoneg Disabled */
+		reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+		    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
+
+	/* Enable/Disable Autodetection */
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+	    &reg_val);
+	reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
+	    MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
+	reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
+
+	if (vars->line_speed == SPEED_AUTO_NEG)
+		reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
+	else
+		reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+	    reg_val);
+
+	/* Enable TetonII and BAM autoneg. */
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_BAM_NEXT_PAGE, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+	    &reg_val);
+	if (vars->line_speed == SPEED_AUTO_NEG) {
+		/* Enable BAM aneg Mode and TetonII aneg Mode. */
+		reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
+		    MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
+	} else {
+		/* TetonII and BAM Autoneg Disabled. */
+		reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
+		    MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
+	}
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_BAM_NEXT_PAGE, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+	    reg_val);
+
+	if (enable_cl73) {
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_CL73_USERB0, MDIO_CL73_USERB0_CL73_UCTRL,
+		    0xe);
+
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_CL73_USERB0, MDIO_CL73_USERB0_CL73_BAM_CTRL1,
+		    MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
+		    MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
+		    MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
+
+		/* Set the CL73 AN speed. */
+		CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_CL73_IEEEB1, MDIO_CL73_IEEEB1_AN_ADV2,
+		    &reg_val);
+		if (params->speed_cap_mask &
+		    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+			reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
+		if (params->speed_cap_mask &
+		    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
+			reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
+
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_CL73_IEEEB1, MDIO_CL73_IEEEB1_AN_ADV2,
+		    reg_val);
+
+		/* CL73 Autoneg Enabled. */
+		reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
+
+	} else /* CL73 Autoneg Disabled */
+		reg_val = 0;
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_CL73_IEEEB0, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+	    reg_val);
+}
+
+/* Program SerDes, forced speed. */
+static void
+bxe_program_serdes(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint16_t reg_val;
+
+	sc = params->sc;
+	/* Program duplex, disable autoneg and sgmii.*/
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
+	reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
+	    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+	    MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
+	if (params->req_duplex == DUPLEX_FULL)
+		reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
+
+	/*
+	 * Program speed
+	 * - needed only if the speed is greater than 1G (2.5G or 10G).
+	 */
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_MISC1, &reg_val);
+	/* Clearing the speed value before setting the right speed. */
+	DBPRINT(sc, BXE_VERBOSE_PHY, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n",
+	    reg_val);
+
+	reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
+	    MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
+
+	if (!((vars->line_speed == SPEED_1000) ||
+	    (vars->line_speed == SPEED_100) ||
+	    (vars->line_speed == SPEED_10))) {
+		reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
+		    MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
+		if (vars->line_speed == SPEED_10000)
+			reg_val |=
+			    MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
+		if (vars->line_speed == SPEED_13000)
+			reg_val |=
+			    MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
+	}
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_MISC1, reg_val);
+}
+
+static void
+bxe_set_brcm_cl37_advertisment(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t val;
+
+	sc = params->sc;
+	val = 0;
+
+	/* Configure the 48 bits for BAM AN. */
+
+	/* Set extended capabilities. */
+	if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
+		val |= MDIO_OVER_1G_UP1_2_5G;
+	if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+		val |= MDIO_OVER_1G_UP1_10G;
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
+}
+
+static void
+bxe_calc_ieee_aneg_adv(struct link_params *params, uint16_t *ieee_fc)
+{
+
+	*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
+	/*
+	 * Resolve pause mode and advertisement.
+	 * Please refer to Table 28B-3 of the 802.3ab-1999 spec.
+	 */
+
+	switch (params->req_flow_ctrl) {
+	case FLOW_CTRL_AUTO:
+		if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) {
+			*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+		} else {
+			*ieee_fc |=
+			    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+		}
+		break;
+	case FLOW_CTRL_TX:
+		*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+		break;
+	case FLOW_CTRL_RX:
+	case FLOW_CTRL_BOTH:
+		*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+		break;
+	case FLOW_CTRL_NONE:
+	default:
+		*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
+		break;
+	}
+}
+
+static void
+bxe_set_ieee_aneg_advertisment(struct link_params *params, uint16_t ieee_fc)
+{
+	struct bxe_softc *sc;
+	uint16_t val;
+
+	sc = params->sc;
+
+	/* For AN, we are always publishing full duplex. */
+
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_CL73_IEEEB1, MDIO_CL73_IEEEB1_AN_ADV1, &val);
+	val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
+	val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_CL73_IEEEB1, MDIO_CL73_IEEEB1_AN_ADV1, val);
+}
+
+static void
+bxe_restart_autoneg(struct link_params *params, uint8_t enable_cl73)
+{
+	struct bxe_softc *sc;
+	uint16_t mii_control;
+
+	sc = params->sc;
+	DBPRINT(sc, BXE_VERBOSE_PHY, "bxe_restart_autoneg\n");
+	/* Enable and restart BAM/CL37 aneg. */
+
+	if (enable_cl73) {
+		CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_CL73_IEEEB0, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+		    &mii_control);
+
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_CL73_IEEEB0, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+		    (mii_control | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
+		    MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
+	} else {
+		CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+		    &mii_control);
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "bxe_restart_autoneg mii_control before = 0x%x\n",
+		    mii_control);
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+		    (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+		    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
+	}
+}
+
+static void
+bxe_initialize_sgmii_process(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint16_t control1, mii_control;
+
+	sc = params->sc;
+	/* In SGMII mode, the unicore is always slave. */
+
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+	    &control1);
+	control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
+	/* set sgmii mode (and not fiber) */
+	control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
+	    MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
+	    MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+	    control1);
+
+	/* if forced speed */
+	if (!(vars->line_speed == SPEED_AUTO_NEG)) {
+		/* Set speed, disable autoneg. */
+		CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+		    &mii_control);
+		mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+		    MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
+		    MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
+
+		switch (vars->line_speed) {
+		case SPEED_100:
+			mii_control |=
+			    MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
+			break;
+		case SPEED_1000:
+			mii_control |=
+			    MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
+			break;
+		case SPEED_10:
+			/* There is nothing to set for 10M. */
+			break;
+		default:
+			/* Invalid speed for SGMII. */
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Invalid line_speed 0x%x\n", vars->line_speed);
+			break;
+		}
+
+		/* Setting the full duplex. */
+		if (params->req_duplex == DUPLEX_FULL)
+			mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+		    mii_control);
+	} else { /* AN mode */
+		/* Enable and restart AN. */
+		bxe_restart_autoneg(params, 0);
+	}
+}
+
+/*
+ * Link management.
+ */
+static void
+bxe_pause_resolve(struct link_vars *vars, uint32_t pause_result)
+{
+
+						/*  LD	    LP	 */
+	switch (pause_result) { 		/* ASYM P ASYM P */
+	case 0xb:       			/*   1  0   1  1 */
+		vars->flow_ctrl = FLOW_CTRL_TX;
+		break;
+	case 0xe:       			/*   1  1   1  0 */
+		vars->flow_ctrl = FLOW_CTRL_RX;
+		break;
+	case 0x5:       			/*   0  1   0  1 */
+	case 0x7:       			/*   0  1   1  1 */
+	case 0xd:       			/*   1  1   0  1 */
+	case 0xf:       			/*   1  1   1  1 */
+		vars->flow_ctrl = FLOW_CTRL_BOTH;
+		break;
+	default:
+		break;
+	}
+	if (pause_result & (1<<0))
+		vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
+	if (pause_result & (1<<1))
+		vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
+}
+
+static uint8_t
+bxe_ext_phy_resolve_fc(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint8_t ext_phy_addr;
+	uint16_t ld_pause;   /* local */
+	uint16_t lp_pause;   /* link partner */
+	uint16_t pause_result;
+	uint8_t port, ret;
+
+	sc = params->sc;
+	ret = 0;
+	port = params->port;
+	/* Read twice. */
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	if (vars->autoneg & AUTO_NEG_COMPLETE) {
+		ret = 1;
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &ld_pause);
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_AN_DEVAD, MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
+		pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
+		pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Ext PHY pause result 0x%x \n",
+		    pause_result);
+		bxe_pause_resolve(vars, pause_result);
+		if (vars->flow_ctrl == FLOW_CTRL_NONE && ext_phy_type ==
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+			bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+			    MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &ld_pause);
+
+			bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+			    MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, &lp_pause);
+			pause_result = (ld_pause &
+			    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
+			pause_result |= (lp_pause &
+			    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
+
+			bxe_pause_resolve(vars, pause_result);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Ext PHY CL37 pause result 0x%x \n", pause_result);
+		}
+	}
+	return (ret);
+}
+
+uint8_t bxe_direct_parallel_detect_used(struct link_params *);
+
+uint8_t
+bxe_direct_parallel_detect_used(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t pd_10g, status2_1000x;
+
+	sc = params->sc;
+	if (params->req_line_speed != SPEED_AUTO_NEG)
+		return (0);
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
+	    &status2_1000x);
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
+	    &status2_1000x);
+	if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "1G parallel detect link on port %d\n", params->port);
+		return (1);
+	}
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_10G_PARALLEL_DETECT,
+	    MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
+	if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "10G parallel detect link on port %d\n", params->port);
+		return (1);
+	}
+	return (0);
+}
+
+static void
+bxe_flow_ctrl_resolve(struct link_params *params, struct link_vars *vars,
+    uint32_t gp_status)
+{
+	struct bxe_softc *sc;
+	uint16_t ld_pause;   /* local driver */
+	uint16_t lp_pause;   /* link partner */
+	uint16_t pause_result;
+
+	sc = params->sc;
+	vars->flow_ctrl = FLOW_CTRL_NONE;
+
+	/* Resolve from gp_status in case of AN complete and not sgmii. */
+	if (params->req_flow_ctrl != FLOW_CTRL_AUTO)
+                vars->flow_ctrl = params->req_flow_ctrl;
+	else if (params->req_line_speed != SPEED_AUTO_NEG)
+		vars->flow_ctrl = params->req_fc_auto_adv;
+	else if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
+	    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
+		bxe_ext_phy_resolve_fc(params, vars);
+	else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
+	    (!(vars->phy_flags & PHY_SGMII_FLAG))) {
+		if (bxe_direct_parallel_detect_used(params)) {
+			vars->flow_ctrl = params->req_fc_auto_adv;
+			return;
+		}
+		if ((gp_status &
+		    (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
+		    MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
+		    (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
+		    MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
+			CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+			    MDIO_REG_BANK_CL73_IEEEB1, MDIO_CL73_IEEEB1_AN_ADV1,
+			    &ld_pause);
+			CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+			    MDIO_REG_BANK_CL73_IEEEB1,
+			    MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
+			pause_result = (ld_pause &
+			    MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
+			pause_result |= (lp_pause &
+			    MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
+			DBPRINT(sc, BXE_VERBOSE_PHY, "pause_result CL73 0x%x\n",
+			    pause_result);
+		} else {
+			CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+			    MDIO_REG_BANK_COMBO_IEEE0,
+			    MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
+			CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+			    MDIO_REG_BANK_COMBO_IEEE0,
+			    MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
+			    &lp_pause);
+			pause_result = (ld_pause &
+			    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
+			pause_result |= (lp_pause &
+			    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
+			DBPRINT(sc, BXE_VERBOSE_PHY, "pause_result CL37 0x%x\n",
+			    pause_result);
+		}
+		bxe_pause_resolve(vars, pause_result);
+	}
+	DBPRINT(sc, BXE_INFO, "flow_ctrl 0x%x\n", vars->flow_ctrl);
+}
+
+static void
+bxe_check_fallback_to_cl37(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t rx_status, ustat_val, cl37_fsm_recieved;
+
+	sc = params->sc;
+	DBPRINT(sc, BXE_INFO, "bxe_check_fallback_to_cl37\n");
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr, MDIO_REG_BANK_RX0,
+	    MDIO_RX0_RX_STATUS, &rx_status);
+	if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
+	    (MDIO_RX0_RX_STATUS_SIGDET)) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Signal is not detected. Restoring CL73."
+		    "rx_status(0x80b0) = 0x%x\n", rx_status);
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+		    MDIO_REG_BANK_CL73_IEEEB0, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+		    MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
+		return;
+	}
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_CL73_USERB0, MDIO_CL73_USERB0_CL73_USTAT1,
+	    &ustat_val);
+	if ((ustat_val & (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
+	    MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
+	    (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
+	    MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "CL73 state-machine is not stable. "
+		    "ustat_val(0x8371) = 0x%x\n", ustat_val);
+		return;
+	}
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_REMOTE_PHY, MDIO_REMOTE_PHY_MISC_RX_STATUS,
+	    &cl37_fsm_recieved);
+	if ((cl37_fsm_recieved &
+	    (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
+	    MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
+	    (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
+	    MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "No CL37 FSM were received. "
+		    "misc_rx_status(0x8330) = 0x%x\n", cl37_fsm_recieved);
+		return;
+	}
+	CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_CL73_IEEEB0, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
+	bxe_restart_autoneg(params, 0);
+	DBPRINT(sc, BXE_INFO, "Disabling CL73, and restarting CL37 autoneg\n");
+}
+
+static void
+bxe_an_resolve(struct link_params *params, struct link_vars *vars,
+    uint32_t gp_status)
+
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t val;
+	uint8_t ext_phy_addr;
+
+	sc = params->sc;
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+	switch (ext_phy_type) {
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+		if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
+			vars->autoneg |= AUTO_NEG_COMPLETE;
+			vars->link_status |=
+			    LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+		}
+
+		if (bxe_direct_parallel_detect_used(params)) {
+			vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
+			vars->link_status |=
+			    LINK_STATUS_PARALLEL_DETECTION_USED;
+		}
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
+		if (vars->line_speed < SPEED_10000) {
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD,
+			    MDIO_AN_REG_8481_LEGACY_MII_STATUS, &val);
+			if (val & (1 << 5)) {
+				vars->autoneg |= AUTO_NEG_COMPLETE;
+				vars->link_status |=
+				    LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+			}
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD,
+			    MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, &val);
+			if ((val & (1 << 0)) == 0) {
+				vars->autoneg |=
+				    AUTO_NEG_PARALLEL_DETECTION_USED;
+				vars->link_status |=
+					LINK_STATUS_PARALLEL_DETECTION_USED;
+			}
+			break;
+		};
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+		bxe_cl45_read(sc, params->port, ext_phy_type, ext_phy_addr,
+		    MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
+		bxe_cl45_read(sc, params->port, ext_phy_type, ext_phy_addr,
+		    MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
+		if (val & (1 << 5)) {
+			vars->autoneg |= AUTO_NEG_COMPLETE;
+			vars->link_status |=
+			    LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+		}
+		if ((val & (1 << 0)) == 0) {
+			vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
+			vars->link_status |=
+			    LINK_STATUS_PARALLEL_DETECTION_USED;
+		}
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+		vars->autoneg |= AUTO_NEG_COMPLETE;
+		vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+		break;
+	default:
+		break;
+	}
+	DBPRINT(sc, BXE_VERBOSE_PHY, "AN result for port %d: 0x%x\n",
+	    params->port, vars->autoneg);
+}
+
+static uint8_t
+bxe_link_settings_status(struct link_params *params, struct link_vars *vars,
+    uint32_t gp_status, uint8_t ext_phy_link_up)
+{
+	struct bxe_softc *sc;
+	uint16_t new_line_speed;
+
+	sc = params->sc;
+	vars->link_status = 0;
+	vars->autoneg = 0;
+	if (params->req_line_speed == SPEED_AUTO_NEG) {
+		vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
+		vars->autoneg |= AUTO_NEG_ENABLED;
+	}
+	if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "phy link up gp_status=0x%x\n",
+			 gp_status);
+
+		vars->phy_link_up = 1;
+		vars->link_status |= LINK_STATUS_LINK_UP;
+
+		if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
+			vars->duplex = DUPLEX_FULL;
+		else
+			vars->duplex = DUPLEX_HALF;
+		if (params->req_line_speed == SPEED_AUTO_NEG)
+			bxe_an_resolve(params, vars, gp_status);
+
+		bxe_flow_ctrl_resolve(params, vars, gp_status);
+
+		switch (gp_status & GP_STATUS_SPEED_MASK) {
+		case GP_STATUS_10M:
+			new_line_speed = SPEED_10;
+			if (vars->duplex == DUPLEX_FULL)
+				vars->link_status |= LINK_10TFD;
+			else
+				vars->link_status |= LINK_10THD;
+			break;
+		case GP_STATUS_100M:
+			new_line_speed = SPEED_100;
+			if (vars->duplex == DUPLEX_FULL)
+				vars->link_status |= LINK_100TXFD;
+			else
+				vars->link_status |= LINK_100TXHD;
+			break;
+		case GP_STATUS_1G:
+		case GP_STATUS_1G_KX:
+			new_line_speed = SPEED_1000;
+			if (vars->duplex == DUPLEX_FULL)
+				vars->link_status |= LINK_1000TFD;
+			else
+				vars->link_status |= LINK_1000THD;
+			break;
+		case GP_STATUS_2_5G:
+			new_line_speed = SPEED_2500;
+			if (vars->duplex == DUPLEX_FULL)
+				vars->link_status |= LINK_2500TFD;
+			else
+				vars->link_status |= LINK_2500THD;
+			break;
+		case GP_STATUS_5G:
+		case GP_STATUS_6G:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+				 "link speed unsupported  gp_status 0x%x\n",
+				  gp_status);
+			return (-EINVAL);
+		case GP_STATUS_10G_KX4:
+		case GP_STATUS_10G_HIG:
+		case GP_STATUS_10G_CX4:
+			new_line_speed = SPEED_10000;
+			vars->link_status |= LINK_10GTFD;
+			break;
+		case GP_STATUS_12G_HIG:
+			new_line_speed = SPEED_12000;
+			vars->link_status |= LINK_12GTFD;
+			break;
+		case GP_STATUS_12_5G:
+			new_line_speed = SPEED_12500;
+			vars->link_status |= LINK_12_5GTFD;
+			break;
+		case GP_STATUS_13G:
+			new_line_speed = SPEED_13000;
+			vars->link_status |= LINK_13GTFD;
+			break;
+		case GP_STATUS_15G:
+			new_line_speed = SPEED_15000;
+			vars->link_status |= LINK_15GTFD;
+			break;
+		case GP_STATUS_16G:
+			new_line_speed = SPEED_16000;
+			vars->link_status |= LINK_16GTFD;
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "link speed unsupported gp_status 0x%x\n",
+			    gp_status);
+			return (-EINVAL);
+		}
+
+		/*
+		 * Upon link speed change set the NIG into drain mode.
+		 * Comes to deals with possible FIFO glitch due to clk change
+		 * when speed is decreased without link down indicator.
+		 */
+		if (new_line_speed != vars->line_speed) {
+			if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
+			    ext_phy_link_up) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Internal link speed %d is different "
+				    "than the external link speed %d\n",
+				    new_line_speed, vars->line_speed);
+				vars->phy_link_up = 0;
+				return (0);
+			}
+			REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE +
+			    params->port * 4, 0);
+			msleep(1);
+		}
+		vars->line_speed = new_line_speed;
+
+		if (vars->flow_ctrl & FLOW_CTRL_TX)
+			vars->link_status |=
+			    LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
+
+		if (vars->flow_ctrl & FLOW_CTRL_RX)
+			vars->link_status |=
+			    LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
+
+		if (!ext_phy_link_up)
+			vars->link_status = 0;
+	} else { /* link_down */
+		DBPRINT(sc, BXE_VERBOSE_PHY, "phy link down\n");
+
+		vars->phy_link_up = 0;
+
+		vars->duplex = DUPLEX_FULL;
+		vars->flow_ctrl = FLOW_CTRL_NONE;
+		vars->autoneg = AUTO_NEG_DISABLED;
+		vars->mac_type = MAC_TYPE_NONE;
+		if ((params->req_line_speed == SPEED_AUTO_NEG) &&
+		    ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT))) {
+			bxe_check_fallback_to_cl37(params);
+		}
+	}
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "gp_status 0x%x  phy_link_up %x line_speed %x \n", gp_status,
+	    vars->phy_link_up, vars->line_speed);
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "duplex %x  flow_ctrl 0x%x autoneg 0x%x\n", vars->duplex,
+	    vars->flow_ctrl, vars->autoneg);
+	DBPRINT(sc, BXE_VERBOSE_PHY, "link_status 0x%x\n", vars->link_status);
+
+	return (0);
+}
+
+static void
+bxe_set_gmii_tx_driver(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t lp_up2;
+	uint16_t tx_driver;
+	uint16_t bank;
+
+	sc = params->sc;
+	/* read precomp */
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
+
+	/* bits [10:7] at lp_up2, positioned at [15:12] */
+	lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
+	    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
+	    MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
+
+	if (lp_up2 == 0)
+		return;
+
+	for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
+	    bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
+		CL45_RD_OVER_CL22(sc, params->port, params->phy_addr, bank,
+		    MDIO_TX0_TX_DRIVER, &tx_driver);
+
+		/* Replace tx_driver bits [15:12] */
+		if (lp_up2 != (tx_driver &
+		    MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
+			tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
+			tx_driver |= lp_up2;
+			CL45_WR_OVER_CL22(sc, params->port, params->phy_addr,
+			    bank, MDIO_TX0_TX_DRIVER, tx_driver);
+		}
+	}
+}
+
+static uint8_t
+bxe_emac_program(struct link_params *params, uint32_t line_speed,
+    uint32_t duplex)
+{
+	struct bxe_softc *sc;
+	uint16_t mode;
+	uint8_t port;
+
+	sc = params->sc;
+	port = params->port;
+	mode = 0;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "setting link speed & duplex\n");
+	bxe_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE,
+	    (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_MII_10M |
+	    EMAC_MODE_HALF_DUPLEX));
+	switch (line_speed) {
+	case SPEED_10:
+		mode |= EMAC_MODE_PORT_MII_10M;
+		break;
+	case SPEED_100:
+		mode |= EMAC_MODE_PORT_MII;
+		break;
+	case SPEED_1000:
+		mode |= EMAC_MODE_PORT_GMII;
+		break;
+	case SPEED_2500:
+		mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
+		break;
+	default:
+		/* 10G not valid for EMAC */
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Invalid line_speed 0x%x\n",
+		    line_speed);
+		return (-EINVAL);
+	}
+
+	if (duplex == DUPLEX_HALF)
+		mode |= EMAC_MODE_HALF_DUPLEX;
+	bxe_bits_en(sc, GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE,
+	    mode);
+
+	bxe_set_led(params, LED_MODE_OPER, line_speed);
+	return (0);
+}
+
+/*
+ * External Phy section
+ */
+void
+bxe_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port)
+{
+
+	bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_OUTPUT_LOW,
+	    port);
+	msleep(1);
+	bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+	    port);
+}
+
+static void
+bxe_ext_phy_reset(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint8_t ext_phy_addr;
+
+	sc = params->sc;
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Port %x: bxe_ext_phy_reset\n",
+	    params->port);
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	/*
+	 * The PHY reset is controled by GPIO 1.
+	 * Give it 1ms of reset pulse.
+	 */
+	if (vars->phy_flags & PHY_XGXS_FLAG) {
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS Direct\n");
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 8705/8706\n");
+
+			/* Restore normal power mode*/
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+
+			/* HW reset */
+			bxe_ext_phy_hw_reset(sc, params->port);
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_CTRL, 0xa040);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+			/* Restore normal power mode*/
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+			    1 << 15);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 8072\n");
+
+			/*
+			 * Unset Low Power Mode and SW reset.
+			 * Restore normal power mode.
+			 */
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+			    1 << 15);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 8073\n");
+
+			/* Restore normal power mode. */
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS SFX7101\n");
+
+			/* Restore normal power mode. */
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+
+			/* HW reset */
+			bxe_ext_phy_hw_reset(sc, params->port);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+			/* Restore normal power mode. */
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
+
+			/* HW reset */
+			bxe_ext_phy_hw_reset(sc, params->port);
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+			    1 << 15);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "XGXS PHY Failure detected\n");
+			break;
+
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "BAD XGXS ext_phy_config 0x%x\n",
+			    params->ext_phy_config);
+			break;
+		}
+
+	} else { /* SerDes */
+		ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes Direct\n");
+			break;
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes 5482\n");
+			bxe_ext_phy_hw_reset(sc, params->port);
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "BAD SerDes ext_phy_config 0x%x\n",
+			    params->ext_phy_config);
+			break;
+		}
+	}
+}
+
+static void
+bxe_save_spirom_version(struct bxe_softc *sc, uint8_t port, uint32_t shmem_base,
+    uint32_t spirom_ver)
+{
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "FW version 0x%x:0x%x\n",
+	    (uint16_t)(spirom_ver >> 16), (uint16_t)spirom_ver);
+	REG_WR(sc, shmem_base + offsetof(struct shmem_region,
+	    port_mb[port].ext_phy_fw_version), spirom_ver);
+}
+
+static void
+bxe_save_bcm_spirom_ver(struct bxe_softc *sc, uint8_t port,
+    uint32_t ext_phy_type, uint8_t ext_phy_addr, uint32_t shmem_base)
+{
+	uint16_t fw_ver1, fw_ver2;
+	uint8_t status;
+
+	status = 0;
+	status = bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &fw_ver1);
+	status |= bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &fw_ver2);
+	bxe_save_spirom_version(sc, port, shmem_base,
+	    (uint32_t)(fw_ver1 << 16 | fw_ver2));
+
+	if (status)
+		BXE_PRINTF("Reading the external PHY ROM failed. Status:0x%x\n",
+		    status);
+}
+
+static void
+bxe_save_8481_spirom_version(struct bxe_softc *sc, uint8_t port,
+    uint8_t ext_phy_addr, uint32_t shmem_base)
+{
+	uint16_t val, fw_ver1, fw_ver2, cnt;
+	/*
+	 * For the 32 bits registers in 8481, access via MDIO2ARM interface.
+	 * (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000.
+	 */
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA819, 0x0014);
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA817, 0x0009);
+
+	for (cnt = 0; cnt < 100; cnt++) {
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+		    ext_phy_addr, MDIO_PMA_DEVAD, 0xA818, &val);
+		if (val & 1)
+			break;
+		DELAY(5);
+	}
+	if (cnt == 100) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Unable to read 8481 phy fw version(1)\n");
+		bxe_save_spirom_version(sc, port, shmem_base, 0);
+		return;
+	}
+
+	/* 2) read register 0xc200_0000 (SPI_FW_STATUS). */
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA819, 0x0000);
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA817, 0x000A);
+	for (cnt = 0; cnt < 100; cnt++) {
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+		    ext_phy_addr, MDIO_PMA_DEVAD, 0xA818, &val);
+		if (val & 1)
+			break;
+		DELAY(5);
+	}
+	if (cnt == 100) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Unable to read 8481 phy fw version(2)\n");
+		bxe_save_spirom_version(sc, port, shmem_base, 0);
+		return;
+	}
+
+	/* Lower 16 bits of the register SPI_FW_STATUS. */
+	bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
+	/* Upper 16 bits of register SPI_FW_STATUS. */
+	bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
+	    ext_phy_addr, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
+
+	bxe_save_spirom_version(sc, port, shmem_base, (fw_ver2<<16) | fw_ver1);
+}
+
+static void
+bxe_bcm8072_external_rom_boot(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	/* Need to wait 200ms after reset. */
+	msleep(200);
+	/*
+	 * Boot port from external ROM.
+	 * Set ser_boot_ctl bit in the MISC_CTRL1 register.
+	 */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+
+	/* Reset internal microprocessor */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+	/* Set micro reset = 0. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
+	/* Reset internal microprocessor. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+	/* Wait for 100ms for code download via SPI port. */
+	msleep(100);
+
+	/* Clear ser_boot_ctl bit. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+	/* Wait 100ms. */
+	msleep(100);
+
+	bxe_save_bcm_spirom_ver(sc, port, ext_phy_type, ext_phy_addr,
+	    params->shmem_base);
+}
+
+/* This is only required for 8073A1, version 102 only. */
+static uint8_t
+bxe_8073_is_snr_needed(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint8_t ext_phy_addr;
+	uint16_t val;
+
+	sc = params->sc;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+	/* Read 8073 HW revision. */
+	bxe_cl45_read(sc, params->port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
+
+	if (val != 1) {
+		/* No need to workaround in 8073 A1. */
+		return (0);
+	}
+
+	bxe_cl45_read(sc, params->port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
+
+	/* SNR should be applied only for version 0x102. */
+	if (val != 0x102)
+		return (0);
+
+	return (1);
+}
+
+static uint8_t
+bxe_bcm8073_xaui_wa(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t cnt, cnt1, val;
+	uint8_t ext_phy_addr;
+
+	sc = params->sc;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+	bxe_cl45_read(sc, params->port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
+
+	if (val > 0) {
+		/* No need to workaround in 8073 A1. */
+		return (0);
+	}
+	/* XAUI workaround in 8073 A0: */
+
+	/*
+	 * After loading the boot ROM and restarting Autoneg,
+	 * poll Dev1, Reg $C820:
+	 */
+
+	for (cnt = 0; cnt < 1000; cnt++) {
+		bxe_cl45_read(sc, params->port,
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
+		/*
+		 * If bit [14] = 0 or bit [13] = 0, continue on with
+		 * system initialization (XAUI work-around not required,
+		 * as these bits indicate 2.5G or 1G link up).
+		 */
+		if (!(val & (1<<14)) || !(val & (1<<13))) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "XAUI work-around not required\n");
+			return (0);
+		} else if (!(val & (1<<15))) {
+			DBPRINT(sc, BXE_VERBOSE_PHY, "clc bit 15 went off\n");
+			/*
+			 * If bit 15 is 0, then poll Dev1, Reg $C841 until
+			 * it's MSB (bit 15) goes to 1 (indicating that the
+			 * XAUI workaround has completed), then continue on
+			 * with system initialization.
+			 */
+			for (cnt1 = 0; cnt1 < 1000; cnt1++) {
+				bxe_cl45_read(sc, params->port,
+				    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_8073_XAUI_WA, &val);
+				if (val & (1<<15)) {
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "XAUI workaround has completed\n");
+					return (0);
+				 }
+				 msleep(3);
+			}
+			break;
+		}
+		msleep(3);
+	}
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Warning: XAUI work-around timeout !!!\n");
+	return (-EINVAL);
+}
+
+static void
+bxe_bcm8073_bcm8727_external_rom_boot(struct bxe_softc *sc, uint8_t port,
+    uint8_t ext_phy_addr, uint32_t ext_phy_type, uint32_t shmem_base)
+{
+
+	/* Boot port from external ROM.  */
+	/* EDC grst */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, 0x0001);
+
+	/* ucode reboot and rst. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, 0x008c);
+
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+
+	/* Reset internal microprocessor. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
+
+	/* Release srst bit. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+
+	/* Wait for 100ms for code download via SPI port. */
+	msleep(100);
+
+	/* Clear ser_boot_ctl bit. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+
+	bxe_save_bcm_spirom_ver(sc, port, ext_phy_type, ext_phy_addr,
+	    shmem_base);
+}
+
+static void
+bxe_bcm8073_external_rom_boot(struct bxe_softc *sc, uint8_t port,
+    uint8_t ext_phy_addr, uint32_t shmem_base)
+{
+
+	bxe_bcm8073_bcm8727_external_rom_boot(sc, port, ext_phy_addr,
+	    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, shmem_base);
+}
+
+static void
+bxe_bcm8727_external_rom_boot(struct bxe_softc *sc, uint8_t port,
+    uint8_t ext_phy_addr, uint32_t shmem_base)
+{
+
+	bxe_bcm8073_bcm8727_external_rom_boot(sc, port, ext_phy_addr,
+	    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, shmem_base);
+}
+
+static void
+bxe_bcm8726_external_rom_boot(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	/* Need to wait 100ms after reset. */
+	msleep(100);
+
+	/* Set serial boot control for external load. */
+
+	/* Micro controller re-boot. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, 0x018B);
+
+	/* Set soft reset. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
+
+	/* Set PLL register value to be same like in P13 ver. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_MISC_CTRL1, 0x0001);
+
+	/*
+	 * Clear soft reset.
+	 * Will automatically reset micro-controller re-boot.
+	 */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
+
+	/* Wait for 150ms for microcode load. */
+	msleep(150);
+
+	/* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_MISC_CTRL1, 0x0000);
+
+	msleep(200);
+	bxe_save_bcm_spirom_ver(sc, port, ext_phy_type, ext_phy_addr,
+	    params->shmem_base);
+}
+
+static void
+bxe_sfp_set_transmitter(struct bxe_softc *sc, uint8_t port,
+    uint32_t ext_phy_type, uint8_t ext_phy_addr, uint8_t tx_en)
+{
+	uint16_t val;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "Setting transmitter tx_en=%x for port %x\n", tx_en, port);
+	/* Disable/Enable transmitter ( TX laser of the SFP+ module.). */
+	bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_PHY_IDENTIFIER, &val);
+
+	if (tx_en)
+		val &= ~(1<<15);
+	else
+		val |= (1<<15);
+
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_PHY_IDENTIFIER, val);
+}
+
+static uint8_t
+bxe_8726_read_sfp_module_eeprom(struct link_params *params, uint16_t addr,
+    uint8_t byte_cnt, uint8_t *o_buf)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t i, val;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	val = 0;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	if (byte_cnt > 16) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Reading from eeprom is is limited to 0xf\n");
+		return (-EINVAL);
+	}
+	/* Set the read command byte count. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, (byte_cnt | 0xa000));
+
+	/* Set the read command address. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
+
+	/* Activate read command. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x2c0f);
+
+	/* Wait up to 500us for command complete status. */
+	for (i = 0; i < 100; i++) {
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
+			break;
+		DELAY(5);
+	}
+
+	if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
+	    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Got bad status 0x%x when reading from SFP+ EEPROM\n",
+		    (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+		return (-EINVAL);
+	}
+
+	/* Read the buffer. */
+	for (i = 0; i < byte_cnt; i++) {
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i,
+		    &val);
+		o_buf[i] = (uint8_t)(val &
+		    MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
+	}
+
+	for (i = 0; i < 100; i++) {
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
+			return (0);
+		msleep(1);
+	}
+	return (-EINVAL);
+}
+
+static uint8_t
+bxe_8727_read_sfp_module_eeprom(struct link_params *params, uint16_t addr,
+    uint8_t byte_cnt, uint8_t *o_buf)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t val, i;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	if (byte_cnt > 16) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Reading from eeprom is is limited to 0xf\n");
+		return (-EINVAL);
+	}
+
+	/* Need to read from 1.8000 to clear it. */
+	bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
+	    &val);
+
+	/* Set the read command byte count. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
+	    ((byte_cnt < 2) ? 2 : byte_cnt));
+
+	/* Set the read command address. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
+	/* Set the destination address. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
+
+	/* Activate read command. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
+	/*
+	 * Wait appropriate time for two-wire command to finish before
+	 * polling the status register.
+	 */
+	msleep(1);
+
+	/* Wait up to 500us for command complete status. */
+	for (i = 0; i < 100; i++) {
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
+			break;
+		DELAY(5);
+	}
+
+	if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
+	    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Got bad status 0x%x when reading from SFP+ EEPROM\n",
+		    (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
+		return (-EINVAL);
+	}
+
+	/* Read the buffer. */
+	for (i = 0; i < byte_cnt; i++) {
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i,
+		    &val);
+		o_buf[i] = (uint8_t)(val &
+		    MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
+	}
+
+	for (i = 0; i < 100; i++) {
+		bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
+		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
+		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
+			return (0);
+		msleep(1);
+	}
+
+	return (-EINVAL);
+}
+
+uint8_t
+bxe_read_sfp_module_eeprom(struct link_params *params, uint16_t addr,
+    uint8_t byte_cnt, uint8_t *o_buf)
+{
+	uint32_t ext_phy_type;
+
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+	if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
+		return (bxe_8726_read_sfp_module_eeprom(params, addr, byte_cnt,
+		    o_buf));
+	else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
+		return (bxe_8727_read_sfp_module_eeprom(params, addr, byte_cnt,
+		    o_buf));
+	return (-EINVAL);
+}
+
+static uint8_t
+bxe_get_edc_mode(struct link_params *params, uint16_t *edc_mode)
+{
+#ifdef BXE_DEBUG
+	struct bxe_softc *sc = params->sc;
+#endif
+	uint8_t copper_module_type;
+	uint8_t options[SFP_EEPROM_OPTIONS_SIZE];
+	uint8_t val, check_limiting_mode;
+
+	check_limiting_mode = 0;
+	*edc_mode = EDC_MODE_LIMITING;
+
+	/* First check for copper cable. */
+	if (bxe_read_sfp_module_eeprom(params, SFP_EEPROM_CON_TYPE_ADDR, 1,
+	    &val) != 0) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Failed to read from SFP+ module EEPROM\n");
+		return (-EINVAL);
+	}
+
+	switch (val) {
+	case SFP_EEPROM_CON_TYPE_VAL_COPPER:
+		/*
+		 * Check if its active cable( includes SFP+ module)
+		 * of passive cable.
+		 */
+		if (bxe_read_sfp_module_eeprom(params,
+		    SFP_EEPROM_FC_TX_TECH_ADDR, 1, &copper_module_type) != 0) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Failed to read copper-cable-type"
+			    " from SFP+ EEPROM\n");
+			return (-EINVAL);
+		}
+
+		if (copper_module_type &
+		    SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Active Copper cable detected\n");
+			check_limiting_mode = 1;
+		} else if (copper_module_type &
+		    SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Passive Copper cable detected\n");
+			*edc_mode = EDC_MODE_PASSIVE_DAC;
+		} else {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Unknown copper-cable-type 0x%x !!!\n",
+			    copper_module_type);
+			return (-EINVAL);
+		}
+		break;
+	case SFP_EEPROM_CON_TYPE_VAL_LC:
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Optic module detected\n");
+		check_limiting_mode = 1;
+		break;
+	default:
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Unable to determine module type 0x%x !!!\n", val);
+		return (-EINVAL);
+	}
+
+	if (check_limiting_mode) {
+		if (bxe_read_sfp_module_eeprom(params, SFP_EEPROM_OPTIONS_ADDR,
+		    SFP_EEPROM_OPTIONS_SIZE, options) != 0) {
+			DBPRINT(sc, BXE_VERBOSE_PHY, "Failed to read Option"
+			    " field from module EEPROM\n");
+			return (-EINVAL);
+		}
+		if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
+			*edc_mode = EDC_MODE_LINEAR;
+		else
+			*edc_mode = EDC_MODE_LIMITING;
+	}
+	DBPRINT(sc, BXE_VERBOSE_PHY, "EDC mode is set to 0x%x\n", *edc_mode);
+	return (0);
+}
+
+/*
+ * This function read the relevant field from the module ( SFP+ ),
+ * and verify it is compliant with this board.
+ */
+static uint8_t bxe_verify_sfp_module(struct link_params *params)
+{
+	struct bxe_softc *sc = params->sc;
+	uint32_t val;
+	/* uint32_t fw_resp; */
+	char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE + 1];
+	char vendor_pn[SFP_EEPROM_PART_NO_SIZE + 1];
+
+	sc = params->sc;
+	val = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
+	    dev_info.port_feature_config[params->port].config));
+	if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+	    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "NOT enforcing module verification\n");
+		return (0);
+	}
+
+	/* Ask the FW to validate the module. */
+	if (!(params->feature_config_flags &
+	    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "FW does not support OPT MDL verification\n");
+		return (-EINVAL);
+	}
+	/* Format the warning message. */
+	if (bxe_read_sfp_module_eeprom(params, SFP_EEPROM_VENDOR_NAME_ADDR,
+	    SFP_EEPROM_VENDOR_NAME_SIZE, (uint8_t *)vendor_name))
+		vendor_name[0] = '\0';
+	else
+		vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
+	if (bxe_read_sfp_module_eeprom(params, SFP_EEPROM_PART_NO_ADDR,
+	    SFP_EEPROM_PART_NO_SIZE, (uint8_t *)vendor_pn))
+		vendor_pn[0] = '\0';
+	else
+		vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
+
+	printf("Warning: Unqualified SFP+ module detected on %s, "
+	    "Port %d from %s part number %s\n", sc->name, params->port,
+	    vendor_name, vendor_pn);
+	return (-EINVAL);
+}
+
+static uint8_t
+bxe_bcm8726_set_limiting_mode(struct link_params *params, uint16_t edc_mode)
+{
+	struct bxe_softc *sc;
+	uint16_t cur_limiting_mode;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+	bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2,
+	    &cur_limiting_mode);
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Current Limiting mode is 0x%x\n",
+	    cur_limiting_mode);
+
+	if (edc_mode == EDC_MODE_LIMITING) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Setting LIMITING MODE\n");
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+		    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2,
+		    EDC_MODE_LIMITING);
+	} else { /* LRM mode ( default )*/
+
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Setting LRM MODE\n");
+
+		/*
+		 * Changing to LRM mode takes quite few seconds.
+		 * So do it only if current mode is limiting
+		 * ( default is LRM ).
+		 */
+		if (cur_limiting_mode != EDC_MODE_LIMITING)
+			return (0);
+
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+		    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+		    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+		    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL0,
+		    0x4008);
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+		    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE,
+		    0xaaaa);
+	}
+	return (0);
+}
+
+static uint8_t
+bxe_bcm8727_set_limiting_mode(struct link_params *params, uint16_t edc_mode)
+{
+	struct bxe_softc *sc;
+	uint8_t ext_phy_addr, port;
+	uint16_t phy_identifier;
+	uint16_t rom_ver2_val;
+
+	sc = params->sc;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+	bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+	    &phy_identifier);
+
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+	    (phy_identifier & ~(1 << 9)));
+
+	bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
+	/* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode. */
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2,
+	    (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
+
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+	    (phy_identifier | (1<<9)));
+
+	return (0);
+}
+
+static uint8_t
+bxe_wait_for_sfp_module_initialized(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint16_t timeout;
+	uint8_t val;
+
+	sc = params->sc;
+	/*
+	 * Initialization time after hot-plug may take up to 300ms for some
+	 * phys type ( e.g. JDSU ).
+	 */
+	for (timeout = 0; timeout < 60; timeout++) {
+		if (bxe_read_sfp_module_eeprom(params, 1, 1, &val)
+		    == 0) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "SFP+ module initialization took %d ms\n",
+			    timeout * 5);
+			return (0);
+		}
+		msleep(5);
+	}
+	return (-EINVAL);
+}
+
+/* Make sure GPIOs are not using for LED mode. */
+static void
+bxe_8727_power_module(struct bxe_softc *sc, struct link_params *params,
+    uint8_t ext_phy_addr, uint8_t is_power_up)
+{
+	uint16_t val;
+	uint8_t port;
+
+	port = params->port;
+	/*
+	 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
+	 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
+	 * output
+	 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
+	 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
+	 * where the 1st bit is the over-current(only input), and 2nd bit is
+	 * for power( only output ).
+	 */
+
+	/*
+	 * In case of NOC feature is disabled and power is up, set GPIO control
+	 *  as input to enable listening of over-current indication.
+	 */
+
+	if (!(params->feature_config_flags & FEATURE_CONFIG_BCM8727_NOC) &&
+	    is_power_up)
+		val = (1<<4);
+	else
+		/*
+		 * Set GPIO control to OUTPUT, and set the power bit
+		 * to according to the is_power_up.
+		 */
+		val = ((!(is_power_up)) << 1);
+
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
+}
+
+static uint8_t
+bxe_sfp_module_detection(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type, val;
+	uint16_t edc_mode;
+	uint8_t ext_phy_addr, rc;
+
+	sc = params->sc;
+	rc = 0;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+	val = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
+	    dev_info.port_feature_config[params->port].config));
+
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "SFP+ module plugged in/out detected on port %d\n", params->port);
+
+	if (bxe_get_edc_mode(params, &edc_mode) != 0) {
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Failed to get valid module type\n");
+		return (-EINVAL);
+	} else if (bxe_verify_sfp_module(params) != 0) {
+		/* Check SFP+ module compatibility. */
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Module verification failed!!\n");
+		rc = -EINVAL;
+		/* Turn on fault module-detected led. */
+		bxe_set_gpio(sc, MISC_REGISTERS_GPIO_0,
+		    MISC_REGISTERS_GPIO_HIGH, params->port);
+		if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
+		    ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+		    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
+			/* Shutdown SFP+ module. */
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Shutdown SFP+ module!!\n");
+			bxe_8727_power_module(sc, params, ext_phy_addr, 0);
+			return (rc);
+		}
+	} else {
+		/* Turn off fault module-detected led. */
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "Turn off fault module-detected led\n");
+		bxe_set_gpio(sc, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW,
+		    params->port);
+	}
+
+	/* Power up the SFP module. */
+	if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
+		bxe_8727_power_module(sc, params, ext_phy_addr, 1);
+
+	/*
+	 * Check and set limiting mode / LRM mode on 8726.
+	 * On 8727 it is done automatically.
+	 */
+	if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
+		bxe_bcm8726_set_limiting_mode(params, edc_mode);
+	else
+		bxe_bcm8727_set_limiting_mode(params, edc_mode);
+	/*
+	 * Enable transmit for this module if the module is approved, or
+	 * if unapproved modules should also enable the Tx laser.
+	 */
+	if (rc == 0 || (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
+	    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+		bxe_sfp_set_transmitter(sc, params->port, ext_phy_type,
+		    ext_phy_addr, 1);
+	else
+		bxe_sfp_set_transmitter(sc, params->port, ext_phy_type,
+		    ext_phy_addr, 0);
+
+	return (rc);
+}
+
+void
+bxe_handle_module_detect_int(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type, gpio_val, val;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	port = params->port;
+
+	/* Set valid module led off. */
+	bxe_set_gpio(sc, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_HIGH,
+	    params->port);
+
+	/* Get current gpio val refelecting module plugged in / out. */
+	gpio_val = bxe_get_gpio(sc,  MISC_REGISTERS_GPIO_3, port);
+
+	/* Call the handling function in case module is detected. */
+	if (gpio_val == 0) {
+		bxe_set_gpio_int(sc, MISC_REGISTERS_GPIO_3,
+		    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, port);
+
+		if (bxe_wait_for_sfp_module_initialized(params) == 0)
+			bxe_sfp_module_detection(params);
+		else
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "SFP+ module is not initialized\n");
+	} else {
+		ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+		ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+		val = REG_RD(sc, params->shmem_base +
+		    offsetof(struct shmem_region,
+		    dev_info.port_feature_config[params->port].config));
+
+		bxe_set_gpio_int(sc, MISC_REGISTERS_GPIO_3,
+		    MISC_REGISTERS_GPIO_INT_OUTPUT_SET, port);
+		/* Module was plugged out. */
+		/* Disable transmit for this module. */
+		if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+		    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+			bxe_sfp_set_transmitter(sc, params->port, ext_phy_type,
+			    ext_phy_addr, 0);
+	}
+}
+
+static void
+bxe_bcm807x_force_10G(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	/* Force KR or KX. */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_CTRL, 0x2040);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_10G_CTRL2, 0x000b);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
+	    MDIO_PMA_REG_BCM_CTRL, 0x0000);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD,
+	    MDIO_AN_REG_CTRL, 0x0000);
+}
+
+static void
+bxe_bcm8073_set_xaui_low_power_mode(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t val;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	port = params->port;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	bxe_cl45_read(sc, params->port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
+
+	if (val == 0) {
+		/* Mustn't set low power mode in 8073 A0. */
+		return;
+	}
+
+	/* Disable PLL sequencer (use read-modify-write to clear bit 13). */
+	bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    MDIO_XS_PLL_SEQUENCER, &val);
+	val &= ~(1 << 13);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    MDIO_XS_PLL_SEQUENCER, val);
+
+	/* PLL controls */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x805E, 0x1077);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x805D, 0x0000);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x805C, 0x030B);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x805B, 0x1240);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x805A, 0x2490);
+
+	/* Tx Controls */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x80A7, 0x0C74);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x80A6, 0x9041);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x80A5, 0x4640);
+
+	/* Rx Controls */
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x80FE, 0x01C4);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x80FD, 0x9249);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    0x80FC, 0x2015);
+
+	/* Enable PLL sequencer (use read-modify-write to set bit 13). */
+	bxe_cl45_read(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    MDIO_XS_PLL_SEQUENCER, &val);
+	val |= (1 << 13);
+	bxe_cl45_write(sc, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD,
+	    MDIO_XS_PLL_SEQUENCER, val);
+}
+
+static void
+bxe_8073_set_pause_cl37(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t cl37_val;
+	uint8_t ext_phy_addr;
+
+	sc = params->sc;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	bxe_cl45_read(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
+
+	cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
+
+	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
+	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC)
+		cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
+	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
+		cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
+		cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Ext phy AN advertize cl37 0x%x\n",
+	    cl37_val);
+
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
+	msleep(500);
+}
+
+static void
+bxe_ext_phy_set_pause(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t val;
+	uint8_t ext_phy_addr;
+
+	sc = params->sc;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	/* Read modify write pause advertizing. */
+	bxe_cl45_read(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
+
+	val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
+
+	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
+
+	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
+		val |=  MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
+	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
+		val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Ext phy AN advertize 0x%x\n", val);
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
+}
+
+static void
+bxe_set_preemphasis(struct link_params *params)
+{
+	struct bxe_softc *sc = params->sc;
+	uint16_t bank, i;
+
+	sc = params->sc;
+	for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
+	    bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr, bank,
+		    MDIO_RX0_RX_EQ_BOOST, params->xgxs_config_rx[i]);
+	}
+
+	for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
+	    bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
+		CL45_WR_OVER_CL22(sc, params->port, params->phy_addr, bank,
+		    MDIO_TX0_TX_DRIVER, params->xgxs_config_tx[i]);
+	}
+}
+
+static void
+bxe_8481_set_led4(struct link_params *params, uint32_t ext_phy_type,
+    uint8_t ext_phy_addr)
+{
+	struct bxe_softc *sc;
+
+	sc = params->sc;
+	/* PHYC_CTL_LED_CTL */
+
+	/* Enable continous signal to go active on link. */
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
+
+	/* Unmask LED4 for 10G link. */
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_SIGNAL_MASK, (1 << 6));
+	/* Unmask LED4 for 10G link. */
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_AN_DEVAD, 0xFFFB, 0xFFFD);
+}
+
+static void
+bxe_8481_set_legacy_led_mode(struct link_params *params, uint32_t ext_phy_type,
+    uint8_t ext_phy_addr)
+{
+	struct bxe_softc *sc;
+
+	sc = params->sc;
+	/*
+	 * LED1 (10G Link): Disable LED1 when 10/100/1000 link.
+	 * LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link).
+	 */
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_SHADOW, (1<<15) |
+	    (0xd << 10) | (0xc<<4) | 0xe);
+}
+
+static void
+bxe_8481_set_10G_led_mode(struct link_params *params, uint32_t ext_phy_type,
+    uint8_t ext_phy_addr)
+{
+	struct bxe_softc *sc;
+	uint16_t val1;
+
+	sc = params->sc;
+	/*
+	 * LED1 (10G Link)
+	 * Enable continuse based on source 7(10G-link).
+	 */
+	bxe_cl45_read(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val1);
+	/* Set bit 2 to 0, and bits [1:0] to 10. */
+	val1 &= ~((1<<0) | (1<<2) | (1<<7)); /* Clear bits 0,2,7*/
+	val1 |= ((1<<1) | (1<<6)); /* Set bit 1, 6 */
+
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val1);
+
+	/* Unmask LED1 for 10G link. */
+	bxe_cl45_read(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, &val1);
+	/* Set bit 2 to 0, and bits [1:0] to 10. */
+	val1 |= (1<<7);
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, val1);
+
+	/*
+	 * LED2 (1G/100/10G Link).
+	 * Mask LED2 for 10G link.
+	 */
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0);
+
+	/* Unmask LED3 for 10G link. */
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x6);
+	bxe_cl45_write(sc, params->port, ext_phy_type, ext_phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0);
+}
+
+static void
+bxe_init_internal_phy(struct link_params *params, struct link_vars *vars,
+    uint8_t enable_cl73)
+{
+	struct bxe_softc *sc;
+
+	sc = params->sc;
+	if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
+		if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
+		    (params->feature_config_flags &
+		    FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
+			bxe_set_preemphasis(params);
+
+		/* Forced speed requested? */
+		if (vars->line_speed != SPEED_AUTO_NEG ||
+		    ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
+		    params->loopback_mode == LOOPBACK_EXT)) {
+			DBPRINT(sc, BXE_INFO, "not SGMII, no AN\n");
+
+			/* Disable autoneg. */
+			bxe_set_autoneg(params, vars, 0);
+
+			/* Program speed and duplex. */
+			bxe_program_serdes(params, vars);
+
+		} else { /* AN_mode */
+			DBPRINT(sc, BXE_VERBOSE_PHY, "not SGMII, AN\n");
+
+			/* AN enabled. */
+			bxe_set_brcm_cl37_advertisment(params);
+
+			/* Program duplex & pause advertisement (for aneg). */
+			bxe_set_ieee_aneg_advertisment(params, vars->ieee_fc);
+
+			/* Enable autoneg. */
+			bxe_set_autoneg(params, vars, enable_cl73);
+
+			/* Enable and restart AN. */
+			bxe_restart_autoneg(params, enable_cl73);
+		}
+
+	} else { /* SGMII mode */
+		DBPRINT(sc, BXE_VERBOSE_PHY, "SGMII\n");
+
+		bxe_initialize_sgmii_process(params, vars);
+	}
+}
+
+static uint8_t
+bxe_ext_phy_init(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t cnt, ctrl, reg, val;
+	uint16_t fw_ver1, fw_ver2;
+	uint16_t lasi_ctrl_val, rx_alarm_ctrl_val, tmp1;
+	uint16_t mod_abs, phy_ver;
+	uint16_t autoneg_val, an_1000_val, an_10_100_val;
+	uint16_t autoneg_ctrl, pma_ctrl;
+	uint8_t ext_phy_addr, i, rc;
+
+	sc = params->sc;
+	ctrl = 0;
+	val = 0;
+	rc = 0;
+
+	if (vars->phy_flags & PHY_XGXS_FLAG) {
+		ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+
+		ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+		/*
+		 * Make sure that the soft reset is off (expect for the 8072:
+		 * due to the lock, it will be done inside the specific
+		 * handling).
+		 */
+		if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
+		    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
+		    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
+		    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
+		    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
+			/* Wait for soft reset to get cleared upto 1 sec. */
+			for (cnt = 0; cnt < 1000; cnt++) {
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_CTRL, &ctrl);
+				if (!(ctrl & (1<<15)))
+					break;
+				msleep(1);
+			}
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "control reg 0x%x (after %d ms)\n", ctrl, cnt);
+		}
+
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 8705\n");
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_MISC_CTRL, 0x8288);
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_WIS_DEVAD,
+			    MDIO_WIS_REG_LASI_CNTL, 0x1);
+
+			/* BCM8705 doesn't have microcode, hence the 0. */
+			bxe_save_spirom_version(sc, params->port,
+			    params->shmem_base, 0);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+			/* Wait until fw is loaded. */
+			for (cnt = 0; cnt < 100; cnt++) {
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_ROM_VER1, &val);
+				if (val)
+					break;
+				msleep(10);
+			}
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "XGXS 8706 is initialized after %d ms\n", cnt);
+			if ((params->feature_config_flags &
+			    FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
+				for (i = 0; i < 4; i++) {
+					reg = MDIO_XS_8706_REG_BANK_RX0 +
+					    i * (MDIO_XS_8706_REG_BANK_RX1 -
+					    MDIO_XS_8706_REG_BANK_RX0);
+					bxe_cl45_read(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_XS_DEVAD, reg, &val);
+					/* Clear first 3 bits of the control. */
+					val &= ~0x7;
+					/*
+					 * Set control bits according to
+					 * configuation.
+					 */
+					val |= (params->xgxs_config_rx[i] &
+					    0x7);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+		"Setting RX Equalizer to BCM8706 reg 0x%x <-- val 0x%x\n",
+					    reg, val);
+					bxe_cl45_write(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_XS_DEVAD, reg, val);
+				}
+			}
+			/* Force speed */
+			if (params->req_line_speed == SPEED_10000) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "XGXS 8706 force 10Gbps\n");
+
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_LASI_CTRL, 1);
+			} else {
+				/*
+				 * Force 1Gbps using autoneg with 1G
+				 * advertisment.
+				 */
+
+				/* Allow CL37 through CL73. */
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "XGXS 8706 AutoNeg\n");
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CL37_CL73, 0x040c);
+
+				/* Enable Full-Duplex advertisment on CL37. */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CL37_FC_LP, 0x0020);
+				/* Enable CL37 AN. */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CL37_AN, 0x1000);
+				/* 1G support */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_ADV, (1 << 5));
+
+				/* Enable clause 73 AN. */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CTRL, 0x1200);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_RX_ALARM_CTRL, 0x0400);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_LASI_CTRL, 0x0004);
+
+			}
+			bxe_save_bcm_spirom_ver(sc, params->port, ext_phy_type,
+			    ext_phy_addr, params->shmem_base);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "Initializing BCM8726\n");
+			bxe_bcm8726_external_rom_boot(params);
+
+			/*
+			 * Need to call module detected on initialization since
+			 * the module detection triggered by actual module
+			 * insertion might occur before driver is loaded, and
+			 * when driver is loaded, it reset all registers,
+			 * including the transmitter.
+			 */
+			bxe_sfp_module_detection(params);
+
+			/* Set Flow control */
+			bxe_ext_phy_set_pause(params, vars);
+			if (params->req_line_speed == SPEED_1000) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Setting 1G force\n");
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_CTRL, 0x40);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_10G_CTRL2, 0xD);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_LASI_CTRL, 0x5);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_RX_ALARM_CTRL, 0x400);
+			} else if ((params->req_line_speed == SPEED_AUTO_NEG) &&
+			    ((params->speed_cap_mask &
+			    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Setting 1G clause37 \n");
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_ADV, 0x20);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CL37_CL73, 0x040c);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CL37_FC_LD, 0x0020);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CL37_AN, 0x1000);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CTRL, 0x1200);
+
+				/*
+				 * Enable RX-ALARM control to receive
+				 * interrupt for 1G speed change.
+				 */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_LASI_CTRL, 0x4);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_RX_ALARM_CTRL, 0x400);
+
+			} else { /* Default 10G. Set only LASI control */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_LASI_CTRL, 1);
+			}
+
+			/* Set TX PreEmphasis if needed. */
+			if ((params->feature_config_flags &
+			    FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
+				    params->xgxs_config_tx[0],
+				    params->xgxs_config_tx[1]);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_8726_TX_CTRL1,
+				    params->xgxs_config_tx[0]);
+
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_8726_TX_CTRL2,
+				    params->xgxs_config_tx[1]);
+			}
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+			if (ext_phy_type ==
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
+				rx_alarm_ctrl_val = 0x400;
+				lasi_ctrl_val = 0x0004;
+			} else {
+				rx_alarm_ctrl_val = (1<<2);
+				lasi_ctrl_val = 0x0004;
+			}
+
+			/* Enable LASI. */
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_RX_ALARM_CTRL, rx_alarm_ctrl_val);
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
+
+			bxe_8073_set_pause_cl37(params, vars);
+
+			if (ext_phy_type ==
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)
+				bxe_bcm8072_external_rom_boot(params);
+			else {
+				/*
+				 * In case of 8073 with long xaui lines,
+				 * don't set the 8073 xaui low power.
+				 */
+				bxe_bcm8073_set_xaui_low_power_mode(params);
+			}
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_RX_ALARM, &tmp1);
+
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Before rom RX_ALARM(port1):0x%x\n", tmp1);
+
+			/*
+			 * If this is forced speed, set to KR or KX
+			 * (all other are not supported).
+			 */
+			if (params->loopback_mode == LOOPBACK_EXT) {
+				bxe_bcm807x_force_10G(params);
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Forced speed 10G on 807X\n");
+				break;
+			} else {
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_BCM_CTRL, 0x0002);
+			}
+			if (params->req_line_speed != SPEED_AUTO_NEG) {
+				if (params->req_line_speed == SPEED_10000)
+					val = (1 << 7);
+				else if (params->req_line_speed ==
+					   SPEED_2500) {
+					val = (1 << 5);
+					/*
+					 * Note that 2.5G works only
+					 * when used with 1G advertisment.
+					 */
+				} else
+					val = (1 << 5);
+			} else {
+				val = 0;
+				if (params->speed_cap_mask &
+				    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
+					val |= (1 << 7);
+
+				/*
+				 * Note that 2.5G works only when
+				 * used with 1G advertisment.
+				 */
+				if (params->speed_cap_mask &
+				    (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
+				    PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
+					val |= (1 << 5);
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "807x autoneg val = 0x%x\n", val);
+			}
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
+			if (ext_phy_type ==
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8073_2_5G, &tmp1);
+
+				if (((params->speed_cap_mask &
+				    PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
+				    (params->req_line_speed ==
+				    SPEED_AUTO_NEG)) ||
+				    (params->req_line_speed == SPEED_2500)) {
+					/* Allow 2.5G for A1 and above. */
+					bxe_cl45_read(sc, params->port,
+					  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+					    ext_phy_addr, MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_8073_CHIP_REV,
+					    &phy_ver);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Add 2.5G\n");
+					if (phy_ver > 0)
+						tmp1 |= 1;
+					else
+						tmp1 &= 0xfffe;
+				} else {
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Disable 2.5G\n");
+					tmp1 &= 0xfffe;
+				}
+
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8073_2_5G, tmp1);
+			}
+
+			/* Add support for CL37 (passive mode) II. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD,
+			    MDIO_AN_REG_CL37_FC_LD, &tmp1);
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
+			    (tmp1 | ((params->req_duplex == DUPLEX_FULL) ?
+			    0x20 : 0x40)));
+
+			/* Add support for CL37 (passive mode) III. */
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN,
+			    0x1000);
+
+			if (ext_phy_type ==
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+				/*
+				 * The SNR will improve about 2db by changing
+				 * BW and FEE main tap. Rest commands are
+				 * executed after link is up.
+				 */
+				/*
+				 * Change FFE main cursor to 5 in EDC register.
+				 */
+				if (bxe_8073_is_snr_needed(params))
+					bxe_cl45_write(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_EDC_FFE_MAIN, 0xFB0C);
+
+				/*
+				 * Enable FEC (Forware Error Correction)
+				 * Request in the AN.
+				 */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_ADV2, &tmp1);
+				tmp1 |= (1 << 15);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_ADV2, tmp1);
+			}
+
+			bxe_ext_phy_set_pause(params, vars);
+
+			/* Restart autoneg. */
+			msleep(500);
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
+			    0x1200);
+			DBPRINT(sc, BXE_VERBOSE_PHY, "807x Autoneg Restart: "
+			    "Advertise 1G=%x, 10G=%x\n",
+			    ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+			/* Enable PMD link, MOD_ABS_FLT, and 1G link alarm. */
+			rx_alarm_ctrl_val = (1 << 2) | (1 << 5);
+			lasi_ctrl_val = 0x0004;
+
+			DBPRINT(sc, BXE_VERBOSE_PHY, "Initializing BCM8727\n");
+			/* Enable LASI. */
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_RX_ALARM_CTRL, rx_alarm_ctrl_val);
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
+
+			/*
+			 * Initially configure  MOD_ABS to interrupt when
+			 * module is presence( bit 8).
+			 */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
+			/*
+			 * Set EDC off by setting OPTXLOS signal input to low
+			 * (bit 9). When the EDC is off it locks onto a
+			 * reference clock and avoids becoming 'lost'.
+			 */
+			mod_abs &= ~((1 << 8) | (1 << 9));
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
+
+			/* Make MOD_ABS give interrupt on change. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
+			val |= (1 << 12);
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
+
+			/*
+			 * Set 8727 GPIOs to input to allow reading from the
+			 * 8727 GPIO0 status which reflect SFP+ module
+			 * over-current.
+			 */
+			bxe_cl45_read(sc, params->port,
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ext_phy_addr,
+			    MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+			    &val);
+			val &= 0xff8f; /* Reset bits 4-6 */
+			bxe_cl45_write(sc, params->port,
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ext_phy_addr,
+			    MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
+			    val);
+
+			bxe_8727_power_module(sc, params, ext_phy_addr, 1);
+			bxe_bcm8073_set_xaui_low_power_mode(params);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_RX_ALARM, &tmp1);
+
+			/* Set option 1G speed. */
+			if (params->req_line_speed == SPEED_1000) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Setting 1G force\n");
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_CTRL, 0x40);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_10G_CTRL2, 0xD);
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_10G_CTRL2, &tmp1);
+				DBPRINT(sc, BXE_VERBOSE_PHY, "1.7 = 0x%x \n",
+				    tmp1);
+			} else if ((params->req_line_speed == SPEED_AUTO_NEG) &&
+			    ((params->speed_cap_mask &
+			    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Setting 1G clause37 \n");
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_PMA_REG_8727_MISC_CTRL, 0);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CL37_AN, 0x1300);
+			} else {
+				/*
+				 * Since the 8727 has only single reset pin,
+				 * need to set the 10G registers although it
+				 * is default.
+				 */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_CTRL, 0x0020);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    0x7, 0x0100);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_CTRL, 0x2040);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_10G_CTRL2, 0x0008);
+			}
+
+			/*
+			 * Set 2-wire transfer rate to 400Khz since 100Khz
+			 * is not operational.
+			 */
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 0xa101);
+
+			/* Set TX PreEmphasis if needed. */
+			if ((params->feature_config_flags &
+			    FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
+				    params->xgxs_config_tx[0],
+				    params->xgxs_config_tx[1]);
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_8727_TX_CTRL1,
+				    params->xgxs_config_tx[0]);
+
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_8727_TX_CTRL2,
+				    params->xgxs_config_tx[1]);
+			}
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Setting the SFX7101 LASI indication\n");
+
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_CTRL, 0x1);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Setting the SFX7101 LED to blink on traffic\n");
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
+
+			bxe_ext_phy_set_pause(params, vars);
+			/* Restart autoneg. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
+			    &val);
+			val |= 0x200;
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
+
+			/* Save spirom version. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_7101_VER1, &fw_ver1);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_7101_VER2, &fw_ver2);
+
+			bxe_save_spirom_version(params->sc, params->port,
+			    params->shmem_base,
+			    (uint32_t)(fw_ver1 << 16 | fw_ver2));
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
+			/*
+			 * This phy uses the NIG latch mechanism since link
+			 * indication arrives through its LED4 and not via
+			 * its LASI signal, so we get steady signal
+			 * instead of clear on read.
+			 */
+			bxe_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4,
+			    1 << NIG_LATCH_BC_ENABLE_MI_INT);
+			bxe_cl45_write(sc, params->port,
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ext_phy_addr,
+			    MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
+
+			bxe_8481_set_led4(params, ext_phy_type, ext_phy_addr);
+			if (params->req_line_speed == SPEED_AUTO_NEG) {
+				/* Set 1000 speed advertisement. */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_1000T_CTRL, &an_1000_val);
+
+				bxe_ext_phy_set_pause(params, vars);
+				if (params->speed_cap_mask &
+				    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
+					an_1000_val |= (1 << 8);
+					if (params->req_duplex == DUPLEX_FULL)
+						an_1000_val |= (1 << 9);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Advertising 1G\n");
+				} else
+					an_1000_val &= ~((1 << 8) | (1 << 9));
+
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_1000T_CTRL, an_1000_val);
+
+				/* Set 100 speed advertisement. */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_LEGACY_AN_ADV,
+				    &an_10_100_val);
+
+				if (params->speed_cap_mask &
+				  (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
+				  PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
+					an_10_100_val |= (1 << 7);
+					if (params->req_duplex == DUPLEX_FULL)
+						an_10_100_val |= (1 << 8);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Advertising 100M\n");
+				} else
+					an_10_100_val &= ~((1 << 7) | (1 << 8));
+
+				/* Set 10 speed advertisement. */
+				if (params->speed_cap_mask &
+				    (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
+				    PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
+					an_10_100_val |= (1 << 5);
+					if (params->req_duplex == DUPLEX_FULL)
+						an_10_100_val |= (1 << 6);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Advertising 10M\n");
+				} else
+					an_10_100_val &= ~((1 << 5) | (1 << 6));
+
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_LEGACY_AN_ADV,
+				    an_10_100_val);
+
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+				    &autoneg_val);
+
+				/* Disable forced speed. */
+				autoneg_val &= ~(1 << 6 | 1 << 13);
+
+				/*
+				 * Enable autoneg and restart autoneg
+				 * for legacy speeds.
+				 */
+				autoneg_val |= (1 << 9 | 1 << 12);
+
+				if (params->req_duplex == DUPLEX_FULL)
+					autoneg_val |= (1 << 8);
+				else
+					autoneg_val &= ~(1 << 8);
+
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+				    autoneg_val);
+
+				if (params->speed_cap_mask &
+				    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Advertising 10G\n");
+					/* Restart autoneg for 10G */
+					bxe_cl45_write(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_AN_DEVAD,
+					    MDIO_AN_REG_CTRL, val);
+				}
+			} else {
+				/* Force speed */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+				    &autoneg_ctrl);
+
+				/* Disable autoneg. */
+				autoneg_ctrl &= ~(1 << 12);
+
+				/* Set 1000 force. */
+				switch (params->req_line_speed) {
+				case SPEED_10000:
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Unable to set 10G force !\n");
+					break;
+				case SPEED_1000:
+					bxe_cl45_read(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+					    &pma_ctrl);
+					autoneg_ctrl &= ~(1 << 13);
+					autoneg_ctrl |= (1 << 6);
+					pma_ctrl &= ~(1 << 13);
+					pma_ctrl |= (1 << 6);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Setting 1000M force\n");
+					bxe_cl45_write(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+					    pma_ctrl);
+					break;
+				case SPEED_100:
+					autoneg_ctrl |= (1 << 13);
+					autoneg_ctrl &= ~(1 << 6);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Setting 100M force\n");
+					break;
+				case SPEED_10:
+					autoneg_ctrl &= ~(1 << 13);
+					autoneg_ctrl &= ~(1 << 6);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Setting 10M force\n");
+					break;
+				}
+
+				/* Duplex mode */
+				if (params->req_duplex == DUPLEX_FULL) {
+					autoneg_ctrl |= (1 << 8);
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+					    "Setting full duplex\n");
+				} else
+					autoneg_ctrl &= ~(1 << 8);
+
+				/* Update autoneg ctrl and pma ctrl. */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+				    autoneg_ctrl);
+			}
+
+			/* Save spirom version. */
+			bxe_save_8481_spirom_version(sc, params->port,
+			    ext_phy_addr, params->shmem_base);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "XGXS PHY Failure detected 0x%x\n",
+			    params->ext_phy_config);
+			rc = -EINVAL;
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "BAD XGXS ext_phy_config 0x%x\n",
+			    params->ext_phy_config);
+			rc = -EINVAL;
+			break;
+		}
+
+	} else { /* SerDes */
+		ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes Direct\n");
+			break;
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes 5482\n");
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "BAD SerDes ext_phy_config 0x%x\n",
+			    params->ext_phy_config);
+			break;
+		}
+	}
+	return (rc);
+}
+
+static void
+bxe_8727_handle_mod_abs(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t val;
+	uint16_t mod_abs, rx_alarm_status;
+	uint8_t ext_phy_addr;
+
+	sc = params->sc;
+	ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+	val = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
+	    dev_info.port_feature_config[params->port].config));
+
+	bxe_cl45_read(sc, params->port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
+	    &mod_abs);
+	if (mod_abs & (1 << 8)) {
+		/* Module is absent. */
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "MOD_ABS indication show module is absent\n");
+
+		/*
+		 * 1. Set mod_abs to detect next module presence event
+		 * 2. Set EDC off by setting OPTXLOS signal input to low
+		 *    (bit 9).
+		 *    When the EDC is off it locks onto a reference clock and
+		 *    avoids becoming 'lost'.
+		 */
+		mod_abs &= ~((1 << 8) | (1 << 9));
+		bxe_cl45_write(sc, params->port,
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
+
+		/*
+		 * Clear RX alarm since it stays up as long as
+		 * the mod_abs wasn't changed.
+		 */
+		bxe_cl45_read(sc, params->port,
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
+	} else {
+		/* Module is present. */
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "MOD_ABS indication show module is present\n");
+		/*
+		 * First thing, disable transmitter, and if the
+		 * module is ok, the module_detection will enable
+		 * it. */
+
+		/*
+		 * 1. Set mod_abs to detect next module absent event ( bit 8)
+		 * 2. Restore the default polarity of the OPRXLOS signal and
+		 *    this signal will then correctly indicate the presence or
+		 *    absence of the Rx signal. (bit 9)
+		 */
+		mod_abs |= ((1 << 8) | (1 << 9));
+		bxe_cl45_write(sc, params->port,
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
+
+		/*
+		 * Clear RX alarm since it stays up as long as the mod_abs
+		 * wasn't changed. This is need to be done before calling
+		 * the module detection, otherwise it will clear the link
+		 * update alarm.
+		 */
+		bxe_cl45_read(sc, params->port,
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ext_phy_addr,
+		    MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
+
+		if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+		    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+			bxe_sfp_set_transmitter(sc, params->port,
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, ext_phy_addr,
+			    0);
+
+		if (bxe_wait_for_sfp_module_initialized(params) == 0)
+			bxe_sfp_module_detection(params);
+		else
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "SFP+ module is not initialized\n");
+	}
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "8727 RX_ALARM_STATUS 0x%x\n",
+		 rx_alarm_status);
+	/* No need to check link status in case of module plugged in/out. */
+}
+
+static uint8_t
+bxe_ext_phy_is_link_up(struct link_params *params, struct link_vars *vars,
+    uint8_t is_mi_int)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t val1, val2;
+	uint16_t rx_sd, pcs_status;
+	uint16_t link_status;
+	uint16_t rx_alarm_status;
+	uint16_t an1000_status;
+	uint16_t legacy_status, legacy_speed;
+	uint8_t ext_phy_addr, ext_phy_link_up, port;
+
+	sc = params->sc;
+	val1 = 0;
+	ext_phy_link_up = 0;
+	port = params->port;
+
+	if (vars->phy_flags & PHY_XGXS_FLAG) {
+		ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+		ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS Direct\n");
+			ext_phy_link_up = 1;
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 8705\n");
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_WIS_DEVAD,
+			    MDIO_WIS_REG_LASI_STATUS, &val1);
+			DBPRINT(sc, BXE_VERBOSE_PHY, "8705 LASI status 0x%x\n",
+			    val1);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_WIS_DEVAD,
+			    MDIO_WIS_REG_LASI_STATUS, &val1);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "8705 LASI status 0x%x\n", val1);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
+			    &rx_sd);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, 1, 0xc809, &val1);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, 1, 0xc809, &val1);
+
+			DBPRINT(sc, BXE_VERBOSE_PHY, "8705 1.c809 val=0x%x\n",
+			    val1);
+			ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) &&
+			    ((val1 & (1 << 8)) == 0));
+			if (ext_phy_link_up)
+				vars->line_speed = SPEED_10000;
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 8706/8726\n");
+			/* Clear RX Alarm. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
+			    &val2);
+			/* Clear LASI indication. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_STATUS, &val1);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_STATUS, &val2);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "8706/8726 LASI status 0x%x-->0x%x\n", val1, val2);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
+			    &rx_sd);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
+			    &pcs_status);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD,
+			    MDIO_AN_REG_LINK_STATUS, &val2);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD,
+			    MDIO_AN_REG_LINK_STATUS, &val2);
+
+			DBPRINT(sc, BXE_VERBOSE_PHY, "8706/8726 rx_sd 0x%x "
+			    "pcs_status 0x%x 1Gbps link_status 0x%x\n",
+			    rx_sd, pcs_status, val2);
+			/*
+			 * Link is up if both bit 0 of pmd_rx_sd and bit 0
+			 * of pcs_status are set, or if the autoneg bit 1
+			 * is set.
+			 */
+			ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
+			    (val2 & (1 << 1)));
+			if (ext_phy_link_up) {
+				if (ext_phy_type ==
+				     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
+					/*
+					 * If transmitter is disabled,
+					 * ignore false link up indication.
+					 */
+					bxe_cl45_read(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_PHY_IDENTIFIER,
+					    &val1);
+					if (val1 & (1<<15)) {
+						DBPRINT(sc, BXE_VERBOSE_PHY,
+						    "Tx is disabled\n");
+						ext_phy_link_up = 0;
+						break;
+					}
+				}
+				if (val2 & (1 << 1))
+					vars->line_speed = SPEED_1000;
+				else
+					vars->line_speed = SPEED_10000;
+			}
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+			link_status = 0;
+			/* Check the LASI. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
+
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_STATUS, &val1);
+
+			DBPRINT(sc, BXE_VERBOSE_PHY, "8727 LASI status 0x%x\n",
+			    val1);
+
+			/* Clear MSG-OUT */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
+
+			/*
+			 * If a module is present and there is need to check
+			 * for over current.
+			 */
+			if (!(params->feature_config_flags &
+			    FEATURE_CONFIG_BCM8727_NOC) &&
+			    !(rx_alarm_status & (1<<5))) {
+				/* Check over-current using 8727 GPIO0 input. */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_8727_GPIO_CTRL, &val1);
+
+				if ((val1 & (1 << 8)) == 0) {
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+			"8727 Power fault has been detected on port %d\n",
+					    params->port);
+					printf(
+			"Error: Power fault on %s Port %d has been detected "
+			"and the power to that SFP+ module has been removed "
+			"to prevent failure of the card. Please remove the "
+			"SFP+ module and restart the system to clear this "
+			"error.\n",
+					    sc->name, params->port);
+					/*
+					 * Disable all RX_ALARMs except for
+					 * mod_abs.
+					 */
+					bxe_cl45_write(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_RX_ALARM_CTRL,
+					    (1 << 5));
+
+					bxe_cl45_read(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
+					/* Wait for module_absent_event. */
+					val1 |= (1 << 8);
+					bxe_cl45_write(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_PHY_IDENTIFIER, val1);
+					/* Clear RX alarm. */
+					bxe_cl45_read(sc, params->port,
+					    ext_phy_type, ext_phy_addr,
+					    MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_RX_ALARM,
+					    &rx_alarm_status);
+					break;
+				}
+			} /* Over current check */
+
+			/* When module absent bit is set, check module. */
+			if (rx_alarm_status & (1 << 5)) {
+				bxe_8727_handle_mod_abs(params);
+				/*
+				 * Enable all mod_abs and link detection bits.
+				 */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_RX_ALARM_CTRL,
+				    ((1 << 5) | (1 << 2)));
+			}
+
+			/*
+			 * If transmitter is disabled, ignore false link
+			 * up indication.
+			 */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
+			if (val1 & (1 << 15)) {
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Tx is disabled\n");
+				ext_phy_link_up = 0;
+				break;
+			}
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
+
+			/*
+			 * Bits 0..2 --> speed detected,
+			 * bits 13..15--> link is down
+			 */
+			if ((link_status & (1 << 2)) &&
+			    (!(link_status & (1 << 15)))) {
+				ext_phy_link_up = 1;
+				vars->line_speed = SPEED_10000;
+			} else if ((link_status & (1 << 0)) &&
+			    (!(link_status & (1 << 13)))) {
+				ext_phy_link_up = 1;
+				vars->line_speed = SPEED_1000;
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "port %x: External link up in 1G\n",
+				    params->port);
+			} else {
+				ext_phy_link_up = 0;
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "port %x: External link is down\n",
+				    params->port);
+			}
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+			link_status = 0;
+			an1000_status = 0;
+			if (ext_phy_type ==
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PCS_DEVAD,
+				    MDIO_PCS_REG_LASI_STATUS, &val1);
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PCS_DEVAD,
+				    MDIO_PCS_REG_LASI_STATUS, &val2);
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "870x LASI status 0x%x->0x%x\n", val1,
+				    val2);
+			} else {
+				/*
+				 * In 8073, port1 is directed through emac0 and
+				 * port0 is directed through emac1.
+				 */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_LASI_STATUS, &val1);
+
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "8703 LASI status 0x%x\n", val1);
+			}
+
+			/* Clear the interrupt LASI status register. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PCS_DEVAD,
+			    MDIO_PCS_REG_STATUS, &val2);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PCS_DEVAD,
+			    MDIO_PCS_REG_STATUS, &val1);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "807x PCS status 0x%x->0x%x\n", val2, val1);
+			/* Clear MSG-OUT. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
+
+			/* Check the LASI. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
+			    &val2);
+
+			DBPRINT(sc, BXE_VERBOSE_PHY, "KR 0x9003 0x%x\n", val2);
+
+			/* Check the link status. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
+			    &val2);
+			DBPRINT(sc, BXE_VERBOSE_PHY, "KR PCS status 0x%x\n",
+			    val2);
+
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS,
+			    &val2);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS,
+			    &val1);
+			ext_phy_link_up = ((val1 & 4) == 4);
+			DBPRINT(sc, BXE_VERBOSE_PHY, "PMA_REG_STATUS=0x%x\n",
+			    val1);
+			if (ext_phy_type ==
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+				if (ext_phy_link_up &&
+				    ((params->req_line_speed != SPEED_10000))) {
+					if (bxe_bcm8073_xaui_wa(params) != 0) {
+						ext_phy_link_up = 0;
+						break;
+					}
+				}
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_LINK_STATUS, &an1000_status);
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_LINK_STATUS, &an1000_status);
+
+				/* Check the link status on 1.1.2. */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_STATUS, &val2);
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_STATUS, &val1);
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+			"KR PMA status 0x%x->0x%x, an_link_status=0x%x\n",
+				    val2, val1, an1000_status);
+
+				ext_phy_link_up = (((val1 & 4) == 4) ||
+				    (an1000_status & (1 << 1)));
+				if (ext_phy_link_up &&
+				    bxe_8073_is_snr_needed(params)) {
+					/*
+					 * The SNR will improve about 2dbby
+					 * changing the BW and FEE main tap.
+					 *
+					 * The 1st write to change FFE main
+					 * tap is set before restart AN.
+					 * Change PLL Bandwidth in EDC
+					 * register.
+					 */
+					bxe_cl45_write(sc, port, ext_phy_type,
+					    ext_phy_addr, MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_PLL_BANDWIDTH, 0x26BC);
+
+					/*
+					 * Change CDR Bandwidth in EDC register.
+					  */
+					bxe_cl45_write(sc, port, ext_phy_type,
+					    ext_phy_addr, MDIO_PMA_DEVAD,
+					    MDIO_PMA_REG_CDR_BANDWIDTH, 0x0333);
+				}
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_PMA_DEVAD,
+				    MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
+				    &link_status);
+
+				/*
+				 * Bits 0..2 --> speed detected,
+				 * bits 13..15--> link is down
+				 */
+				if ((link_status & (1<<2)) &&
+				    (!(link_status & (1<<15)))) {
+					ext_phy_link_up = 1;
+					vars->line_speed = SPEED_10000;
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+				"port %x: External link up in 10G\n",
+					    params->port);
+				} else if ((link_status & (1<<1)) &&
+				    (!(link_status & (1<<14)))) {
+					ext_phy_link_up = 1;
+					vars->line_speed = SPEED_2500;
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+				"port %x: External link up in 2.5G\n",
+					    params->port);
+				} else if ((link_status & (1<<0)) &&
+				    (!(link_status & (1<<13)))) {
+					ext_phy_link_up = 1;
+					vars->line_speed = SPEED_1000;
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+				"port %x: External link up in 1G\n",
+					    params->port);
+				} else {
+					ext_phy_link_up = 0;
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+				"port %x: External link is down\n",
+					    params->port);
+				}
+			} else {
+				/* See if 1G link is up for the 8072. */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_LINK_STATUS, &an1000_status);
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_LINK_STATUS, &an1000_status);
+				if (an1000_status & (1 << 1)) {
+					ext_phy_link_up = 1;
+					vars->line_speed = SPEED_1000;
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+				"port %x: External link up in 1G\n",
+					    params->port);
+				} else if (ext_phy_link_up) {
+					ext_phy_link_up = 1;
+					vars->line_speed = SPEED_10000;
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+				"port %x: External link up in 10G\n",
+					    params->port);
+				}
+			}
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_STATUS, &val2);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_LASI_STATUS, &val1);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "10G-base-T LASI status 0x%x->0x%x\n", val2, val1);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_STATUS, &val2);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_STATUS, &val1);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "10G-base-T PMA status 0x%x->0x%x\n", val2, val1);
+			ext_phy_link_up = ((val1 & 4) == 4);
+			/*
+			 * if link is up print the AN outcome of the
+			 * SFX7101 PHY.
+			 */
+			if (ext_phy_link_up) {
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_MASTER_STATUS, &val2);
+				vars->line_speed = SPEED_10000;
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "SFX7101 AN status 0x%x->Master=%x\n",
+				    val2, (val2 & (1 << 14)));
+			}
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
+			/* Check 10G-BaseT link status. */
+			/* Check PMD signal ok. */
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_AN_DEVAD, 0xFFFA, &val1);
+			bxe_cl45_read(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD,
+			    MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
+
+			/* Check link 10G. */
+			if (val2 & (1 << 11)) {
+				vars->line_speed = SPEED_10000;
+				ext_phy_link_up = 1;
+				bxe_8481_set_10G_led_mode(params, ext_phy_type,
+				    ext_phy_addr);
+			} else { /* Check Legacy speed link */
+				/*
+				 * Enable expansion register 0x42
+				 * (Operation mode status).
+				 */
+				bxe_cl45_write(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
+				    0xf42);
+
+				/* Get legacy speed operation status. */
+				bxe_cl45_read(sc, params->port, ext_phy_type,
+				    ext_phy_addr, MDIO_AN_DEVAD,
+				    MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
+				    &legacy_status);
+
+				DBPRINT(sc, BXE_VERBOSE_PHY,
+				    "Legacy speed status = 0x%x\n",
+				    legacy_status);
+				ext_phy_link_up = ((legacy_status &
+				    (1 << 11)) == (1<<11));
+				if (ext_phy_link_up) {
+					legacy_speed = (legacy_status &
+					    (3 << 9));
+					if (legacy_speed == (0 << 9))
+						vars->line_speed = SPEED_10;
+					else if (legacy_speed == (1 << 9))
+						vars->line_speed = SPEED_100;
+					else if (legacy_speed == (2 << 9))
+						vars->line_speed = SPEED_1000;
+					else /* Should not happen */
+						vars->line_speed = 0;
+					if (legacy_status & (1 << 8))
+						vars->duplex = DUPLEX_FULL;
+					else
+						vars->duplex = DUPLEX_HALF;
+
+					DBPRINT(sc, BXE_VERBOSE_PHY,
+				"Link is up in %dMbps, is_duplex_full = %d\n",
+					    vars->line_speed,
+					    (vars->duplex == DUPLEX_FULL));
+					bxe_8481_set_legacy_led_mode(params,
+					    ext_phy_type, ext_phy_addr);
+				}
+			}
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "BAD XGXS ext_phy_config 0x%x\n",
+			    params->ext_phy_config);
+			ext_phy_link_up = 0;
+			break;
+		}
+		/* Set SGMII mode for external phy */
+		if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
+			if (vars->line_speed < SPEED_1000)
+				vars->phy_flags |= PHY_SGMII_FLAG;
+			else
+				vars->phy_flags &= ~PHY_SGMII_FLAG;
+		}
+
+	} else { /* SerDes */
+		ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes Direct\n");
+			ext_phy_link_up = 1;
+			break;
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes 5482\n");
+			ext_phy_link_up = 1;
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "BAD SerDes ext_phy_config 0x%x\n",
+			    params->ext_phy_config);
+			ext_phy_link_up = 0;
+			break;
+		}
+	}
+
+	return (ext_phy_link_up);
+}
+
+static void
+bxe_link_int_enable(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type, mask;
+	uint8_t port;
+
+	sc = params->sc;
+	port = params->port;
+
+	/* Setting the status to report on link up for either XGXS or SerDes. */
+
+	if (params->switch_cfg == SWITCH_CFG_10G) {
+		mask = (NIG_MASK_XGXS0_LINK10G | NIG_MASK_XGXS0_LINK_STATUS);
+		DBPRINT(sc, BXE_VERBOSE_PHY, "enabled XGXS interrupt\n");
+		ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+		if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
+		    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
+		    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
+			mask |= NIG_MASK_MI_INT;
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "enabled external phy int\n");
+		}
+	} else { /* SerDes */
+		mask = NIG_MASK_SERDES0_LINK_STATUS;
+		DBPRINT(sc, BXE_VERBOSE_PHY, "enabled SerDes interrupt\n");
+		ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+		if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
+		    (ext_phy_type !=
+		    PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
+			mask |= NIG_MASK_MI_INT;
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "enabled external phy int\n");
+		}
+	}
+	bxe_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "port %x, is_xgxs %x, int_status 0x%x\n",
+	    port, (params->switch_cfg == SWITCH_CFG_10G), REG_RD(sc,
+	    NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
+	DBPRINT(sc, BXE_VERBOSE_PHY, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
+	    REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
+	    REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
+	    REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
+	DBPRINT(sc, BXE_VERBOSE_PHY, " 10G %x, XGXS_LINK %x\n",
+	    REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
+	    REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
+}
+
+static void
+bxe_8481_rearm_latch_signal(struct bxe_softc *sc, uint8_t port,
+uint8_t is_mi_int)
+{
+	uint32_t latch_status, is_mi_int_status;
+
+	latch_status = 0;
+
+	/*
+	 * Disable the MI INT ( external phy int )
+	 * by writing 1 to the status register. Link down indication
+	 * is high-active-signal, so in this case we need to write
+	 * the status to clear the XOR.
+	 */
+	/* Read Latched signals. */
+	latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
+	is_mi_int_status = REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
+	    port * 4);
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "original_signal = 0x%x, nig_status = 0x%x, latch_status = 0x%x\n",
+	    is_mi_int, is_mi_int_status, latch_status);
+	/* Handle only those with latched-signal=up. */
+	if (latch_status & 1) {
+		/* For all latched-signal=up,Write original_signal to status. */
+		if (is_mi_int)
+			bxe_bits_en(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
+			    port * 4, NIG_STATUS_EMAC0_MI_INT);
+		else
+			bxe_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
+			    port * 4, NIG_STATUS_EMAC0_MI_INT);
+		/* For all latched-signal=up : Re-Arm Latch signals. */
+		REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8,
+		    (latch_status & 0xfffe) | (latch_status & 1));
+	}
+}
+
+/*
+ * Link management
+ */
+static void
+bxe_link_int_ack(struct link_params *params, struct link_vars *vars,
+    uint8_t is_10g, uint8_t is_mi_int)
+{
+	struct bxe_softc *sc;
+	uint32_t ser_lane;
+	uint8_t port;
+
+	sc = params->sc;
+	port = params->port;
+
+	/*
+	 * First reset all status, we assume only one line will be
+	 * change at a time.
+	 */
+	bxe_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
+	    (NIG_STATUS_XGXS0_LINK10G | NIG_STATUS_XGXS0_LINK_STATUS |
+	     NIG_STATUS_SERDES0_LINK_STATUS));
+	if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+	    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
+	    (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+	    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823))
+		bxe_8481_rearm_latch_signal(sc, port, is_mi_int);
+	if (vars->phy_link_up) {
+		if (is_10g) {
+			/*
+			 * Disable the 10G link interrupt by writing 1 to
+			 * the status register.
+			 */
+			DBPRINT(sc, BXE_VERBOSE_PHY, "10G XGXS phy link up\n");
+			bxe_bits_en(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
+			    port * 4, NIG_STATUS_XGXS0_LINK10G);
+		} else if (params->switch_cfg == SWITCH_CFG_10G) {
+			/*
+			 * Disable the link interrupt by writing 1 to
+			 * the relevant lane in the status register.
+			 */
+			ser_lane = ((params->lane_config &
+			    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+			    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "%d speed XGXS phy link up\n", vars->line_speed);
+			bxe_bits_en(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
+			    port * 4, ((1 << ser_lane) <<
+			    NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
+		} else { /* SerDes */
+			DBPRINT(sc, BXE_VERBOSE_PHY, "SerDes phy link up\n");
+			/*
+			 * Disable the link interrupt by writing 1 to
+			 * the status register.
+			 */
+			bxe_bits_en(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
+			    port * 4, NIG_STATUS_SERDES0_LINK_STATUS);
+		}
+
+	} else { /* link_down */
+	}
+}
+
+static uint8_t
+bxe_format_ver(uint32_t num, uint8_t *str, uint16_t len)
+{
+	uint32_t mask;
+	uint8_t *str_ptr;
+	uint8_t digit, shift;
+
+	str_ptr = str;
+	mask = 0xf0000000;
+	shift = 8 * 4;
+	if (len < 10) {
+		/* Need more than 10 chars for this format. */
+		*str_ptr = '\0';
+		return (-EINVAL);
+	}
+	while (shift > 0) {
+		shift -= 4;
+		digit = ((num & mask) >> shift);
+		if (digit < 0xa)
+			*str_ptr = digit + '0';
+		else
+			*str_ptr = digit - 0xa + 'a';
+		str_ptr++;
+		mask = mask >> 4;
+		if (shift == 4*4) {
+			*str_ptr = ':';
+			str_ptr++;
+		}
+	}
+	*str_ptr = '\0';
+	return (0);
+}
+
+uint8_t
+bxe_get_ext_phy_fw_version(struct link_params *params, uint8_t driver_loaded,
+    uint8_t *version, uint16_t len)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type, spirom_ver;
+	uint8_t status;
+
+	sc = params->sc;
+	if (version == NULL || params == NULL)
+		return (-EINVAL);
+
+	spirom_ver = REG_RD(sc, params->shmem_base +
+	    offsetof(struct shmem_region,
+	    port_mb[params->port].ext_phy_fw_version));
+
+	status = 0;
+	/* Reset the returned value to zero. */
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+	switch (ext_phy_type) {
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+		if (len < 5)
+			return (-EINVAL);
+		version[0] = (spirom_ver & 0xFF);
+		version[1] = (spirom_ver & 0xFF00) >> 8;
+		version[2] = (spirom_ver & 0xFF0000) >> 16;
+		version[3] = (spirom_ver & 0xFF000000) >> 24;
+		version[4] = '\0';
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+		status = bxe_format_ver(spirom_ver, version, len);
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
+		spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
+		    (spirom_ver & 0x7F);
+		status = bxe_format_ver(spirom_ver, version, len);
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+		version[0] = '\0';
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "bxe_get_ext_phy_fw_version: type is FAILURE!\n");
+		status = -EINVAL;
+		break;
+	default:
+		break;
+	}
+	return (status);
+}
+
+static void
+bxe_set_xgxs_loopback(struct link_params *params, struct link_vars *vars,
+    uint8_t is_10g)
+{
+	struct bxe_softc *sc;
+	uint32_t md_devad;
+	uint16_t mii_control;
+	uint8_t port;
+
+	sc = params->sc;
+	port = params->port;
+
+	if (is_10g) {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 10G loopback enable\n");
+
+		/* Change the uni_phy_addr in the nig. */
+		md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
+		    port * 0x18));
+
+		REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18, 0x5);
+
+		bxe_cl45_write(sc, port, 0, params->phy_addr, 5,
+		    (MDIO_REG_BANK_AER_BLOCK + (MDIO_AER_BLOCK_AER_REG & 0xf)),
+		    0x2800);
+
+		bxe_cl45_write(sc, port, 0, params->phy_addr, 5,
+		    (MDIO_REG_BANK_CL73_IEEEB0 +
+		     (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 0x6041);
+		msleep(200);
+		/* Set aer mmd back. */
+		bxe_set_aer_mmd(params, vars);
+
+		/* and md_devad */
+		REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18, md_devad);
+	} else {
+		DBPRINT(sc, BXE_VERBOSE_PHY, "XGXS 1G loopback enable\n");
+
+		CL45_RD_OVER_CL22(sc, port, params->phy_addr,
+		    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+		    &mii_control);
+
+		CL45_WR_OVER_CL22(sc, port, params->phy_addr,
+		    MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL,
+		    (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
+	}
+}
+
+static void
+bxe_ext_phy_loopback(struct link_params *params)
+{
+	struct bxe_softc *sc;
+	uint8_t ext_phy_addr;
+	uint32_t ext_phy_type;
+
+	sc = params->sc;
+	if (params->switch_cfg == SWITCH_CFG_10G) {
+		ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+		ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+		/* CL37 Autoneg Enabled */
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "ext_phy_loopback: We should not get here\n");
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "ext_phy_loopback: 8705\n");
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "ext_phy_loopback: 8706\n");
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "PMA/PMD ext_phy_loopback: 8726\n");
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+			    0x0001);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+			/* SFX7101_XGXS_TEST1 */
+			bxe_cl45_write(sc, params->port, ext_phy_type,
+			    ext_phy_addr, MDIO_XS_DEVAD,
+			    MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "ext_phy_loopback: set ext phy loopback\n");
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+			break;
+		} /* switch external PHY type */
+	} else {
+		/* serdes */
+		ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
+		ext_phy_addr = (params->ext_phy_config &
+		    PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
+		    PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
+	}
+}
+
+/* Override the led value of the requsted led. */
+uint8_t bxe_override_led_value(struct bxe_softc *sc, uint8_t port,
+    uint32_t led_idx, uint32_t value)
+{
+	uint32_t reg_val;
+	uint32_t emac_base;
+
+	/* If port 0 then use EMAC0, else use EMAC1. */
+	emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "bxe_override_led_value() port %x led_idx %d value %d\n", port,
+	    led_idx, value);
+
+	switch (led_idx) {
+	case 0: /* 10MB led */
+		/*
+		 * Read the current value of the LED register in the EMAC block.
+		 */
+		reg_val = REG_RD(sc, emac_base + EMAC_REG_EMAC_LED);
+		/* Set the OVERRIDE bit to 1. */
+		reg_val |= EMAC_LED_OVERRIDE;
+		/*
+		 * If value is 1, set the 10M_OVERRIDE bit, otherwise reset it.
+		 */
+		reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
+		    (reg_val & ~EMAC_LED_10MB_OVERRIDE);
+		REG_WR(sc, emac_base + EMAC_REG_EMAC_LED, reg_val);
+		break;
+	case 1: /*100MB led    */
+		/*
+		 * Read the current value of the LED register in the EMAC block.
+		 */
+		reg_val = REG_RD(sc, emac_base + EMAC_REG_EMAC_LED);
+		/* Set the OVERRIDE bit to 1. */
+		reg_val |= EMAC_LED_OVERRIDE;
+		/*
+		 * If value is 1, set the 100M_OVERRIDE bit, otherwise reset it.
+		 */
+		reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
+		    (reg_val & ~EMAC_LED_100MB_OVERRIDE);
+		REG_WR(sc, emac_base + EMAC_REG_EMAC_LED, reg_val);
+		break;
+	case 2: /* 1000MB led */
+		/*
+		 * Read the current value of the LED register in the EMAC block.
+		 */
+		reg_val = REG_RD(sc, emac_base + EMAC_REG_EMAC_LED);
+		/* Set the OVERRIDE bit to 1. */
+		reg_val |= EMAC_LED_OVERRIDE;
+		/*
+		 * If value is 1, set the 1000M_OVERRIDE bit, otherwise reset
+		 * it.
+		 */
+		reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
+		    (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
+		REG_WR(sc, emac_base + EMAC_REG_EMAC_LED, reg_val);
+		break;
+	case 3: /* 2500MB led */
+		/*
+		 * Read the current value of the LED register in the EMAC block.
+		 */
+		reg_val = REG_RD(sc, emac_base + EMAC_REG_EMAC_LED);
+		/* Set the OVERRIDE bit to 1. */
+		reg_val |= EMAC_LED_OVERRIDE;
+		/*
+		 * If value is 1, set the 2500M_OVERRIDE bit, otherwise reset
+		 * it.
+		 */
+		reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
+		    (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
+		REG_WR(sc, emac_base + EMAC_REG_EMAC_LED, reg_val);
+		break;
+	case 4: /*10G led */
+		if (port == 0)
+			REG_WR(sc, NIG_REG_LED_10G_P0, value);
+		else
+			REG_WR(sc, NIG_REG_LED_10G_P1, value);
+		break;
+	case 5: /* TRAFFIC led */
+		/* Find if the traffic control is via BMAC or EMAC. */
+		if (port == 0)
+			reg_val = REG_RD(sc, NIG_REG_NIG_EMAC0_EN);
+		else
+			reg_val = REG_RD(sc, NIG_REG_NIG_EMAC1_EN);
+
+		/*  Override the traffic led in the EMAC. */
+		if (reg_val == 1) {
+			/*
+			 * Read the current value of the LED register in
+			 * the EMAC block.
+			 */
+			reg_val = REG_RD(sc, emac_base + EMAC_REG_EMAC_LED);
+			/* Set the TRAFFIC_OVERRIDE bit to 1. */
+			reg_val |= EMAC_LED_OVERRIDE;
+			/*
+			 * If value is 1, set the TRAFFIC bit, otherwise reset
+			 * it.
+			 */
+			reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
+			    (reg_val & ~EMAC_LED_TRAFFIC);
+			REG_WR(sc, emac_base + EMAC_REG_EMAC_LED, reg_val);
+		} else {
+			/* Override the traffic led in the BMAC. */
+			REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
+			    port * 4, 1);
+			REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port * 4,
+			    value);
+		}
+		break;
+	default:
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+	"bxe_override_led_value() unknown led index %d (should be 0-5)\n",
+		    led_idx);
+		return (-EINVAL);
+	}
+
+	return (0);
+}
+
+uint8_t
+bxe_set_led(struct link_params *params, uint8_t mode, uint32_t speed)
+{
+	struct bxe_softc *sc;
+	uint32_t emac_base, ext_phy_type, tmp;
+	uint16_t hw_led_mode;
+	uint8_t port, rc;
+
+	sc = params->sc;
+	port = params->port;
+	hw_led_mode = params->hw_led_mode;
+	rc = 0;
+	emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	DBPRINT(sc, BXE_INFO, "bxe_set_led: port %x, mode %d\n", port, mode);
+	DBPRINT(sc, BXE_VERBOSE_PHY, "speed 0x%x, hw_led_mode 0x%x\n", speed,
+	    hw_led_mode);
+	switch (mode) {
+	case LED_MODE_OFF:
+		REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0);
+		REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
+		    SHARED_HW_CFG_LED_MAC1);
+		tmp = EMAC_RD(sc, EMAC_REG_EMAC_LED);
+		EMAC_WR(sc, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
+		break;
+	case LED_MODE_OPER:
+		if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
+			REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
+			REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
+		} else
+			REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, hw_led_mode);
+		REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4,
+		    0);
+		/* Set blinking rate to ~15.9Hz. */
+		REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
+		    LED_BLINK_RATE_VAL);
+		REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
+		tmp = EMAC_RD(sc, EMAC_REG_EMAC_LED);
+		EMAC_WR(sc, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
+
+		if (CHIP_IS_E1(sc) && ((speed == SPEED_2500) ||
+		    (speed == SPEED_1000) || (speed == SPEED_100) ||
+		    (speed == SPEED_10))) {
+			/*
+			 * On Everest 1 Ax chip versions for speeds less than
+			 * 10G LED scheme is different.
+			 */
+			REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
+			    port * 4, 1);
+			REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port * 4,
+			    0);
+			REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
+			    port * 4, 1);
+		}
+		break;
+	default:
+		rc = -EINVAL;
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "bxe_set_led: Invalid led mode %d\n", mode);
+		break;
+	}
+	return (rc);
+}
+
+uint8_t
+bxe_test_link(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint16_t gp_status;
+
+	sc = params->sc;
+	gp_status = 0;
+	CL45_RD_OVER_CL22(sc, params->port, params->phy_addr,
+	    MDIO_REG_BANK_GP_STATUS, MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
+	/* Link is up only if both local phy and external phy are up. */
+	if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
+	    bxe_ext_phy_is_link_up(params, vars, 1))
+		return (0);
+
+	return (-EINVAL);
+}
+
+static uint8_t
+bxe_link_initialize(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint8_t port, rc;
+	uint8_t non_ext_phy;
+
+	sc = params->sc;
+	port = params->port;
+	rc = 0;
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	/* Activate the external PHY. */
+	bxe_ext_phy_reset(params, vars);
+
+	bxe_set_aer_mmd(params, vars);
+
+	if (vars->phy_flags & PHY_XGXS_FLAG)
+		bxe_set_master_ln(params);
+
+	rc = bxe_reset_unicore(params);
+	/* Reset the SerDes and wait for reset bit return low. */
+	if (rc != 0)
+		return (rc);
+
+	bxe_set_aer_mmd(params, vars);
+
+	/* Setting the masterLn_def again after the reset. */
+	if (vars->phy_flags & PHY_XGXS_FLAG) {
+		bxe_set_master_ln(params);
+		bxe_set_swap_lanes(params);
+	}
+
+	if (vars->phy_flags & PHY_XGXS_FLAG) {
+		if ((params->req_line_speed &&
+		    ((params->req_line_speed == SPEED_100) ||
+		    (params->req_line_speed == SPEED_10))) ||
+		    (!params->req_line_speed &&
+		    (params->speed_cap_mask >=
+		    PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
+		    (params->speed_cap_mask <
+		    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)))
+			vars->phy_flags |= PHY_SGMII_FLAG;
+		else
+			vars->phy_flags &= ~PHY_SGMII_FLAG;
+	}
+	/*
+	 * In case of external phy existance, the line speed would be the
+	 * line speed linked up by the external phy. In case it is direct
+	 * only, then the line_speed during initialization will be equal
+	 * to the req_line_speed.
+	 */
+	vars->line_speed = params->req_line_speed;
+
+	bxe_calc_ieee_aneg_adv(params, &vars->ieee_fc);
+
+	/* Init ext phy and enable link state int. */
+	non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
+	    (params->loopback_mode == LOOPBACK_XGXS_10));
+
+	if (non_ext_phy ||
+	    (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
+	    (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
+	    (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
+	    (params->loopback_mode == LOOPBACK_EXT_PHY)) {
+		if (params->req_line_speed == SPEED_AUTO_NEG)
+			bxe_set_parallel_detection(params, vars->phy_flags);
+		bxe_init_internal_phy(params, vars, 0);
+	}
+
+	if (!non_ext_phy)
+		rc |= bxe_ext_phy_init(params, vars);
+
+	bxe_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
+	    (NIG_STATUS_XGXS0_LINK10G | NIG_STATUS_XGXS0_LINK_STATUS |
+	    NIG_STATUS_SERDES0_LINK_STATUS));
+
+	return (rc);
+}
+
+uint8_t
+bxe_phy_init(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t val;
+
+	sc = params->sc;
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Phy Initialization started\n");
+	DBPRINT(sc, BXE_VERBOSE_PHY, "req_speed %d, req_flowctrl %d\n",
+	    params->req_line_speed, params->req_flow_ctrl);
+	vars->link_status = 0;
+	vars->phy_link_up = 0;
+	vars->link_up = 0;
+	vars->line_speed = 0;
+	vars->duplex = DUPLEX_FULL;
+	vars->flow_ctrl = FLOW_CTRL_NONE;
+	vars->mac_type = MAC_TYPE_NONE;
+
+	if (params->switch_cfg ==  SWITCH_CFG_1G)
+		vars->phy_flags = PHY_SERDES_FLAG;
+	else
+		vars->phy_flags = PHY_XGXS_FLAG;
+
+	/* disable attentions */
+	bxe_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
+	    (NIG_MASK_XGXS0_LINK_STATUS | NIG_MASK_XGXS0_LINK10G |
+	    NIG_MASK_SERDES0_LINK_STATUS | NIG_MASK_MI_INT));
+
+	bxe_emac_init(params, vars);
+
+	if (params->loopback_mode == LOOPBACK_BMAC) {
+		vars->link_up = 1;
+		vars->line_speed = SPEED_10000;
+		vars->duplex = DUPLEX_FULL;
+		vars->flow_ctrl = FLOW_CTRL_NONE;
+		vars->mac_type = MAC_TYPE_BMAC;
+
+		vars->phy_flags = PHY_XGXS_FLAG;
+
+		bxe_phy_deassert(params, vars->phy_flags);
+		/* Set bmac loopback. */
+		bxe_bmac_enable(params, vars, 1);
+
+		REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
+	} else if (params->loopback_mode == LOOPBACK_EMAC) {
+		vars->link_up = 1;
+		vars->line_speed = SPEED_1000;
+		vars->duplex = DUPLEX_FULL;
+		vars->flow_ctrl = FLOW_CTRL_NONE;
+		vars->mac_type = MAC_TYPE_EMAC;
+
+		vars->phy_flags = PHY_XGXS_FLAG;
+
+		bxe_phy_deassert(params, vars->phy_flags);
+		/* Set bmac loopback. */
+		bxe_emac_enable(params, vars, 1);
+		bxe_emac_program(params, vars->line_speed, vars->duplex);
+		REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
+	} else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
+	    (params->loopback_mode == LOOPBACK_EXT_PHY)) {
+		vars->link_up = 1;
+		vars->line_speed = SPEED_10000;
+		vars->duplex = DUPLEX_FULL;
+		vars->flow_ctrl = FLOW_CTRL_NONE;
+
+		vars->phy_flags = PHY_XGXS_FLAG;
+
+		val = REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR +
+		    params->port * 0x18);
+		params->phy_addr = (uint8_t)val;
+
+		bxe_phy_deassert(params, vars->phy_flags);
+		bxe_link_initialize(params, vars);
+
+		vars->mac_type = MAC_TYPE_BMAC;
+
+		bxe_bmac_enable(params, vars, 0);
+
+		if (params->loopback_mode == LOOPBACK_XGXS_10) {
+			/* Set 10G XGXS loopback. */
+			bxe_set_xgxs_loopback(params, vars, 1);
+		} else {
+			/* Set external phy loopback. */
+			bxe_ext_phy_loopback(params);
+		}
+		REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
+		bxe_set_led(params, LED_MODE_OPER, vars->line_speed);
+	} else {
+		/* No loopback. */
+		bxe_phy_deassert(params, vars->phy_flags);
+		switch (params->switch_cfg) {
+		case SWITCH_CFG_1G:
+			vars->phy_flags |= PHY_SERDES_FLAG;
+			if ((params->ext_phy_config &
+			    PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
+			    PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
+				vars->phy_flags |= PHY_SGMII_FLAG;
+			}
+
+			val = REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR +
+			    params->port * 0x10);
+			params->phy_addr = (uint8_t)val;
+			break;
+		case SWITCH_CFG_10G:
+			vars->phy_flags |= PHY_XGXS_FLAG;
+			val = REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR +
+			    params->port * 0x18);
+			params->phy_addr = (uint8_t)val;
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "Invalid switch_cfg\n");
+			return (-EINVAL);
+		}
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Phy address = 0x%x\n",
+		    params->phy_addr);
+
+		bxe_link_initialize(params, vars);
+		msleep(30);
+		bxe_link_int_enable(params);
+	}
+	return (0);
+}
+
+static void
+bxe_8726_reset_phy(struct bxe_softc *sc, uint8_t port, uint8_t ext_phy_addr)
+{
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "bxe_8726_reset_phy port %d\n", port);
+
+	/* Set serial boot control for external load. */
+	bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
+	    ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
+}
+
+uint8_t
+bxe_link_reset(struct link_params *params, struct link_vars *vars,
+    uint8_t reset_ext_phy)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_config, ext_phy_type, val;
+	uint8_t ext_phy_addr, port;
+
+	sc = params->sc;
+	ext_phy_config = params->ext_phy_config;
+	port = params->port;
+	ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
+	val = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
+	    dev_info.port_feature_config[params->port].config));
+	DBPRINT(sc, BXE_INFO, "Resetting the link of port %d\n", port);
+	/* Disable attentions. */
+	vars->link_status = 0;
+	bxe_update_mng(params, vars->link_status);
+	bxe_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
+	    (NIG_MASK_XGXS0_LINK_STATUS | NIG_MASK_XGXS0_LINK10G |
+	    NIG_MASK_SERDES0_LINK_STATUS | NIG_MASK_MI_INT));
+
+	/* Activate nig drain. */
+	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
+
+	/* Disable nig egress interface. */
+	REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
+	REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
+
+	/* Stop BigMac rx. */
+	bxe_bmac_rx_disable(sc, params->chip_id, port);
+
+	/* Disable emac. */
+	REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
+
+	msleep(10);
+	/* The PHY reset is controled by GPIO 1 Hold it as vars low. */
+	 /* Clear link led. */
+	bxe_set_led(params, LED_MODE_OFF, 0);
+	if (reset_ext_phy) {
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+			/* Disable Transmitter */
+			ext_phy_addr =
+			    XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+			if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
+			    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
+				bxe_sfp_set_transmitter(sc, port,
+				    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+				    ext_phy_addr, 0);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "Setting 8073 port %d into low power mode\n",
+			    port);
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+			ext_phy_addr =
+			    XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+			/* Set soft reset. */
+			bxe_8726_reset_phy(sc, params->port, ext_phy_addr);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
+			ext_phy_addr =
+			    XGXS_EXT_PHY_ADDR(params->ext_phy_config);
+			bxe_cl45_write(sc, port,
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ext_phy_addr,
+			    MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
+			bxe_cl45_write(sc, port,
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, ext_phy_addr,
+			    MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
+			break;
+		default:
+			/* HW reset */
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1,
+			    MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+			    MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+			DBPRINT(sc, BXE_VERBOSE_PHY, "reset external PHY\n");
+		}
+	}
+	/* Reset the SerDes/XGXS. */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
+	    (0x1ff << (port * 16)));
+
+	/* Reset BigMac. */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+	    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+	/* Disable nig ingress interface. */
+	REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
+	REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
+	REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
+	REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
+	vars->link_up = 0;
+	return (0);
+}
+
+static uint8_t
+bxe_update_link_down(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint8_t port;
+
+	sc = params->sc;
+	port = params->port;
+
+	DBPRINT(sc, BXE_INFO, "Port %x: Link is down\n", port);
+	bxe_set_led(params, LED_MODE_OFF, 0);
+
+	/* Indicate no mac active. */
+	vars->mac_type = MAC_TYPE_NONE;
+
+	/* Update shared memory. */
+	vars->link_status = 0;
+	vars->line_speed = 0;
+	bxe_update_mng(params, vars->link_status);
+
+	/* Activate nig drain. */
+	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
+
+	/* Disable emac. */
+	REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
+
+	msleep(10);
+
+	/* Reset BigMac. */
+	bxe_bmac_rx_disable(sc, params->chip_id, params->port);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+	    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+	return (0);
+}
+
+static uint8_t
+bxe_update_link_up(struct link_params *params, struct link_vars *vars,
+    uint8_t link_10g, uint32_t gp_status)
+{
+	struct bxe_softc *sc;
+	uint8_t port, rc;
+
+	sc = params->sc;
+	port = params->port;
+	rc = 0;
+
+	vars->link_status |= LINK_STATUS_LINK_UP;
+	if (link_10g) {
+		bxe_bmac_enable(params, vars, 0);
+		bxe_set_led(params, LED_MODE_OPER, SPEED_10000);
+	} else {
+		rc = bxe_emac_program(params, vars->line_speed, vars->duplex);
+		bxe_emac_enable(params, vars, 0);
+		/* AN complete? */
+		if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
+			if (!(vars->phy_flags & PHY_SGMII_FLAG))
+				bxe_set_gmii_tx_driver(params);
+		}
+	}
+
+	/* PBF - link up */
+	rc |= bxe_pbf_update(params, vars->flow_ctrl, vars->line_speed);
+
+	/* Disable drain. */
+	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0);
+
+	/* Update shared memory. */
+	bxe_update_mng(params, vars->link_status);
+	msleep(20);
+	return (rc);
+}
+
+/*
+ * This function should called upon link interrupt.
+ * In case vars->link_up, driver needs to
+ *	1. Update the pbf
+ *	2. Disable drain
+ *	3. Update the shared memory
+ *	4. Indicate link up
+ *	5. Set LEDs
+ *  Otherwise,
+ *	1. Update shared memory
+ *	2. Reset BigMac
+ *	3. Report link down
+ *	4. Unset LEDs
+ */
+uint8_t
+bxe_link_update(struct link_params *params, struct link_vars *vars)
+{
+	struct bxe_softc *sc;
+	uint32_t ext_phy_type;
+	uint16_t gp_status;
+	uint8_t link_10g, port;
+	uint8_t ext_phy_link_up, rc;
+	uint8_t is_mi_int;
+
+	sc = params->sc;
+	port = params->port;
+	rc = 0;
+	is_mi_int = 0;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "port %x, XGXS?%x, int_status 0x%x\n",
+	    port, (vars->phy_flags & PHY_XGXS_FLAG), REG_RD(sc,
+	    NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
+
+	is_mi_int = (uint8_t)(REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
+	    port * 0x18) > 0);
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", REG_RD(sc,
+	    NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), is_mi_int, REG_RD(sc,
+	    NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, " 10G %x, XGXS_LINK %x\n",
+	    REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
+	    REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
+
+	/* Disable emac. */
+	REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
+
+	ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
+
+	/* Check external link change only for non-direct. */
+	ext_phy_link_up = bxe_ext_phy_is_link_up(params, vars, is_mi_int);
+
+	/* Read gp_status. */
+	CL45_RD_OVER_CL22(sc, port, params->phy_addr, MDIO_REG_BANK_GP_STATUS,
+	    MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
+
+	rc = bxe_link_settings_status(params, vars, gp_status, ext_phy_link_up);
+	if (rc != 0)
+		return (rc);
+
+	/* Anything 10 and over uses the bmac. */
+	link_10g = ((vars->line_speed == SPEED_10000) ||
+	    (vars->line_speed == SPEED_12000) ||
+	    (vars->line_speed == SPEED_12500) ||
+	    (vars->line_speed == SPEED_13000) ||
+	    (vars->line_speed == SPEED_15000) ||
+	    (vars->line_speed == SPEED_16000));
+
+	bxe_link_int_ack(params, vars, link_10g, is_mi_int);
+
+	/*
+	 * In case external phy link is up, and internal link is down,
+	 * not initialized yet probably after link initialization, it
+	 * needs to be initialized.
+	 * Note that after link down-up as result of cable plug,
+	 * the xgxs link would probably become up again without the need
+	 * to initialize it.
+	 */
+	if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
+	    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
+	    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) &&
+	    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
+	    (ext_phy_link_up && !vars->phy_link_up)) {
+			bxe_init_internal_phy(params, vars, 0);
+	}
+
+	/* Link is up only if both local phy and external phy are up. */
+	vars->link_up = (ext_phy_link_up && vars->phy_link_up);
+	if (vars->link_up)
+		rc = bxe_update_link_up(params, vars, link_10g, gp_status);
+	else
+		rc = bxe_update_link_down(params, vars);
+
+	return (rc);
+}
+
+static uint8_t
+bxe_8073_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base)
+{
+	uint32_t ext_phy_config;
+	uint16_t fw_ver1, val;
+	uint8_t ext_phy_addr[PORT_MAX];
+	int port;
+
+	/* PART1 - Reset both phys. */
+	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+		/* Extract the ext phy address for the port. */
+		ext_phy_config = REG_RD(sc, shmem_base +
+		    offsetof(struct shmem_region,
+		    dev_info.port_hw_config[port].external_phy_config));
+
+		/* Disable attentions. */
+		bxe_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
+		    (NIG_MASK_XGXS0_LINK_STATUS | NIG_MASK_XGXS0_LINK10G |
+		    NIG_MASK_SERDES0_LINK_STATUS | NIG_MASK_MI_INT));
+
+		ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
+
+		/*
+		 * Need to take the phy out of low power mode in order
+		 * to write to access its registers.
+		 */
+		bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+		    MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
+
+		/* Reset the phy. */
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+		    1 << 15);
+	}
+
+	/* Add delay of 150ms after reset. */
+	msleep(150);
+
+	/* PART2 - Download firmware to both phys. */
+	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+		bxe_bcm8073_external_rom_boot(sc, port, ext_phy_addr[port],
+		    shmem_base);
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1,
+		    &fw_ver1);
+		if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "bxe_8073_common_init_phy port %x:"
+			    "Download failed. fw version = 0x%x\n", port,
+			    fw_ver1);
+			return (-EINVAL);
+		}
+
+		/* Only set bit 10 = 1 (Tx power down). */
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD,
+		    MDIO_PMA_REG_TX_POWER_DOWN, &val);
+
+		/* Phase1 of TX_POWER_DOWN reset. */
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD,
+		    MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
+	}
+
+	/*
+	 * Toggle Transmitter: Power down and then up with 600ms
+	 * delay between.
+	 */
+	msleep(600);
+
+	/* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low. */
+	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
+		/* Phase2 of POWER_DOWN_RESET */
+		/* Release bit 10 (Release Tx power down). */
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD,
+		    MDIO_PMA_REG_TX_POWER_DOWN, &val);
+
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD,
+		    MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1 << 10))));
+		msleep(15);
+
+		/* Read modify write the SPI-ROM version select register. */
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD,
+		    MDIO_PMA_REG_EDC_FFE_MAIN, &val);
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD,
+		    MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12)));
+
+		/* Set GPIO2 back to LOW. */
+		bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+		     MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+	}
+	return (0);
+}
+
+static uint8_t
+bxe_8727_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base)
+{
+	uint32_t swap_val, swap_override;
+	uint32_t ext_phy_config;
+	uint16_t fw_ver1;
+	uint8_t ext_phy_addr[PORT_MAX];
+	uint8_t port, first_port, i;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Executing BCM8727 common init\n");
+	swap_val = REG_RD(sc,  NIG_REG_PORT_SWAP);
+	swap_override = REG_RD(sc,  NIG_REG_STRAP_OVERRIDE);
+
+	bxe_ext_phy_hw_reset(sc, 1 ^ (swap_val && swap_override));
+	msleep(5);
+
+	if (swap_val && swap_override)
+		first_port = PORT_0;
+	else
+		first_port = PORT_1;
+	/* PART1 - Reset both phys. */
+	for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
+		/* Extract the ext phy address for the port. */
+		ext_phy_config = REG_RD(sc, shmem_base +
+		    offsetof(struct shmem_region,
+		    dev_info.port_hw_config[port].external_phy_config));
+
+		/* Disable attentions. */
+		bxe_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
+		    (NIG_MASK_XGXS0_LINK_STATUS | NIG_MASK_XGXS0_LINK10G |
+		    NIG_MASK_SERDES0_LINK_STATUS | NIG_MASK_MI_INT));
+
+		ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
+
+		/* Reset the phy. */
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL,
+		    1 << 15);
+	}
+
+	/* Add delay of 150ms after reset. */
+	msleep(150);
+
+	/* PART2 - Download firmware to both phys. */
+	for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
+		bxe_bcm8727_external_rom_boot(sc, port, ext_phy_addr[port],
+		    shmem_base);
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
+		    ext_phy_addr[port], MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1,
+		    &fw_ver1);
+		if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
+			DBPRINT(sc, 1/*BXE_VERBOSE_PHY*/,
+			    "bxe_8727_common_init_phy port %x:"
+			    "Download failed. fw version = 0x%x\n", port,
+			    fw_ver1);
+			return (-EINVAL);
+		}
+	}
+
+	return (0);
+}
+
+static uint8_t
+bxe_8726_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base)
+{
+	uint32_t ext_phy_config, val;
+	uint8_t ext_phy_addr;
+	uint8_t port;
+
+	/* Use port1 because of the static port-swap. */
+	/* Enable the module detection interrupt. */
+	val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
+	val |= ((1 << MISC_REGISTERS_GPIO_3) | (1 << (MISC_REGISTERS_GPIO_3 +
+	    MISC_REGISTERS_GPIO_PORT_SHIFT)));
+	REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
+
+	bxe_ext_phy_hw_reset(sc, 1);
+	msleep(5);
+	for (port = 0; port < PORT_MAX; port++) {
+		/* Extract the ext phy address for the port. */
+		ext_phy_config = REG_RD(sc, shmem_base +
+		    offsetof(struct shmem_region,
+		    dev_info.port_hw_config[port].external_phy_config));
+
+		ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "8726_common_init : ext_phy_addr = 0x%x\n", ext_phy_addr);
+
+		bxe_8726_reset_phy(sc, port, ext_phy_addr);
+
+		/* Set fault module detected LED on. */
+		bxe_set_gpio(sc, MISC_REGISTERS_GPIO_0,
+		    MISC_REGISTERS_GPIO_HIGH, port);
+	}
+
+	return (0);
+}
+
+static uint8_t
+bxe_84823_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base)
+{
+
+	bxe_ext_phy_hw_reset(sc, 1);
+	return (0);
+}
+
+uint8_t
+bxe_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base)
+{
+	uint32_t ext_phy_type;
+	uint8_t rc;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "Begin common phy init\n");
+
+	rc = 0;
+	ext_phy_type = 0;
+	/* Read the ext_phy_type for arbitrary port(0) */
+	ext_phy_type = XGXS_EXT_PHY_TYPE( REG_RD(sc, shmem_base +
+	    offsetof(struct shmem_region,
+	    dev_info.port_hw_config[0].external_phy_config)));
+
+	switch (ext_phy_type) {
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+		rc = bxe_8073_common_init_phy(sc, shmem_base);
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
+		rc = bxe_8727_common_init_phy(sc, shmem_base);
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+		/*
+		 * GPIO1 affects both ports, so there's need to pull
+		 * it for single port alone.
+		 */
+		rc = bxe_8726_common_init_phy(sc, shmem_base);
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
+		rc = bxe_84823_common_init_phy(sc, shmem_base);
+		break;
+	default:
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "bxe_common_init_phy: ext_phy 0x%x not required\n",
+		    ext_phy_type);
+		break;
+	}
+
+	return (rc);
+}
+
+void
+bxe_sfx7101_sp_sw_reset(struct bxe_softc *sc, uint8_t port, uint8_t phy_addr)
+{
+	uint16_t val, cnt;
+
+	bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, phy_addr,
+	    MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_RESET, &val);
+
+	for (cnt = 0; cnt < 10; cnt++) {
+		msleep(50);
+		/* Writes a self-clearing reset. */
+		bxe_cl45_write(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+		    phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_RESET,
+		    (val | (1 << 15)));
+		/* Wait for clear. */
+		bxe_cl45_read(sc, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
+		    phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_RESET, &val);
+		if ((val & (1 << 15)) == 0)
+			break;
+	}
+}
diff --git a/sys/dev/bxe/bxe_link.h b/sys/dev/bxe/bxe_link.h
new file mode 100755
index 0000000..99404ee
--- /dev/null
+++ b/sys/dev/bxe/bxe_link.h
@@ -0,0 +1,239 @@
+/*-
+ * Copyright (c) 2007-2010 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef BXE_LINK_H
+#define	BXE_LINK_H
+
+/*
+ * Defines
+ */
+#define	DEFAULT_PHY_DEV_ADDR	3
+
+
+
+#define	FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
+#define	FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
+#define	FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
+#define	FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
+#define	FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE
+
+#define	SPEED_AUTO_NEG		0
+#define	SPEED_12000		12000
+#define	SPEED_12500		12500
+#define	SPEED_13000		13000
+#define	SPEED_15000		15000
+#define	SPEED_16000		16000
+
+#define	SFP_EEPROM_VENDOR_NAME_ADDR	0x14
+#define	SFP_EEPROM_VENDOR_NAME_SIZE	16
+#define	SFP_EEPROM_VENDOR_OUI_ADDR	0x25
+#define	SFP_EEPROM_VENDOR_OUI_SIZE	3
+#define	SFP_EEPROM_PART_NO_ADDR 	0x28
+#define	SFP_EEPROM_PART_NO_SIZE		16
+#define	PWR_FLT_ERR_MSG_LEN		250
+
+/*
+ * Structs
+ */
+/* Inputs parameters to the CLC. */
+struct link_params {
+	uint8_t port;
+	/* Default / User Configuration */
+	uint8_t loopback_mode;
+#define	LOOPBACK_NONE			0
+#define	LOOPBACK_EMAC			1
+#define	LOOPBACK_BMAC			2
+#define	LOOPBACK_XGXS_10		3
+#define	LOOPBACK_EXT_PHY		4
+#define	LOOPBACK_EXT 			5
+
+	uint16_t req_duplex;
+	uint16_t req_flow_ctrl;
+	/* Should be set to TX / BOTH when req_flow_ctrl is set to AUTO. */
+	uint16_t req_fc_auto_adv;
+	/* Also determine AutoNeg. */
+	uint16_t req_line_speed;
+
+	/* Device parameters */
+	uint8_t mac_addr[6];
+
+	/* shmem parameters */
+	uint32_t shmem_base;
+	uint32_t speed_cap_mask;
+	uint32_t switch_cfg;
+#define	SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
+#define	SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
+#define	SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT
+
+	/* Part of the hw_config read from the shmem. */
+	uint16_t hw_led_mode;
+
+	/* phy_addr populated by the CLC. */
+	uint8_t phy_addr;
+	/* uint8_t reserved1; */
+
+	uint32_t lane_config;
+	uint32_t ext_phy_config;
+#define	XGXS_EXT_PHY_TYPE(ext_phy_config)				\
+	((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
+#define	XGXS_EXT_PHY_ADDR(ext_phy_config)				\
+	(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>	\
+	    PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
+#define	SERDES_EXT_PHY_TYPE(ext_phy_config)				\
+	((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
+
+	/* Phy register parameter */
+	uint32_t chip_id;
+
+	uint16_t xgxs_config_rx[4]; /* preemphasis values for the rx side */
+	uint16_t xgxs_config_tx[4]; /* preemphasis values for the tx side */
+
+	uint32_t feature_config_flags;
+#define	FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED	(1<<0)
+#define	FEATURE_CONFIG_PFC_ENABLED			(1<<1)
+#define	FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY		(1<<2)
+#define	FEATURE_CONFIG_BCM8727_NOC			(1<<3)
+
+	/* Device pointer passed to all callback functions. */
+	struct bxe_softc *sc;
+};
+
+/* Output parameters */
+struct link_vars {
+	uint8_t phy_flags;
+
+	uint8_t mac_type;
+#define	MAC_TYPE_NONE		0
+#define	MAC_TYPE_EMAC		1
+#define	MAC_TYPE_BMAC		2
+
+	/* Internal phy link indication. */
+	uint8_t phy_link_up;
+	uint8_t link_up;
+
+	uint16_t line_speed;
+	uint16_t duplex;
+
+	uint16_t flow_ctrl;
+	uint16_t ieee_fc;
+
+	uint32_t autoneg;
+#define	AUTO_NEG_DISABLED			0x0
+#define	AUTO_NEG_ENABLED			0x1
+#define	AUTO_NEG_COMPLETE			0x2
+#define	AUTO_NEG_PARALLEL_DETECTION_USED	0x4
+
+	/* The same definitions as the shmem parameter. */
+	uint32_t link_status;
+};
+
+/*
+ * Functions
+ */
+
+/* Initialize the phy. */
+uint8_t bxe_phy_init(struct link_params *input, struct link_vars *output);
+
+/*
+ * Reset the link. Should be called when driver or interface goes down
+ * Before calling phy firmware upgrade, the reset_ext_phy should be set
+ * to 0.
+ */
+uint8_t bxe_link_reset(struct link_params *params, struct link_vars *vars,
+    uint8_t reset_ext_phy);
+
+/* bxe_link_update should be called upon link interrupt */
+uint8_t bxe_link_update(struct link_params *input, struct link_vars *output);
+
+/*
+ * Use the following cl45 functions to read/write from external_phy
+ * In order to use it to read/write internal phy registers, use
+ * DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
+ * Use ext_phy_type of 0 in case of cl22 over cl45
+ * the register.
+ */
+uint8_t bxe_cl45_read(struct bxe_softc *sc, uint8_t port, uint32_t ext_phy_type,
+    uint8_t phy_addr, uint8_t devad, uint16_t reg, uint16_t *ret_val);
+
+uint8_t bxe_cl45_write(struct bxe_softc *sc, uint8_t port,
+    uint32_t ext_phy_type, uint8_t phy_addr, uint8_t devad, uint16_t reg,
+    uint16_t val);
+
+/*
+ * Reads the link_status from the shmem, and update the link vars accordingly.
+ */
+void bxe_link_status_update(struct link_params *input,
+    struct link_vars *output);
+/* Returns string representing the fw_version of the external phy. */
+uint8_t bxe_get_ext_phy_fw_version(struct link_params *params,
+    uint8_t driver_loaded, uint8_t *version, uint16_t len);
+
+/*
+ * Set/Unset the led
+ * Basically, the CLC takes care of the led for the link, but in case one needs
+ * to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to blink
+ * the led, and LED_MODE_OFF to set the led off.
+ */
+uint8_t bxe_set_led(struct link_params *params, uint8_t mode, uint32_t speed);
+#define	LED_MODE_OFF	0
+#define	LED_MODE_OPER 	2
+
+uint8_t bxe_override_led_value(struct bxe_softc *sc, uint8_t port,
+    uint32_t led_idx, uint32_t value);
+
+/*
+ * bxe_handle_module_detect_int should be called upon module detection
+ * interrupt.
+ */
+void bxe_handle_module_detect_int(struct link_params *params);
+
+/*
+ * Get the actual link status. In case it returns 0, link is up, otherwise
+ * link is down.
+ */
+uint8_t bxe_test_link(struct link_params *input, struct link_vars *vars);
+
+/* One-time initialization for external phy after power up. */
+uint8_t bxe_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base);
+
+/* Reset the external PHY using GPIO. */
+void bxe_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port);
+
+void bxe_sfx7101_sp_sw_reset(struct bxe_softc *sc, uint8_t port,
+    uint8_t phy_addr);
+
+uint8_t bxe_read_sfp_module_eeprom(struct link_params *params, uint16_t addr,
+    uint8_t byte_cnt, uint8_t *o_buf);
+
+#endif /* BXE_LINK_H */
diff --git a/sys/dev/bxe/bxe_reg.h b/sys/dev/bxe/bxe_reg.h
new file mode 100755
index 0000000..e561ce6
--- /dev/null
+++ b/sys/dev/bxe/bxe_reg.h
@@ -0,0 +1,6391 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+/* bxe_reg.h: Broadcom Everest network driver.
+ * The registers description starts with the register Access type followed
+ * by size in bits. For example [RW 32]. The access types are:
+ * R  - Read only
+ * RC - Clear on read
+ * RW - Read/Write
+ * ST - Statistics register (clear on read)
+ * W  - Write only
+ * WB - Wide bus register - the size is over 32 bits and it should be
+ *      read/write in consecutive 32 bits accesses
+ * WR - Write Clear (write 1 to clear the bit)
+ */
+
+#ifndef _BXE_REG_H
+#define	_BXE_REG_H
+
+/* [R 19] Interrupt register #0 read */
+#define	BRB1_REG_BRB1_INT_STS					0x6011c
+/* [RW 4] Parity mask register #0 read/write */
+#define	BRB1_REG_BRB1_PRTY_MASK					0x60138
+/* [R 4] Parity register #0 read */
+#define	BRB1_REG_BRB1_PRTY_STS					0x6012c
+/*
+ * [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
+ * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
+ * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit.
+ */
+#define	BRB1_REG_FREE_LIST_PRS_CRDT				0x60200
+/*
+ * [RW 10] The number of free blocks above which the High_llfc signal to
+ *  interface #n is de-asserted.
+ */
+#define	BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0			0x6014c
+/*
+ * [RW 10] The number of free blocks below which the High_llfc signal to
+ * interface #n is asserted.
+ */
+#define	BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0			0x6013c
+/* [RW 23] LL RAM data. */
+#define	BRB1_REG_LL_RAM 					0x61000
+/*
+ * [RW 10] The number of free blocks above which the Low_llfc signal to
+ * interface #n is de-asserted.
+ */
+#define	BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0			0x6016c
+/*
+ * [RW 10] The number of free blocks below which the Low_llfc signal to
+ * interface #n is asserted.
+ */
+#define	BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0			0x6015c
+/* [R 24] The number of full blocks. */
+#define	BRB1_REG_NUM_OF_FULL_BLOCKS				0x60090
+/*
+ * [ST 32] The number of cycles that the write_full signal towards MAC #0
+ * was asserted.
+ */
+#define	BRB1_REG_NUM_OF_FULL_CYCLES_0				0x600c8
+#define	BRB1_REG_NUM_OF_FULL_CYCLES_1				0x600cc
+#define	BRB1_REG_NUM_OF_FULL_CYCLES_4				0x600d8
+/*
+ * [ST 32] The number of cycles that the pause signal towards MAC #0 was
+ * asserted.
+ */
+#define	BRB1_REG_NUM_OF_PAUSE_CYCLES_0				0x600b8
+#define	BRB1_REG_NUM_OF_PAUSE_CYCLES_1				0x600bc
+/* [RW 10] Write client 0: De-assert pause threshold. */
+#define	BRB1_REG_PAUSE_HIGH_THRESHOLD_0				0x60078
+#define	BRB1_REG_PAUSE_HIGH_THRESHOLD_1				0x6007c
+/* [RW 10] Write client 0: Assert pause threshold. */
+#define	BRB1_REG_PAUSE_LOW_THRESHOLD_0				0x60068
+#define	BRB1_REG_PAUSE_LOW_THRESHOLD_1				0x6006c
+/* [R 24] The number of full blocks occupied by port. */
+#define	BRB1_REG_PORT_NUM_OCC_BLOCKS_0				0x60094
+/* [RW 1] Reset the design by software. */
+#define	BRB1_REG_SOFT_RESET					0x600dc
+/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
+#define	CCM_REG_CAM_OCCUP					0xd0188
+/*
+ * [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	CCM_REG_CCM_CFC_IFEN					0xd003c
+/*
+ * [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	CCM_REG_CCM_CQM_IFEN					0xd000c
+/*
+ * [RW 1] If set the Q index; received from the QM is inserted to event ID.
+ * Otherwise 0 is inserted.
+ */
+#define	CCM_REG_CCM_CQM_USE_Q					0xd00c0
+/* [RW 11] Interrupt mask register #0 read/write */
+#define	CCM_REG_CCM_INT_MASK					0xd01e4
+/* [R 11] Interrupt register #0 read */
+#define	CCM_REG_CCM_INT_STS					0xd01d8
+/* [R 27] Parity register #0 read */
+#define	CCM_REG_CCM_PRTY_STS					0xd01e8
+/*
+ * [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
+ * REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+ * Is used to determine the number of the AG context REG-pairs written back;
+ * when the input message Reg1WbFlg isn't set.
+ */
+#define	CCM_REG_CCM_REG0_SZ					0xd00c4
+/*
+ * [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	CCM_REG_CCM_STORM0_IFEN					0xd0004
+/*
+ * [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	CCM_REG_CCM_STORM1_IFEN					0xd0008
+/*
+ * [RW 1] CDU AG read Interface enable. If 0 - the request input is
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	CCM_REG_CDU_AG_RD_IFEN					0xd0030
+/*
+ * [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
+ * are disregarded; all other signals are treated as usual; if 1 - normal
+ * activity.
+ */
+#define	CCM_REG_CDU_AG_WR_IFEN					0xd002c
+/*
+ * [RW 1] CDU STORM read Interface enable. If 0 - the request input is
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	CCM_REG_CDU_SM_RD_IFEN					0xd0038
+/*
+ * [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
+ * input is disregarded; all other signals are treated as usual; if 1 -
+ * normal activity.
+ */
+#define	CCM_REG_CDU_SM_WR_IFEN					0xd0034
+/*
+ * [RW 4] CFC output initial credit. Max credit available - 15.Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define	CCM_REG_CFC_INIT_CRD					0xd0204
+/* [RW 2] Auxillary counter flag Q number 1. */
+#define	CCM_REG_CNT_AUX1_Q					0xd00c8
+/* [RW 2] Auxillary counter flag Q number 2. */
+#define	CCM_REG_CNT_AUX2_Q					0xd00cc
+/* [RW 28] The CM header value for QM request (primary). */
+#define	CCM_REG_CQM_CCM_HDR_P					0xd008c
+/* [RW 28] The CM header value for QM request (secondary). */
+#define	CCM_REG_CQM_CCM_HDR_S					0xd0090
+/*
+ * [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	CCM_REG_CQM_CCM_IFEN					0xd0014
+/*
+ * [RW 6] QM output initial credit. Max credit available - 32. Write writes
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define	CCM_REG_CQM_INIT_CRD					0xd020c
+/*
+ * [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	CCM_REG_CQM_P_WEIGHT					0xd00b8
+/*
+ * [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	CCM_REG_CQM_S_WEIGHT					0xd00bc
+/*
+ * [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	CCM_REG_CSDM_IFEN					0xd0018
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the SDM interface is detected.
+ */
+#define	CCM_REG_CSDM_LENGTH_MIS					0xd0170
+/*
+ * [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	CCM_REG_CSDM_WEIGHT					0xd00b4
+/*
+ * [RW 28] The CM header for QM formatting in case of an error in the QM
+ * inputs.
+ */
+#define	CCM_REG_ERR_CCM_HDR					0xd0094
+/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
+#define	CCM_REG_ERR_EVNT_ID					0xd0098
+/*
+ * [RW 8] FIC0 output initial credit. Max credit available - 255. Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	CCM_REG_FIC0_INIT_CRD					0xd0210
+/*
+ * [RW 8] FIC1 output initial credit. Max credit available - 255.Write
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	CCM_REG_FIC1_INIT_CRD					0xd0214
+/*
+ * [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
+ * - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
+ * ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
+ * ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
+ * outputs to STORM: aggregation; load FIC0; load FIC1 and store.
+ */
+#define	CCM_REG_GR_ARB_TYPE					0xd015c
+/*
+ * [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
+ * highest priority is 3. It is supposed; that the Store channel priority is
+ * the compliment to 4 of the rest priorities - Aggregation channel; Load
+ * (FIC0) channel and Load (FIC1).
+ */
+#define	CCM_REG_GR_LD0_PR					0xd0164
+/*
+ * [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
+ * highest priority is 3. It is supposed; that the Store channel priority is
+ * the compliment to 4 of the rest priorities - Aggregation channel; Load
+ * (FIC0) channel and Load (FIC1).
+ */
+#define	CCM_REG_GR_LD1_PR					0xd0168
+/* [RW 2] General flags index. */
+#define	CCM_REG_INV_DONE_Q					0xd0108
+/*
+ * [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
+ * context and sent to STORM; for a specific connection type. The double
+ * REG-pairs are used in order to align to STORM context row size of 128
+ * bits. The offset of these data in the STORM context is always 0. Index
+ * _(0..15) stands for the connection type (one of 16).
+ */
+#define	CCM_REG_N_SM_CTX_LD_0					0xd004c
+#define	CCM_REG_N_SM_CTX_LD_1					0xd0050
+#define	CCM_REG_N_SM_CTX_LD_2					0xd0054
+#define	CCM_REG_N_SM_CTX_LD_3					0xd0058
+#define	CCM_REG_N_SM_CTX_LD_4					0xd005c
+/*
+ * [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	CCM_REG_PBF_IFEN					0xd0028
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the pbf interface is detected.
+ */
+#define	CCM_REG_PBF_LENGTH_MIS					0xd0180
+/*
+ * [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	CCM_REG_PBF_WEIGHT					0xd00ac
+#define	CCM_REG_PHYS_QNUM1_0					0xd0134
+#define	CCM_REG_PHYS_QNUM1_1					0xd0138
+#define	CCM_REG_PHYS_QNUM2_0					0xd013c
+#define	CCM_REG_PHYS_QNUM2_1					0xd0140
+#define	CCM_REG_PHYS_QNUM3_0					0xd0144
+#define	CCM_REG_PHYS_QNUM3_1					0xd0148
+#define	CCM_REG_QOS_PHYS_QNUM0_0				0xd0114
+#define	CCM_REG_QOS_PHYS_QNUM0_1				0xd0118
+#define	CCM_REG_QOS_PHYS_QNUM1_0				0xd011c
+#define	CCM_REG_QOS_PHYS_QNUM1_1				0xd0120
+#define	CCM_REG_QOS_PHYS_QNUM2_0				0xd0124
+#define	CCM_REG_QOS_PHYS_QNUM2_1				0xd0128
+#define	CCM_REG_QOS_PHYS_QNUM3_0				0xd012c
+#define	CCM_REG_QOS_PHYS_QNUM3_1				0xd0130
+/*
+ * [RW 1] STORM - CM Interface enable. If 0 - the valid input is
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	CCM_REG_STORM_CCM_IFEN					0xd0010
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the STORM interface is detected.
+ */
+#define	CCM_REG_STORM_LENGTH_MIS				0xd016c
+/*
+ * [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
+ * mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
+ * weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
+ * tc.
+ */
+#define	CCM_REG_STORM_WEIGHT					0xd009c
+/*
+ * [RW 1] Input tsem Interface enable. If 0 - the valid input is
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	CCM_REG_TSEM_IFEN					0xd001c
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the tsem interface is detected.
+ */
+#define	CCM_REG_TSEM_LENGTH_MIS					0xd0174
+/*
+ * [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	CCM_REG_TSEM_WEIGHT					0xd00a0
+/*
+ * [RW 1] Input usem Interface enable. If 0 - the valid input is
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	CCM_REG_USEM_IFEN					0xd0024
+/*
+ * [RC 1] Set when message length mismatch (relative to last indication) at
+ * the usem interface is detected.
+ */
+#define	CCM_REG_USEM_LENGTH_MIS					0xd017c
+/*
+ * [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
+ * weight 8 (the most prioritised); 1 stands for weight 1(least prioritised);
+ * 2 stands for weight 2; tc.
+ */
+#define	CCM_REG_USEM_WEIGHT					0xd00a8
+/*
+ * [RW 1] Input xsem Interface enable. If 0 - the valid input is
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	CCM_REG_XSEM_IFEN					0xd0020
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication)
+ * at the xsem interface is detected.
+ */
+#define	CCM_REG_XSEM_LENGTH_MIS					0xd0178
+/*
+ * [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	CCM_REG_XSEM_WEIGHT					0xd00a4
+/*
+ * [RW 19] Indirect access to the descriptor table of the XX protection
+ * mechanism. The fields are: [5:0] - message length; [12:6] - message
+ * pointer; 18:13] - next pointer.
+ */
+#define	CCM_REG_XX_DESCR_TABLE					0xd0300
+#define	CCM_REG_XX_DESCR_TABLE_SIZE				36
+/* [R 7] Used to read the value of XX protection Free counter. */
+#define	CCM_REG_XX_FREE						0xd0184
+/*
+ * [RW 6] Initial value for the credit counter; responsible for fulfilling
+ * of the Input Stage XX protection buffer by the XX protection pending
+ * messages. Max credit available - 127. Write writes the initial credit
+ * value; read returns the current value of the credit counter. Must be
+ * initialized to maximum XX protected message size - 2 at start-up.
+ */
+#define	CCM_REG_XX_INIT_CRD					0xd0220
+/*
+ * [RW 7] The maximum number of pending messages; which may be stored in XX
+ * protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
+ * At write comprises the start value of the ~ccm_registers_xx_free.xx_free
+ * counter.
+ */
+#define	CCM_REG_XX_MSG_NUM					0xd0224
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define	CCM_REG_XX_OVFL_EVNT_ID					0xd0044
+/*
+ * [RW 18] Indirect access to the XX table of the XX protection mechanism.
+ * The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
+ * header pointer.
+ */
+#define	CCM_REG_XX_TABLE					0xd0280
+#define	CDU_REG_CDU_CHK_MASK0					0x101000
+#define	CDU_REG_CDU_CHK_MASK1					0x101004
+#define	CDU_REG_CDU_CONTROL0					0x101008
+#define	CDU_REG_CDU_DEBUG					0x101010
+#define	CDU_REG_CDU_GLOBAL_PARAMS				0x101020
+/* [RW 7] Interrupt mask register #0 read/write */
+#define	CDU_REG_CDU_INT_MASK					0x10103c
+/* [R 7] Interrupt register #0 read */
+#define	CDU_REG_CDU_INT_STS					0x101030
+/* [RW 5] Parity mask register #0 read/write */
+#define	CDU_REG_CDU_PRTY_MASK					0x10104c
+/* [R 5] Parity register #0 read */
+#define	CDU_REG_CDU_PRTY_STS					0x101040
+/*
+ * [RC 32] logging of error data in case of a CDU load error:
+ * {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
+ * ype_error; ctual_active; ctual_compressed_context};
+ */
+#define	CDU_REG_ERROR_DATA					0x101014
+/*
+ * [WB 216] L1TT ram access. each entry has the following format :
+ * {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
+ * ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]}
+ */
+#define	CDU_REG_L1TT						0x101800
+/*
+ * [WB 24] MATT ram access. each entry has the following
+ * format:{RegionLength[11:0]; egionOffset[11:0]}
+ */
+#define	CDU_REG_MATT						0x101100
+/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
+#define	CDU_REG_MF_MODE 					0x101050
+/*
+ * [R 1] indication the initializing the activity counter by the hardware
+ * was done.
+ */
+#define	CFC_REG_AC_INIT_DONE					0x104078
+/* [RW 13] activity counter ram access */
+#define	CFC_REG_ACTIVITY_COUNTER				0x104400
+#define	CFC_REG_ACTIVITY_COUNTER_SIZE				 256
+/* [R 1] indication the initializing the cams by the hardware was done. */
+#define	CFC_REG_CAM_INIT_DONE					0x10407c
+/* [RW 2] Interrupt mask register #0 read/write */
+#define	CFC_REG_CFC_INT_MASK					0x104108
+/* [R 2] Interrupt register #0 read */
+#define	CFC_REG_CFC_INT_STS					0x1040fc
+/* [RC 2] Interrupt register #0 read clear */
+#define	CFC_REG_CFC_INT_STS_CLR 				0x104100
+/* [RW 4] Parity mask register #0 read/write */
+#define	CFC_REG_CFC_PRTY_MASK					0x104118
+/* [R 4] Parity register #0 read */
+#define	CFC_REG_CFC_PRTY_STS					0x10410c
+/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
+#define	CFC_REG_CID_CAM 					0x104800
+#define	CFC_REG_CONTROL0					0x104028
+#define	CFC_REG_DEBUG0						0x104050
+/*
+ * [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
+ * vector) whether the cfc should be disabled upon it.
+ */
+#define	CFC_REG_DISABLE_ON_ERROR				0x104044
+/*
+ * [RC 14] CFC error vector. when the CFC detects an internal error it will
+ * set one of these bits. the bit description can be found in CFC
+ * specifications.
+ */
+#define	CFC_REG_ERROR_VECTOR					0x10403c
+/* [WB 93] LCID info ram access */
+#define	CFC_REG_INFO_RAM					0x105000
+#define	CFC_REG_INFO_RAM_SIZE					1024
+#define	CFC_REG_INIT_REG					0x10404c
+#define	CFC_REG_INTERFACES					0x104058
+/*
+ * [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
+ * field allows changing the priorities of the weighted-round-robin arbiter
+ * which selects which CFC load client should be served next.
+ */
+#define	CFC_REG_LCREQ_WEIGHTS					0x104084
+/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
+#define	CFC_REG_LINK_LIST					0x104c00
+#define	CFC_REG_LINK_LIST_SIZE					256
+/* [R 1] indication the initializing the link list by the hardware was done. */
+#define	CFC_REG_LL_INIT_DONE					0x104074
+/* [R 9] Number of allocated LCIDs which are at empty state */
+#define	CFC_REG_NUM_LCIDS_ALLOC 				0x104020
+/* [R 9] Number of Arriving LCIDs in Link List Block */
+#define	CFC_REG_NUM_LCIDS_ARRIVING				0x104004
+/* [R 9] Number of Leaving LCIDs in Link List Block */
+#define	CFC_REG_NUM_LCIDS_LEAVING				0x104018
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define	CSDM_REG_AGG_INT_EVENT_0				0xc2038
+#define	CSDM_REG_AGG_INT_EVENT_10				0xc2060
+#define	CSDM_REG_AGG_INT_EVENT_11				0xc2064
+#define	CSDM_REG_AGG_INT_EVENT_12				0xc2068
+#define	CSDM_REG_AGG_INT_EVENT_13				0xc206c
+#define	CSDM_REG_AGG_INT_EVENT_14				0xc2070
+#define	CSDM_REG_AGG_INT_EVENT_15				0xc2074
+#define	CSDM_REG_AGG_INT_EVENT_16				0xc2078
+#define	CSDM_REG_AGG_INT_EVENT_2				0xc2040
+#define	CSDM_REG_AGG_INT_EVENT_3				0xc2044
+#define	CSDM_REG_AGG_INT_EVENT_4				0xc2048
+#define	CSDM_REG_AGG_INT_EVENT_5				0xc204c
+#define	CSDM_REG_AGG_INT_EVENT_6				0xc2050
+#define	CSDM_REG_AGG_INT_EVENT_7				0xc2054
+#define	CSDM_REG_AGG_INT_EVENT_8				0xc2058
+#define	CSDM_REG_AGG_INT_EVENT_9				0xc205c
+/*
+ * [RW 1] For each aggregated interrupt index whether the mode is normal (0)
+ * or auto-mask-mode (1).
+ */
+#define	CSDM_REG_AGG_INT_MODE_10				0xc21e0
+#define	CSDM_REG_AGG_INT_MODE_11				0xc21e4
+#define	CSDM_REG_AGG_INT_MODE_12				0xc21e8
+#define	CSDM_REG_AGG_INT_MODE_13				0xc21ec
+#define	CSDM_REG_AGG_INT_MODE_14				0xc21f0
+#define	CSDM_REG_AGG_INT_MODE_15				0xc21f4
+#define	CSDM_REG_AGG_INT_MODE_16				0xc21f8
+#define	CSDM_REG_AGG_INT_MODE_6 				0xc21d0
+#define	CSDM_REG_AGG_INT_MODE_7 				0xc21d4
+#define	CSDM_REG_AGG_INT_MODE_8 				0xc21d8
+#define	CSDM_REG_AGG_INT_MODE_9 				0xc21dc
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define	CSDM_REG_CFC_RSP_START_ADDR				0xc2008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define	CSDM_REG_CMP_COUNTER_MAX0				0xc201c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define	CSDM_REG_CMP_COUNTER_MAX1				0xc2020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define	CSDM_REG_CMP_COUNTER_MAX2				0xc2024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define	CSDM_REG_CMP_COUNTER_MAX3				0xc2028
+/*
+ * [RW 13] The start address in the internal RAM for the completion
+ * counters.
+ */
+#define	CSDM_REG_CMP_COUNTER_START_ADDR 			0xc200c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	CSDM_REG_CSDM_INT_MASK_0				0xc229c
+#define	CSDM_REG_CSDM_INT_MASK_1				0xc22ac
+/* [R 32] Interrupt register #0 read */
+#define	CSDM_REG_CSDM_INT_STS_0 				0xc2290
+#define	CSDM_REG_CSDM_INT_STS_1 				0xc22a0
+/* [RW 11] Parity mask register #0 read/write */
+#define	CSDM_REG_CSDM_PRTY_MASK 				0xc22bc
+/* [R 11] Parity register #0 read */
+#define	CSDM_REG_CSDM_PRTY_STS					0xc22b0
+#define	CSDM_REG_ENABLE_IN1					0xc2238
+#define	CSDM_REG_ENABLE_IN2					0xc223c
+#define	CSDM_REG_ENABLE_OUT1					0xc2240
+#define	CSDM_REG_ENABLE_OUT2					0xc2244
+/*
+ * [RW 4] The initial number of messages that can be sent to the pxp control
+ * interface without receiving any ACK.
+ */
+#define	CSDM_REG_INIT_CREDIT_PXP_CTRL				0xc24bc
+/* [ST 32] The number of ACK after placement messages received */
+#define	CSDM_REG_NUM_OF_ACK_AFTER_PLACE 			0xc227c
+/* [ST 32] The number of packet end messages received from the parser */
+#define	CSDM_REG_NUM_OF_PKT_END_MSG				0xc2274
+/* [ST 32] The number of requests received from the pxp async if */
+#define	CSDM_REG_NUM_OF_PXP_ASYNC_REQ				0xc2278
+/* [ST 32] The number of commands received in queue 0 */
+#define	CSDM_REG_NUM_OF_Q0_CMD					0xc2248
+/* [ST 32] The number of commands received in queue 10 */
+#define	CSDM_REG_NUM_OF_Q10_CMD 				0xc226c
+/* [ST 32] The number of commands received in queue 11 */
+#define	CSDM_REG_NUM_OF_Q11_CMD 				0xc2270
+/* [ST 32] The number of commands received in queue 1 */
+#define	CSDM_REG_NUM_OF_Q1_CMD					0xc224c
+/* [ST 32] The number of commands received in queue 3 */
+#define	CSDM_REG_NUM_OF_Q3_CMD					0xc2250
+/* [ST 32] The number of commands received in queue 4 */
+#define	CSDM_REG_NUM_OF_Q4_CMD					0xc2254
+/* [ST 32] The number of commands received in queue 5 */
+#define	CSDM_REG_NUM_OF_Q5_CMD					0xc2258
+/* [ST 32] The number of commands received in queue 6 */
+#define	CSDM_REG_NUM_OF_Q6_CMD					0xc225c
+/* [ST 32] The number of commands received in queue 7 */
+#define	CSDM_REG_NUM_OF_Q7_CMD					0xc2260
+/* [ST 32] The number of commands received in queue 8 */
+#define	CSDM_REG_NUM_OF_Q8_CMD					0xc2264
+/* [ST 32] The number of commands received in queue 9 */
+#define	CSDM_REG_NUM_OF_Q9_CMD					0xc2268
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define	CSDM_REG_Q_COUNTER_START_ADDR				0xc2010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define	CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY			0xc2548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define	CSDM_REG_SYNC_PARSER_EMPTY				0xc2550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define	CSDM_REG_SYNC_SYNC_EMPTY				0xc2558
+/*
+ * [RW 32] Tick for timer counter. Applicable only when
+ * ~csdm_registers_timer_tick_enable.timer_tick_enable =1
+ */
+#define	CSDM_REG_TIMER_TICK					0xc2000
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define	CSEM_REG_ARB_CYCLE_SIZE 				0x200034
+/*
+ * [RW 3] The source that is associated with arbitration element 0. Source
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2
+ */
+#define	CSEM_REG_ARB_ELEMENT0					0x200020
+/*
+ * [RW 3] The source that is associated with arbitration element 1. Source
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~csem_registers_arb_element0.arb_element0.
+ */
+#define	CSEM_REG_ARB_ELEMENT1					0x200024
+/*
+ * [RW 3] The source that is associated with arbitration element 2. Source
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~csem_registers_arb_element0.arb_element0
+ * and ~csem_registers_arb_element1.arb_element1.
+ */
+#define	CSEM_REG_ARB_ELEMENT2					0x200028
+/*
+ * [RW 3] The source that is associated with arbitration element 3. Source
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+ * not be equal to register ~csem_registers_arb_element0.arb_element0 and
+ * ~csem_registers_arb_element1.arb_element1 and
+ * ~csem_registers_arb_element2.arb_element2.
+ */
+#define	CSEM_REG_ARB_ELEMENT3					0x20002c
+/*
+ * [RW 3] The source that is associated with arbitration element 4. Source
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~csem_registers_arb_element0.arb_element0
+ * and ~csem_registers_arb_element1.arb_element1 and
+ * ~csem_registers_arb_element2.arb_element2 and
+ * ~csem_registers_arb_element3.arb_element3.
+ */
+#define	CSEM_REG_ARB_ELEMENT4					0x200030
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	CSEM_REG_CSEM_INT_MASK_0				0x200110
+#define	CSEM_REG_CSEM_INT_MASK_1				0x200120
+/* [R 32] Interrupt register #0 read */
+#define	CSEM_REG_CSEM_INT_STS_0 				0x200104
+#define	CSEM_REG_CSEM_INT_STS_1 				0x200114
+/* [RW 32] Parity mask register #0 read/write */
+#define	CSEM_REG_CSEM_PRTY_MASK_0				0x200130
+#define	CSEM_REG_CSEM_PRTY_MASK_1				0x200140
+/* [R 32] Parity register #0 read */
+#define	CSEM_REG_CSEM_PRTY_STS_0				0x200124
+#define	CSEM_REG_CSEM_PRTY_STS_1				0x200134
+#define	CSEM_REG_ENABLE_IN					0x2000a4
+#define	CSEM_REG_ENABLE_OUT					0x2000a8
+/*
+ * [RW 32] This address space contains all registers and memories that are
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the sem_fast registers the base address
+ * ~fast_memory.fast_memory should be added to eachsem_fast register offset.
+ */
+#define	CSEM_REG_FAST_MEMORY					0x220000
+/*
+ * [RW 1] Disables input messages from FIC0 May be updated during run_time
+ * by the microcode.
+ */
+#define	CSEM_REG_FIC0_DISABLE					0x200224
+/*
+ * [RW 1] Disables input messages from FIC1 May be updated during run_time
+ * by the microcode.
+ */
+#define	CSEM_REG_FIC1_DISABLE					0x200234
+/*
+ * [RW 15] Interrupt table Read and write access to it is not possible in
+ * the middle of the work
+ */
+#define	CSEM_REG_INT_TABLE					0x200400
+/*
+ * [ST 24] Statistics register. The number of messages that entered through
+ FIC0
+ */
+#define	CSEM_REG_MSG_NUM_FIC0					0x200000
+/*
+ * [ST 24] Statistics register. The number of messages that entered through
+ * FIC1
+ */
+#define	CSEM_REG_MSG_NUM_FIC1					0x200004
+/*
+ * [ST 24] Statistics register. The number of messages that were sent to
+ * FOC0
+ */
+#define	CSEM_REG_MSG_NUM_FOC0					0x200008
+/*
+ * [ST 24] Statistics register. The number of messages that were sent to
+ * FOC1
+ */
+#define	CSEM_REG_MSG_NUM_FOC1					0x20000c
+/*
+ * [ST 24] Statistics register. The number of messages that were sent to
+ * FOC2
+ */
+#define	CSEM_REG_MSG_NUM_FOC2					0x200010
+/*
+ * [ST 24] Statistics register. The number of messages that were sent to
+ * FOC3
+ */
+#define	CSEM_REG_MSG_NUM_FOC3					0x200014
+/*
+ * [RW 1] Disables input messages from the passive buffer May be updated
+ * during run_time by the microcode.
+ */
+#define	CSEM_REG_PAS_DISABLE					0x20024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define	CSEM_REG_PASSIVE_BUFFER 				0x202000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define	CSEM_REG_PRAM						0x240000
+/* [R 16] Valid sleeping threads indication have bit per thread */
+#define	CSEM_REG_SLEEP_THREADS_VALID				0x20026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define	CSEM_REG_SLOW_EXT_STORE_EMPTY				0x2002a0
+/* [RW 16] List of free threads . There is a bit per thread. */
+#define	CSEM_REG_THREADS_LIST					0x2002e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define	CSEM_REG_TS_0_AS					0x200038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define	CSEM_REG_TS_10_AS					0x200060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define	CSEM_REG_TS_11_AS					0x200064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define	CSEM_REG_TS_12_AS					0x200068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define	CSEM_REG_TS_13_AS					0x20006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define	CSEM_REG_TS_14_AS					0x200070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define	CSEM_REG_TS_15_AS					0x200074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define	CSEM_REG_TS_16_AS					0x200078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define	CSEM_REG_TS_17_AS					0x20007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define	CSEM_REG_TS_18_AS					0x200080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define	CSEM_REG_TS_1_AS					0x20003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define	CSEM_REG_TS_2_AS					0x200040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define	CSEM_REG_TS_3_AS					0x200044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define	CSEM_REG_TS_4_AS					0x200048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define	CSEM_REG_TS_5_AS					0x20004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define	CSEM_REG_TS_6_AS					0x200050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define	CSEM_REG_TS_7_AS					0x200054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define	CSEM_REG_TS_8_AS					0x200058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define	CSEM_REG_TS_9_AS					0x20005c
+/* [RW 1] Parity mask register #0 read/write */
+#define	DBG_REG_DBG_PRTY_MASK					0xc0a8
+/* [R 1] Parity register #0 read */
+#define	DBG_REG_DBG_PRTY_STS					0xc09c
+/*
+ * [RW 32] Commands memory. The address to command X; row Y is to calculated
+ * as 14*X+Y.
+ */
+#define	DMAE_REG_CMD_MEM					0x102400
+#define	DMAE_REG_CMD_MEM_SIZE					 224
+/*
+ * [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
+ * initial value is all ones.
+ */
+#define	DMAE_REG_CRC16C_INIT					0x10201c
+/*
+ * [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
+ * CRC-16 T10 initial value is all ones.
+ */
+#define	DMAE_REG_CRC16T10_INIT					0x102020
+/* [RW 2] Interrupt mask register #0 read/write */
+#define	DMAE_REG_DMAE_INT_MASK					0x102054
+/* [RW 4] Parity mask register #0 read/write */
+#define	DMAE_REG_DMAE_PRTY_MASK 				0x102064
+/* [R 4] Parity register #0 read */
+#define	DMAE_REG_DMAE_PRTY_STS					0x102058
+/* [RW 1] Command 0 go. */
+#define	DMAE_REG_GO_C0						0x102080
+/* [RW 1] Command 1 go. */
+#define	DMAE_REG_GO_C1						0x102084
+/* [RW 1] Command 10 go. */
+#define	DMAE_REG_GO_C10 					0x102088
+/* [RW 1] Command 11 go. */
+#define	DMAE_REG_GO_C11 					0x10208c
+/* [RW 1] Command 12 go. */
+#define	DMAE_REG_GO_C12 					0x102090
+/* [RW 1] Command 13 go. */
+#define	DMAE_REG_GO_C13 					0x102094
+/* [RW 1] Command 14 go. */
+#define	DMAE_REG_GO_C14 					0x102098
+/* [RW 1] Command 15 go. */
+#define	DMAE_REG_GO_C15 					0x10209c
+/* [RW 1] Command 2 go. */
+#define	DMAE_REG_GO_C2						0x1020a0
+/* [RW 1] Command 3 go. */
+#define	DMAE_REG_GO_C3						0x1020a4
+/* [RW 1] Command 4 go. */
+#define	DMAE_REG_GO_C4						0x1020a8
+/* [RW 1] Command 5 go. */
+#define	DMAE_REG_GO_C5						0x1020ac
+/* [RW 1] Command 6 go. */
+#define	DMAE_REG_GO_C6						0x1020b0
+/* [RW 1] Command 7 go. */
+#define	DMAE_REG_GO_C7						0x1020b4
+/* [RW 1] Command 8 go. */
+#define	DMAE_REG_GO_C8						0x1020b8
+/* [RW 1] Command 9 go. */
+#define	DMAE_REG_GO_C9						0x1020bc
+/*
+ * [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
+ * input is disregarded; valid is deasserted; all other signals are treated
+ * as usual; if 1 - normal activity.
+ */
+#define	DMAE_REG_GRC_IFEN					0x102008
+/*
+ * [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
+ * acknowledge input is disregarded; valid is deasserted; full is asserted;
+ * all other signals are treated as usual; if 1 - normal activity.
+ */
+#define	DMAE_REG_PCI_IFEN					0x102004
+/*
+ * [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
+ * initial value to the credit counter; related to the address. Read returns
+ * the current value of the counter.
+ */
+#define	DMAE_REG_PXP_REQ_INIT_CRD				0x1020c0
+/* [RW 8] Aggregation command. */
+#define	DORQ_REG_AGG_CMD0					0x170060
+/* [RW 8] Aggregation command. */
+#define	DORQ_REG_AGG_CMD1					0x170064
+/* [RW 8] Aggregation command. */
+#define	DORQ_REG_AGG_CMD2					0x170068
+/* [RW 8] Aggregation command. */
+#define	DORQ_REG_AGG_CMD3					0x17006c
+/* [RW 28] UCM Header. */
+#define	DORQ_REG_CMHEAD_RX					0x170050
+/* [RW 32] Doorbell address for RBC doorbells (function 0). */
+#define	DORQ_REG_DB_ADDR0					0x17008c
+/* [RW 5] Interrupt mask register #0 read/write */
+#define	DORQ_REG_DORQ_INT_MASK					0x170180
+/* [R 5] Interrupt register #0 read */
+#define	DORQ_REG_DORQ_INT_STS					0x170174
+/* [RC 5] Interrupt register #0 read clear */
+#define	DORQ_REG_DORQ_INT_STS_CLR				0x170178
+/* [RW 2] Parity mask register #0 read/write */
+#define	DORQ_REG_DORQ_PRTY_MASK 				0x170190
+/* [R 2] Parity register #0 read */
+#define	DORQ_REG_DORQ_PRTY_STS					0x170184
+/* [RW 8] The address to write the DPM CID to STORM. */
+#define	DORQ_REG_DPM_CID_ADDR					0x170044
+/* [RW 5] The DPM mode CID extraction offset. */
+#define	DORQ_REG_DPM_CID_OFST					0x170030
+/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
+#define	DORQ_REG_DQ_FIFO_AFULL_TH				0x17007c
+/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
+#define	DORQ_REG_DQ_FIFO_FULL_TH				0x170078
+/*
+ * [R 13] Current value of the DQ FIFO fill level according to following
+ * pointer. The range is 0 - 256 FIFO rows; where each row stands for the
+ * doorbell.
+ */
+#define	DORQ_REG_DQ_FILL_LVLF					0x1700a4
+/*
+ * [R 1] DQ FIFO full status. Is set; when FIFO filling level is more o
+ * equal to full threshold; reset on full clear.
+ */
+#define	DORQ_REG_DQ_FULL_ST					0x1700c0
+/* [RW 28] The value sent to CM header in the case of CFC load error. */
+#define	DORQ_REG_ERR_CMHEAD					0x170058
+#define	DORQ_REG_IF_EN						0x170004
+#define	DORQ_REG_MODE_ACT					0x170008
+/* [RW 5] The normal mode CID extraction offset. */
+#define	DORQ_REG_NORM_CID_OFST					0x17002c
+/* [RW 28] TCM Header when only TCP context is loaded. */
+#define	DORQ_REG_NORM_CMHEAD_TX 				0x17004c
+/*
+ * [RW 3] The number of simultaneous outstanding requests to Context Fetc
+ * Interface.
+ */
+#define	DORQ_REG_OUTST_REQ					0x17003c
+#define	DORQ_REG_REGN						0x170038
+/*
+ * [R 4] Current value of response A counter credit. Initial credit i
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register.
+ */
+#define	DORQ_REG_RSPA_CRD_CNT					0x1700ac
+/*
+ * [R 4] Current value of response B counter credit. Initial credit i
+ * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
+ * register.
+ */
+#define	DORQ_REG_RSPB_CRD_CNT					0x1700b0
+/*
+ * [RW 4] The initial credit at the Doorbell Response Interface. The writ
+ * writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
+ * read reads this written value.
+ */
+#define	DORQ_REG_RSP_INIT_CRD					0x170048
+/*
+ * [RW 4] Initial activity counter value on the load request; when th
+ * shortcut is done.
+ */
+#define	DORQ_REG_SHRT_ACT_CNT					0x170070
+/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
+#define	DORQ_REG_SHRT_CMHEAD					0x170054
+#define	HC_CONFIG_0_REG_ATTN_BIT_EN_0				 (0x1<<4)
+#define	HC_CONFIG_0_REG_INT_LINE_EN_0				 (0x1<<3)
+#define	HC_CONFIG_0_REG_MSI_ATTN_EN_0				 (0x1<<7)
+#define	HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0			 (0x1<<2)
+#define	HC_CONFIG_0_REG_SINGLE_ISR_EN_0 			 (0x1<<1)
+#define	HC_REG_AGG_INT_0					0x108050
+#define	HC_REG_AGG_INT_1					0x108054
+#define	HC_REG_ATTN_BIT 					0x108120
+#define	HC_REG_ATTN_IDX 					0x108100
+#define	HC_REG_ATTN_MSG0_ADDR_L 				0x108018
+#define	HC_REG_ATTN_MSG1_ADDR_L 				0x108020
+#define	HC_REG_ATTN_NUM_P0					0x108038
+#define	HC_REG_ATTN_NUM_P1					0x10803c
+#define	HC_REG_COMMAND_REG					0x108180
+#define	HC_REG_CONFIG_0 					0x108000
+#define	HC_REG_CONFIG_1 					0x108004
+#define	HC_REG_FUNC_NUM_P0					0x1080ac
+#define	HC_REG_FUNC_NUM_P1					0x1080b0
+/* [RW 3] Parity mask register #0 read/write */
+#define	HC_REG_HC_PRTY_MASK					0x1080a0
+/* [R 3] Parity register #0 read */
+#define	HC_REG_HC_PRTY_STS					0x108094
+#define	HC_REG_INT_MASK 					0x108108
+#define	HC_REG_LEADING_EDGE_0					0x108040
+#define	HC_REG_LEADING_EDGE_1					0x108048
+#define	HC_REG_P0_PROD_CONS					0x108200
+#define	HC_REG_P1_PROD_CONS					0x108400
+#define	HC_REG_PBA_COMMAND					0x108140
+#define	HC_REG_PCI_CONFIG_0					0x108010
+#define	HC_REG_PCI_CONFIG_1					0x108014
+#define	HC_REG_STATISTIC_COUNTERS				0x109000
+#define	HC_REG_TRAILING_EDGE_0					0x108044
+#define	HC_REG_TRAILING_EDGE_1					0x10804c
+#define	HC_REG_UC_RAM_ADDR_0					0x108028
+#define	HC_REG_UC_RAM_ADDR_1					0x108030
+#define	HC_REG_USTORM_ADDR_FOR_COALESCE 			0x108068
+#define	HC_REG_VQID_0						0x108008
+#define	HC_REG_VQID_1						0x10800c
+#define	MCP_REG_MCPR_NVM_ACCESS_ENABLE				0x86424
+#define	MCP_REG_MCPR_NVM_ADDR					0x8640c
+#define	MCP_REG_MCPR_NVM_CFG4					0x8642c
+#define	MCP_REG_MCPR_NVM_COMMAND				0x86400
+#define	MCP_REG_MCPR_NVM_READ					0x86410
+#define	MCP_REG_MCPR_NVM_SW_ARB 				0x86420
+#define	MCP_REG_MCPR_NVM_WRITE					0x86408
+#define	MCP_REG_MCPR_SCRATCH					0xa0000
+/*
+ * [R 32] read first 32 bit after inversion of function 0. mapped a
+ * follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
+ * [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
+ * GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
+ * glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
+ * [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
+ * MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
+ * Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
+ * interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
+ * error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
+ * interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
+ * Parity error; [31] PBF Hw interrupt;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_1_FUNC_0			0xa42c
+#define	MISC_REG_AEU_AFTER_INVERT_1_FUNC_1			0xa430
+/*
+ * [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
+ * interrupt;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_1_MCP 			0xa434
+/*
+ * [R 32] read second 32 bit after inversion of function 0. mapped a
+ * follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+ * Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+ * interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+ * error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+ * interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+ * NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+ * [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+ * interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+ * Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+ * Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+ * Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+ * interrupt;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_2_FUNC_0			0xa438
+#define	MISC_REG_AEU_AFTER_INVERT_2_FUNC_1			0xa43c
+/*
+ * [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0
+ * PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
+ * [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
+ * [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
+ * XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_2_MCP 			0xa440
+/*
+ * [R 32] read third 32 bit after inversion of function 0. mapped a
+ * follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
+ * error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
+ * PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_3_FUNC_0			0xa444
+#define	MISC_REG_AEU_AFTER_INVERT_3_FUNC_1			0xa448
+/*
+ * [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0
+ * CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
+ * Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
+ * Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
+ * error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
+ * interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
+ * MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
+ * Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
+ * timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
+ * func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
+ * func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
+ * timers attn_4 func1; [30] General attn0; [31] General attn1;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_3_MCP 			0xa44c
+/*
+ * [R 32] read fourth 32 bit after inversion of function 0. mapped a
+ * follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_4_FUNC_0			0xa450
+#define	MISC_REG_AEU_AFTER_INVERT_4_FUNC_1			0xa454
+/*
+ * [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0
+ * General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
+ * [4] General attn6; [5] General attn7; [6] General attn8; [7] General
+ * attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
+ * General attn13; [12] General attn14; [13] General attn15; [14] General
+ * attn16; [15] General attn17; [16] General attn18; [17] General attn19;
+ * [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
+ * RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
+ * RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
+ * attention; [27] GRC Latched reserved access attention; [28] MCP Latched
+ * rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
+ * ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define	MISC_REG_AEU_AFTER_INVERT_4_MCP 			0xa458
+/*
+ * [W 14] write to this register results with the clear of the latche
+ * signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
+ * d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
+ * latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
+ * GRC Latched reserved access attention; one in d7 clears Latched
+ * rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
+ * Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
+ * ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
+ * pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
+ * from this register return zero
+ */
+#define	MISC_REG_AEU_CLR_LATCH_SIGNAL				0xa45c
+/*
+ * [RW 32] first 32b for enabling the output for function 0 output0. mappe
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+ * 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0			0xa06c
+#define	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1			0xa07c
+#define	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2			0xa08c
+#define	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3			0xa09c
+#define	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5			0xa0bc
+#define	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6			0xa0cc
+#define	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7			0xa0dc
+/*
+ * [RW 32] first 32b for enabling the output for function 1 output0. mappe
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
+ * 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0			0xa10c
+#define	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1			0xa11c
+#define	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2			0xa12c
+#define	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3			0xa13c
+#define	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5			0xa15c
+#define	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6			0xa16c
+#define	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7			0xa17c
+/*
+ * [RW 32] first 32b for enabling the output for close the gate nig. mappe
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+ * 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE1_NIG_0				0xa0ec
+#define	MISC_REG_AEU_ENABLE1_NIG_1				0xa18c
+/*
+ * [RW 32] first 32b for enabling the output for close the gate pxp. mappe
+ * as follows: [0] NIG attention for function0; [1] NIG attention for
+ * function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
+ * 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
+ * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
+ * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
+ * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
+ * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
+ * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
+ * TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE1_PXP_0				0xa0fc
+#define	MISC_REG_AEU_ENABLE1_PXP_1				0xa19c
+/*
+ * [RW 32] second 32b for enabling the output for function 0 output0. mappe
+ * as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+ * Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+ * interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+ * error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+ * interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+ * NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+ * [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+ * interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+ * Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+ * Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+ * Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+ * interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0			0xa070
+#define	MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1			0xa080
+/*
+ * [RW 32] second 32b for enabling the output for function 1 output0. mappe
+ * as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+ * Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+ * interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+ * error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+ * interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+ * NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+ * [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+ * interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+ * Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+ * Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+ * Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+ * interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0			0xa110
+#define	MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1			0xa120
+/*
+ * [RW 32] second 32b for enabling the output for close the gate nig. mappe
+ * as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+ * Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+ * interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+ * error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+ * interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+ * NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+ * [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+ * interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+ * Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+ * Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+ * Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+ * interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE2_NIG_0				0xa0f0
+#define	MISC_REG_AEU_ENABLE2_NIG_1				0xa190
+/*
+ * [RW 32] second 32b for enabling the output for close the gate pxp. mappe
+ * as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
+ * Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
+ * interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
+ * error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
+ * interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
+ * NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
+ * [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
+ * interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
+ * Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
+ * Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
+ * Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
+ * interrupt;
+ */
+#define	MISC_REG_AEU_ENABLE2_PXP_0				0xa100
+#define	MISC_REG_AEU_ENABLE2_PXP_1				0xa1a0
+/*
+ * [RW 32] third 32b for enabling the output for function 0 output0. mappe
+ * as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+ * Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+ * [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1;
+ */
+#define	MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0			0xa074
+#define	MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1			0xa084
+/*
+ * [RW 32] third 32b for enabling the output for function 1 output0. mappe
+ * as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+ * Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+ * [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1;
+ */
+#define	MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0			0xa114
+#define	MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1			0xa124
+/*
+ * [RW 32] third 32b for enabling the output for close the gate nig. mappe
+ * as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+ * Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+ * [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1;
+ */
+#define	MISC_REG_AEU_ENABLE3_NIG_0				0xa0f4
+#define	MISC_REG_AEU_ENABLE3_NIG_1				0xa194
+/*
+ * [RW 32] third 32b for enabling the output for close the gate pxp. mappe
+ * as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
+ * Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
+ * [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
+ * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
+ * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
+ * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
+ * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
+ * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
+ * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
+ * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
+ * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
+ * attn1;
+ */
+#define	MISC_REG_AEU_ENABLE3_PXP_0				0xa104
+#define	MISC_REG_AEU_ENABLE3_PXP_1				0xa1a4
+/*
+ * [RW 32] fourth 32b for enabling the output for function 0 output0.mappe
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0			0xa078
+#define	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2			0xa098
+#define	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4			0xa0b8
+#define	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5			0xa0c8
+#define	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6			0xa0d8
+#define	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7			0xa0e8
+/*
+ * [RW 32] fourth 32b for enabling the output for function 1 output0.mappe
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0			0xa118
+#define	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2			0xa138
+#define	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4			0xa158
+#define	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5			0xa168
+#define	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6			0xa178
+#define	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7			0xa188
+/*
+ * [RW 32] fourth 32b for enabling the output for close the gate nig.mappe
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define	MISC_REG_AEU_ENABLE4_NIG_0				0xa0f8
+#define	MISC_REG_AEU_ENABLE4_NIG_1				0xa198
+/*
+ * [RW 32] fourth 32b for enabling the output for close the gate pxp.mappe
+ * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
+ * General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
+ * [7] General attn9; [8] General attn10; [9] General attn11; [10] General
+ * attn12; [11] General attn13; [12] General attn14; [13] General attn15;
+ * [14] General attn16; [15] General attn17; [16] General attn18; [17]
+ * General attn19; [18] General attn20; [19] General attn21; [20] Main power
+ * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
+ * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
+ * Latched timeout attention; [27] GRC Latched reserved access attention;
+ * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
+ * Latched ump_tx_parity; [31] MCP Latched scpad_parity;
+ */
+#define	MISC_REG_AEU_ENABLE4_PXP_0				0xa108
+#define	MISC_REG_AEU_ENABLE4_PXP_1				0xa1a8
+/*
+ * [RW 1] set/clr general attention 0; this will set/clr bit 94 in the ae
+ * 128 bit vector
+ */
+#define	MISC_REG_AEU_GENERAL_ATTN_0				0xa000
+#define	MISC_REG_AEU_GENERAL_ATTN_1				0xa004
+#define	MISC_REG_AEU_GENERAL_ATTN_10				0xa028
+#define	MISC_REG_AEU_GENERAL_ATTN_11				0xa02c
+#define	MISC_REG_AEU_GENERAL_ATTN_12				0xa030
+#define	MISC_REG_AEU_GENERAL_ATTN_2				0xa008
+#define	MISC_REG_AEU_GENERAL_ATTN_3				0xa00c
+#define	MISC_REG_AEU_GENERAL_ATTN_4				0xa010
+#define	MISC_REG_AEU_GENERAL_ATTN_5				0xa014
+#define	MISC_REG_AEU_GENERAL_ATTN_6				0xa018
+#define	MISC_REG_AEU_GENERAL_ATTN_7				0xa01c
+#define	MISC_REG_AEU_GENERAL_ATTN_8				0xa020
+#define	MISC_REG_AEU_GENERAL_ATTN_9				0xa024
+#define	MISC_REG_AEU_GENERAL_MASK				0xa61c
+/*
+ * [RW 32] first 32b for inverting the input for function 0; for each bit
+ * 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
+ * function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
+ * [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
+ * [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
+ * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
+ * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
+ * SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
+ * for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
+ * Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
+ * interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
+ * Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
+ * Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt;
+ */
+#define	MISC_REG_AEU_INVERTER_1_FUNC_0				0xa22c
+#define	MISC_REG_AEU_INVERTER_1_FUNC_1				0xa23c
+/*
+ * [RW 32] second 32b for inverting the input for function 0; for each bit
+ * 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
+ * error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
+ * interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
+ * Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
+ * interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
+ * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
+ * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
+ * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
+ * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
+ * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
+ * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
+ * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt;
+ */
+#define	MISC_REG_AEU_INVERTER_2_FUNC_0				0xa230
+#define	MISC_REG_AEU_INVERTER_2_FUNC_1				0xa240
+/*
+ * [RW 10] [7:0] = mask 8 attention output signals toward IGU function0
+ * [9:8] = raserved. Zero = mask; one = unmask
+ */
+#define	MISC_REG_AEU_MASK_ATTN_FUNC_0				0xa060
+#define	MISC_REG_AEU_MASK_ATTN_FUNC_1				0xa064
+/* [RW 1] If set a system kill occurred */
+#define	MISC_REG_AEU_SYS_KILL_OCCURRED				0xa610
+/*
+ * [RW 32] Represent the status of the input vector to the AEU when a syste
+ * kill occurred. The register is reset in por reset. Mapped as follows: [0]
+ * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
+ * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
+ * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
+ * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
+ * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
+ * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
+ * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
+ * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
+ * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
+ * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
+ * Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
+ * interrupt;
+ */
+#define	MISC_REG_AEU_SYS_KILL_STATUS_0				0xa600
+#define	MISC_REG_AEU_SYS_KILL_STATUS_1				0xa604
+#define	MISC_REG_AEU_SYS_KILL_STATUS_2				0xa608
+#define	MISC_REG_AEU_SYS_KILL_STATUS_3				0xa60c
+/*
+ * [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' -
+ * Port.
+ */
+#define	MISC_REG_BOND_ID					0xa400
+/*
+ * [R 8] These bits indicate the metal revision of the chip. This valu
+ * starts at 0x00 for each all-layer tape-out and increments by one for each
+ * tape-out.
+ */
+#define	MISC_REG_CHIP_METAL					0xa404
+/* [R 16] These bits indicate the part number for the chip. */
+#define	MISC_REG_CHIP_NUM					0xa408
+/*
+ * [R 4] These bits indicate the base revision of the chip. This valu
+ * starts at 0x0 for the A0 tape-out and increments by one for each
+ * all-layer tape-out.
+ */
+#define	MISC_REG_CHIP_REV					0xa40c
+/*
+ * [RW 32] The following driver registers(1...16) represent 16 drivers an
+ * 32 clients. Each client can be controlled by one driver only. One in each
+ * bit represent that this driver control the appropriate client (Ex: bit 5
+ * is set means this driver control client number 5). addr1 = set; addr0 =
+ * clear; read from both addresses will give the same result = status. write
+ * to address 1 will set a request to control all the clients that their
+ * appropriate bit (in the write command) is set. if the client is free (the
+ * appropriate bit in all the other drivers is clear) one will be written to
+ * that driver register; if the client isn't free the bit will remain zero.
+ * if the appropriate bit is set (the driver request to gain control on a
+ * client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
+ * interrupt will be asserted). write to address 0 will set a request to
+ * free all the clients that their appropriate bit (in the write command) is
+ * set. if the appropriate bit is clear (the driver request to free a client
+ * it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
+ * be asserted).
+ */
+#define	MISC_REG_DRIVER_CONTROL_1				0xa510
+#define	MISC_REG_DRIVER_CONTROL_7				0xa3c8
+/*
+ * [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit
+ * only.
+ */
+#define	MISC_REG_E1HMF_MODE					0xa5f8
+/* [RW 32] Debug only: spare RW register reset by core reset */
+#define	MISC_REG_GENERIC_CR_0					0xa460
+/*
+ * [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any o
+ * these bits is written as a '1'; the corresponding SPIO bit will turn off
+ * it's drivers and become an input. This is the reset state of all GPIO
+ * pins. The read value of these bits will be a '1' if that last command
+ * (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
+ * [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
+ * as a '1'; the corresponding GPIO bit will drive low. The read value of
+ * these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
+ * this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
+ * SET When any of these bits is written as a '1'; the corresponding GPIO
+ * bit will drive high (if it has that capability). The read value of these
+ * bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
+ * bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
+ * RO; These bits indicate the read value of each of the eight GPIO pins.
+ * This is the result value of the pin; not the drive value. Writing these
+ * bits will have not effect.
+ */
+#define	MISC_REG_GPIO						0xa490
+/*
+ * [RW 8] These bits enable the GPIO_INTs to signals event to th
+ * IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
+ * p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
+ * [7] p1_gpio_3;
+ */
+#define	MISC_REG_GPIO_EVENT_EN					0xa2bc
+/*
+ * [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing
+ * '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
+ * This will acknowledge an interrupt on the falling edge of corresponding
+ * GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
+ * Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
+ * register. This will acknowledge an interrupt on the rising edge of
+ * corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
+ * OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
+ * value. When the ~INT_STATE bit is set; this bit indicates the OLD value
+ * of the pin such that if ~INT_STATE is set and this bit is '0'; then the
+ * interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
+ * is '1'; then the interrupt is due to a high to low edge (reset value 0).
+ * [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
+ * current GPIO interrupt state for each GPIO pin. This bit is cleared when
+ * the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
+ * set when the GPIO input does not match the current value in #OLD_VALUE
+ * (reset value 0).
+ */
+#define	MISC_REG_GPIO_INT					0xa494
+/*
+ * [R 28] this field hold the last information that caused reserve
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae
+ */
+#define	MISC_REG_GRC_RSV_ATTN					0xa3c0
+/*
+ * [R 28] this field hold the last information that caused timeou
+ * attention. bits [19:0] - address; [22:20] function; [23] reserved;
+ * [27:24] the master that caused the attention - according to the following
+ * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
+ * dbu; 8 = dmae
+ */
+#define	MISC_REG_GRC_TIMEOUT_ATTN				0xa3c4
+/*
+ * [RW 1] Setting this bit enables a timer in the GRC block to timeout an
+ * access that does not finish within
+ * ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
+ * cleared; this timeout is disabled. If this timeout occurs; the GRC shall
+ * assert it attention output.
+ */
+#define	MISC_REG_GRC_TIMEOUT_EN 				0xa280
+/*
+ * [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order o
+ * the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
+ * 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
+ * (reset value 001) Charge pump current control; 111 for 720u; 011 for
+ * 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
+ * Global bias control; When bit 7 is high bias current will be 10 0gh; When
+ * bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
+ * Pll_observe (reset value 010) Bits to control observability. bit 10 is
+ * for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
+ * (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
+ * and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
+ * sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
+ * internally). [14] reserved (reset value 0) Reset for VCO sequencer is
+ * connected to RESET input directly. [15] capRetry_en (reset value 0)
+ * enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
+ * value 0) bit to continuously monitor vco freq (inverted). [17]
+ * freqDetRestart_en (reset value 0) bit to enable restart when not freq
+ * locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
+ * retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
+ * 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
+ * pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
+ * (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
+ * 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
+ * bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
+ * enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
+ * capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
+ * restart. [27] capSelectM_en (reset value 0) bit to enable cap select
+ * register bits.
+ */
+#define	MISC_REG_LCPLL_CTRL_1					0xa2a4
+#define	MISC_REG_LCPLL_CTRL_REG_2				0xa2a8
+/* [RW 4] Interrupt mask register #0 read/write */
+#define	MISC_REG_MISC_INT_MASK					0xa388
+/* [RW 1] Parity mask register #0 read/write */
+#define	MISC_REG_MISC_PRTY_MASK 				0xa398
+/* [R 1] Parity register #0 read */
+#define	MISC_REG_MISC_PRTY_STS					0xa38c
+#define	MISC_REG_NIG_WOL_P0					0xa270
+#define	MISC_REG_NIG_WOL_P1					0xa274
+/*
+ * [R 1] If set indicate that the pcie_rst_b was asserted without pers
+ * assertion
+ */
+#define	MISC_REG_PCIE_HOT_RESET 				0xa618
+/*
+ * [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911
+ * inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
+ * divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
+ * divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
+ * divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
+ * divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
+ * freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
+ * (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
+ * 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
+ * Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
+ * value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
+ * 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
+ * [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
+ * Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
+ * testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
+ * testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
+ * testa_en (reset value 0);
+ */
+#define	MISC_REG_PLL_STORM_CTRL_1				0xa294
+#define	MISC_REG_PLL_STORM_CTRL_2				0xa298
+#define	MISC_REG_PLL_STORM_CTRL_3				0xa29c
+#define	MISC_REG_PLL_STORM_CTRL_4				0xa2a0
+/*
+ * [RW 32] reset reg#2; rite/read one = the specific block is out of reset
+ * write/read zero = the specific block is in reset; addr 0-wr- the write
+ * value will be written to the register; addr 1-set - one will be written
+ * to all the bits that have the value of one in the data written (bits that
+ * have the value of zero will not be change) ; addr 2-clear - zero will be
+ * written to all the bits that have the value of one in the data written
+ * (bits that have the value of zero will not be change); addr 3-ignore;
+ * read ignore from all addr except addr 00; inside order of the bits is:
+ * [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
+ * [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
+ * rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
+ * [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
+ * Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
+ * rst_pxp_rq_rd_wr; 31:17] reserved
+ */
+#define	MISC_REG_RESET_REG_2					0xa590
+/*
+ * [RW 20] 20 bit GRC address where the scratch-pad of the MCP that i
+ * shared with the driver resides
+ */
+#define	MISC_REG_SHARED_MEM_ADDR				0xa2b4
+/*
+ * [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'
+ * the corresponding SPIO bit will turn off it's drivers and become an
+ * input. This is the reset state of all SPIO pins. The read value of these
+ * bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
+ * bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
+ * is written as a '1'; the corresponding SPIO bit will drive low. The read
+ * value of these bits will be a '1' if that last command (#SET; #CLR; or
+ * #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
+ * these bits is written as a '1'; the corresponding SPIO bit will drive
+ * high (if it has that capability). The read value of these bits will be a
+ * '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
+ * (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
+ * each of the eight SPIO pins. This is the result value of the pin; not the
+ * drive value. Writing these bits will have not effect. Each 8 bits field
+ * is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
+ * from VAUX. (This is an output pin only; the FLOAT field is not applicable
+ * for this pin); [1] VAUX Disable; when pulsed low; disables supply form
+ * VAUX. (This is an output pin only; FLOAT field is not applicable for this
+ * pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
+ * select VAUX supply. (This is an output pin only; it is not controlled by
+ * the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
+ * field is not applicable for this pin; only the VALUE fields is relevant -
+ * it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
+ * Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
+ * device ID select; read by UMP firmware.
+ */
+#define	MISC_REG_SPIO						0xa4fc
+/*
+ * [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC
+ * according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
+ * [7:0] reserved
+ */
+#define	MISC_REG_SPIO_EVENT_EN					0xa2b8
+/*
+ * [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears th
+ * corresponding bit in the #OLD_VALUE register. This will acknowledge an
+ * interrupt on the falling edge of corresponding SPIO input (reset value
+ * 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
+ * in the #OLD_VALUE register. This will acknowledge an interrupt on the
+ * rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
+ * RO; These bits indicate the old value of the SPIO input value. When the
+ * ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
+ * that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
+ * to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
+ * interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
+ * RO; These bits indicate the current SPIO interrupt state for each SPIO
+ * pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
+ * command bit is written. This bit is set when the SPIO input does not
+ * match the current value in #OLD_VALUE (reset value 0).
+ */
+#define	MISC_REG_SPIO_INT					0xa500
+/*
+ * [RW 32] reload value for counter 4 if reload; the value will be reload i
+ * the counter reached zero and the reload bit
+ * (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set.
+ */
+#define	MISC_REG_SW_TIMER_RELOAD_VAL_4				0xa2fc
+/*
+ * [RW 32] the value of the counter for sw timers1-8. there are 8 addresse
+ * in this register. addres 0 - timer 1; address - timer 2�address 7 -
+ * timer 8.
+ */
+#define	MISC_REG_SW_TIMER_VAL					0xa5c0
+/*
+ * [RW 1] Set by the MCP to remember if one or more of the drivers is/ar
+ * loaded; 0-prepare; -unprepare
+ */
+#define	MISC_REG_UNPREPARED					0xa424
+#define	NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST	 (0x1<<0)
+#define	NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST	 (0x1<<1)
+#define	NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN	 (0x1<<4)
+#define	NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST	 (0x1<<2)
+#define	NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN	 (0x1<<3)
+#define	NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT	 (0x1<<0)
+#define	NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS	 (0x1<<9)
+#define	NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 	 (0x1<<15)
+#define	NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS	 (0xf<<18)
+/* [RW 1] Input enable for RX_BMAC0 IF */
+#define	NIG_REG_BMAC0_IN_EN					0x100ac
+/* [RW 1] output enable for TX_BMAC0 IF */
+#define	NIG_REG_BMAC0_OUT_EN					0x100e0
+/* [RW 1] output enable for TX BMAC pause port 0 IF */
+#define	NIG_REG_BMAC0_PAUSE_OUT_EN				0x10110
+/* [RW 1] output enable for RX_BMAC0_REGS IF */
+#define	NIG_REG_BMAC0_REGS_OUT_EN				0x100e8
+/* [RW 1] output enable for RX BRB1 port0 IF */
+#define	NIG_REG_BRB0_OUT_EN					0x100f8
+/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
+#define	NIG_REG_BRB0_PAUSE_IN_EN				0x100c4
+/* [RW 1] output enable for RX BRB1 port1 IF */
+#define	NIG_REG_BRB1_OUT_EN					0x100fc
+/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
+#define	NIG_REG_BRB1_PAUSE_IN_EN				0x100c8
+/* [RW 1] output enable for RX BRB1 LP IF */
+#define	NIG_REG_BRB_LB_OUT_EN					0x10100
+/*
+ * [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64
+ * error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
+ * 72:73]-vnic_num; 81:74]-sideband_info
+ */
+#define	NIG_REG_DEBUG_PACKET_LB 				0x10800
+/* [RW 1] Input enable for TX Debug packet */
+#define	NIG_REG_EGRESS_DEBUG_IN_EN				0x100dc
+/*
+ * [RW 1] If 1 - egress drain mode for port0 is active. In this mode al
+ * packets from PBFare not forwarded to the MAC and just deleted from FIFO.
+ * First packet may be deleted from the middle. And last packet will be
+ * always deleted till the end.
+ */
+#define	NIG_REG_EGRESS_DRAIN0_MODE				0x10060
+/* [RW 1] Output enable to EMAC0 */
+#define	NIG_REG_EGRESS_EMAC0_OUT_EN				0x10120
+/*
+ * [RW 1] MAC configuration for packets of port0. If 1 - all packet output
+ * to emac for port0; other way to bmac for port0
+ */
+#define	NIG_REG_EGRESS_EMAC0_PORT				0x10058
+/* [RW 1] Input enable for TX PBF user packet port0 IF */
+#define	NIG_REG_EGRESS_PBF0_IN_EN				0x100cc
+/* [RW 1] Input enable for TX PBF user packet port1 IF */
+#define	NIG_REG_EGRESS_PBF1_IN_EN				0x100d0
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define	NIG_REG_EGRESS_UMP0_IN_EN				0x100d4
+/* [RW 1] Input enable for RX_EMAC0 IF */
+#define	NIG_REG_EMAC0_IN_EN					0x100a4
+/* [RW 1] output enable for TX EMAC pause port 0 IF */
+#define	NIG_REG_EMAC0_PAUSE_OUT_EN				0x10118
+/*
+ * [R 1] status from emac0. This bit is set when MDINT from either th
+ * EXT_MDINT pin or from the Copper PHY is driven low. This condition must
+ * be cleared in the attached PHY device that is driving the MINT pin.
+ */
+#define	NIG_REG_EMAC0_STATUS_MISC_MI_INT			0x10494
+/*
+ * [WB 48] This address space contains BMAC0 registers. The BMAC register
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
+ * added to each BMAC register offset
+ */
+#define	NIG_REG_INGRESS_BMAC0_MEM				0x10c00
+/*
+ * [WB 48] This address space contains BMAC1 registers. The BMAC register
+ * are described in appendix A. In order to access the BMAC0 registers; the
+ * base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
+ * added to each BMAC register offset
+ */
+#define	NIG_REG_INGRESS_BMAC1_MEM				0x11000
+/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
+#define	NIG_REG_INGRESS_EOP_LB_EMPTY				0x104e0
+/*
+ * [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Dat
+ * packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16]
+ */
+#define	NIG_REG_INGRESS_EOP_LB_FIFO				0x104e4
+/*
+ * [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latc
+ * logic for interrupts must be used. Enable per bit of interrupt of
+ * ~latch_status.latch_status
+ */
+#define	NIG_REG_LATCH_BC_0					0x16210
+/*
+ * [RW 27] Latch for each interrupt from Unicore.b[0
+ * status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
+ * b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
+ * b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
+ * b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
+ * b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
+ * b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
+ * b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
+ * b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
+ * b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
+ * b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
+ * b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
+ * b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs
+ */
+#define	NIG_REG_LATCH_STATUS_0					0x18000
+/* [RW 1] led 10g for port 0 */
+#define	NIG_REG_LED_10G_P0					0x10320
+/* [RW 1] led 10g for port 1 */
+#define	NIG_REG_LED_10G_P1					0x10324
+/*
+ * [RW 1] Port0: This bit is set to enable the use of th
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
+ * defined below. If this bit is cleared; then the blink rate will be about
+ * 8Hz.
+ */
+#define	NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0			0x10318
+/*
+ * [RW 12] Port0: Specifies the period of each blink cycle (on + off) fo
+ * Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
+ * is reset to 0x080; giving a default blink period of approximately 8Hz.
+ */
+#define	NIG_REG_LED_CONTROL_BLINK_RATE_P0			0x10310
+/*
+ * [RW 1] Port0: If set along with th
+ * ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
+ * bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
+ * bit; the Traffic LED will blink with the blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields.
+ */
+#define	NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0			0x10308
+/*
+ * [RW 1] Port0: If set overrides hardware control of the Traffic LED. Th
+ * Traffic LED will then be controlled via bit ~nig_registers_
+ * led_control_traffic_p0.led_control_traffic_p0 and bit
+ * ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0
+ */
+#define	NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 		0x102f8
+/*
+ * [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit
+ * turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
+ * set; the LED will blink with blink rate specified in
+ * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
+ * ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
+ * fields.
+ */
+#define	NIG_REG_LED_CONTROL_TRAFFIC_P0				0x10300
+/*
+ * [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3
+ * 9-11PHY7; 12 MAC4; 13-15 PHY10;
+ */
+#define	NIG_REG_LED_MODE_P0					0x102f0
+/*
+ * [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1
+ * tsdm enable; b2- usdm enable
+ */
+#define	NIG_REG_LLFC_EGRESS_SRC_ENABLE_0			0x16070
+#define	NIG_REG_LLFC_EGRESS_SRC_ENABLE_1			0x16074
+/*
+ * [RW 1] SAFC enable for port0. This register may get 1 only whe
+ * ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
+ * port
+ */
+#define	NIG_REG_LLFC_ENABLE_0					0x16208
+/* [RW 16] classes are high-priority for port0 */
+#define	NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0			0x16058
+/* [RW 16] classes are low-priority for port0 */
+#define	NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0			0x16060
+/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
+#define	NIG_REG_LLFC_OUT_EN_0					0x160c8
+#define	NIG_REG_LLH0_ACPI_PAT_0_CRC				0x1015c
+#define	NIG_REG_LLH0_ACPI_PAT_6_LEN				0x10154
+#define	NIG_REG_LLH0_BRB1_DRV_MASK				0x10244
+#define	NIG_REG_LLH0_BRB1_DRV_MASK_MF				0x16048
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define	NIG_REG_LLH0_BRB1_NOT_MCP				0x1025c
+/*
+ * [RW 2] Determine the classification participants. 0: no classification.1
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr.
+ */
+#define	NIG_REG_LLH0_CLS_TYPE					0x16080
+/* [RW 32] cm header for llh0 */
+#define	NIG_REG_LLH0_CM_HEADER					0x1007c
+#define	NIG_REG_LLH0_DEST_IP_0_1				0x101dc
+#define	NIG_REG_LLH0_DEST_MAC_0_0				0x101c0
+/*
+ * [RW 16] destination TCP address 1. The LLH will look for this address i
+ * all incoming packets.
+ */
+#define	NIG_REG_LLH0_DEST_TCP_0 				0x10220
+/*
+ * [RW 16] destination UDP address 1 The LLH will look for this address i
+ * all incoming packets.
+ */
+#define	NIG_REG_LLH0_DEST_UDP_0 				0x10214
+#define	NIG_REG_LLH0_ERROR_MASK 				0x1008c
+/* [RW 8] event id for llh0 */
+#define	NIG_REG_LLH0_EVENT_ID					0x10084
+#define	NIG_REG_LLH0_FUNC_EN					0x160fc
+#define	NIG_REG_LLH0_FUNC_VLAN_ID				0x16100
+/*
+ * [RW 1] Determine the IP version to look for i
+ * ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4
+ */
+#define	NIG_REG_LLH0_IPV4_IPV6_0				0x10208
+/* [RW 1] t bit for llh0 */
+#define	NIG_REG_LLH0_T_BIT					0x10074
+/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
+#define	NIG_REG_LLH0_VLAN_ID_0					0x1022c
+/* [RW 8] init credit counter for port0 in LLH */
+#define	NIG_REG_LLH0_XCM_INIT_CREDIT				0x10554
+#define	NIG_REG_LLH0_XCM_MASK					0x10130
+#define	NIG_REG_LLH1_BRB1_DRV_MASK				0x10248
+/* [RW 1] send to BRB1 if no match on any of RMP rules. */
+#define	NIG_REG_LLH1_BRB1_NOT_MCP				0x102dc
+/*
+ * [RW 2] Determine the classification participants. 0: no classification.1
+ * classification upon VLAN id. 2: classification upon MAC address. 3:
+ * classification upon both VLAN id & MAC addr.
+ */
+#define	NIG_REG_LLH1_CLS_TYPE					0x16084
+/* [RW 32] cm header for llh1 */
+#define	NIG_REG_LLH1_CM_HEADER					0x10080
+#define	NIG_REG_LLH1_ERROR_MASK 				0x10090
+/* [RW 8] event id for llh1 */
+#define	NIG_REG_LLH1_EVENT_ID					0x10088
+/* [RW 8] init credit counter for port1 in LLH */
+#define	NIG_REG_LLH1_XCM_INIT_CREDIT				0x10564
+#define	NIG_REG_LLH1_XCM_MASK					0x10134
+/*
+ * [RW 1] When this bit is set; the LLH will expect all packets to be wit
+ * e1hov
+ */
+#define	NIG_REG_LLH_E1HOV_MODE					0x160d8
+/*
+ * [RW 1] When this bit is set; the LLH will classify the packet befor
+ * sending it to the BRB or calculating WoL on it.
+ */
+#define	NIG_REG_LLH_MF_MODE					0x16024
+#define	NIG_REG_MASK_INTERRUPT_PORT0				0x10330
+#define	NIG_REG_MASK_INTERRUPT_PORT1				0x10334
+/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
+#define	NIG_REG_NIG_EMAC0_EN					0x1003c
+/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
+#define	NIG_REG_NIG_EMAC1_EN					0x10040
+/*
+ * [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to th
+ * EMAC0 to strip the CRC from the ingress packets.
+ */
+#define	NIG_REG_NIG_INGRESS_EMAC0_NO_CRC			0x10044
+/* [R 32] Interrupt register #0 read */
+#define	NIG_REG_NIG_INT_STS_0					0x103b0
+#define	NIG_REG_NIG_INT_STS_1					0x103c0
+/* [R 32] Parity register #0 read */
+#define	NIG_REG_NIG_PRTY_STS					0x103d0
+/*
+ * [RW 1] Pause enable for port0. This register may get 1 only whe
+ * ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
+ * port
+ */
+#define	NIG_REG_PAUSE_ENABLE_0					0x160c0
+/* [RW 1] Input enable for RX PBF LP IF */
+#define	NIG_REG_PBF_LB_IN_EN					0x100b4
+/*
+ * [RW 1] Value of this register will be transmitted to port swap whe
+ * ~nig_registers_strap_override.strap_override =1
+ */
+#define	NIG_REG_PORT_SWAP					0x10394
+/* [RW 1] output enable for RX parser descriptor IF */
+#define	NIG_REG_PRS_EOP_OUT_EN					0x10104
+/* [RW 1] Input enable for RX parser request IF */
+#define	NIG_REG_PRS_REQ_IN_EN					0x100b8
+/* [RW 5] control to serdes - CL45 DEVAD */
+#define	NIG_REG_SERDES0_CTRL_MD_DEVAD				0x10370
+/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
+#define	NIG_REG_SERDES0_CTRL_MD_ST				0x1036c
+/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
+#define	NIG_REG_SERDES0_CTRL_PHY_ADDR				0x10374
+/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
+#define	NIG_REG_SERDES0_STATUS_LINK_STATUS			0x10578
+/*
+ * [R 32] Rx statistics : In user packets discarded due to BRB backpressur
+ * for port0
+ */
+#define	NIG_REG_STAT0_BRB_DISCARD				0x105f0
+/*
+ * [R 32] Rx statistics : In user packets truncated due to BRB backpressur
+ * for port0
+ */
+#define	NIG_REG_STAT0_BRB_TRUNCATE				0x105f8
+/*
+ * [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 tha
+ * between 1024 and 1522 bytes for port0
+ */
+#define	NIG_REG_STAT0_EGRESS_MAC_PKT0				0x10750
+/*
+ * [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 tha
+ * between 1523 bytes and above for port0
+ */
+#define	NIG_REG_STAT0_EGRESS_MAC_PKT1				0x10760
+/*
+ * [R 32] Rx statistics : In user packets discarded due to BRB backpressur
+ * for port1
+ */
+#define	NIG_REG_STAT1_BRB_DISCARD				0x10628
+/*
+ * [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 tha
+ * between 1024 and 1522 bytes for port1
+ */
+#define	NIG_REG_STAT1_EGRESS_MAC_PKT0				0x107a0
+/*
+ * [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 tha
+ * between 1523 bytes and above for port1
+ */
+#define	NIG_REG_STAT1_EGRESS_MAC_PKT1				0x107b0
+/* [WB_R 64] Rx statistics : User octets received for LP */
+#define	NIG_REG_STAT2_BRB_OCTET 				0x107e0
+#define	NIG_REG_STATUS_INTERRUPT_PORT0				0x10328
+#define	NIG_REG_STATUS_INTERRUPT_PORT1				0x1032c
+/*
+ * [RW 1] port swap mux selection. If this register equal to 0 then por
+ * swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
+ * ort swap is equal to ~nig_registers_port_swap.port_swap
+ */
+#define	NIG_REG_STRAP_OVERRIDE					0x10398
+/* [RW 1] output enable for RX_XCM0 IF */
+#define	NIG_REG_XCM0_OUT_EN					0x100f0
+/* [RW 1] output enable for RX_XCM1 IF */
+#define	NIG_REG_XCM1_OUT_EN					0x100f4
+/* [RW 1] control to xgxs - remote PHY in-band MDIO */
+#define	NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST			0x10348
+/* [RW 5] control to xgxs - CL45 DEVAD */
+#define	NIG_REG_XGXS0_CTRL_MD_DEVAD				0x1033c
+/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
+#define	NIG_REG_XGXS0_CTRL_MD_ST				0x10338
+/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
+#define	NIG_REG_XGXS0_CTRL_PHY_ADDR				0x10340
+/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
+#define	NIG_REG_XGXS0_STATUS_LINK10G				0x10680
+/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
+#define	NIG_REG_XGXS0_STATUS_LINK_STATUS			0x10684
+/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
+#define	NIG_REG_XGXS_LANE_SEL_P0				0x102e8
+/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
+#define	NIG_REG_XGXS_SERDES0_MODE_SEL				0x102e0
+#define	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT  (0x1<<0)
+#define	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
+#define	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G	 (0x1<<15)
+#define	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS  (0xf<<18)
+#define	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
+/*
+ * [RW 1] Disable processing further tasks from port 0 (after ending th
+ * current task in process).
+ */
+#define	PBF_REG_DISABLE_NEW_TASK_PROC_P0			0x14005c
+/*
+ * [RW 1] Disable processing further tasks from port 1 (after ending th
+ * current task in process).
+ */
+#define	PBF_REG_DISABLE_NEW_TASK_PROC_P1			0x140060
+/*
+ * [RW 1] Disable processing further tasks from port 4 (after ending th
+ * current task in process).
+ */
+#define	PBF_REG_DISABLE_NEW_TASK_PROC_P4			0x14006c
+#define	PBF_REG_IF_ENABLE_REG					0x140044
+/*
+ * [RW 1] Init bit. When set the initial credits are copied to the credi
+ * registers (except the port credits). Should be set and then reset after
+ * the configuration of the block has ended.
+ */
+#define	PBF_REG_INIT						0x140000
+/*
+ * [RW 1] Init bit for port 0. When set the initial credit of port 0 i
+ * copied to the credit register. Should be set and then reset after the
+ * configuration of the port has ended.
+ */
+#define	PBF_REG_INIT_P0 					0x140004
+/*
+ * [RW 1] Init bit for port 1. When set the initial credit of port 1 i
+ * copied to the credit register. Should be set and then reset after the
+ * configuration of the port has ended.
+ */
+#define	PBF_REG_INIT_P1 					0x140008
+/*
+ * [RW 1] Init bit for port 4. When set the initial credit of port 4 i
+ * copied to the credit register. Should be set and then reset after the
+ * configuration of the port has ended.
+ */
+#define	PBF_REG_INIT_P4 					0x14000c
+/* [RW 1] Enable for mac interface 0. */
+#define	PBF_REG_MAC_IF0_ENABLE					0x140030
+/* [RW 1] Enable for mac interface 1. */
+#define	PBF_REG_MAC_IF1_ENABLE					0x140034
+/* [RW 1] Enable for the loopback interface. */
+#define	PBF_REG_MAC_LB_ENABLE					0x140040
+/*
+ * [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when paus
+ * not suppoterd.
+ */
+#define	PBF_REG_P0_ARB_THRSH					0x1400e4
+/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
+#define	PBF_REG_P0_CREDIT					0x140200
+/*
+ * [RW 11] Initial credit for port 0 in the tx port buffers in 16 byt
+ * lines.
+ */
+#define	PBF_REG_P0_INIT_CRD					0x1400d0
+/* [RW 1] Indication that pause is enabled for port 0. */
+#define	PBF_REG_P0_PAUSE_ENABLE 				0x140014
+/* [R 8] Number of tasks in port 0 task queue. */
+#define	PBF_REG_P0_TASK_CNT					0x140204
+/* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
+#define	PBF_REG_P1_CREDIT					0x140208
+/*
+ * [RW 11] Initial credit for port 1 in the tx port buffers in 16 byt
+ * lines.
+ */
+#define	PBF_REG_P1_INIT_CRD					0x1400d4
+/* [R 8] Number of tasks in port 1 task queue. */
+#define	PBF_REG_P1_TASK_CNT					0x14020c
+/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
+#define	PBF_REG_P4_CREDIT					0x140210
+/*
+ * [RW 11] Initial credit for port 4 in the tx port buffers in 16 byt
+ * lines.
+ */
+#define	PBF_REG_P4_INIT_CRD					0x1400e0
+/* [R 8] Number of tasks in port 4 task queue. */
+#define	PBF_REG_P4_TASK_CNT					0x140214
+/* [RW 5] Interrupt mask register #0 read/write */
+#define	PBF_REG_PBF_INT_MASK					0x1401d4
+/* [R 5] Interrupt register #0 read */
+#define	PBF_REG_PBF_INT_STS					0x1401c8
+#define	PB_REG_CONTROL						 0
+/* [RW 2] Interrupt mask register #0 read/write */
+#define	PB_REG_PB_INT_MASK					0x28
+/* [R 2] Interrupt register #0 read */
+#define	PB_REG_PB_INT_STS					0x1c
+/* [RW 4] Parity mask register #0 read/write */
+#define	PB_REG_PB_PRTY_MASK					0x38
+/* [R 4] Parity register #0 read */
+#define	PB_REG_PB_PRTY_STS					0x2c
+#define	PRS_REG_A_PRSU_20					0x40134
+/* [R 8] debug only: CFC load request current credit. Transaction based. */
+#define	PRS_REG_CFC_LD_CURRENT_CREDIT				0x40164
+/* [R 8] debug only: CFC search request current credit. Transaction based. */
+#define	PRS_REG_CFC_SEARCH_CURRENT_CREDIT			0x40168
+/*
+ * [RW 6] The initial credit for the search message to the CFC interface
+ * Credit is transaction based.
+ */
+#define	PRS_REG_CFC_SEARCH_INITIAL_CREDIT			0x4011c
+/* [RW 24] CID for port 0 if no match */
+#define	PRS_REG_CID_PORT_0					0x400fc
+/*
+ * [RW 32] The CM header for flush message where 'load existed' bit in CF
+ * load response is reset and packet type is 0. Used in packet start message
+ * to TCM.
+ */
+#define	PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0			0x400dc
+#define	PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1			0x400e0
+#define	PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2			0x400e4
+#define	PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3			0x400e8
+#define	PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4			0x400ec
+#define	PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5			0x400f0
+/*
+ * [RW 32] The CM header for flush message where 'load existed' bit in CF
+ * load response is set and packet type is 0. Used in packet start message
+ * to TCM.
+ */
+#define	PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0			0x400bc
+#define	PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1			0x400c0
+#define	PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2			0x400c4
+#define	PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3			0x400c8
+#define	PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4			0x400cc
+#define	PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5			0x400d0
+/*
+ * [RW 32] The CM header for a match and packet type 1 for loopback port
+ * Used in packet start message to TCM.
+ */
+#define	PRS_REG_CM_HDR_LOOPBACK_TYPE_1				0x4009c
+#define	PRS_REG_CM_HDR_LOOPBACK_TYPE_2				0x400a0
+#define	PRS_REG_CM_HDR_LOOPBACK_TYPE_3				0x400a4
+#define	PRS_REG_CM_HDR_LOOPBACK_TYPE_4				0x400a8
+/*
+ * [RW 32] The CM header for a match and packet type 0. Used in packet star
+ * message to TCM.
+ */
+#define	PRS_REG_CM_HDR_TYPE_0					0x40078
+#define	PRS_REG_CM_HDR_TYPE_1					0x4007c
+#define	PRS_REG_CM_HDR_TYPE_2					0x40080
+#define	PRS_REG_CM_HDR_TYPE_3					0x40084
+#define	PRS_REG_CM_HDR_TYPE_4					0x40088
+/* [RW 32] The CM header in case there was not a match on the connection */
+#define	PRS_REG_CM_NO_MATCH_HDR 				0x400b8
+/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
+#define	PRS_REG_E1HOV_MODE					0x401c8
+/*
+ * [RW 8] The 8-bit event ID for a match and packet type 1. Used in packe
+ * start message to TCM.
+ */
+#define	PRS_REG_EVENT_ID_1					0x40054
+#define	PRS_REG_EVENT_ID_2					0x40058
+#define	PRS_REG_EVENT_ID_3					0x4005c
+/* [RW 16] The Ethernet type value for FCoE */
+#define	PRS_REG_FCOE_TYPE					0x401d0
+/*
+ * [RW 8] Context region for flush packet with packet type 0. Used in CF
+ * load request message.
+ */
+#define	PRS_REG_FLUSH_REGIONS_TYPE_0				0x40004
+#define	PRS_REG_FLUSH_REGIONS_TYPE_1				0x40008
+#define	PRS_REG_FLUSH_REGIONS_TYPE_2				0x4000c
+#define	PRS_REG_FLUSH_REGIONS_TYPE_3				0x40010
+#define	PRS_REG_FLUSH_REGIONS_TYPE_4				0x40014
+#define	PRS_REG_FLUSH_REGIONS_TYPE_5				0x40018
+#define	PRS_REG_FLUSH_REGIONS_TYPE_6				0x4001c
+#define	PRS_REG_FLUSH_REGIONS_TYPE_7				0x40020
+/* [RW 4] The increment value to send in the CFC load request message */
+#define	PRS_REG_INC_VALUE					0x40048
+/* [RW 1] If set indicates not to send messages to CFC on received packets */
+#define	PRS_REG_NIC_MODE					0x40138
+/*
+ * [RW 8] The 8-bit event ID for cases where there is no match on th
+ * connection. Used in packet start message to TCM.
+ */
+#define	PRS_REG_NO_MATCH_EVENT_ID				0x40070
+/* [ST 24] The number of input CFC flush packets */
+#define	PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES			0x40128
+/*
+ * [ST 32] The number of cycles the Parser halted its operation since i
+ * could not allocate the next serial number
+ */
+#define	PRS_REG_NUM_OF_DEAD_CYCLES				0x40130
+/* [ST 24] The number of input packets */
+#define	PRS_REG_NUM_OF_PACKETS					0x40124
+/* [ST 24] The number of input transparent flush packets */
+#define	PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES		0x4012c
+/*
+ * [RW 8] Context region for received Ethernet packet with a match an
+ * packet type 0. Used in CFC load request message
+ */
+#define	PRS_REG_PACKET_REGIONS_TYPE_0				0x40028
+#define	PRS_REG_PACKET_REGIONS_TYPE_1				0x4002c
+#define	PRS_REG_PACKET_REGIONS_TYPE_2				0x40030
+#define	PRS_REG_PACKET_REGIONS_TYPE_3				0x40034
+#define	PRS_REG_PACKET_REGIONS_TYPE_4				0x40038
+#define	PRS_REG_PACKET_REGIONS_TYPE_5				0x4003c
+#define	PRS_REG_PACKET_REGIONS_TYPE_6				0x40040
+#define	PRS_REG_PACKET_REGIONS_TYPE_7				0x40044
+/* [R 2] debug only: Number of pending requests for CAC on port 0. */
+#define	PRS_REG_PENDING_BRB_CAC0_RQ				0x40174
+/* [R 2] debug only: Number of pending requests for header parsing. */
+#define	PRS_REG_PENDING_BRB_PRS_RQ				0x40170
+/* [R 1] Interrupt register #0 read */
+#define	PRS_REG_PRS_INT_STS					0x40188
+/* [RW 8] Parity mask register #0 read/write */
+#define	PRS_REG_PRS_PRTY_MASK					0x401a4
+/* [R 8] Parity register #0 read */
+#define	PRS_REG_PRS_PRTY_STS					0x40198
+/*
+ * [RW 8] Context region for pure acknowledge packets. Used in CFC loa
+ * request message
+ */
+#define	PRS_REG_PURE_REGIONS					0x40024
+/*
+ * [R 32] debug only: Serial number status lsb 32 bits. '1' indicates thi
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released.
+ */
+#define	PRS_REG_SERIAL_NUM_STATUS_LSB				0x40154
+/*
+ * [R 32] debug only: Serial number status msb 32 bits. '1' indicates thi
+ * serail number was released by SDM but cannot be used because a previous
+ * serial number was not released.
+ */
+#define	PRS_REG_SERIAL_NUM_STATUS_MSB				0x40158
+/* [R 4] debug only: SRC current credit. Transaction based. */
+#define	PRS_REG_SRC_CURRENT_CREDIT				0x4016c
+/* [R 8] debug only: TCM current credit. Cycle based. */
+#define	PRS_REG_TCM_CURRENT_CREDIT				0x40160
+/* [R 8] debug only: TSDM current credit. Transaction based. */
+#define	PRS_REG_TSDM_CURRENT_CREDIT				0x4015c
+/* [R 6] Debug only: Number of used entries in the data FIFO */
+#define	PXP2_REG_HST_DATA_FIFO_STATUS				0x12047c
+/* [R 7] Debug only: Number of used entries in the header FIFO */
+#define	PXP2_REG_HST_HEADER_FIFO_STATUS 			0x120478
+#define	PXP2_REG_PGL_ADDR_88_F0 				0x120534
+#define	PXP2_REG_PGL_ADDR_8C_F0 				0x120538
+#define	PXP2_REG_PGL_ADDR_90_F0 				0x12053c
+#define	PXP2_REG_PGL_ADDR_94_F0 				0x120540
+#define	PXP2_REG_PGL_CONTROL0					0x120490
+#define	PXP2_REG_PGL_CONTROL1					0x120514
+#define	PXP2_REG_PGL_DEBUG					0x120520
+/*
+ * [RW 32] third dword data of expansion rom request. this register i
+ * special. reading from it provides a vector outstanding read requests. if
+ * a bit is zero it means that a read request on the corresponding tag did
+ * not finish yet (not all completions have arrived for it)
+ */
+#define	PXP2_REG_PGL_EXP_ROM2					0x120808
+/*
+ * [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask
+ * its[15:0]-address
+ */
+#define	PXP2_REG_PGL_INT_CSDM_0 				0x1204f4
+#define	PXP2_REG_PGL_INT_CSDM_1 				0x1204f8
+#define	PXP2_REG_PGL_INT_CSDM_2 				0x1204fc
+#define	PXP2_REG_PGL_INT_CSDM_3 				0x120500
+#define	PXP2_REG_PGL_INT_CSDM_4 				0x120504
+#define	PXP2_REG_PGL_INT_CSDM_5 				0x120508
+#define	PXP2_REG_PGL_INT_CSDM_6 				0x12050c
+#define	PXP2_REG_PGL_INT_CSDM_7 				0x120510
+/*
+ * [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask
+ * its[15:0]-address
+ */
+#define	PXP2_REG_PGL_INT_TSDM_0 				0x120494
+#define	PXP2_REG_PGL_INT_TSDM_1 				0x120498
+#define	PXP2_REG_PGL_INT_TSDM_2 				0x12049c
+#define	PXP2_REG_PGL_INT_TSDM_3 				0x1204a0
+#define	PXP2_REG_PGL_INT_TSDM_4 				0x1204a4
+#define	PXP2_REG_PGL_INT_TSDM_5 				0x1204a8
+#define	PXP2_REG_PGL_INT_TSDM_6 				0x1204ac
+#define	PXP2_REG_PGL_INT_TSDM_7 				0x1204b0
+/*
+ * [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask
+ * its[15:0]-address
+ */
+#define	PXP2_REG_PGL_INT_USDM_0 				0x1204b4
+#define	PXP2_REG_PGL_INT_USDM_1 				0x1204b8
+#define	PXP2_REG_PGL_INT_USDM_2 				0x1204bc
+#define	PXP2_REG_PGL_INT_USDM_3 				0x1204c0
+#define	PXP2_REG_PGL_INT_USDM_4 				0x1204c4
+#define	PXP2_REG_PGL_INT_USDM_5 				0x1204c8
+#define	PXP2_REG_PGL_INT_USDM_6 				0x1204cc
+#define	PXP2_REG_PGL_INT_USDM_7 				0x1204d0
+/*
+ * [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask
+ * its[15:0]-address
+ */
+#define	PXP2_REG_PGL_INT_XSDM_0 				0x1204d4
+#define	PXP2_REG_PGL_INT_XSDM_1 				0x1204d8
+#define	PXP2_REG_PGL_INT_XSDM_2 				0x1204dc
+#define	PXP2_REG_PGL_INT_XSDM_3 				0x1204e0
+#define	PXP2_REG_PGL_INT_XSDM_4 				0x1204e4
+#define	PXP2_REG_PGL_INT_XSDM_5 				0x1204e8
+#define	PXP2_REG_PGL_INT_XSDM_6 				0x1204ec
+#define	PXP2_REG_PGL_INT_XSDM_7 				0x1204f0
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F0				0x120674
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F1				0x120678
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F2				0x12067c
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F3				0x120680
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F4				0x120684
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F5				0x120688
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F6				0x12068c
+/*
+ * [RW 3] this field allows one function to pretend being another functio
+ * when accessing any BAR mapped resource within the device. the value of
+ * the field is the number of the function that will be accessed
+ * effectively. after software write to this bit it must read it in order to
+ * know that the new value is updated.
+ */
+#define	PXP2_REG_PGL_PRETEND_FUNC_F7				0x120690
+/*
+ * [R 1] this bit indicates that a read request was blocked because o
+ * bus_master_en was deasserted.
+ */
+#define	PXP2_REG_PGL_READ_BLOCKED				0x120568
+#define	PXP2_REG_PGL_TAGS_LIMIT 				0x1205a8
+/* [R 18] debug only */
+#define	PXP2_REG_PGL_TXW_CDTS					0x12052c
+/*
+ * [R 1] this bit indicates that a write request was blocked because o
+ * bus_master_en was deasserted.
+ */
+#define	PXP2_REG_PGL_WRITE_BLOCKED				0x120564
+#define	PXP2_REG_PSWRQ_BW_ADD1					0x1201c0
+#define	PXP2_REG_PSWRQ_BW_ADD10 				0x1201e4
+#define	PXP2_REG_PSWRQ_BW_ADD11 				0x1201e8
+#define	PXP2_REG_PSWRQ_BW_ADD2					0x1201c4
+#define	PXP2_REG_PSWRQ_BW_ADD28 				0x120228
+#define	PXP2_REG_PSWRQ_BW_ADD3					0x1201c8
+#define	PXP2_REG_PSWRQ_BW_ADD6					0x1201d4
+#define	PXP2_REG_PSWRQ_BW_ADD7					0x1201d8
+#define	PXP2_REG_PSWRQ_BW_ADD8					0x1201dc
+#define	PXP2_REG_PSWRQ_BW_ADD9					0x1201e0
+#define	PXP2_REG_PSWRQ_BW_CREDIT				0x12032c
+#define	PXP2_REG_PSWRQ_BW_L1					0x1202b0
+#define	PXP2_REG_PSWRQ_BW_L10					0x1202d4
+#define	PXP2_REG_PSWRQ_BW_L11					0x1202d8
+#define	PXP2_REG_PSWRQ_BW_L2					0x1202b4
+#define	PXP2_REG_PSWRQ_BW_L28					0x120318
+#define	PXP2_REG_PSWRQ_BW_L3					0x1202b8
+#define	PXP2_REG_PSWRQ_BW_L6					0x1202c4
+#define	PXP2_REG_PSWRQ_BW_L7					0x1202c8
+#define	PXP2_REG_PSWRQ_BW_L8					0x1202cc
+#define	PXP2_REG_PSWRQ_BW_L9					0x1202d0
+#define	PXP2_REG_PSWRQ_BW_RD					0x120324
+#define	PXP2_REG_PSWRQ_BW_UB1					0x120238
+#define	PXP2_REG_PSWRQ_BW_UB10					0x12025c
+#define	PXP2_REG_PSWRQ_BW_UB11					0x120260
+#define	PXP2_REG_PSWRQ_BW_UB2					0x12023c
+#define	PXP2_REG_PSWRQ_BW_UB28					0x1202a0
+#define	PXP2_REG_PSWRQ_BW_UB3					0x120240
+#define	PXP2_REG_PSWRQ_BW_UB6					0x12024c
+#define	PXP2_REG_PSWRQ_BW_UB7					0x120250
+#define	PXP2_REG_PSWRQ_BW_UB8					0x120254
+#define	PXP2_REG_PSWRQ_BW_UB9					0x120258
+#define	PXP2_REG_PSWRQ_BW_WR					0x120328
+#define	PXP2_REG_PSWRQ_CDU0_L2P 				0x120000
+#define	PXP2_REG_PSWRQ_QM0_L2P					0x120038
+#define	PXP2_REG_PSWRQ_SRC0_L2P 				0x120054
+#define	PXP2_REG_PSWRQ_TM0_L2P					0x12001c
+#define	PXP2_REG_PSWRQ_TSDM0_L2P				0x1200e0
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	PXP2_REG_PXP2_INT_MASK_0				0x120578
+/* [R 32] Interrupt register #0 read */
+#define	PXP2_REG_PXP2_INT_STS_0 				0x12056c
+#define	PXP2_REG_PXP2_INT_STS_1 				0x120608
+/* [RC 32] Interrupt register #0 read clear */
+#define	PXP2_REG_PXP2_INT_STS_CLR_0				0x120570
+/* [RW 32] Parity mask register #0 read/write */
+#define	PXP2_REG_PXP2_PRTY_MASK_0				0x120588
+#define	PXP2_REG_PXP2_PRTY_MASK_1				0x120598
+/* [R 32] Parity register #0 read */
+#define	PXP2_REG_PXP2_PRTY_STS_0				0x12057c
+#define	PXP2_REG_PXP2_PRTY_STS_1				0x12058c
+/*
+ * [R 1] Debug only: The 'almost full' indication from each fifo (give
+ * indication about backpressure)
+ */
+#define	PXP2_REG_RD_ALMOST_FULL_0				0x120424
+/* [R 8] Debug only: The blocks counter - number of unused block ids */
+#define	PXP2_REG_RD_BLK_CNT					0x120418
+/*
+ * [RW 8] Debug only: Total number of available blocks in Tetris Buffer
+ * Must be bigger than 6. Normally should not be changed.
+ */
+#define	PXP2_REG_RD_BLK_NUM_CFG 				0x12040c
+/* [RW 2] CDU byte swapping mode configuration for master read requests */
+#define	PXP2_REG_RD_CDURD_SWAP_MODE				0x120404
+/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
+#define	PXP2_REG_RD_DISABLE_INPUTS				0x120374
+/* [R 1] PSWRD internal memories initialization is done */
+#define	PXP2_REG_RD_INIT_DONE					0x120370
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq10.
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ10				0x1203a0
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq11
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ11				0x1203a4
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq17
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ17				0x1203bc
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq18
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ18				0x1203c0
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq19
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ19				0x1203c4
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq22
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ22				0x1203d0
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq25
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ25				0x1203dc
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq6
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ6				0x120390
+/*
+ * [RW 8] The maximum number of blocks in Tetris Buffer that can b
+ * allocated for vq9
+ */
+#define	PXP2_REG_RD_MAX_BLKS_VQ9				0x12039c
+/* [RW 2] PBF byte swapping mode configuration for master read requests */
+#define	PXP2_REG_RD_PBF_SWAP_MODE				0x1203f4
+/* [R 1] Debug only: Indication if delivery ports are idle */
+#define	PXP2_REG_RD_PORT_IS_IDLE_0				0x12041c
+#define	PXP2_REG_RD_PORT_IS_IDLE_1				0x120420
+/* [RW 2] QM byte swapping mode configuration for master read requests */
+#define	PXP2_REG_RD_QM_SWAP_MODE				0x1203f8
+/* [R 7] Debug only: The SR counter - number of unused sub request ids */
+#define	PXP2_REG_RD_SR_CNT					0x120414
+/* [RW 2] SRC byte swapping mode configuration for master read requests */
+#define	PXP2_REG_RD_SRC_SWAP_MODE				0x120400
+/*
+ * [RW 7] Debug only: Total number of available PCI read sub-requests. Mus
+ * be bigger than 1. Normally should not be changed.
+ */
+#define	PXP2_REG_RD_SR_NUM_CFG					0x120408
+/* [RW 1] Signals the PSWRD block to start initializing internal memories */
+#define	PXP2_REG_RD_START_INIT					0x12036c
+/* [RW 2] TM byte swapping mode configuration for master read requests */
+#define	PXP2_REG_RD_TM_SWAP_MODE				0x1203fc
+/* [RW 10] Bandwidth addition to VQ0 write requests */
+#define	PXP2_REG_RQ_BW_RD_ADD0					0x1201bc
+/* [RW 10] Bandwidth addition to VQ12 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD12 				0x1201ec
+/* [RW 10] Bandwidth addition to VQ13 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD13 				0x1201f0
+/* [RW 10] Bandwidth addition to VQ14 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD14 				0x1201f4
+/* [RW 10] Bandwidth addition to VQ15 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD15 				0x1201f8
+/* [RW 10] Bandwidth addition to VQ16 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD16 				0x1201fc
+/* [RW 10] Bandwidth addition to VQ17 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD17 				0x120200
+/* [RW 10] Bandwidth addition to VQ18 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD18 				0x120204
+/* [RW 10] Bandwidth addition to VQ19 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD19 				0x120208
+/* [RW 10] Bandwidth addition to VQ20 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD20 				0x12020c
+/* [RW 10] Bandwidth addition to VQ22 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD22 				0x120210
+/* [RW 10] Bandwidth addition to VQ23 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD23 				0x120214
+/* [RW 10] Bandwidth addition to VQ24 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD24 				0x120218
+/* [RW 10] Bandwidth addition to VQ25 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD25 				0x12021c
+/* [RW 10] Bandwidth addition to VQ26 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD26 				0x120220
+/* [RW 10] Bandwidth addition to VQ27 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD27 				0x120224
+/* [RW 10] Bandwidth addition to VQ4 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD4					0x1201cc
+/* [RW 10] Bandwidth addition to VQ5 read requests */
+#define	PXP2_REG_RQ_BW_RD_ADD5					0x1201d0
+/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L0					0x1202ac
+/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L12					0x1202dc
+/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L13					0x1202e0
+/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L14					0x1202e4
+/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L15					0x1202e8
+/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L16					0x1202ec
+/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L17					0x1202f0
+/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L18					0x1202f4
+/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L19					0x1202f8
+/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L20					0x1202fc
+/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L22					0x120300
+/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L23					0x120304
+/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L24					0x120308
+/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L25					0x12030c
+/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L26					0x120310
+/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L27					0x120314
+/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
+#define	PXP2_REG_RQ_BW_RD_L4					0x1202bc
+/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
+#define	PXP2_REG_RQ_BW_RD_L5					0x1202c0
+/* [RW 7] Bandwidth upper bound for VQ0 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND0				0x120234
+/* [RW 7] Bandwidth upper bound for VQ12 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND12				0x120264
+/* [RW 7] Bandwidth upper bound for VQ13 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND13				0x120268
+/* [RW 7] Bandwidth upper bound for VQ14 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND14				0x12026c
+/* [RW 7] Bandwidth upper bound for VQ15 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND15				0x120270
+/* [RW 7] Bandwidth upper bound for VQ16 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND16				0x120274
+/* [RW 7] Bandwidth upper bound for VQ17 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND17				0x120278
+/* [RW 7] Bandwidth upper bound for VQ18 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND18				0x12027c
+/* [RW 7] Bandwidth upper bound for VQ19 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND19				0x120280
+/* [RW 7] Bandwidth upper bound for VQ20 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND20				0x120284
+/* [RW 7] Bandwidth upper bound for VQ22 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND22				0x120288
+/* [RW 7] Bandwidth upper bound for VQ23 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND23				0x12028c
+/* [RW 7] Bandwidth upper bound for VQ24 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND24				0x120290
+/* [RW 7] Bandwidth upper bound for VQ25 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND25				0x120294
+/* [RW 7] Bandwidth upper bound for VQ26 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND26				0x120298
+/* [RW 7] Bandwidth upper bound for VQ27 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND27				0x12029c
+/* [RW 7] Bandwidth upper bound for VQ4 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND4				0x120244
+/* [RW 7] Bandwidth upper bound for VQ5 read requests */
+#define	PXP2_REG_RQ_BW_RD_UBOUND5				0x120248
+/* [RW 10] Bandwidth addition to VQ29 write requests */
+#define	PXP2_REG_RQ_BW_WR_ADD29 				0x12022c
+/* [RW 10] Bandwidth addition to VQ30 write requests */
+#define	PXP2_REG_RQ_BW_WR_ADD30 				0x120230
+/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
+#define	PXP2_REG_RQ_BW_WR_L29					0x12031c
+/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
+#define	PXP2_REG_RQ_BW_WR_L30					0x120320
+/* [RW 7] Bandwidth upper bound for VQ29 */
+#define	PXP2_REG_RQ_BW_WR_UBOUND29				0x1202a4
+/* [RW 7] Bandwidth upper bound for VQ30 */
+#define	PXP2_REG_RQ_BW_WR_UBOUND30				0x1202a8
+/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
+#define	PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR			0x120008
+/* [RW 2] Endian mode for cdu */
+#define	PXP2_REG_RQ_CDU_ENDIAN_M				0x1201a0
+#define	PXP2_REG_RQ_CDU_FIRST_ILT				0x12061c
+#define	PXP2_REG_RQ_CDU_LAST_ILT				0x120620
+/*
+ * [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k
+ * -128k
+ */
+#define	PXP2_REG_RQ_CDU_P_SIZE					0x120018
+/*
+ * [R 1] 1' indicates that the requester has finished its interna
+ * configuration
+ */
+#define	PXP2_REG_RQ_CFG_DONE					0x1201b4
+/* [RW 2] Endian mode for debug */
+#define	PXP2_REG_RQ_DBG_ENDIAN_M				0x1201a4
+/*
+ * [RW 1] When '1'; requests will enter input buffers but wont get ou
+ * towards the glue
+ */
+#define	PXP2_REG_RQ_DISABLE_INPUTS				0x120330
+/* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
+#define	PXP2_REG_RQ_DRAM_ALIGN					0x1205b0
+/*
+ * [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt wil
+ * be asserted
+ */
+#define	PXP2_REG_RQ_ELT_DISABLE 				0x12066c
+/* [RW 2] Endian mode for hc */
+#define	PXP2_REG_RQ_HC_ENDIAN_M 				0x1201a8
+/*
+ * [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for bac
+ * compatibility needs; Note that different registers are used per mode
+ */
+#define	PXP2_REG_RQ_ILT_MODE					0x1205b4
+/* [WB 53] Onchip address table */
+#define	PXP2_REG_RQ_ONCHIP_AT					0x122000
+/* [WB 53] Onchip address table - B0 */
+#define	PXP2_REG_RQ_ONCHIP_AT_B0				0x128000
+/* [RW 13] Pending read limiter threshold; in Dwords */
+#define	PXP2_REG_RQ_PDR_LIMIT					0x12033c
+/* [RW 2] Endian mode for qm */
+#define	PXP2_REG_RQ_QM_ENDIAN_M 				0x120194
+#define	PXP2_REG_RQ_QM_FIRST_ILT				0x120634
+#define	PXP2_REG_RQ_QM_LAST_ILT 				0x120638
+/*
+ * [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k
+ * -128k
+ */
+#define	PXP2_REG_RQ_QM_P_SIZE					0x120050
+/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
+#define	PXP2_REG_RQ_RBC_DONE					0x1201b0
+/*
+ * [RW 3] Max burst size filed for read requests port 0; 000 - 128B
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K
+ */
+#define	PXP2_REG_RQ_RD_MBS0					0x120160
+/*
+ * [RW 3] Max burst size filed for read requests port 1; 000 - 128B
+ * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K
+ */
+#define	PXP2_REG_RQ_RD_MBS1					0x120168
+/* [RW 2] Endian mode for src */
+#define	PXP2_REG_RQ_SRC_ENDIAN_M				0x12019c
+#define	PXP2_REG_RQ_SRC_FIRST_ILT				0x12063c
+#define	PXP2_REG_RQ_SRC_LAST_ILT				0x120640
+/*
+ * [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k
+ * -128k
+ */
+#define	PXP2_REG_RQ_SRC_P_SIZE					0x12006c
+/* [RW 2] Endian mode for tm */
+#define	PXP2_REG_RQ_TM_ENDIAN_M 				0x120198
+#define	PXP2_REG_RQ_TM_FIRST_ILT				0x120644
+#define	PXP2_REG_RQ_TM_LAST_ILT 				0x120648
+/*
+ * [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k
+ *  -128k
+ */
+#define	PXP2_REG_RQ_TM_P_SIZE					0x120034
+/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
+#define	PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY				0x12080c
+/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
+#define	PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR			0x120094
+/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
+#define	PXP2_REG_RQ_VQ0_ENTRY_CNT				0x120810
+/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
+#define	PXP2_REG_RQ_VQ10_ENTRY_CNT				0x120818
+/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
+#define	PXP2_REG_RQ_VQ11_ENTRY_CNT				0x120820
+/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
+#define	PXP2_REG_RQ_VQ12_ENTRY_CNT				0x120828
+/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
+#define	PXP2_REG_RQ_VQ13_ENTRY_CNT				0x120830
+/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
+#define	PXP2_REG_RQ_VQ14_ENTRY_CNT				0x120838
+/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
+#define	PXP2_REG_RQ_VQ15_ENTRY_CNT				0x120840
+/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
+#define	PXP2_REG_RQ_VQ16_ENTRY_CNT				0x120848
+/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
+#define	PXP2_REG_RQ_VQ17_ENTRY_CNT				0x120850
+/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
+#define	PXP2_REG_RQ_VQ18_ENTRY_CNT				0x120858
+/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
+#define	PXP2_REG_RQ_VQ19_ENTRY_CNT				0x120860
+/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
+#define	PXP2_REG_RQ_VQ1_ENTRY_CNT				0x120868
+/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
+#define	PXP2_REG_RQ_VQ20_ENTRY_CNT				0x120870
+/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
+#define	PXP2_REG_RQ_VQ21_ENTRY_CNT				0x120878
+/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
+#define	PXP2_REG_RQ_VQ22_ENTRY_CNT				0x120880
+/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
+#define	PXP2_REG_RQ_VQ23_ENTRY_CNT				0x120888
+/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
+#define	PXP2_REG_RQ_VQ24_ENTRY_CNT				0x120890
+/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
+#define	PXP2_REG_RQ_VQ25_ENTRY_CNT				0x120898
+/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
+#define	PXP2_REG_RQ_VQ26_ENTRY_CNT				0x1208a0
+/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
+#define	PXP2_REG_RQ_VQ27_ENTRY_CNT				0x1208a8
+/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
+#define	PXP2_REG_RQ_VQ28_ENTRY_CNT				0x1208b0
+/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
+#define	PXP2_REG_RQ_VQ29_ENTRY_CNT				0x1208b8
+/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
+#define	PXP2_REG_RQ_VQ2_ENTRY_CNT				0x1208c0
+/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
+#define	PXP2_REG_RQ_VQ30_ENTRY_CNT				0x1208c8
+/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
+#define	PXP2_REG_RQ_VQ31_ENTRY_CNT				0x1208d0
+/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
+#define	PXP2_REG_RQ_VQ3_ENTRY_CNT				0x1208d8
+/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
+#define	PXP2_REG_RQ_VQ4_ENTRY_CNT				0x1208e0
+/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
+#define	PXP2_REG_RQ_VQ5_ENTRY_CNT				0x1208e8
+/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
+#define	PXP2_REG_RQ_VQ6_ENTRY_CNT				0x1208f0
+/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
+#define	PXP2_REG_RQ_VQ7_ENTRY_CNT				0x1208f8
+/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
+#define	PXP2_REG_RQ_VQ8_ENTRY_CNT				0x120900
+/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
+#define	PXP2_REG_RQ_VQ9_ENTRY_CNT				0x120908
+/*
+ * [RW 3] Max burst size filed for write requests port 0; 000 - 128B
+ * 001:256B; 010: 512B;
+ */
+#define	PXP2_REG_RQ_WR_MBS0					0x12015c
+/*
+ * [RW 3] Max burst size filed for write requests port 1; 000 - 128B
+ * 001:256B; 010: 512B;
+ */
+#define	PXP2_REG_RQ_WR_MBS1					0x120164
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_CDU_MPS					0x1205f0
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_CSDM_MPS					0x1205d0
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_DBG_MPS					0x1205e8
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_DMAE_MPS					0x1205ec
+/*
+ * [RW 10] if Number of entries in dmae fifo will be higher than thi
+ * threshold then has_payload indication will be asserted; the default value
+ * should be equal to &gt;  write MBS size!
+ */
+#define	PXP2_REG_WR_DMAE_TH					0x120368
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_HC_MPS					0x1205c8
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_QM_MPS					0x1205dc
+/* [RW 1] 0 - working in A0 mode;  - working in B0 mode */
+#define	PXP2_REG_WR_REV_MODE					0x120670
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_SRC_MPS					0x1205e4
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_TM_MPS					0x1205e0
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_TSDM_MPS					0x1205d4
+/*
+ * [RW 10] if Number of entries in usdmdp fifo will be higher than thi
+ * threshold then has_payload indication will be asserted; the default value
+ * should be equal to &gt;  write MBS size!
+ */
+#define	PXP2_REG_WR_USDMDP_TH					0x120348
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_USDM_MPS					0x1205cc
+/*
+ * [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in th
+ * buffer reaches this number has_payload will be asserted
+ */
+#define	PXP2_REG_WR_XSDM_MPS					0x1205d8
+/* [R 1] debug only: Indication if PSWHST arbiter is idle */
+#define	PXP_REG_HST_ARB_IS_IDLE 				0x103004
+/*
+ * [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' mean
+ * this client is waiting for the arbiter.
+ */
+#define	PXP_REG_HST_CLIENTS_WAITING_TO_ARB			0x103008
+/*
+ * [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bi
+ * should update accoring to 'hst_discard_doorbells' register when the state
+ * machine is idle
+ */
+#define	PXP_REG_HST_DISCARD_DOORBELLS_STATUS			0x1030a0
+/*
+ * [R 6] debug only: A bit mask for all PSWHST internal write clients. '1
+ * means this PSWHST is discarding inputs from this client. Each bit should
+ * update accoring to 'hst_discard_internal_writes' register when the state
+ * machine is idle.
+ */
+#define	PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS		0x10309c
+/* [WB 160] Used for initialization of the inbound interrupts memory */
+#define	PXP_REG_HST_INBOUND_INT 				0x103800
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	PXP_REG_PXP_INT_MASK_0					0x103074
+#define	PXP_REG_PXP_INT_MASK_1					0x103084
+/* [R 32] Interrupt register #0 read */
+#define	PXP_REG_PXP_INT_STS_0					0x103068
+#define	PXP_REG_PXP_INT_STS_1					0x103078
+/* [RC 32] Interrupt register #0 read clear */
+#define	PXP_REG_PXP_INT_STS_CLR_0				0x10306c
+/* [RW 26] Parity mask register #0 read/write */
+#define	PXP_REG_PXP_PRTY_MASK					0x103094
+/* [R 26] Parity register #0 read */
+#define	PXP_REG_PXP_PRTY_STS					0x103088
+/*
+ * [RW 4] The activity counter initial increment value sent in the loa
+ * request
+ */
+#define	QM_REG_ACTCTRINITVAL_0					0x168040
+#define	QM_REG_ACTCTRINITVAL_1					0x168044
+#define	QM_REG_ACTCTRINITVAL_2					0x168048
+#define	QM_REG_ACTCTRINITVAL_3					0x16804c
+/*
+ * [RW 32] The base logical address (in bytes) of each physical queue. Th
+ * index I represents the physical queue number. The 12 lsbs are ignore and
+ * considered zero so practically there are only 20 bits in this register;
+ * queues 63-0
+ */
+#define	QM_REG_BASEADDR 					0x168900
+/*
+ * [RW 32] The base logical address (in bytes) of each physical queue. Th
+ * index I represents the physical queue number. The 12 lsbs are ignore and
+ * considered zero so practically there are only 20 bits in this register;
+ * queues 127-64
+ */
+#define	QM_REG_BASEADDR_EXT_A					0x16e100
+/* [RW 16] The byte credit cost for each task. This value is for both ports */
+#define	QM_REG_BYTECRDCOST					0x168234
+/* [RW 16] The initial byte credit value for both ports. */
+#define	QM_REG_BYTECRDINITVAL					0x168238
+/*
+ * [RW 32] A bit per physical queue. If the bit is cleared then the physica
+ * queue uses port 0 else it uses port 1; queues 31-0
+ */
+#define	QM_REG_BYTECRDPORT_LSB					0x168228
+/*
+ * [RW 32] A bit per physical queue. If the bit is cleared then the physica
+ * queue uses port 0 else it uses port 1; queues 95-64
+ */
+#define	QM_REG_BYTECRDPORT_LSB_EXT_A				0x16e520
+/*
+ * [RW 32] A bit per physical queue. If the bit is cleared then the physica
+ * queue uses port 0 else it uses port 1; queues 63-32
+ */
+#define	QM_REG_BYTECRDPORT_MSB					0x168224
+/*
+ * [RW 32] A bit per physical queue. If the bit is cleared then the physica
+ * queue uses port 0 else it uses port 1; queues 127-96
+ */
+#define	QM_REG_BYTECRDPORT_MSB_EXT_A				0x16e51c
+/*
+ * [RW 16] The byte credit value that if above the QM is considered almos
+ * full
+ */
+#define	QM_REG_BYTECREDITAFULLTHR				0x168094
+/* [RW 4] The initial credit for interface */
+#define	QM_REG_CMINITCRD_0					0x1680cc
+#define	QM_REG_CMINITCRD_1					0x1680d0
+#define	QM_REG_CMINITCRD_2					0x1680d4
+#define	QM_REG_CMINITCRD_3					0x1680d8
+#define	QM_REG_CMINITCRD_4					0x1680dc
+#define	QM_REG_CMINITCRD_5					0x1680e0
+#define	QM_REG_CMINITCRD_6					0x1680e4
+#define	QM_REG_CMINITCRD_7					0x1680e8
+/*
+ * [RW 8] A mask bit per CM interface. If this bit is 0 then this interfac
+ * is masked
+ */
+#define	QM_REG_CMINTEN						0x1680ec
+/*
+ * [RW 12] A bit vector which indicates which one of the queues are tied t
+ * interface 0
+ */
+#define	QM_REG_CMINTVOQMASK_0					0x1681f4
+#define	QM_REG_CMINTVOQMASK_1					0x1681f8
+#define	QM_REG_CMINTVOQMASK_2					0x1681fc
+#define	QM_REG_CMINTVOQMASK_3					0x168200
+#define	QM_REG_CMINTVOQMASK_4					0x168204
+#define	QM_REG_CMINTVOQMASK_5					0x168208
+#define	QM_REG_CMINTVOQMASK_6					0x16820c
+#define	QM_REG_CMINTVOQMASK_7					0x168210
+/*
+ * [RW 20] The number of connections divided by 16 which dictates the siz
+ * of each queue which belongs to even function number.
+ */
+#define	QM_REG_CONNNUM_0					0x168020
+/* [R 6] Keep the fill level of the fifo from write client 4 */
+#define	QM_REG_CQM_WRC_FIFOLVL					0x168018
+/* [RW 8] The context regions sent in the CFC load request */
+#define	QM_REG_CTXREG_0 					0x168030
+#define	QM_REG_CTXREG_1 					0x168034
+#define	QM_REG_CTXREG_2 					0x168038
+#define	QM_REG_CTXREG_3 					0x16803c
+/*
+ * [RW 12] The VOQ mask used to select the VOQs which needs to be full fo
+ * bypass enable
+ */
+#define	QM_REG_ENBYPVOQMASK					0x16823c
+/*
+ * [RW 32] A bit mask per each physical queue. If a bit is set then th
+ * physical queue uses the byte credit; queues 31-0
+ */
+#define	QM_REG_ENBYTECRD_LSB					0x168220
+/*
+ * [RW 32] A bit mask per each physical queue. If a bit is set then th
+ * physical queue uses the byte credit; queues 95-64
+ */
+#define	QM_REG_ENBYTECRD_LSB_EXT_A				0x16e518
+/*
+ * [RW 32] A bit mask per each physical queue. If a bit is set then th
+ * physical queue uses the byte credit; queues 63-32
+ */
+#define	QM_REG_ENBYTECRD_MSB					0x16821c
+/*
+ * [RW 32] A bit mask per each physical queue. If a bit is set then th
+ * physical queue uses the byte credit; queues 127-96
+ */
+#define	QM_REG_ENBYTECRD_MSB_EXT_A				0x16e514
+/*
+ * [RW 4] If cleared then the secondary interface will not be served by th
+ * RR arbiter
+ */
+#define	QM_REG_ENSEC						0x1680f0
+/* [RW 32] NA */
+#define	QM_REG_FUNCNUMSEL_LSB					0x168230
+/* [RW 32] NA */
+#define	QM_REG_FUNCNUMSEL_MSB					0x16822c
+/*
+ * [RW 32] A mask register to mask the Almost empty signals which will no
+ * be use for the almost empty indication to the HW block; queues 31:0
+ */
+#define	QM_REG_HWAEMPTYMASK_LSB 				0x168218
+/*
+ * [RW 32] A mask register to mask the Almost empty signals which will no
+ * be use for the almost empty indication to the HW block; queues 95-64
+ */
+#define	QM_REG_HWAEMPTYMASK_LSB_EXT_A				0x16e510
+/*
+ * [RW 32] A mask register to mask the Almost empty signals which will no
+ * be use for the almost empty indication to the HW block; queues 63:32
+ */
+#define	QM_REG_HWAEMPTYMASK_MSB 				0x168214
+/*
+ * [RW 32] A mask register to mask the Almost empty signals which will no
+ * be use for the almost empty indication to the HW block; queues 127-96
+ */
+#define	QM_REG_HWAEMPTYMASK_MSB_EXT_A				0x16e50c
+/* [RW 4] The number of outstanding request to CFC */
+#define	QM_REG_OUTLDREQ 					0x168804
+/*
+ * [RC 1] A flag to indicate that overflow error occurred in one of th
+ * queues.
+ */
+#define	QM_REG_OVFERROR 					0x16805c
+/* [RC 7] the Q were the qverflow occurs */
+#define	QM_REG_OVFQNUM						0x168058
+/* [R 16] Pause state for physical queues 15-0 */
+#define	QM_REG_PAUSESTATE0					0x168410
+/* [R 16] Pause state for physical queues 31-16 */
+#define	QM_REG_PAUSESTATE1					0x168414
+/* [R 16] Pause state for physical queues 47-32 */
+#define	QM_REG_PAUSESTATE2					0x16e684
+/* [R 16] Pause state for physical queues 63-48 */
+#define	QM_REG_PAUSESTATE3					0x16e688
+/* [R 16] Pause state for physical queues 79-64 */
+#define	QM_REG_PAUSESTATE4					0x16e68c
+/* [R 16] Pause state for physical queues 95-80 */
+#define	QM_REG_PAUSESTATE5					0x16e690
+/* [R 16] Pause state for physical queues 111-96 */
+#define	QM_REG_PAUSESTATE6					0x16e694
+/* [R 16] Pause state for physical queues 127-112 */
+#define	QM_REG_PAUSESTATE7					0x16e698
+/* [RW 2] The PCI attributes field used in the PCI request. */
+#define	QM_REG_PCIREQAT 					0x168054
+/* [R 16] The byte credit of port 0 */
+#define	QM_REG_PORT0BYTECRD					0x168300
+/* [R 16] The byte credit of port 1 */
+#define	QM_REG_PORT1BYTECRD					0x168304
+/* [RW 3] pci function number of queues 15-0 */
+#define	QM_REG_PQ2PCIFUNC_0					0x16e6bc
+#define	QM_REG_PQ2PCIFUNC_1					0x16e6c0
+#define	QM_REG_PQ2PCIFUNC_2					0x16e6c4
+#define	QM_REG_PQ2PCIFUNC_3					0x16e6c8
+#define	QM_REG_PQ2PCIFUNC_4					0x16e6cc
+#define	QM_REG_PQ2PCIFUNC_5					0x16e6d0
+#define	QM_REG_PQ2PCIFUNC_6					0x16e6d4
+#define	QM_REG_PQ2PCIFUNC_7					0x16e6d8
+/*
+ * [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow
+ * ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
+ * bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;
+ */
+#define	QM_REG_PTRTBL						0x168a00
+/*
+ * [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow
+ * ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
+ * bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;
+ */
+#define	QM_REG_PTRTBL_EXT_A					0x16e200
+/* [RW 2] Interrupt mask register #0 read/write */
+#define	QM_REG_QM_INT_MASK					0x168444
+/* [R 2] Interrupt register #0 read */
+#define	QM_REG_QM_INT_STS					0x168438
+/* [RW 12] Parity mask register #0 read/write */
+#define	QM_REG_QM_PRTY_MASK					0x168454
+/* [R 12] Parity register #0 read */
+#define	QM_REG_QM_PRTY_STS					0x168448
+/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
+#define	QM_REG_QSTATUS_HIGH					0x16802c
+/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
+#define	QM_REG_QSTATUS_HIGH_EXT_A				0x16e408
+/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
+#define	QM_REG_QSTATUS_LOW					0x168028
+/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
+#define	QM_REG_QSTATUS_LOW_EXT_A				0x16e404
+/* [R 24] The number of tasks queued for each queue; queues 63-0 */
+#define	QM_REG_QTASKCTR_0					0x168308
+/* [R 24] The number of tasks queued for each queue; queues 127-64 */
+#define	QM_REG_QTASKCTR_EXT_A_0 				0x16e584
+/* [RW 4] Queue tied to VOQ */
+#define	QM_REG_QVOQIDX_0					0x1680f4
+#define	QM_REG_QVOQIDX_10					0x16811c
+#define	QM_REG_QVOQIDX_100					0x16e49c
+#define	QM_REG_QVOQIDX_101					0x16e4a0
+#define	QM_REG_QVOQIDX_102					0x16e4a4
+#define	QM_REG_QVOQIDX_103					0x16e4a8
+#define	QM_REG_QVOQIDX_104					0x16e4ac
+#define	QM_REG_QVOQIDX_105					0x16e4b0
+#define	QM_REG_QVOQIDX_106					0x16e4b4
+#define	QM_REG_QVOQIDX_107					0x16e4b8
+#define	QM_REG_QVOQIDX_108					0x16e4bc
+#define	QM_REG_QVOQIDX_109					0x16e4c0
+#define	QM_REG_QVOQIDX_11					0x168120
+#define	QM_REG_QVOQIDX_110					0x16e4c4
+#define	QM_REG_QVOQIDX_111					0x16e4c8
+#define	QM_REG_QVOQIDX_112					0x16e4cc
+#define	QM_REG_QVOQIDX_113					0x16e4d0
+#define	QM_REG_QVOQIDX_114					0x16e4d4
+#define	QM_REG_QVOQIDX_115					0x16e4d8
+#define	QM_REG_QVOQIDX_116					0x16e4dc
+#define	QM_REG_QVOQIDX_117					0x16e4e0
+#define	QM_REG_QVOQIDX_118					0x16e4e4
+#define	QM_REG_QVOQIDX_119					0x16e4e8
+#define	QM_REG_QVOQIDX_12					0x168124
+#define	QM_REG_QVOQIDX_120					0x16e4ec
+#define	QM_REG_QVOQIDX_121					0x16e4f0
+#define	QM_REG_QVOQIDX_122					0x16e4f4
+#define	QM_REG_QVOQIDX_123					0x16e4f8
+#define	QM_REG_QVOQIDX_124					0x16e4fc
+#define	QM_REG_QVOQIDX_125					0x16e500
+#define	QM_REG_QVOQIDX_126					0x16e504
+#define	QM_REG_QVOQIDX_127					0x16e508
+#define	QM_REG_QVOQIDX_13					0x168128
+#define	QM_REG_QVOQIDX_14					0x16812c
+#define	QM_REG_QVOQIDX_15					0x168130
+#define	QM_REG_QVOQIDX_16					0x168134
+#define	QM_REG_QVOQIDX_17					0x168138
+#define	QM_REG_QVOQIDX_21					0x168148
+#define	QM_REG_QVOQIDX_22					0x16814c
+#define	QM_REG_QVOQIDX_23					0x168150
+#define	QM_REG_QVOQIDX_24					0x168154
+#define	QM_REG_QVOQIDX_25					0x168158
+#define	QM_REG_QVOQIDX_26					0x16815c
+#define	QM_REG_QVOQIDX_27					0x168160
+#define	QM_REG_QVOQIDX_28					0x168164
+#define	QM_REG_QVOQIDX_29					0x168168
+#define	QM_REG_QVOQIDX_30					0x16816c
+#define	QM_REG_QVOQIDX_31					0x168170
+#define	QM_REG_QVOQIDX_32					0x168174
+#define	QM_REG_QVOQIDX_33					0x168178
+#define	QM_REG_QVOQIDX_34					0x16817c
+#define	QM_REG_QVOQIDX_35					0x168180
+#define	QM_REG_QVOQIDX_36					0x168184
+#define	QM_REG_QVOQIDX_37					0x168188
+#define	QM_REG_QVOQIDX_38					0x16818c
+#define	QM_REG_QVOQIDX_39					0x168190
+#define	QM_REG_QVOQIDX_40					0x168194
+#define	QM_REG_QVOQIDX_41					0x168198
+#define	QM_REG_QVOQIDX_42					0x16819c
+#define	QM_REG_QVOQIDX_43					0x1681a0
+#define	QM_REG_QVOQIDX_44					0x1681a4
+#define	QM_REG_QVOQIDX_45					0x1681a8
+#define	QM_REG_QVOQIDX_46					0x1681ac
+#define	QM_REG_QVOQIDX_47					0x1681b0
+#define	QM_REG_QVOQIDX_48					0x1681b4
+#define	QM_REG_QVOQIDX_49					0x1681b8
+#define	QM_REG_QVOQIDX_5					0x168108
+#define	QM_REG_QVOQIDX_50					0x1681bc
+#define	QM_REG_QVOQIDX_51					0x1681c0
+#define	QM_REG_QVOQIDX_52					0x1681c4
+#define	QM_REG_QVOQIDX_53					0x1681c8
+#define	QM_REG_QVOQIDX_54					0x1681cc
+#define	QM_REG_QVOQIDX_55					0x1681d0
+#define	QM_REG_QVOQIDX_56					0x1681d4
+#define	QM_REG_QVOQIDX_57					0x1681d8
+#define	QM_REG_QVOQIDX_58					0x1681dc
+#define	QM_REG_QVOQIDX_59					0x1681e0
+#define	QM_REG_QVOQIDX_6					0x16810c
+#define	QM_REG_QVOQIDX_60					0x1681e4
+#define	QM_REG_QVOQIDX_61					0x1681e8
+#define	QM_REG_QVOQIDX_62					0x1681ec
+#define	QM_REG_QVOQIDX_63					0x1681f0
+#define	QM_REG_QVOQIDX_64					0x16e40c
+#define	QM_REG_QVOQIDX_65					0x16e410
+#define	QM_REG_QVOQIDX_69					0x16e420
+#define	QM_REG_QVOQIDX_7					0x168110
+#define	QM_REG_QVOQIDX_70					0x16e424
+#define	QM_REG_QVOQIDX_71					0x16e428
+#define	QM_REG_QVOQIDX_72					0x16e42c
+#define	QM_REG_QVOQIDX_73					0x16e430
+#define	QM_REG_QVOQIDX_74					0x16e434
+#define	QM_REG_QVOQIDX_75					0x16e438
+#define	QM_REG_QVOQIDX_76					0x16e43c
+#define	QM_REG_QVOQIDX_77					0x16e440
+#define	QM_REG_QVOQIDX_78					0x16e444
+#define	QM_REG_QVOQIDX_79					0x16e448
+#define	QM_REG_QVOQIDX_8					0x168114
+#define	QM_REG_QVOQIDX_80					0x16e44c
+#define	QM_REG_QVOQIDX_81					0x16e450
+#define	QM_REG_QVOQIDX_85					0x16e460
+#define	QM_REG_QVOQIDX_86					0x16e464
+#define	QM_REG_QVOQIDX_87					0x16e468
+#define	QM_REG_QVOQIDX_88					0x16e46c
+#define	QM_REG_QVOQIDX_89					0x16e470
+#define	QM_REG_QVOQIDX_9					0x168118
+#define	QM_REG_QVOQIDX_90					0x16e474
+#define	QM_REG_QVOQIDX_91					0x16e478
+#define	QM_REG_QVOQIDX_92					0x16e47c
+#define	QM_REG_QVOQIDX_93					0x16e480
+#define	QM_REG_QVOQIDX_94					0x16e484
+#define	QM_REG_QVOQIDX_95					0x16e488
+#define	QM_REG_QVOQIDX_96					0x16e48c
+#define	QM_REG_QVOQIDX_97					0x16e490
+#define	QM_REG_QVOQIDX_98					0x16e494
+#define	QM_REG_QVOQIDX_99					0x16e498
+/* [RW 1] Initialization bit command */
+#define	QM_REG_SOFT_RESET					0x168428
+/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
+#define	QM_REG_TASKCRDCOST_0					0x16809c
+#define	QM_REG_TASKCRDCOST_1					0x1680a0
+#define	QM_REG_TASKCRDCOST_2					0x1680a4
+#define	QM_REG_TASKCRDCOST_4					0x1680ac
+#define	QM_REG_TASKCRDCOST_5					0x1680b0
+/* [R 6] Keep the fill level of the fifo from write client 3 */
+#define	QM_REG_TQM_WRC_FIFOLVL					0x168010
+/* [R 6] Keep the fill level of the fifo from write client 2 */
+#define	QM_REG_UQM_WRC_FIFOLVL					0x168008
+/* [RC 32] Credit update error register */
+#define	QM_REG_VOQCRDERRREG					0x168408
+/* [R 16] The credit value for each VOQ */
+#define	QM_REG_VOQCREDIT_0					0x1682d0
+#define	QM_REG_VOQCREDIT_1					0x1682d4
+#define	QM_REG_VOQCREDIT_4					0x1682e0
+/* [RW 16] The credit value that if above the QM is considered almost full */
+#define	QM_REG_VOQCREDITAFULLTHR				0x168090
+/* [RW 16] The init and maximum credit for each VoQ */
+#define	QM_REG_VOQINITCREDIT_0					0x168060
+#define	QM_REG_VOQINITCREDIT_1					0x168064
+#define	QM_REG_VOQINITCREDIT_2					0x168068
+#define	QM_REG_VOQINITCREDIT_4					0x168070
+#define	QM_REG_VOQINITCREDIT_5					0x168074
+/* [RW 1] The port of which VOQ belongs */
+#define	QM_REG_VOQPORT_0					0x1682a0
+#define	QM_REG_VOQPORT_1					0x1682a4
+#define	QM_REG_VOQPORT_2					0x1682a8
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_0_LSB					0x168240
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_0_LSB_EXT_A				0x16e524
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_0_MSB					0x168244
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_0_MSB_EXT_A				0x16e528
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_10_LSB					0x168290
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_10_LSB_EXT_A				0x16e574
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_10_MSB					0x168294
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_10_MSB_EXT_A				0x16e578
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_11_LSB					0x168298
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_11_LSB_EXT_A				0x16e57c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_11_MSB					0x16829c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_11_MSB_EXT_A				0x16e580
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_1_LSB					0x168248
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_1_LSB_EXT_A				0x16e52c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_1_MSB					0x16824c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_1_MSB_EXT_A				0x16e530
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_2_LSB					0x168250
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_2_LSB_EXT_A				0x16e534
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_2_MSB					0x168254
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_2_MSB_EXT_A				0x16e538
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_3_LSB					0x168258
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_3_LSB_EXT_A				0x16e53c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_3_MSB_EXT_A				0x16e540
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_4_LSB					0x168260
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_4_LSB_EXT_A				0x16e544
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_4_MSB					0x168264
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_4_MSB_EXT_A				0x16e548
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_5_LSB					0x168268
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_5_LSB_EXT_A				0x16e54c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_5_MSB					0x16826c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_5_MSB_EXT_A				0x16e550
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_6_LSB					0x168270
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_6_LSB_EXT_A				0x16e554
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_6_MSB					0x168274
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_6_MSB_EXT_A				0x16e558
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_7_LSB					0x168278
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_7_LSB_EXT_A				0x16e55c
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_7_MSB					0x16827c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_7_MSB_EXT_A				0x16e560
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_8_LSB					0x168280
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_8_LSB_EXT_A				0x16e564
+/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
+#define	QM_REG_VOQQMASK_8_MSB					0x168284
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_8_MSB_EXT_A				0x16e568
+/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
+#define	QM_REG_VOQQMASK_9_LSB					0x168288
+/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
+#define	QM_REG_VOQQMASK_9_LSB_EXT_A				0x16e56c
+/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
+#define	QM_REG_VOQQMASK_9_MSB_EXT_A				0x16e570
+/* [RW 32] Wrr weights */
+#define	QM_REG_WRRWEIGHTS_0					0x16880c
+#define	QM_REG_WRRWEIGHTS_1					0x168810
+#define	QM_REG_WRRWEIGHTS_10					0x168814
+#define	QM_REG_WRRWEIGHTS_11					0x168818
+#define	QM_REG_WRRWEIGHTS_12					0x16881c
+#define	QM_REG_WRRWEIGHTS_13					0x168820
+#define	QM_REG_WRRWEIGHTS_14					0x168824
+#define	QM_REG_WRRWEIGHTS_15					0x168828
+#define	QM_REG_WRRWEIGHTS_16					0x16e000
+#define	QM_REG_WRRWEIGHTS_17					0x16e004
+#define	QM_REG_WRRWEIGHTS_18					0x16e008
+#define	QM_REG_WRRWEIGHTS_19					0x16e00c
+#define	QM_REG_WRRWEIGHTS_2					0x16882c
+#define	QM_REG_WRRWEIGHTS_20					0x16e010
+#define	QM_REG_WRRWEIGHTS_21					0x16e014
+#define	QM_REG_WRRWEIGHTS_22					0x16e018
+#define	QM_REG_WRRWEIGHTS_23					0x16e01c
+#define	QM_REG_WRRWEIGHTS_24					0x16e020
+#define	QM_REG_WRRWEIGHTS_25					0x16e024
+#define	QM_REG_WRRWEIGHTS_26					0x16e028
+#define	QM_REG_WRRWEIGHTS_27					0x16e02c
+#define	QM_REG_WRRWEIGHTS_28					0x16e030
+#define	QM_REG_WRRWEIGHTS_29					0x16e034
+#define	QM_REG_WRRWEIGHTS_3					0x168830
+#define	QM_REG_WRRWEIGHTS_30					0x16e038
+#define	QM_REG_WRRWEIGHTS_31					0x16e03c
+#define	QM_REG_WRRWEIGHTS_4					0x168834
+#define	QM_REG_WRRWEIGHTS_5					0x168838
+#define	QM_REG_WRRWEIGHTS_6					0x16883c
+#define	QM_REG_WRRWEIGHTS_7					0x168840
+#define	QM_REG_WRRWEIGHTS_8					0x168844
+#define	QM_REG_WRRWEIGHTS_9					0x168848
+/* [R 6] Keep the fill level of the fifo from write client 1 */
+#define	QM_REG_XQM_WRC_FIFOLVL					0x168000
+#define	SRC_REG_COUNTFREE0					0x40500
+/*
+ * [RW 1] If clr the searcher is compatible to E1 A0 - support only tw
+ * ports. If set the searcher support 8 functions.
+ */
+#define	SRC_REG_E1HMF_ENABLE					0x404cc
+#define	SRC_REG_FIRSTFREE0					0x40510
+#define	SRC_REG_KEYRSS0_0					0x40408
+#define	SRC_REG_KEYRSS0_7					0x40424
+#define	SRC_REG_KEYRSS1_9					0x40454
+#define	SRC_REG_KEYSEARCH_0					0x40458
+#define	SRC_REG_KEYSEARCH_1					0x4045c
+#define	SRC_REG_KEYSEARCH_2					0x40460
+#define	SRC_REG_KEYSEARCH_3					0x40464
+#define	SRC_REG_KEYSEARCH_4					0x40468
+#define	SRC_REG_KEYSEARCH_5					0x4046c
+#define	SRC_REG_KEYSEARCH_6					0x40470
+#define	SRC_REG_KEYSEARCH_7					0x40474
+#define	SRC_REG_KEYSEARCH_8					0x40478
+#define	SRC_REG_KEYSEARCH_9					0x4047c
+#define	SRC_REG_LASTFREE0					0x40530
+#define	SRC_REG_NUMBER_HASH_BITS0				0x40400
+/* [RW 1] Reset internal state machines. */
+#define	SRC_REG_SOFT_RST					0x4049c
+/* [R 3] Interrupt register #0 read */
+#define	SRC_REG_SRC_INT_STS					0x404ac
+/* [RW 3] Parity mask register #0 read/write */
+#define	SRC_REG_SRC_PRTY_MASK					0x404c8
+/* [R 3] Parity register #0 read */
+#define	SRC_REG_SRC_PRTY_STS					0x404bc
+/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
+#define	TCM_REG_CAM_OCCUP					0x5017c
+/*
+ * [RW 1] CDU AG read Interface enable. If 0 - the request input i
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	TCM_REG_CDU_AG_RD_IFEN					0x50034
+/*
+ * [RW 1] CDU AG write Interface enable. If 0 - the request and valid inpu
+ * are disregarded; all other signals are treated as usual; if 1 - normal
+ * activity.
+ */
+#define	TCM_REG_CDU_AG_WR_IFEN					0x50030
+/*
+ * [RW 1] CDU STORM read Interface enable. If 0 - the request input i
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	TCM_REG_CDU_SM_RD_IFEN					0x5003c
+/*
+ * [RW 1] CDU STORM write Interface enable. If 0 - the request and vali
+ * input is disregarded; all other signals are treated as usual; if 1 -
+ * normal activity.
+ */
+#define	TCM_REG_CDU_SM_WR_IFEN					0x50038
+/*
+ * [RW 4] CFC output initial credit. Max credit available - 15.Write write
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define	TCM_REG_CFC_INIT_CRD					0x50204
+/*
+ * [RW 3] The weight of the CP input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_CP_WEIGHT					0x500c0
+/*
+ * [RW 1] Input csem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	TCM_REG_CSEM_IFEN					0x5002c
+/*
+ * [RC 1] Message length mismatch (relative to last indication) at the In#
+ * interface.
+ */
+#define	TCM_REG_CSEM_LENGTH_MIS 				0x50174
+/*
+ * [RW 3] The weight of the input csem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_CSEM_WEIGHT					0x500bc
+/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
+#define	TCM_REG_ERR_EVNT_ID					0x500a0
+/* [RW 28] The CM erroneous header for QM and Timers formatting. */
+#define	TCM_REG_ERR_TCM_HDR					0x5009c
+/* [RW 8] The Event ID for Timers expiration. */
+#define	TCM_REG_EXPR_EVNT_ID					0x500a4
+/*
+ * [RW 8] FIC0 output initial credit. Max credit available - 255.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	TCM_REG_FIC0_INIT_CRD					0x5020c
+/*
+ * [RW 8] FIC1 output initial credit. Max credit available - 255.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	TCM_REG_FIC1_INIT_CRD					0x50210
+/*
+ * [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin;
+ * - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
+ * ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
+ * ~tcm_registers_gr_ld1_pr.gr_ld1_pr.
+ */
+#define	TCM_REG_GR_ARB_TYPE					0x50114
+/*
+ * [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; th
+ * highest priority is 3. It is supposed that the Store channel is the
+ * compliment of the other 3 groups.
+ */
+#define	TCM_REG_GR_LD0_PR					0x5011c
+/*
+ * [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; th
+ * highest priority is 3. It is supposed that the Store channel is the
+ * compliment of the other 3 groups.
+ */
+#define	TCM_REG_GR_LD1_PR					0x50120
+/*
+ * [RW 4] The number of double REG-pairs; loaded from the STORM context an
+ * sent to STORM; for a specific connection type. The double REG-pairs are
+ * used to align to STORM context row size of 128 bits. The offset of these
+ * data in the STORM context is always 0. Index _i stands for the connection
+ * type (one of 16).
+ */
+#define	TCM_REG_N_SM_CTX_LD_0					0x50050
+#define	TCM_REG_N_SM_CTX_LD_1					0x50054
+#define	TCM_REG_N_SM_CTX_LD_2					0x50058
+#define	TCM_REG_N_SM_CTX_LD_3					0x5005c
+#define	TCM_REG_N_SM_CTX_LD_4					0x50060
+#define	TCM_REG_N_SM_CTX_LD_5					0x50064
+/*
+ * [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_PBF_IFEN					0x50024
+/*
+ * [RC 1] Message length mismatch (relative to last indication) at the In#
+ * interface.
+ */
+#define	TCM_REG_PBF_LENGTH_MIS					0x5016c
+/*
+ * [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_PBF_WEIGHT					0x500b4
+#define	TCM_REG_PHYS_QNUM0_0					0x500e0
+#define	TCM_REG_PHYS_QNUM0_1					0x500e4
+#define	TCM_REG_PHYS_QNUM1_0					0x500e8
+#define	TCM_REG_PHYS_QNUM1_1					0x500ec
+#define	TCM_REG_PHYS_QNUM2_0					0x500f0
+#define	TCM_REG_PHYS_QNUM2_1					0x500f4
+#define	TCM_REG_PHYS_QNUM3_0					0x500f8
+#define	TCM_REG_PHYS_QNUM3_1					0x500fc
+/*
+ * [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_PRS_IFEN					0x50020
+/*
+ * [RC 1] Message length mismatch (relative to last indication) at the In#
+ * interface.
+ */
+#define	TCM_REG_PRS_LENGTH_MIS					0x50168
+/*
+ * [RW 3] The weight of the input prs in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_PRS_WEIGHT					0x500b0
+/* [RW 8] The Event ID for Timers formatting in case of stop done. */
+#define	TCM_REG_STOP_EVNT_ID					0x500a8
+/*
+ * [RC 1] Message length mismatch (relative to last indication) at the STOR
+ * interface.
+ */
+#define	TCM_REG_STORM_LENGTH_MIS				0x50160
+/*
+ * [RW 1] STORM - CM Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	TCM_REG_STORM_TCM_IFEN					0x50010
+/*
+ * [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_STORM_WEIGHT					0x500ac
+/*
+ * [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_TCM_CFC_IFEN					0x50040
+/* [RW 11] Interrupt mask register #0 read/write */
+#define	TCM_REG_TCM_INT_MASK					0x501dc
+/* [R 11] Interrupt register #0 read */
+#define	TCM_REG_TCM_INT_STS					0x501d0
+/* [R 27] Parity register #0 read */
+#define	TCM_REG_TCM_PRTY_STS					0x501e0
+/*
+ * [RW 3] The size of AG context region 0 in REG-pairs. Designates the M
+ * REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+ * Is used to determine the number of the AG context REG-pairs written back;
+ * when the input message Reg1WbFlg isn't set.
+ */
+#define	TCM_REG_TCM_REG0_SZ					0x500d8
+/*
+ * [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_TCM_STORM0_IFEN 				0x50004
+/*
+ * [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_TCM_STORM1_IFEN 				0x50008
+/*
+ * [RW 1] CM - QM Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_TCM_TQM_IFEN					0x5000c
+/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
+#define	TCM_REG_TCM_TQM_USE_Q					0x500d4
+/* [RW 28] The CM header for Timers expiration command. */
+#define	TCM_REG_TM_TCM_HDR					0x50098
+/*
+ * [RW 1] Timers - CM Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	TCM_REG_TM_TCM_IFEN					0x5001c
+/*
+ * [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_TM_WEIGHT					0x500d0
+/*
+ * [RW 6] QM output initial credit. Max credit available - 32.Write write
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define	TCM_REG_TQM_INIT_CRD					0x5021c
+/*
+ * [RW 3] The weight of the QM (primary) input in the WRR mechanism.
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_TQM_P_WEIGHT					0x500c8
+/*
+ * [RW 3] The weight of the QM (secondary) input in the WRR mechanism.
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_TQM_S_WEIGHT					0x500cc
+/* [RW 28] The CM header value for QM request (primary). */
+#define	TCM_REG_TQM_TCM_HDR_P					0x50090
+/* [RW 28] The CM header value for QM request (secondary). */
+#define	TCM_REG_TQM_TCM_HDR_S					0x50094
+/*
+ * [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_TQM_TCM_IFEN					0x50014
+/*
+ * [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	TCM_REG_TSDM_IFEN					0x50018
+/*
+ * [RC 1] Message length mismatch (relative to last indication) at the SD
+ * interface.
+ */
+#define	TCM_REG_TSDM_LENGTH_MIS 				0x50164
+/*
+ * [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_TSDM_WEIGHT					0x500c4
+/*
+ * [RW 1] Input usem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	TCM_REG_USEM_IFEN					0x50028
+/*
+ * [RC 1] Message length mismatch (relative to last indication) at the In#
+ * interface.
+ */
+#define	TCM_REG_USEM_LENGTH_MIS 				0x50170
+/*
+ * [RW 3] The weight of the input usem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	TCM_REG_USEM_WEIGHT					0x500b8
+/*
+ * [RW 21] Indirect access to the descriptor table of the XX protectio
+ * mechanism. The fields are: [5:0] - length of the message; 15:6] - message
+ * pointer; 20:16] - next pointer.
+ */
+#define	TCM_REG_XX_DESCR_TABLE					0x50280
+#define	TCM_REG_XX_DESCR_TABLE_SIZE				 32
+/* [R 6] Use to read the value of XX protection Free counter. */
+#define	TCM_REG_XX_FREE 					0x50178
+/*
+ * [RW 6] Initial value for the credit counter; responsible for fulfillin
+ * of the Input Stage XX protection buffer by the XX protection pending
+ * messages. Max credit available - 127.Write writes the initial credit
+ * value; read returns the current value of the credit counter. Must be
+ * initialized to 19 at start-up.
+ */
+#define	TCM_REG_XX_INIT_CRD					0x50220
+/*
+ * [RW 6] Maximum link list size (messages locked) per connection in the X
+ * protection.
+ */
+#define	TCM_REG_XX_MAX_LL_SZ					0x50044
+/*
+ * [RW 6] The maximum number of pending messages; which may be stored in X
+ * protection. ~tcm_registers_xx_free.xx_free is read on read.
+ */
+#define	TCM_REG_XX_MSG_NUM					0x50224
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define	TCM_REG_XX_OVFL_EVNT_ID 				0x50048
+/*
+ * [RW 16] Indirect access to the XX table of the XX protection mechanism
+ * The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
+ * header pointer.
+ */
+#define	TCM_REG_XX_TABLE					0x50240
+/* [RW 4] Load value for for cfc ac credit cnt. */
+#define	TM_REG_CFC_AC_CRDCNT_VAL				0x164208
+/* [RW 4] Load value for cfc cld credit cnt. */
+#define	TM_REG_CFC_CLD_CRDCNT_VAL				0x164210
+/* [RW 8] Client0 context region. */
+#define	TM_REG_CL0_CONT_REGION					0x164030
+/* [RW 8] Client1 context region. */
+#define	TM_REG_CL1_CONT_REGION					0x164034
+/* [RW 8] Client2 context region. */
+#define	TM_REG_CL2_CONT_REGION					0x164038
+/* [RW 2] Client in High priority client number. */
+#define	TM_REG_CLIN_PRIOR0_CLIENT				0x164024
+/* [RW 4] Load value for clout0 cred cnt. */
+#define	TM_REG_CLOUT_CRDCNT0_VAL				0x164220
+/* [RW 4] Load value for clout1 cred cnt. */
+#define	TM_REG_CLOUT_CRDCNT1_VAL				0x164228
+/* [RW 4] Load value for clout2 cred cnt. */
+#define	TM_REG_CLOUT_CRDCNT2_VAL				0x164230
+/* [RW 1] Enable client0 input. */
+#define	TM_REG_EN_CL0_INPUT					0x164008
+/* [RW 1] Enable client1 input. */
+#define	TM_REG_EN_CL1_INPUT					0x16400c
+/* [RW 1] Enable client2 input. */
+#define	TM_REG_EN_CL2_INPUT					0x164010
+#define	TM_REG_EN_LINEAR0_TIMER 				0x164014
+/* [RW 1] Enable real time counter. */
+#define	TM_REG_EN_REAL_TIME_CNT 				0x1640d8
+/* [RW 1] Enable for Timers state machines. */
+#define	TM_REG_EN_TIMERS					0x164000
+/*
+ * [RW 4] Load value for expiration credit cnt. CFC max number o
+ * outstanding load requests for timers (expiration) context loading.
+ */
+#define	TM_REG_EXP_CRDCNT_VAL					0x164238
+/* [RW 32] Linear0 logic address. */
+#define	TM_REG_LIN0_LOGIC_ADDR					0x164240
+/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
+#define	TM_REG_LIN0_MAX_ACTIVE_CID				0x164048
+/* [WB 64] Linear0 phy address. */
+#define	TM_REG_LIN0_PHY_ADDR					0x164270
+/* [RW 1] Linear0 physical address valid. */
+#define	TM_REG_LIN0_PHY_ADDR_VALID				0x164248
+#define	TM_REG_LIN0_SCAN_ON					0x1640d0
+/* [RW 24] Linear0 array scan timeout. */
+#define	TM_REG_LIN0_SCAN_TIME					0x16403c
+/* [RW 32] Linear1 logic address. */
+#define	TM_REG_LIN1_LOGIC_ADDR					0x164250
+/* [WB 64] Linear1 phy address. */
+#define	TM_REG_LIN1_PHY_ADDR					0x164280
+/* [RW 1] Linear1 physical address valid. */
+#define	TM_REG_LIN1_PHY_ADDR_VALID				0x164258
+/* [RW 6] Linear timer set_clear fifo threshold. */
+#define	TM_REG_LIN_SETCLR_FIFO_ALFULL_THR			0x164070
+/* [RW 2] Load value for pci arbiter credit cnt. */
+#define	TM_REG_PCIARB_CRDCNT_VAL				0x164260
+/* [RW 20] The amount of hardware cycles for each timer tick. */
+#define	TM_REG_TIMER_TICK_SIZE					0x16401c
+/* [RW 8] Timers Context region. */
+#define	TM_REG_TM_CONTEXT_REGION				0x164044
+/* [RW 1] Interrupt mask register #0 read/write */
+#define	TM_REG_TM_INT_MASK					0x1640fc
+/* [R 1] Interrupt register #0 read */
+#define	TM_REG_TM_INT_STS					0x1640f0
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define	TSDM_REG_AGG_INT_EVENT_0				0x42038
+#define	TSDM_REG_AGG_INT_EVENT_1				0x4203c
+#define	TSDM_REG_AGG_INT_EVENT_2				0x42040
+#define	TSDM_REG_AGG_INT_EVENT_3				0x42044
+#define	TSDM_REG_AGG_INT_EVENT_4				0x42048
+/* [RW 1] The T bit for aggregated interrupt 0 */
+#define	TSDM_REG_AGG_INT_T_0					0x420b8
+#define	TSDM_REG_AGG_INT_T_1					0x420bc
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define	TSDM_REG_CFC_RSP_START_ADDR				0x42008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define	TSDM_REG_CMP_COUNTER_MAX0				0x4201c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define	TSDM_REG_CMP_COUNTER_MAX1				0x42020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define	TSDM_REG_CMP_COUNTER_MAX2				0x42024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define	TSDM_REG_CMP_COUNTER_MAX3				0x42028
+/*
+ * [RW 13] The start address in the internal RAM for the completio
+ * counters.
+ */
+#define	TSDM_REG_CMP_COUNTER_START_ADDR 			0x4200c
+#define	TSDM_REG_ENABLE_IN1					0x42238
+#define	TSDM_REG_ENABLE_IN2					0x4223c
+#define	TSDM_REG_ENABLE_OUT1					0x42240
+#define	TSDM_REG_ENABLE_OUT2					0x42244
+/*
+ * [RW 4] The initial number of messages that can be sent to the pxp contro
+ * interface without receiving any ACK.
+ */
+#define	TSDM_REG_INIT_CREDIT_PXP_CTRL				0x424bc
+/* [ST 32] The number of ACK after placement messages received */
+#define	TSDM_REG_NUM_OF_ACK_AFTER_PLACE 			0x4227c
+/* [ST 32] The number of packet end messages received from the parser */
+#define	TSDM_REG_NUM_OF_PKT_END_MSG				0x42274
+/* [ST 32] The number of requests received from the pxp async if */
+#define	TSDM_REG_NUM_OF_PXP_ASYNC_REQ				0x42278
+/* [ST 32] The number of commands received in queue 0 */
+#define	TSDM_REG_NUM_OF_Q0_CMD					0x42248
+/* [ST 32] The number of commands received in queue 10 */
+#define	TSDM_REG_NUM_OF_Q10_CMD 				0x4226c
+/* [ST 32] The number of commands received in queue 11 */
+#define	TSDM_REG_NUM_OF_Q11_CMD 				0x42270
+/* [ST 32] The number of commands received in queue 1 */
+#define	TSDM_REG_NUM_OF_Q1_CMD					0x4224c
+/* [ST 32] The number of commands received in queue 3 */
+#define	TSDM_REG_NUM_OF_Q3_CMD					0x42250
+/* [ST 32] The number of commands received in queue 4 */
+#define	TSDM_REG_NUM_OF_Q4_CMD					0x42254
+/* [ST 32] The number of commands received in queue 5 */
+#define	TSDM_REG_NUM_OF_Q5_CMD					0x42258
+/* [ST 32] The number of commands received in queue 6 */
+#define	TSDM_REG_NUM_OF_Q6_CMD					0x4225c
+/* [ST 32] The number of commands received in queue 7 */
+#define	TSDM_REG_NUM_OF_Q7_CMD					0x42260
+/* [ST 32] The number of commands received in queue 8 */
+#define	TSDM_REG_NUM_OF_Q8_CMD					0x42264
+/* [ST 32] The number of commands received in queue 9 */
+#define	TSDM_REG_NUM_OF_Q9_CMD					0x42268
+/* [RW 13] The start address in the internal RAM for the packet end message */
+#define	TSDM_REG_PCK_END_MSG_START_ADDR 			0x42014
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define	TSDM_REG_Q_COUNTER_START_ADDR				0x42010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define	TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY			0x42548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define	TSDM_REG_SYNC_PARSER_EMPTY				0x42550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define	TSDM_REG_SYNC_SYNC_EMPTY				0x42558
+/*
+ * [RW 32] Tick for timer counter. Applicable only whe
+ * ~tsdm_registers_timer_tick_enable.timer_tick_enable =1
+ */
+#define	TSDM_REG_TIMER_TICK					0x42000
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	TSDM_REG_TSDM_INT_MASK_0				0x4229c
+#define	TSDM_REG_TSDM_INT_MASK_1				0x422ac
+/* [R 32] Interrupt register #0 read */
+#define	TSDM_REG_TSDM_INT_STS_0 				0x42290
+#define	TSDM_REG_TSDM_INT_STS_1 				0x422a0
+/* [RW 11] Parity mask register #0 read/write */
+#define	TSDM_REG_TSDM_PRTY_MASK 				0x422bc
+/* [R 11] Parity register #0 read */
+#define	TSDM_REG_TSDM_PRTY_STS					0x422b0
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define	TSEM_REG_ARB_CYCLE_SIZE 				0x180034
+/*
+ * [RW 3] The source that is associated with arbitration element 0. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2
+ */
+#define	TSEM_REG_ARB_ELEMENT0					0x180020
+/*
+ * [RW 3] The source that is associated with arbitration element 1. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~tsem_registers_arb_element0.arb_element0
+ */
+#define	TSEM_REG_ARB_ELEMENT1					0x180024
+/*
+ * [RW 3] The source that is associated with arbitration element 2. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~tsem_registers_arb_element0.arb_element0
+ * and ~tsem_registers_arb_element1.arb_element1
+ */
+#define	TSEM_REG_ARB_ELEMENT2					0x180028
+/*
+ * [RW 3] The source that is associated with arbitration element 3. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+ * not be equal to register ~tsem_registers_arb_element0.arb_element0 and
+ * ~tsem_registers_arb_element1.arb_element1 and
+ * ~tsem_registers_arb_element2.arb_element2
+ */
+#define	TSEM_REG_ARB_ELEMENT3					0x18002c
+/*
+ * [RW 3] The source that is associated with arbitration element 4. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~tsem_registers_arb_element0.arb_element0
+ * and ~tsem_registers_arb_element1.arb_element1 and
+ * ~tsem_registers_arb_element2.arb_element2 and
+ * ~tsem_registers_arb_element3.arb_element3
+ */
+#define	TSEM_REG_ARB_ELEMENT4					0x180030
+#define	TSEM_REG_ENABLE_IN					0x1800a4
+#define	TSEM_REG_ENABLE_OUT					0x1800a8
+/*
+ * [RW 32] This address space contains all registers and memories that ar
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the sem_fast registers the base address
+ * ~fast_memory.fast_memory should be added to eachsem_fast register offset.
+ */
+#define	TSEM_REG_FAST_MEMORY					0x1a0000
+/*
+ * [RW 1] Disables input messages from FIC0 May be updated during run_tim
+ * by the microcode
+ */
+#define	TSEM_REG_FIC0_DISABLE					0x180224
+/*
+ * [RW 1] Disables input messages from FIC1 May be updated during run_tim
+ * by the microcode
+ */
+#define	TSEM_REG_FIC1_DISABLE					0x180234
+/*
+ * [RW 15] Interrupt table Read and write access to it is not possible i
+ * the middle of the work
+ */
+#define	TSEM_REG_INT_TABLE					0x180400
+/*
+ * [ST 24] Statistics register. The number of messages that entered throug
+ * FIC0
+ */
+#define	TSEM_REG_MSG_NUM_FIC0					0x180000
+/*
+ * [ST 24] Statistics register. The number of messages that entered throug
+ * FIC1
+ */
+#define	TSEM_REG_MSG_NUM_FIC1					0x180004
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC0
+ */
+#define	TSEM_REG_MSG_NUM_FOC0					0x180008
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC1
+ */
+#define	TSEM_REG_MSG_NUM_FOC1					0x18000c
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC2
+ */
+#define	TSEM_REG_MSG_NUM_FOC2					0x180010
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC3
+ */
+#define	TSEM_REG_MSG_NUM_FOC3					0x180014
+/*
+ * [RW 1] Disables input messages from the passive buffer May be update
+ * during run_time by the microcode
+ */
+#define	TSEM_REG_PAS_DISABLE					0x18024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define	TSEM_REG_PASSIVE_BUFFER 				0x181000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define	TSEM_REG_PRAM						0x1c0000
+/* [R 8] Valid sleeping threads indication have bit per thread */
+#define	TSEM_REG_SLEEP_THREADS_VALID				0x18026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define	TSEM_REG_SLOW_EXT_STORE_EMPTY				0x1802a0
+/* [RW 8] List of free threads . There is a bit per thread. */
+#define	TSEM_REG_THREADS_LIST					0x1802e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define	TSEM_REG_TS_0_AS					0x180038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define	TSEM_REG_TS_10_AS					0x180060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define	TSEM_REG_TS_11_AS					0x180064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define	TSEM_REG_TS_12_AS					0x180068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define	TSEM_REG_TS_13_AS					0x18006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define	TSEM_REG_TS_14_AS					0x180070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define	TSEM_REG_TS_15_AS					0x180074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define	TSEM_REG_TS_16_AS					0x180078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define	TSEM_REG_TS_17_AS					0x18007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define	TSEM_REG_TS_18_AS					0x180080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define	TSEM_REG_TS_1_AS					0x18003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define	TSEM_REG_TS_2_AS					0x180040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define	TSEM_REG_TS_3_AS					0x180044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define	TSEM_REG_TS_4_AS					0x180048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define	TSEM_REG_TS_5_AS					0x18004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define	TSEM_REG_TS_6_AS					0x180050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define	TSEM_REG_TS_7_AS					0x180054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define	TSEM_REG_TS_8_AS					0x180058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define	TSEM_REG_TS_9_AS					0x18005c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	TSEM_REG_TSEM_INT_MASK_0				0x180100
+#define	TSEM_REG_TSEM_INT_MASK_1				0x180110
+/* [R 32] Interrupt register #0 read */
+#define	TSEM_REG_TSEM_INT_STS_0 				0x1800f4
+#define	TSEM_REG_TSEM_INT_STS_1 				0x180104
+/* [RW 32] Parity mask register #0 read/write */
+#define	TSEM_REG_TSEM_PRTY_MASK_0				0x180120
+#define	TSEM_REG_TSEM_PRTY_MASK_1				0x180130
+/* [R 32] Parity register #0 read */
+#define	TSEM_REG_TSEM_PRTY_STS_0				0x180114
+#define	TSEM_REG_TSEM_PRTY_STS_1				0x180124
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define	UCM_REG_CAM_OCCUP					0xe0170
+/*
+ * [RW 1] CDU AG read Interface enable. If 0 - the request input i
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	UCM_REG_CDU_AG_RD_IFEN					0xe0038
+/*
+ * [RW 1] CDU AG write Interface enable. If 0 - the request and valid inpu
+ * are disregarded; all other signals are treated as usual; if 1 - normal
+ * activity.
+ */
+#define	UCM_REG_CDU_AG_WR_IFEN					0xe0034
+/*
+ * [RW 1] CDU STORM read Interface enable. If 0 - the request input i
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	UCM_REG_CDU_SM_RD_IFEN					0xe0040
+/*
+ * [RW 1] CDU STORM write Interface enable. If 0 - the request and vali
+ * input is disregarded; all other signals are treated as usual; if 1 -
+ * normal activity.
+ */
+#define	UCM_REG_CDU_SM_WR_IFEN					0xe003c
+/*
+ * [RW 4] CFC output initial credit. Max credit available - 15.Write write
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define	UCM_REG_CFC_INIT_CRD					0xe0204
+/*
+ * [RW 3] The weight of the CP input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_CP_WEIGHT					0xe00c4
+/*
+ * [RW 1] Input csem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	UCM_REG_CSEM_IFEN					0xe0028
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication
+ * at the csem interface is detected.
+ */
+#define	UCM_REG_CSEM_LENGTH_MIS 				0xe0160
+/*
+ * [RW 3] The weight of the input csem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_CSEM_WEIGHT					0xe00b8
+/*
+ * [RW 1] Input dorq Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	UCM_REG_DORQ_IFEN					0xe0030
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication
+ * at the dorq interface is detected.
+ */
+#define	UCM_REG_DORQ_LENGTH_MIS 				0xe0168
+/*
+ * [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_DORQ_WEIGHT					0xe00c0
+/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
+#define	UCM_REG_ERR_EVNT_ID					0xe00a4
+/* [RW 28] The CM erroneous header for QM and Timers formatting. */
+#define	UCM_REG_ERR_UCM_HDR					0xe00a0
+/* [RW 8] The Event ID for Timers expiration. */
+#define	UCM_REG_EXPR_EVNT_ID					0xe00a8
+/*
+ * [RW 8] FIC0 output initial credit. Max credit available - 255.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	UCM_REG_FIC0_INIT_CRD					0xe020c
+/*
+ * [RW 8] FIC1 output initial credit. Max credit available - 255.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	UCM_REG_FIC1_INIT_CRD					0xe0210
+/*
+ * [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin;
+ * - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
+ * ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
+ * ~ucm_registers_gr_ld1_pr.gr_ld1_pr.
+ */
+#define	UCM_REG_GR_ARB_TYPE					0xe0144
+/*
+ * [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; th
+ * highest priority is 3. It is supposed that the Store channel group is
+ * compliment to the others.
+ */
+#define	UCM_REG_GR_LD0_PR					0xe014c
+/*
+ * [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; th
+ * highest priority is 3. It is supposed that the Store channel group is
+ * compliment to the others.
+ */
+#define	UCM_REG_GR_LD1_PR					0xe0150
+/* [RW 2] The queue index for invalidate counter flag decision. */
+#define	UCM_REG_INV_CFLG_Q					0xe00e4
+/*
+ * [RW 5] The number of double REG-pairs; loaded from the STORM context an
+ * sent to STORM; for a specific connection type. the double REG-pairs are
+ * used in order to align to STORM context row size of 128 bits. The offset
+ * of these data in the STORM context is always 0. Index _i stands for the
+ * connection type (one of 16).
+ */
+#define	UCM_REG_N_SM_CTX_LD_0					0xe0054
+#define	UCM_REG_N_SM_CTX_LD_1					0xe0058
+#define	UCM_REG_N_SM_CTX_LD_2					0xe005c
+#define	UCM_REG_N_SM_CTX_LD_3					0xe0060
+#define	UCM_REG_N_SM_CTX_LD_4					0xe0064
+#define	UCM_REG_N_SM_CTX_LD_5					0xe0068
+#define	UCM_REG_PHYS_QNUM0_0					0xe0110
+#define	UCM_REG_PHYS_QNUM0_1					0xe0114
+#define	UCM_REG_PHYS_QNUM1_0					0xe0118
+#define	UCM_REG_PHYS_QNUM1_1					0xe011c
+#define	UCM_REG_PHYS_QNUM2_0					0xe0120
+#define	UCM_REG_PHYS_QNUM2_1					0xe0124
+#define	UCM_REG_PHYS_QNUM3_0					0xe0128
+#define	UCM_REG_PHYS_QNUM3_1					0xe012c
+/* [RW 8] The Event ID for Timers formatting in case of stop done. */
+#define	UCM_REG_STOP_EVNT_ID					0xe00ac
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication
+ * at the STORM interface is detected.
+ */
+#define	UCM_REG_STORM_LENGTH_MIS				0xe0154
+/*
+ * [RW 1] STORM - CM Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	UCM_REG_STORM_UCM_IFEN					0xe0010
+/*
+ * [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_STORM_WEIGHT					0xe00b0
+/*
+ * [RW 4] Timers output initial credit. Max credit available - 15.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up.
+ */
+#define	UCM_REG_TM_INIT_CRD					0xe021c
+/* [RW 28] The CM header for Timers expiration command. */
+#define	UCM_REG_TM_UCM_HDR					0xe009c
+/*
+ * [RW 1] Timers - CM Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	UCM_REG_TM_UCM_IFEN					0xe001c
+/*
+ * [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_TM_WEIGHT					0xe00d4
+/*
+ * [RW 1] Input tsem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	UCM_REG_TSEM_IFEN					0xe0024
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication
+ * at the tsem interface is detected.
+ */
+#define	UCM_REG_TSEM_LENGTH_MIS 				0xe015c
+/*
+ * [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_TSEM_WEIGHT					0xe00b4
+/*
+ * [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	UCM_REG_UCM_CFC_IFEN					0xe0044
+/* [RW 11] Interrupt mask register #0 read/write */
+#define	UCM_REG_UCM_INT_MASK					0xe01d4
+/* [R 11] Interrupt register #0 read */
+#define	UCM_REG_UCM_INT_STS					0xe01c8
+/* [R 27] Parity register #0 read */
+#define	UCM_REG_UCM_PRTY_STS					0xe01d8
+/*
+ * [RW 2] The size of AG context region 0 in REG-pairs. Designates the M
+ * REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+ * Is used to determine the number of the AG context REG-pairs written back;
+ * when the Reg1WbFlg isn't set.
+ */
+#define	UCM_REG_UCM_REG0_SZ					0xe00dc
+/*
+ * [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	UCM_REG_UCM_STORM0_IFEN 				0xe0004
+/*
+ * [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	UCM_REG_UCM_STORM1_IFEN 				0xe0008
+/*
+ * [RW 1] CM - Timers Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	UCM_REG_UCM_TM_IFEN					0xe0020
+/*
+ * [RW 1] CM - QM Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	UCM_REG_UCM_UQM_IFEN					0xe000c
+/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
+#define	UCM_REG_UCM_UQM_USE_Q					0xe00d8
+/*
+ * [RW 6] QM output initial credit. Max credit available - 32.Write write
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define	UCM_REG_UQM_INIT_CRD					0xe0220
+/*
+ * [RW 3] The weight of the QM (primary) input in the WRR mechanism.
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_UQM_P_WEIGHT					0xe00cc
+/*
+ * [RW 3] The weight of the QM (secondary) input in the WRR mechanism.
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_UQM_S_WEIGHT					0xe00d0
+/* [RW 28] The CM header value for QM request (primary). */
+#define	UCM_REG_UQM_UCM_HDR_P					0xe0094
+/* [RW 28] The CM header value for QM request (secondary). */
+#define	UCM_REG_UQM_UCM_HDR_S					0xe0098
+/*
+ * [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	UCM_REG_UQM_UCM_IFEN					0xe0014
+/*
+ * [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	UCM_REG_USDM_IFEN					0xe0018
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication
+ * at the SDM interface is detected.
+ */
+#define	UCM_REG_USDM_LENGTH_MIS 				0xe0158
+/*
+ * [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_USDM_WEIGHT					0xe00c8
+/*
+ * [RW 1] Input xsem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	UCM_REG_XSEM_IFEN					0xe002c
+/*
+ * [RC 1] Set when the message length mismatch (relative to last indication
+ * at the xsem interface isdetected.
+ */
+#define	UCM_REG_XSEM_LENGTH_MIS 				0xe0164
+/*
+ * [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	UCM_REG_XSEM_WEIGHT					0xe00bc
+/*
+ * [RW 20] Indirect access to the descriptor table of the XX protectio
+ * mechanism. The fields are:[5:0] - message length; 14:6] - message
+ * pointer; 19:15] - next pointer.
+ */
+#define	UCM_REG_XX_DESCR_TABLE					0xe0280
+#define	UCM_REG_XX_DESCR_TABLE_SIZE				 32
+/* [R 6] Use to read the XX protection Free counter. */
+#define	UCM_REG_XX_FREE 					0xe016c
+/*
+ * [RW 6] Initial value for the credit counter; responsible for fulfillin
+ * of the Input Stage XX protection buffer by the XX protection pending
+ * messages. Write writes the initial credit value; read returns the current
+ * value of the credit counter. Must be initialized to 12 at start-up.
+ */
+#define	UCM_REG_XX_INIT_CRD					0xe0224
+/*
+ * [RW 6] The maximum number of pending messages; which may be stored in X
+ * protection. ~ucm_registers_xx_free.xx_free read on read.
+ */
+#define	UCM_REG_XX_MSG_NUM					0xe0228
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define	UCM_REG_XX_OVFL_EVNT_ID 				0xe004c
+/*
+ * [RW 16] Indirect access to the XX table of the XX protection mechanism
+ * The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
+ * header pointer.
+ */
+#define	UCM_REG_XX_TABLE					0xe0300
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define	USDM_REG_AGG_INT_EVENT_0				0xc4038
+#define	USDM_REG_AGG_INT_EVENT_1				0xc403c
+#define	USDM_REG_AGG_INT_EVENT_2				0xc4040
+#define	USDM_REG_AGG_INT_EVENT_4				0xc4048
+#define	USDM_REG_AGG_INT_EVENT_5				0xc404c
+#define	USDM_REG_AGG_INT_EVENT_6				0xc4050
+/*
+ * [RW 1] For each aggregated interrupt index whether the mode is normal (0
+ * or auto-mask-mode (1)
+ */
+#define	USDM_REG_AGG_INT_MODE_0 				0xc41b8
+#define	USDM_REG_AGG_INT_MODE_1 				0xc41bc
+#define	USDM_REG_AGG_INT_MODE_4 				0xc41c8
+#define	USDM_REG_AGG_INT_MODE_5 				0xc41cc
+#define	USDM_REG_AGG_INT_MODE_6 				0xc41d0
+/* [RW 1] The T bit for aggregated interrupt 5 */
+#define	USDM_REG_AGG_INT_T_5					0xc40cc
+#define	USDM_REG_AGG_INT_T_6					0xc40d0
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define	USDM_REG_CFC_RSP_START_ADDR				0xc4008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define	USDM_REG_CMP_COUNTER_MAX0				0xc401c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define	USDM_REG_CMP_COUNTER_MAX1				0xc4020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define	USDM_REG_CMP_COUNTER_MAX2				0xc4024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define	USDM_REG_CMP_COUNTER_MAX3				0xc4028
+/*
+ * [RW 13] The start address in the internal RAM for the completio
+ * counters.
+ */
+#define	USDM_REG_CMP_COUNTER_START_ADDR 			0xc400c
+#define	USDM_REG_ENABLE_IN1					0xc4238
+#define	USDM_REG_ENABLE_IN2					0xc423c
+#define	USDM_REG_ENABLE_OUT1					0xc4240
+#define	USDM_REG_ENABLE_OUT2					0xc4244
+/*
+ * [RW 4] The initial number of messages that can be sent to the pxp contro
+ * interface without receiving any ACK.
+ */
+#define	USDM_REG_INIT_CREDIT_PXP_CTRL				0xc44c0
+/* [ST 32] The number of ACK after placement messages received */
+#define	USDM_REG_NUM_OF_ACK_AFTER_PLACE 			0xc4280
+/* [ST 32] The number of packet end messages received from the parser */
+#define	USDM_REG_NUM_OF_PKT_END_MSG				0xc4278
+/* [ST 32] The number of requests received from the pxp async if */
+#define	USDM_REG_NUM_OF_PXP_ASYNC_REQ				0xc427c
+/* [ST 32] The number of commands received in queue 0 */
+#define	USDM_REG_NUM_OF_Q0_CMD					0xc4248
+/* [ST 32] The number of commands received in queue 10 */
+#define	USDM_REG_NUM_OF_Q10_CMD 				0xc4270
+/* [ST 32] The number of commands received in queue 11 */
+#define	USDM_REG_NUM_OF_Q11_CMD 				0xc4274
+/* [ST 32] The number of commands received in queue 1 */
+#define	USDM_REG_NUM_OF_Q1_CMD					0xc424c
+/* [ST 32] The number of commands received in queue 2 */
+#define	USDM_REG_NUM_OF_Q2_CMD					0xc4250
+/* [ST 32] The number of commands received in queue 3 */
+#define	USDM_REG_NUM_OF_Q3_CMD					0xc4254
+/* [ST 32] The number of commands received in queue 4 */
+#define	USDM_REG_NUM_OF_Q4_CMD					0xc4258
+/* [ST 32] The number of commands received in queue 5 */
+#define	USDM_REG_NUM_OF_Q5_CMD					0xc425c
+/* [ST 32] The number of commands received in queue 6 */
+#define	USDM_REG_NUM_OF_Q6_CMD					0xc4260
+/* [ST 32] The number of commands received in queue 7 */
+#define	USDM_REG_NUM_OF_Q7_CMD					0xc4264
+/* [ST 32] The number of commands received in queue 8 */
+#define	USDM_REG_NUM_OF_Q8_CMD					0xc4268
+/* [ST 32] The number of commands received in queue 9 */
+#define	USDM_REG_NUM_OF_Q9_CMD					0xc426c
+/* [RW 13] The start address in the internal RAM for the packet end message */
+#define	USDM_REG_PCK_END_MSG_START_ADDR 			0xc4014
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define	USDM_REG_Q_COUNTER_START_ADDR				0xc4010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define	USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY			0xc4550
+/* [R 1] parser fifo empty in sdm_sync block */
+#define	USDM_REG_SYNC_PARSER_EMPTY				0xc4558
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define	USDM_REG_SYNC_SYNC_EMPTY				0xc4560
+/*
+ * [RW 32] Tick for timer counter. Applicable only whe
+ * ~usdm_registers_timer_tick_enable.timer_tick_enable =1
+ */
+#define	USDM_REG_TIMER_TICK					0xc4000
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	USDM_REG_USDM_INT_MASK_0				0xc42a0
+#define	USDM_REG_USDM_INT_MASK_1				0xc42b0
+/* [R 32] Interrupt register #0 read */
+#define	USDM_REG_USDM_INT_STS_0 				0xc4294
+#define	USDM_REG_USDM_INT_STS_1 				0xc42a4
+/* [RW 11] Parity mask register #0 read/write */
+#define	USDM_REG_USDM_PRTY_MASK 				0xc42c0
+/* [R 11] Parity register #0 read */
+#define	USDM_REG_USDM_PRTY_STS					0xc42b4
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define	USEM_REG_ARB_CYCLE_SIZE 				0x300034
+/*
+ * [RW 3] The source that is associated with arbitration element 0. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2
+ */
+#define	USEM_REG_ARB_ELEMENT0					0x300020
+/*
+ * [RW 3] The source that is associated with arbitration element 1. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~usem_registers_arb_element0.arb_element0
+ */
+#define	USEM_REG_ARB_ELEMENT1					0x300024
+/*
+ * [RW 3] The source that is associated with arbitration element 2. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~usem_registers_arb_element0.arb_element0
+ * and ~usem_registers_arb_element1.arb_element1
+ */
+#define	USEM_REG_ARB_ELEMENT2					0x300028
+/*
+ * [RW 3] The source that is associated with arbitration element 3. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+ * not be equal to register ~usem_registers_arb_element0.arb_element0 and
+ * ~usem_registers_arb_element1.arb_element1 and
+ * ~usem_registers_arb_element2.arb_element2
+ */
+#define	USEM_REG_ARB_ELEMENT3					0x30002c
+/*
+ * [RW 3] The source that is associated with arbitration element 4. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~usem_registers_arb_element0.arb_element0
+ * and ~usem_registers_arb_element1.arb_element1 and
+ * ~usem_registers_arb_element2.arb_element2 and
+ * ~usem_registers_arb_element3.arb_element3
+ */
+#define	USEM_REG_ARB_ELEMENT4					0x300030
+#define	USEM_REG_ENABLE_IN					0x3000a4
+#define	USEM_REG_ENABLE_OUT					0x3000a8
+/*
+ * [RW 32] This address space contains all registers and memories that ar
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the sem_fast registers the base address
+ * ~fast_memory.fast_memory should be added to eachsem_fast register offset.
+ */
+#define	USEM_REG_FAST_MEMORY					0x320000
+/*
+ * [RW 1] Disables input messages from FIC0 May be updated during run_tim
+ * by the microcode
+ */
+#define	USEM_REG_FIC0_DISABLE					0x300224
+/*
+ * [RW 1] Disables input messages from FIC1 May be updated during run_tim
+ * by the microcode
+ */
+#define	USEM_REG_FIC1_DISABLE					0x300234
+/*
+ * [RW 15] Interrupt table Read and write access to it is not possible i
+ * the middle of the work
+ */
+#define	USEM_REG_INT_TABLE					0x300400
+/*
+ * [ST 24] Statistics register. The number of messages that entered throug
+ * FIC0
+ */
+#define	USEM_REG_MSG_NUM_FIC0					0x300000
+/*
+ * [ST 24] Statistics register. The number of messages that entered throug
+ * FIC1
+ */
+#define	USEM_REG_MSG_NUM_FIC1					0x300004
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC0
+ */
+#define	USEM_REG_MSG_NUM_FOC0					0x300008
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC1
+ */
+#define	USEM_REG_MSG_NUM_FOC1					0x30000c
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC2
+ */
+#define	USEM_REG_MSG_NUM_FOC2					0x300010
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC3
+ */
+#define	USEM_REG_MSG_NUM_FOC3					0x300014
+/*
+ * [RW 1] Disables input messages from the passive buffer May be update
+ * during run_time by the microcode
+ */
+#define	USEM_REG_PAS_DISABLE					0x30024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define	USEM_REG_PASSIVE_BUFFER 				0x302000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define	USEM_REG_PRAM						0x340000
+/* [R 16] Valid sleeping threads indication have bit per thread */
+#define	USEM_REG_SLEEP_THREADS_VALID				0x30026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define	USEM_REG_SLOW_EXT_STORE_EMPTY				0x3002a0
+/* [RW 16] List of free threads . There is a bit per thread. */
+#define	USEM_REG_THREADS_LIST					0x3002e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define	USEM_REG_TS_0_AS					0x300038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define	USEM_REG_TS_10_AS					0x300060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define	USEM_REG_TS_11_AS					0x300064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define	USEM_REG_TS_12_AS					0x300068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define	USEM_REG_TS_13_AS					0x30006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define	USEM_REG_TS_14_AS					0x300070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define	USEM_REG_TS_15_AS					0x300074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define	USEM_REG_TS_16_AS					0x300078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define	USEM_REG_TS_17_AS					0x30007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define	USEM_REG_TS_18_AS					0x300080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define	USEM_REG_TS_1_AS					0x30003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define	USEM_REG_TS_2_AS					0x300040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define	USEM_REG_TS_3_AS					0x300044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define	USEM_REG_TS_4_AS					0x300048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define	USEM_REG_TS_5_AS					0x30004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define	USEM_REG_TS_6_AS					0x300050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define	USEM_REG_TS_7_AS					0x300054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define	USEM_REG_TS_8_AS					0x300058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define	USEM_REG_TS_9_AS					0x30005c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	USEM_REG_USEM_INT_MASK_0				0x300110
+#define	USEM_REG_USEM_INT_MASK_1				0x300120
+/* [R 32] Interrupt register #0 read */
+#define	USEM_REG_USEM_INT_STS_0 				0x300104
+#define	USEM_REG_USEM_INT_STS_1 				0x300114
+/* [RW 32] Parity mask register #0 read/write */
+#define	USEM_REG_USEM_PRTY_MASK_0				0x300130
+#define	USEM_REG_USEM_PRTY_MASK_1				0x300140
+/* [R 32] Parity register #0 read */
+#define	USEM_REG_USEM_PRTY_STS_0				0x300124
+#define	USEM_REG_USEM_PRTY_STS_1				0x300134
+/* [RW 2] The queue index for registration on Aux1 counter flag. */
+#define	XCM_REG_AUX1_Q						0x20134
+/* [RW 2] Per each decision rule the queue index to register to. */
+#define	XCM_REG_AUX_CNT_FLG_Q_19				0x201b0
+/* [R 5] Used to read the XX protection CAM occupancy counter. */
+#define	XCM_REG_CAM_OCCUP					0x20244
+/*
+ * [RW 1] CDU AG read Interface enable. If 0 - the request input i
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	XCM_REG_CDU_AG_RD_IFEN					0x20044
+/*
+ * [RW 1] CDU AG write Interface enable. If 0 - the request and valid inpu
+ * are disregarded; all other signals are treated as usual; if 1 - normal
+ * activity.
+ */
+#define	XCM_REG_CDU_AG_WR_IFEN					0x20040
+/*
+ * [RW 1] CDU STORM read Interface enable. If 0 - the request input i
+ * disregarded; valid output is deasserted; all other signals are treated as
+ * usual; if 1 - normal activity.
+ */
+#define	XCM_REG_CDU_SM_RD_IFEN					0x2004c
+/*
+ * [RW 1] CDU STORM write Interface enable. If 0 - the request and vali
+ * input is disregarded; all other signals are treated as usual; if 1 -
+ * normal activity.
+ */
+#define	XCM_REG_CDU_SM_WR_IFEN					0x20048
+/*
+ * [RW 4] CFC output initial credit. Max credit available - 15.Write write
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 1 at start-up.
+ */
+#define	XCM_REG_CFC_INIT_CRD					0x20404
+/*
+ * [RW 3] The weight of the CP input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_CP_WEIGHT					0x200dc
+/*
+ * [RW 1] Input csem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_CSEM_IFEN					0x20028
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the csem interface.
+ */
+#define	XCM_REG_CSEM_LENGTH_MIS 				0x20228
+/*
+ * [RW 3] The weight of the input csem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_CSEM_WEIGHT					0x200c4
+/*
+ * [RW 1] Input dorq Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_DORQ_IFEN					0x20030
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the dorq interface.
+ */
+#define	XCM_REG_DORQ_LENGTH_MIS 				0x20230
+/*
+ * [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_DORQ_WEIGHT					0x200cc
+/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
+#define	XCM_REG_ERR_EVNT_ID					0x200b0
+/* [RW 28] The CM erroneous header for QM and Timers formatting. */
+#define	XCM_REG_ERR_XCM_HDR					0x200ac
+/* [RW 8] The Event ID for Timers expiration. */
+#define	XCM_REG_EXPR_EVNT_ID					0x200b4
+/*
+ * [RW 8] FIC0 output initial credit. Max credit available - 255.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	XCM_REG_FIC0_INIT_CRD					0x2040c
+/*
+ * [RW 8] FIC1 output initial credit. Max credit available - 255.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 64 at start-up.
+ */
+#define	XCM_REG_FIC1_INIT_CRD					0x20410
+#define	XCM_REG_GLB_DEL_ACK_MAX_CNT_0				0x20118
+#define	XCM_REG_GLB_DEL_ACK_MAX_CNT_1				0x2011c
+#define	XCM_REG_GLB_DEL_ACK_TMR_VAL_0				0x20108
+#define	XCM_REG_GLB_DEL_ACK_TMR_VAL_1				0x2010c
+/*
+ * [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin;
+ * - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
+ * ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
+ * ~xcm_registers_gr_ld1_pr.gr_ld1_pr.
+ */
+#define	XCM_REG_GR_ARB_TYPE					0x2020c
+/*
+ * [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; th
+ * highest priority is 3. It is supposed that the Channel group is the
+ * compliment of the other 3 groups.
+ */
+#define	XCM_REG_GR_LD0_PR					0x20214
+/*
+ * [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; th
+ * highest priority is 3. It is supposed that the Channel group is the
+ * compliment of the other 3 groups.
+ */
+#define	XCM_REG_GR_LD1_PR					0x20218
+/*
+ * [RW 1] Input nig0 Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_NIG0_IFEN					0x20038
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the nig0 interface.
+ */
+#define	XCM_REG_NIG0_LENGTH_MIS 				0x20238
+/*
+ * [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_NIG0_WEIGHT					0x200d4
+/*
+ * [RW 1] Input nig1 Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_NIG1_IFEN					0x2003c
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the nig1 interface.
+ */
+#define	XCM_REG_NIG1_LENGTH_MIS 				0x2023c
+/*
+ * [RW 5] The number of double REG-pairs; loaded from the STORM context an
+ * sent to STORM; for a specific connection type. The double REG-pairs are
+ * used in order to align to STORM context row size of 128 bits. The offset
+ * of these data in the STORM context is always 0. Index _i stands for the
+ * connection type (one of 16).
+ */
+#define	XCM_REG_N_SM_CTX_LD_0					0x20060
+#define	XCM_REG_N_SM_CTX_LD_1					0x20064
+#define	XCM_REG_N_SM_CTX_LD_2					0x20068
+#define	XCM_REG_N_SM_CTX_LD_3					0x2006c
+#define	XCM_REG_N_SM_CTX_LD_4					0x20070
+#define	XCM_REG_N_SM_CTX_LD_5					0x20074
+/*
+ * [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	XCM_REG_PBF_IFEN					0x20034
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the pbf interface.
+ */
+#define	XCM_REG_PBF_LENGTH_MIS					0x20234
+/*
+ * [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_PBF_WEIGHT					0x200d0
+#define	XCM_REG_PHYS_QNUM3_0					0x20100
+#define	XCM_REG_PHYS_QNUM3_1					0x20104
+/* [RW 8] The Event ID for Timers formatting in case of stop done. */
+#define	XCM_REG_STOP_EVNT_ID					0x200b8
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the STORM interface.
+ */
+#define	XCM_REG_STORM_LENGTH_MIS				0x2021c
+/*
+ * [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_STORM_WEIGHT					0x200bc
+/*
+ * [RW 1] STORM - CM Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_STORM_XCM_IFEN					0x20010
+/*
+ * [RW 4] Timers output initial credit. Max credit available - 15.Writ
+ * writes the initial credit value; read returns the current value of the
+ * credit counter. Must be initialized to 4 at start-up.
+ */
+#define	XCM_REG_TM_INIT_CRD					0x2041c
+/*
+ * [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_TM_WEIGHT					0x200ec
+/* [RW 28] The CM header for Timers expiration command. */
+#define	XCM_REG_TM_XCM_HDR					0x200a8
+/*
+ * [RW 1] Timers - CM Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_TM_XCM_IFEN					0x2001c
+/*
+ * [RW 1] Input tsem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_TSEM_IFEN					0x20024
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the tsem interface.
+ */
+#define	XCM_REG_TSEM_LENGTH_MIS 				0x20224
+/*
+ * [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_TSEM_WEIGHT					0x200c0
+/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
+#define	XCM_REG_UNA_GT_NXT_Q					0x20120
+/*
+ * [RW 1] Input usem Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_USEM_IFEN					0x2002c
+/*
+ * [RC 1] Message length mismatch (relative to last indication) at the use
+ * interface.
+ */
+#define	XCM_REG_USEM_LENGTH_MIS 				0x2022c
+/*
+ * [RW 3] The weight of the input usem in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_USEM_WEIGHT					0x200c8
+#define	XCM_REG_WU_DA_CNT_CMD00 				0x201d4
+#define	XCM_REG_WU_DA_CNT_CMD01 				0x201d8
+#define	XCM_REG_WU_DA_CNT_CMD10 				0x201dc
+#define	XCM_REG_WU_DA_CNT_CMD11 				0x201e0
+#define	XCM_REG_WU_DA_CNT_UPD_VAL00				0x201e4
+#define	XCM_REG_WU_DA_CNT_UPD_VAL01				0x201e8
+#define	XCM_REG_WU_DA_CNT_UPD_VAL10				0x201ec
+#define	XCM_REG_WU_DA_CNT_UPD_VAL11				0x201f0
+#define	XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00			0x201c4
+#define	XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01			0x201c8
+#define	XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10			0x201cc
+#define	XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11			0x201d0
+/*
+ * [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	XCM_REG_XCM_CFC_IFEN					0x20050
+/* [RW 14] Interrupt mask register #0 read/write */
+#define	XCM_REG_XCM_INT_MASK					0x202b4
+/* [R 14] Interrupt register #0 read */
+#define	XCM_REG_XCM_INT_STS					0x202a8
+/* [R 30] Parity register #0 read */
+#define	XCM_REG_XCM_PRTY_STS					0x202b8
+/*
+ * [RW 4] The size of AG context region 0 in REG-pairs. Designates the M
+ * REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
+ * Is used to determine the number of the AG context REG-pairs written back;
+ * when the Reg1WbFlg isn't set.
+ */
+#define	XCM_REG_XCM_REG0_SZ					0x200f4
+/*
+ * [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	XCM_REG_XCM_STORM0_IFEN 				0x20004
+/*
+ * [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	XCM_REG_XCM_STORM1_IFEN 				0x20008
+/*
+ * [RW 1] CM - Timers Interface enable. If 0 - the valid input i
+ * disregarded; acknowledge output is deasserted; all other signals are
+ * treated as usual; if 1 - normal activity.
+ */
+#define	XCM_REG_XCM_TM_IFEN					0x20020
+/*
+ * [RW 1] CM - QM Interface enable. If 0 - the acknowledge input i
+ * disregarded; valid is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	XCM_REG_XCM_XQM_IFEN					0x2000c
+/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
+#define	XCM_REG_XCM_XQM_USE_Q					0x200f0
+/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
+#define	XCM_REG_XQM_BYP_ACT_UPD 				0x200fc
+/*
+ * [RW 6] QM output initial credit. Max credit available - 32.Write write
+ * the initial credit value; read returns the current value of the credit
+ * counter. Must be initialized to 32 at start-up.
+ */
+#define	XCM_REG_XQM_INIT_CRD					0x20420
+/*
+ * [RW 3] The weight of the QM (primary) input in the WRR mechanism.
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_XQM_P_WEIGHT					0x200e4
+/*
+ * [RW 3] The weight of the QM (secondary) input in the WRR mechanism.
+ * stands for weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_XQM_S_WEIGHT					0x200e8
+/* [RW 28] The CM header value for QM request (primary). */
+#define	XCM_REG_XQM_XCM_HDR_P					0x200a0
+/* [RW 28] The CM header value for QM request (secondary). */
+#define	XCM_REG_XQM_XCM_HDR_S					0x200a4
+/*
+ * [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	XCM_REG_XQM_XCM_IFEN					0x20014
+/*
+ * [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded
+ * acknowledge output is deasserted; all other signals are treated as usual;
+ * if 1 - normal activity.
+ */
+#define	XCM_REG_XSDM_IFEN					0x20018
+/*
+ * [RC 1] Set at message length mismatch (relative to last indication) a
+ * the SDM interface.
+ */
+#define	XCM_REG_XSDM_LENGTH_MIS 				0x20220
+/*
+ * [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands fo
+ * weight 8 (the most prioritised); 1 stands for weight 1(least
+ * prioritised); 2 stands for weight 2; tc.
+ */
+#define	XCM_REG_XSDM_WEIGHT					0x200e0
+/*
+ * [RW 17] Indirect access to the descriptor table of the XX protectio
+ * mechanism. The fields are: [5:0] - message length; 11:6] - message
+ * pointer; 16:12] - next pointer.
+ */
+#define	XCM_REG_XX_DESCR_TABLE					0x20480
+#define	XCM_REG_XX_DESCR_TABLE_SIZE				 32
+/* [R 6] Used to read the XX protection Free counter. */
+#define	XCM_REG_XX_FREE 					0x20240
+/*
+ * [RW 6] Initial value for the credit counter; responsible for fulfillin
+ * of the Input Stage XX protection buffer by the XX protection pending
+ * messages. Max credit available - 3.Write writes the initial credit value;
+ * read returns the current value of the credit counter. Must be initialized
+ * to 2 at start-up.
+ */
+#define	XCM_REG_XX_INIT_CRD					0x20424
+/*
+ * [RW 6] The maximum number of pending messages; which may be stored in X
+ * protection. ~xcm_registers_xx_free.xx_free read on read.
+ */
+#define	XCM_REG_XX_MSG_NUM					0x20428
+/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
+#define	XCM_REG_XX_OVFL_EVNT_ID 				0x20058
+/*
+ * [RW 16] Indirect access to the XX table of the XX protection mechanism
+ * The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
+ * header pointer.
+ */
+#define	XCM_REG_XX_TABLE					0x20500
+/* [RW 8] The event id for aggregated interrupt 0 */
+#define	XSDM_REG_AGG_INT_EVENT_0				0x166038
+#define	XSDM_REG_AGG_INT_EVENT_1				0x16603c
+#define	XSDM_REG_AGG_INT_EVENT_10				0x166060
+#define	XSDM_REG_AGG_INT_EVENT_11				0x166064
+#define	XSDM_REG_AGG_INT_EVENT_12				0x166068
+#define	XSDM_REG_AGG_INT_EVENT_13				0x16606c
+#define	XSDM_REG_AGG_INT_EVENT_14				0x166070
+#define	XSDM_REG_AGG_INT_EVENT_2				0x166040
+#define	XSDM_REG_AGG_INT_EVENT_3				0x166044
+#define	XSDM_REG_AGG_INT_EVENT_4				0x166048
+#define	XSDM_REG_AGG_INT_EVENT_5				0x16604c
+#define	XSDM_REG_AGG_INT_EVENT_6				0x166050
+#define	XSDM_REG_AGG_INT_EVENT_7				0x166054
+#define	XSDM_REG_AGG_INT_EVENT_8				0x166058
+#define	XSDM_REG_AGG_INT_EVENT_9				0x16605c
+/*
+ * [RW 1] For each aggregated interrupt index whether the mode is normal (0
+ * or auto-mask-mode (1)
+ */
+#define	XSDM_REG_AGG_INT_MODE_0 				0x1661b8
+#define	XSDM_REG_AGG_INT_MODE_1 				0x1661bc
+/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
+#define	XSDM_REG_CFC_RSP_START_ADDR				0x166008
+/* [RW 16] The maximum value of the competion counter #0 */
+#define	XSDM_REG_CMP_COUNTER_MAX0				0x16601c
+/* [RW 16] The maximum value of the competion counter #1 */
+#define	XSDM_REG_CMP_COUNTER_MAX1				0x166020
+/* [RW 16] The maximum value of the competion counter #2 */
+#define	XSDM_REG_CMP_COUNTER_MAX2				0x166024
+/* [RW 16] The maximum value of the competion counter #3 */
+#define	XSDM_REG_CMP_COUNTER_MAX3				0x166028
+/*
+ * [RW 13] The start address in the internal RAM for the completio
+ * counters.
+ */
+#define	XSDM_REG_CMP_COUNTER_START_ADDR 			0x16600c
+#define	XSDM_REG_ENABLE_IN1					0x166238
+#define	XSDM_REG_ENABLE_IN2					0x16623c
+#define	XSDM_REG_ENABLE_OUT1					0x166240
+#define	XSDM_REG_ENABLE_OUT2					0x166244
+/*
+ * [RW 4] The initial number of messages that can be sent to the pxp contro
+ * interface without receiving any ACK.
+ */
+#define	XSDM_REG_INIT_CREDIT_PXP_CTRL				0x1664bc
+/* [ST 32] The number of ACK after placement messages received */
+#define	XSDM_REG_NUM_OF_ACK_AFTER_PLACE 			0x16627c
+/* [ST 32] The number of packet end messages received from the parser */
+#define	XSDM_REG_NUM_OF_PKT_END_MSG				0x166274
+/* [ST 32] The number of requests received from the pxp async if */
+#define	XSDM_REG_NUM_OF_PXP_ASYNC_REQ				0x166278
+/* [ST 32] The number of commands received in queue 0 */
+#define	XSDM_REG_NUM_OF_Q0_CMD					0x166248
+/* [ST 32] The number of commands received in queue 10 */
+#define	XSDM_REG_NUM_OF_Q10_CMD 				0x16626c
+/* [ST 32] The number of commands received in queue 11 */
+#define	XSDM_REG_NUM_OF_Q11_CMD 				0x166270
+/* [ST 32] The number of commands received in queue 1 */
+#define	XSDM_REG_NUM_OF_Q1_CMD					0x16624c
+/* [ST 32] The number of commands received in queue 3 */
+#define	XSDM_REG_NUM_OF_Q3_CMD					0x166250
+/* [ST 32] The number of commands received in queue 4 */
+#define	XSDM_REG_NUM_OF_Q4_CMD					0x166254
+/* [ST 32] The number of commands received in queue 5 */
+#define	XSDM_REG_NUM_OF_Q5_CMD					0x166258
+/* [ST 32] The number of commands received in queue 6 */
+#define	XSDM_REG_NUM_OF_Q6_CMD					0x16625c
+/* [ST 32] The number of commands received in queue 7 */
+#define	XSDM_REG_NUM_OF_Q7_CMD					0x166260
+/* [ST 32] The number of commands received in queue 8 */
+#define	XSDM_REG_NUM_OF_Q8_CMD					0x166264
+/* [ST 32] The number of commands received in queue 9 */
+#define	XSDM_REG_NUM_OF_Q9_CMD					0x166268
+/* [RW 13] The start address in the internal RAM for queue counters */
+#define	XSDM_REG_Q_COUNTER_START_ADDR				0x166010
+/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
+#define	XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY			0x166548
+/* [R 1] parser fifo empty in sdm_sync block */
+#define	XSDM_REG_SYNC_PARSER_EMPTY				0x166550
+/* [R 1] parser serial fifo empty in sdm_sync block */
+#define	XSDM_REG_SYNC_SYNC_EMPTY				0x166558
+/*
+ * [RW 32] Tick for timer counter. Applicable only whe
+ * ~xsdm_registers_timer_tick_enable.timer_tick_enable =1
+ */
+#define	XSDM_REG_TIMER_TICK					0x166000
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	XSDM_REG_XSDM_INT_MASK_0				0x16629c
+#define	XSDM_REG_XSDM_INT_MASK_1				0x1662ac
+/* [R 32] Interrupt register #0 read */
+#define	XSDM_REG_XSDM_INT_STS_0 				0x166290
+#define	XSDM_REG_XSDM_INT_STS_1 				0x1662a0
+/* [RW 11] Parity mask register #0 read/write */
+#define	XSDM_REG_XSDM_PRTY_MASK 				0x1662bc
+/* [R 11] Parity register #0 read */
+#define	XSDM_REG_XSDM_PRTY_STS					0x1662b0
+/* [RW 5] The number of time_slots in the arbitration cycle */
+#define	XSEM_REG_ARB_CYCLE_SIZE 				0x280034
+/*
+ * [RW 3] The source that is associated with arbitration element 0. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2
+ */
+#define	XSEM_REG_ARB_ELEMENT0					0x280020
+/*
+ * [RW 3] The source that is associated with arbitration element 1. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~xsem_registers_arb_element0.arb_element0
+ */
+#define	XSEM_REG_ARB_ELEMENT1					0x280024
+/*
+ * [RW 3] The source that is associated with arbitration element 2. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~xsem_registers_arb_element0.arb_element0
+ * and ~xsem_registers_arb_element1.arb_element1
+ */
+#define	XSEM_REG_ARB_ELEMENT2					0x280028
+/*
+ * [RW 3] The source that is associated with arbitration element 3. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
+ * not be equal to register ~xsem_registers_arb_element0.arb_element0 and
+ * ~xsem_registers_arb_element1.arb_element1 and
+ * ~xsem_registers_arb_element2.arb_element2
+ */
+#define	XSEM_REG_ARB_ELEMENT3					0x28002c
+/*
+ * [RW 3] The source that is associated with arbitration element 4. Sourc
+ * decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
+ * sleeping thread with priority 1; 4- sleeping thread with priority 2.
+ * Could not be equal to register ~xsem_registers_arb_element0.arb_element0
+ * and ~xsem_registers_arb_element1.arb_element1 and
+ * ~xsem_registers_arb_element2.arb_element2 and
+ * ~xsem_registers_arb_element3.arb_element3
+ */
+#define	XSEM_REG_ARB_ELEMENT4					0x280030
+#define	XSEM_REG_ENABLE_IN					0x2800a4
+#define	XSEM_REG_ENABLE_OUT					0x2800a8
+/*
+ * [RW 32] This address space contains all registers and memories that ar
+ * placed in SEM_FAST block. The SEM_FAST registers are described in
+ * appendix B. In order to access the sem_fast registers the base address
+ * ~fast_memory.fast_memory should be added to eachsem_fast register offset.
+ */
+#define	XSEM_REG_FAST_MEMORY					0x2a0000
+/*
+ * [RW 1] Disables input messages from FIC0 May be updated during run_tim
+ * by the microcode
+ */
+#define	XSEM_REG_FIC0_DISABLE					0x280224
+/*
+ * [RW 1] Disables input messages from FIC1 May be updated during run_tim
+ * by the microcode
+ */
+#define	XSEM_REG_FIC1_DISABLE					0x280234
+/*
+ * [RW 15] Interrupt table Read and write access to it is not possible i
+ * the middle of the work
+ */
+#define	XSEM_REG_INT_TABLE					0x280400
+/*
+ * [ST 24] Statistics register. The number of messages that entered throug
+ * FIC0
+ */
+#define	XSEM_REG_MSG_NUM_FIC0					0x280000
+/*
+ * [ST 24] Statistics register. The number of messages that entered throug
+ * FIC1
+ */
+#define	XSEM_REG_MSG_NUM_FIC1					0x280004
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC0
+ */
+#define	XSEM_REG_MSG_NUM_FOC0					0x280008
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC1
+ */
+#define	XSEM_REG_MSG_NUM_FOC1					0x28000c
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC2
+ */
+#define	XSEM_REG_MSG_NUM_FOC2					0x280010
+/*
+ * [ST 24] Statistics register. The number of messages that were sent t
+ * FOC3
+ */
+#define	XSEM_REG_MSG_NUM_FOC3					0x280014
+/*
+ * [RW 1] Disables input messages from the passive buffer May be update
+ * during run_time by the microcode
+ */
+#define	XSEM_REG_PAS_DISABLE					0x28024c
+/* [WB 128] Debug only. Passive buffer memory */
+#define	XSEM_REG_PASSIVE_BUFFER 				0x282000
+/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
+#define	XSEM_REG_PRAM						0x2c0000
+/* [R 16] Valid sleeping threads indication have bit per thread */
+#define	XSEM_REG_SLEEP_THREADS_VALID				0x28026c
+/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
+#define	XSEM_REG_SLOW_EXT_STORE_EMPTY				0x2802a0
+/* [RW 16] List of free threads . There is a bit per thread. */
+#define	XSEM_REG_THREADS_LIST					0x2802e4
+/* [RW 3] The arbitration scheme of time_slot 0 */
+#define	XSEM_REG_TS_0_AS					0x280038
+/* [RW 3] The arbitration scheme of time_slot 10 */
+#define	XSEM_REG_TS_10_AS					0x280060
+/* [RW 3] The arbitration scheme of time_slot 11 */
+#define	XSEM_REG_TS_11_AS					0x280064
+/* [RW 3] The arbitration scheme of time_slot 12 */
+#define	XSEM_REG_TS_12_AS					0x280068
+/* [RW 3] The arbitration scheme of time_slot 13 */
+#define	XSEM_REG_TS_13_AS					0x28006c
+/* [RW 3] The arbitration scheme of time_slot 14 */
+#define	XSEM_REG_TS_14_AS					0x280070
+/* [RW 3] The arbitration scheme of time_slot 15 */
+#define	XSEM_REG_TS_15_AS					0x280074
+/* [RW 3] The arbitration scheme of time_slot 16 */
+#define	XSEM_REG_TS_16_AS					0x280078
+/* [RW 3] The arbitration scheme of time_slot 17 */
+#define	XSEM_REG_TS_17_AS					0x28007c
+/* [RW 3] The arbitration scheme of time_slot 18 */
+#define	XSEM_REG_TS_18_AS					0x280080
+/* [RW 3] The arbitration scheme of time_slot 1 */
+#define	XSEM_REG_TS_1_AS					0x28003c
+/* [RW 3] The arbitration scheme of time_slot 2 */
+#define	XSEM_REG_TS_2_AS					0x280040
+/* [RW 3] The arbitration scheme of time_slot 3 */
+#define	XSEM_REG_TS_3_AS					0x280044
+/* [RW 3] The arbitration scheme of time_slot 4 */
+#define	XSEM_REG_TS_4_AS					0x280048
+/* [RW 3] The arbitration scheme of time_slot 5 */
+#define	XSEM_REG_TS_5_AS					0x28004c
+/* [RW 3] The arbitration scheme of time_slot 6 */
+#define	XSEM_REG_TS_6_AS					0x280050
+/* [RW 3] The arbitration scheme of time_slot 7 */
+#define	XSEM_REG_TS_7_AS					0x280054
+/* [RW 3] The arbitration scheme of time_slot 8 */
+#define	XSEM_REG_TS_8_AS					0x280058
+/* [RW 3] The arbitration scheme of time_slot 9 */
+#define	XSEM_REG_TS_9_AS					0x28005c
+/* [RW 32] Interrupt mask register #0 read/write */
+#define	XSEM_REG_XSEM_INT_MASK_0				0x280110
+#define	XSEM_REG_XSEM_INT_MASK_1				0x280120
+/* [R 32] Interrupt register #0 read */
+#define	XSEM_REG_XSEM_INT_STS_0 				0x280104
+#define	XSEM_REG_XSEM_INT_STS_1 				0x280114
+/* [RW 32] Parity mask register #0 read/write */
+#define	XSEM_REG_XSEM_PRTY_MASK_0				0x280130
+#define	XSEM_REG_XSEM_PRTY_MASK_1				0x280140
+/* [R 32] Parity register #0 read */
+#define	XSEM_REG_XSEM_PRTY_STS_0				0x280124
+#define	XSEM_REG_XSEM_PRTY_STS_1				0x280134
+#define	MCPR_NVM_ACCESS_ENABLE_EN				(1L<<0)
+#define	MCPR_NVM_ACCESS_ENABLE_WR_EN				(1L<<1)
+#define	MCPR_NVM_ADDR_NVM_ADDR_VALUE				(0xffffffL<<0)
+#define	MCPR_NVM_CFG4_FLASH_SIZE				(0x7L<<0)
+#define	MCPR_NVM_COMMAND_DOIT					(1L<<4)
+#define	MCPR_NVM_COMMAND_DONE					(1L<<3)
+#define	MCPR_NVM_COMMAND_FIRST					(1L<<7)
+#define	MCPR_NVM_COMMAND_LAST					(1L<<8)
+#define	MCPR_NVM_COMMAND_WR					(1L<<5)
+#define	MCPR_NVM_SW_ARB_ARB_ARB1				(1L<<9)
+#define	MCPR_NVM_SW_ARB_ARB_REQ_CLR1				(1L<<5)
+#define	MCPR_NVM_SW_ARB_ARB_REQ_SET1				(1L<<1)
+#define	BIGMAC_REGISTER_BMAC_CONTROL				(0x00<<3)
+#define	BIGMAC_REGISTER_BMAC_XGXS_CONTROL			(0x01<<3)
+#define	BIGMAC_REGISTER_CNT_MAX_SIZE				(0x05<<3)
+#define	BIGMAC_REGISTER_RX_CONTROL				(0x21<<3)
+#define	BIGMAC_REGISTER_RX_LLFC_MSG_FLDS			(0x46<<3)
+#define	BIGMAC_REGISTER_RX_MAX_SIZE				(0x23<<3)
+#define	BIGMAC_REGISTER_RX_STAT_GR64				(0x26<<3)
+#define	BIGMAC_REGISTER_RX_STAT_GRIPJ				(0x42<<3)
+#define	BIGMAC_REGISTER_TX_CONTROL				(0x07<<3)
+#define	BIGMAC_REGISTER_TX_MAX_SIZE				(0x09<<3)
+#define	BIGMAC_REGISTER_TX_PAUSE_THRESHOLD			(0x0A<<3)
+#define	BIGMAC_REGISTER_TX_SOURCE_ADDR				(0x08<<3)
+#define	BIGMAC_REGISTER_TX_STAT_GTBYT				(0x20<<3)
+#define	BIGMAC_REGISTER_TX_STAT_GTPKT				(0x0C<<3)
+#define	BIGMAC2_REGISTER_BMAC_CONTROL				(0x00<<3)
+#define	BIGMAC2_REGISTER_BMAC_XGXS_CONTROL			(0x01<<3)
+#define	BIGMAC2_REGISTER_PFC_CONTROL				(0x06<<3)
+#define	BIGMAC2_REGISTER_RX_CONTROL				(0x3A<<3)
+#define	BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS			(0x62<<3)
+#define	BIGMAC2_REGISTER_RX_MAX_SIZE				(0x3C<<3)
+#define	BIGMAC2_REGISTER_TX_CONTROL				(0x1C<<3)
+#define	BIGMAC2_REGISTER_TX_MAX_SIZE				(0x1E<<3)
+#define	BIGMAC2_REGISTER_TX_SOURCE_ADDR				(0x1D<<3)
+#define	EMAC_LED_1000MB_OVERRIDE				(1L<<1)
+#define	EMAC_LED_100MB_OVERRIDE					(1L<<2)
+#define	EMAC_LED_10MB_OVERRIDE					(1L<<3)
+#define	EMAC_LED_2500MB_OVERRIDE				(1L<<12)
+#define	EMAC_LED_OVERRIDE					(1L<<0)
+#define	EMAC_LED_TRAFFIC					(1L<<6)
+#define	EMAC_MDIO_COMM_COMMAND_ADDRESS				(0L<<26)
+#define	EMAC_MDIO_COMM_COMMAND_READ_45				(3L<<26)
+#define	EMAC_MDIO_COMM_COMMAND_WRITE_45				(1L<<26)
+#define	EMAC_MDIO_COMM_DATA					(0xffffL<<0)
+#define	EMAC_MDIO_COMM_START_BUSY				(1L<<29)
+#define	EMAC_MDIO_MODE_AUTO_POLL				(1L<<4)
+#define	EMAC_MDIO_MODE_CLAUSE_45				(1<<31)
+#define	EMAC_MDIO_MODE_CLOCK_CNT				(0x3fL<<16)
+#define	EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT			16
+#define	EMAC_MODE_25G_MODE					(1L<<5)
+#define	EMAC_MODE_HALF_DUPLEX					(1L<<1)
+#define	EMAC_MODE_PORT_GMII					(2L<<2)
+#define	EMAC_MODE_PORT_MII					(1L<<2)
+#define	EMAC_MODE_PORT_MII_10M					(3L<<2)
+#define	EMAC_MODE_RESET						(1L<<0)
+#define	EMAC_REG_EMAC_LED					0xc
+#define	EMAC_REG_EMAC_MAC_MATCH					0x10
+#define	EMAC_REG_EMAC_MDIO_COMM					0xac
+#define	EMAC_REG_EMAC_MDIO_MODE					0xb4
+#define	EMAC_REG_EMAC_MODE					0x0
+#define	EMAC_REG_EMAC_RX_MODE					0xc8
+#define	EMAC_REG_EMAC_RX_MTU_SIZE				0x9c
+#define	EMAC_REG_EMAC_RX_STAT_AC				0x180
+#define	EMAC_REG_EMAC_RX_STAT_AC_28				0x1f4
+#define	EMAC_REG_EMAC_RX_STAT_AC_COUNT				23
+#define	EMAC_REG_EMAC_TX_MODE					0xbc
+#define	EMAC_REG_EMAC_TX_STAT_AC				0x280
+#define	EMAC_REG_EMAC_TX_STAT_AC_COUNT				22
+#define	EMAC_RX_MODE_FLOW_EN					(1L<<2)
+#define	EMAC_RX_MODE_KEEP_VLAN_TAG				(1L<<10)
+#define	EMAC_RX_MODE_PROMISCUOUS				(1L<<8)
+#define	EMAC_RX_MODE_RESET					(1L<<0)
+#define	EMAC_RX_MTU_SIZE_JUMBO_ENA				(1<<31)
+#define	EMAC_TX_MODE_EXT_PAUSE_EN				(1L<<3)
+#define	EMAC_TX_MODE_FLOW_EN					(1L<<4)
+#define	EMAC_TX_MODE_RESET					(1L<<0)
+#define	MISC_REGISTERS_GPIO_0					0
+#define	MISC_REGISTERS_GPIO_1					1
+#define	MISC_REGISTERS_GPIO_2					2
+#define	MISC_REGISTERS_GPIO_3					3
+#define	MISC_REGISTERS_GPIO_CLR_POS				16
+#define	MISC_REGISTERS_GPIO_FLOAT				(0xffL<<24)
+#define	MISC_REGISTERS_GPIO_FLOAT_POS				24
+#define	MISC_REGISTERS_GPIO_HIGH				1
+#define	MISC_REGISTERS_GPIO_INPUT_HI_Z				2
+#define	MISC_REGISTERS_GPIO_INT_CLR_POS				24
+#define	MISC_REGISTERS_GPIO_INT_OUTPUT_CLR			0
+#define	MISC_REGISTERS_GPIO_INT_OUTPUT_SET			1
+#define	MISC_REGISTERS_GPIO_INT_SET_POS				16
+#define	MISC_REGISTERS_GPIO_LOW					0
+#define	MISC_REGISTERS_GPIO_OUTPUT_HIGH				1
+#define	MISC_REGISTERS_GPIO_OUTPUT_LOW				0
+#define	MISC_REGISTERS_GPIO_PORT_SHIFT				4
+#define	MISC_REGISTERS_GPIO_SET_POS				8
+#define	MISC_REGISTERS_RESET_REG_1_CLEAR			0x588
+#define	MISC_REGISTERS_RESET_REG_1_RST_NIG			(0x1<<7)
+#define	MISC_REGISTERS_RESET_REG_1_SET				0x584
+#define	MISC_REGISTERS_RESET_REG_2_CLEAR			0x598
+#define	MISC_REGISTERS_RESET_REG_2_RST_BMAC0			(0x1<<0)
+#define	MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE		(0x1<<14)
+#define	MISC_REGISTERS_RESET_REG_2_SET				0x594
+#define	MISC_REGISTERS_RESET_REG_3_CLEAR			0x5a8
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ	(0x1<<1)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN	(0x1<<2)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW	(0x1<<0)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ	(0x1<<5)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN	(0x1<<6)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD	(0x1<<7)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW	(0x1<<4)
+#define	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
+#define	MISC_REGISTERS_RESET_REG_3_SET				0x5a4
+#define	MISC_REGISTERS_SPIO_4					4
+#define	MISC_REGISTERS_SPIO_5					5
+#define	MISC_REGISTERS_SPIO_7					7
+#define	MISC_REGISTERS_SPIO_CLR_POS				16
+#define	MISC_REGISTERS_SPIO_FLOAT				(0xffL<<24)
+#define	MISC_REGISTERS_SPIO_FLOAT_POS				24
+#define	MISC_REGISTERS_SPIO_INPUT_HI_Z				2
+#define	MISC_REGISTERS_SPIO_INT_OLD_SET_POS			16
+#define	MISC_REGISTERS_SPIO_OUTPUT_HIGH				1
+#define	MISC_REGISTERS_SPIO_OUTPUT_LOW				0
+#define	MISC_REGISTERS_SPIO_SET_POS				8
+#define	HW_LOCK_MAX_RESOURCE_VALUE				31
+#define	HW_LOCK_RESOURCE_GPIO					1
+#define	HW_LOCK_RESOURCE_MDIO					0
+#define	HW_LOCK_RESOURCE_PORT0_ATT_MASK				3
+#define	HW_LOCK_RESOURCE_SPIO					2
+#define	HW_LOCK_RESOURCE_UNDI					5
+#define	PRS_FLAG_OVERETH_IPV4					1
+#define	AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR			(1UL<<18)
+#define	AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT			(1UL<<31)
+#define	AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT			(1UL<<9)
+#define	AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR			(1UL<<8)
+#define	AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT			(1UL<<7)
+#define	AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR			(1UL<<6)
+#define	AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT			(1UL<<29)
+#define	AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR			(1UL<<28)
+#define	AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT			(1UL<<1)
+#define	AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR			(1UL<<0)
+#define	AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR			(1UL<<18)
+#define	AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT			(1UL<<11)
+#define	AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT		(1UL<<13)
+#define	AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR		(1UL<<12)
+#define	AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0			(1UL<<5)
+#define	AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1			(1UL<<9)
+#define	AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR			(1UL<<12)
+#define	AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT			(1UL<<15)
+#define	AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR			(1UL<<14)
+#define	AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR		(1UL<<20)
+#define	AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR		(1UL<<0)
+#define	AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT			(1UL<<31)
+#define	AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT			(1UL<<3)
+#define	AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR			(1UL<<2)
+#define	AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT	(1UL<<5)
+#define	AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR	(1UL<<4)
+#define	AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT			(1UL<<3)
+#define	AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR			(1UL<<2)
+#define	AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR		(1UL<<22)
+#define	AEU_INPUTS_ATTN_BITS_SPIO5				(1UL<<15)
+#define	AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT			(1UL<<27)
+#define	AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT		(1UL<<5)
+#define	AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT			(1UL<<25)
+#define	AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR			(1UL<<24)
+#define	AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT			(1UL<<29)
+#define	AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR			(1UL<<28)
+#define	AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT			(1UL<<23)
+#define	AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT			(1UL<<27)
+#define	AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR			(1UL<<26)
+#define	AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT			(1UL<<21)
+#define	AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR			(1UL<<20)
+#define	AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT			(1UL<<25)
+#define	AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR			(1UL<<24)
+#define	AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR		(1UL<<16)
+#define	AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT			(1UL<<9)
+#define	AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT			(1UL<<7)
+#define	AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR			(1UL<<6)
+#define	AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT			(1UL<<11)
+#define	AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR			(1UL<<10)
+#define	RESERVED_GENERAL_ATTENTION_BIT_0	0
+
+#define	EVEREST_GEN_ATTN_IN_USE_MASK		0x3ffe0
+#define	EVEREST_LATCHED_ATTN_IN_USE_MASK	0xffe00000
+
+#define	RESERVED_GENERAL_ATTENTION_BIT_6	6
+#define	RESERVED_GENERAL_ATTENTION_BIT_7	7
+#define	RESERVED_GENERAL_ATTENTION_BIT_8	8
+#define	RESERVED_GENERAL_ATTENTION_BIT_9	9
+#define	RESERVED_GENERAL_ATTENTION_BIT_10	10
+#define	RESERVED_GENERAL_ATTENTION_BIT_11	11
+#define	RESERVED_GENERAL_ATTENTION_BIT_12	12
+#define	RESERVED_GENERAL_ATTENTION_BIT_13	13
+#define	RESERVED_GENERAL_ATTENTION_BIT_14	14
+#define	RESERVED_GENERAL_ATTENTION_BIT_15	15
+#define	RESERVED_GENERAL_ATTENTION_BIT_16	16
+#define	RESERVED_GENERAL_ATTENTION_BIT_17	17
+#define	RESERVED_GENERAL_ATTENTION_BIT_18	18
+#define	RESERVED_GENERAL_ATTENTION_BIT_19	19
+#define	RESERVED_GENERAL_ATTENTION_BIT_20	20
+#define	RESERVED_GENERAL_ATTENTION_BIT_21	21
+
+/* storm asserts attention bits */
+#define	TSTORM_FATAL_ASSERT_ATTENTION_BIT	RESERVED_GENERAL_ATTENTION_BIT_7
+#define	USTORM_FATAL_ASSERT_ATTENTION_BIT	RESERVED_GENERAL_ATTENTION_BIT_8
+#define	CSTORM_FATAL_ASSERT_ATTENTION_BIT	RESERVED_GENERAL_ATTENTION_BIT_9
+#define	XSTORM_FATAL_ASSERT_ATTENTION_BIT	RESERVED_GENERAL_ATTENTION_BIT_10
+
+/* mcp error attention bit */
+#define	MCP_FATAL_ASSERT_ATTENTION_BIT	RESERVED_GENERAL_ATTENTION_BIT_11
+
+/* E1H NIG status sync attention mapped to group 4-7*/
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_0	RESERVED_GENERAL_ATTENTION_BIT_12
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_1	RESERVED_GENERAL_ATTENTION_BIT_13
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_2	RESERVED_GENERAL_ATTENTION_BIT_14
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_3	RESERVED_GENERAL_ATTENTION_BIT_15
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_4	RESERVED_GENERAL_ATTENTION_BIT_16
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_5	RESERVED_GENERAL_ATTENTION_BIT_17
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_6	RESERVED_GENERAL_ATTENTION_BIT_18
+#define	LINK_SYNC_ATTENTION_BIT_FUNC_7	RESERVED_GENERAL_ATTENTION_BIT_19
+
+#define	LATCHED_ATTN_RBCR			23
+#define	LATCHED_ATTN_RBCT			24
+#define	LATCHED_ATTN_RBCN			25
+#define	LATCHED_ATTN_RBCU			26
+#define	LATCHED_ATTN_RBCP			27
+#define	LATCHED_ATTN_TIMEOUT_GRC		28
+#define	LATCHED_ATTN_RSVD_GRC			29
+#define	LATCHED_ATTN_ROM_PARITY_MCP		30
+#define	LATCHED_ATTN_UM_RX_PARITY_MCP		31
+#define	LATCHED_ATTN_UM_TX_PARITY_MCP		32
+#define	LATCHED_ATTN_SCPAD_PARITY_MCP		33
+
+#define	GENERAL_ATTEN_WORD(atten_name)		((94 + atten_name) / 32)
+#define	GENERAL_ATTEN_OFFSET(atten_name)	\
+	(1UL << ((94 + atten_name) % 32))
+/*
+ * This file defines GRC base address for every block.
+ * This file is included by chipsim, asm microcode and cpp microcode.
+ * These values are used in Design.xml on regBase attribute
+ * Use the base with the generated offsets of specific registers.
+ */
+
+#define	GRCBASE_PXPCS		0x000000
+#define	GRCBASE_PCICONFIG	0x002000
+#define	GRCBASE_PCIREG		0x002400
+#define	GRCBASE_EMAC0		0x008000
+#define	GRCBASE_EMAC1		0x008400
+#define	GRCBASE_DBU		0x008800
+#define	GRCBASE_MISC		0x00A000
+#define	GRCBASE_DBG		0x00C000
+#define	GRCBASE_NIG		0x010000
+#define	GRCBASE_XCM		0x020000
+#define	GRCBASE_PRS		0x040000
+#define	GRCBASE_SRCH		0x040400
+#define	GRCBASE_TSDM		0x042000
+#define	GRCBASE_TCM		0x050000
+#define	GRCBASE_BRB1		0x060000
+#define	GRCBASE_MCP		0x080000
+#define	GRCBASE_UPB		0x0C1000
+#define	GRCBASE_CSDM		0x0C2000
+#define	GRCBASE_USDM		0x0C4000
+#define	GRCBASE_CCM		0x0D0000
+#define	GRCBASE_UCM		0x0E0000
+#define	GRCBASE_CDU		0x101000
+#define	GRCBASE_DMAE		0x102000
+#define	GRCBASE_PXP		0x103000
+#define	GRCBASE_CFC		0x104000
+#define	GRCBASE_HC		0x108000
+#define	GRCBASE_PXP2		0x120000
+#define	GRCBASE_PBF		0x140000
+#define	GRCBASE_XPB		0x161000
+#define	GRCBASE_TIMERS		0x164000
+#define	GRCBASE_XSDM		0x166000
+#define	GRCBASE_QM		0x168000
+#define	GRCBASE_DQ		0x170000
+#define	GRCBASE_TSEM		0x180000
+#define	GRCBASE_CSEM		0x200000
+#define	GRCBASE_XSEM		0x280000
+#define	GRCBASE_USEM		0x300000
+#define	GRCBASE_MISC_AEU	GRCBASE_MISC
+
+/* offset of configuration space in the pci core register */
+#define	PCICFG_OFFSET				0x2000
+#define	PCICFG_VENDOR_ID_OFFSET			0x00
+#define	PCICFG_DEVICE_ID_OFFSET			0x02
+#define	PCICFG_COMMAND_OFFSET			0x04
+#define	PCICFG_COMMAND_IO_SPACE			(1<<0)
+#define	PCICFG_COMMAND_MEM_SPACE		(1<<1)
+#define	PCICFG_COMMAND_BUS_MASTER		(1<<2)
+#define	PCICFG_COMMAND_SPECIAL_CYCLES		(1<<3)
+#define	PCICFG_COMMAND_MWI_CYCLES		(1<<4)
+#define	PCICFG_COMMAND_VGA_SNOOP		(1<<5)
+#define	PCICFG_COMMAND_PERR_ENA			(1<<6)
+#define	PCICFG_COMMAND_STEPPING			(1<<7)
+#define	PCICFG_COMMAND_SERR_ENA			(1<<8)
+#define	PCICFG_COMMAND_FAST_B2B			(1<<9)
+#define	PCICFG_COMMAND_INT_DISABLE		(1<<10)
+#define	PCICFG_COMMAND_RESERVED			(0x1f<<11)
+#define	PCICFG_STATUS_OFFSET			0x06
+#define	PCICFG_REVESION_ID_OFFSET		0x08
+#define	PCICFG_CACHE_LINE_SIZE			0x0c
+#define	PCICFG_LATENCY_TIMER			0x0d
+#define	PCICFG_BAR_1_LOW			0x10
+#define	PCICFG_BAR_1_HIGH			0x14
+#define	PCICFG_BAR_2_LOW			0x18
+#define	PCICFG_BAR_2_HIGH			0x1c
+#define	PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET	0x2c
+#define	PCICFG_SUBSYSTEM_ID_OFFSET		0x2e
+#define	PCICFG_INT_LINE				0x3c
+#define	PCICFG_INT_PIN				0x3d
+#define	PCICFG_PM_CAPABILITY			0x48
+#define	PCICFG_PM_CAPABILITY_VERSION		(0x3<<16)
+#define	PCICFG_PM_CAPABILITY_CLOCK		(1<<19)
+#define	PCICFG_PM_CAPABILITY_RESERVED		(1<<20)
+#define	PCICFG_PM_CAPABILITY_DSI		(1<<21)
+#define	PCICFG_PM_CAPABILITY_AUX_CURRENT	(0x7<<22)
+#define	PCICFG_PM_CAPABILITY_D1_SUPPORT		(1<<25)
+#define	PCICFG_PM_CAPABILITY_D2_SUPPORT		(1<<26)
+#define	PCICFG_PM_CAPABILITY_PME_IN_D0		(1<<27)
+#define	PCICFG_PM_CAPABILITY_PME_IN_D1		(1<<28)
+#define	PCICFG_PM_CAPABILITY_PME_IN_D2		(1<<29)
+#define	PCICFG_PM_CAPABILITY_PME_IN_D3_HOT	(1<<30)
+#define	PCICFG_PM_CAPABILITY_PME_IN_D3_COLD	(1<<31)
+#define	PCICFG_PM_CSR_OFFSET			0x4c
+#define	PCICFG_PM_CSR_STATE			(0x3<<0)
+#define	PCICFG_PM_CSR_PME_ENABLE		(1<<8)
+#define	PCICFG_PM_CSR_PME_STATUS		(1<<15)
+#define	PCICFG_MSI_CAP_ID_OFFSET		0x58
+#define	PCICFG_MSI_CONTROL_ENABLE		(0x1<<16)
+#define	PCICFG_MSI_CONTROL_MCAP			(0x7<<17)
+#define	PCICFG_MSI_CONTROL_MENA			(0x7<<20)
+#define	PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP	(0x1<<23)
+#define	PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE	(0x1<<24)
+#define	PCICFG_GRC_ADDRESS			0x78
+#define	PCICFG_GRC_DATA				0x80
+#define	PCICFG_MSIX_CAP_ID_OFFSET		0xa0
+#define	PCICFG_MSIX_CONTROL_TABLE_SIZE		(0x7ff<<16)
+#define	PCICFG_MSIX_CONTROL_RESERVED		(0x7<<27)
+#define	PCICFG_MSIX_CONTROL_FUNC_MASK		(0x1<<30)
+#define	PCICFG_MSIX_CONTROL_MSIX_ENABLE		(0x1<<31)
+
+#define	PCICFG_DEVICE_CONTROL			0xb4
+#define	PCICFG_DEVICE_STATUS			0xb6
+#define	PCICFG_DEVICE_STATUS_CORR_ERR_DET	(1<<0)
+#define	PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET	(1<<1)
+#define	PCICFG_DEVICE_STATUS_FATAL_ERR_DET	(1<<2)
+#define	PCICFG_DEVICE_STATUS_UNSUP_REQ_DET	(1<<3)
+#define	PCICFG_DEVICE_STATUS_AUX_PWR_DET	(1<<4)
+#define	PCICFG_DEVICE_STATUS_NO_PEND		(1<<5)
+#define	PCICFG_LINK_CONTROL			0xbc
+
+#define	BAR_USTORM_INTMEM			0x400000
+#define	BAR_CSTORM_INTMEM			0x410000
+#define	BAR_XSTORM_INTMEM			0x420000
+#define	BAR_TSTORM_INTMEM			0x430000
+
+/* for accessing the IGU in case of status block ACK */
+#define	BAR_IGU_INTMEM				0x440000
+
+#define	BAR_DOORBELL_OFFSET			0x800000
+
+#define	BAR_ME_REGISTER				0x450000
+#define	ME_REG_PF_NUM				(7L<<0)	/* Relative PF Num */
+#define	ME_REG_PF_NUM_SHIFT			0
+#define	ME_REG_ABS_PF_NUM			(7L<<16) /* Absolute PF Num */
+#define	ME_REG_ABS_PF_NUM_SHIFT			16
+
+/* config_2 offset */
+#define	GRC_CONFIG_2_SIZE_REG			0x408
+#define	PCI_CONFIG_2_BAR1_SIZE			(0xfL<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_DISABLED		(0L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_64K		(1L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_128K		(2L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_256K		(3L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_512K		(4L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_1M		(5L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_2M		(6L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_4M		(7L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_8M		(8L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_16M		(9L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_32M		(10L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_64M		(11L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_128M		(12L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_256M		(13L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_512M		(14L<<0)
+#define	PCI_CONFIG_2_BAR1_SIZE_1G		(15L<<0)
+#define	PCI_CONFIG_2_BAR1_64ENA			(1L<<4)
+#define	PCI_CONFIG_2_EXP_ROM_RETRY		(1L<<5)
+#define	PCI_CONFIG_2_CFG_CYCLE_RETRY		(1L<<6)
+#define	PCI_CONFIG_2_FIRST_CFG_DONE		(1L<<7)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE		(0xffL<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED	(0L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_2K		(1L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_4K		(2L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_8K		(3L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_16K		(4L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_32K		(5L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_64K		(6L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_128K		(7L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_256K		(8L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_512K		(9L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_1M		(10L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_2M		(11L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_4M		(12L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_8M		(13L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_16M		(14L<<8)
+#define	PCI_CONFIG_2_EXP_ROM_SIZE_32M		(15L<<8)
+#define	PCI_CONFIG_2_BAR_PREFETCH		(1L<<16)
+#define	PCI_CONFIG_2_RESERVED0			(0x7fffL<<17)
+
+/* config_3 offset */
+#define	GRC_CONFIG_3_SIZE_REG			0x40c
+#define	PCI_CONFIG_3_STICKY_BYTE		(0xffL<<0)
+#define	PCI_CONFIG_3_FORCE_PME			(1L<<24)
+#define	PCI_CONFIG_3_PME_STATUS			(1L<<25)
+#define	PCI_CONFIG_3_PME_ENABLE			(1L<<26)
+#define	PCI_CONFIG_3_PM_STATE			(0x3L<<27)
+#define	PCI_CONFIG_3_VAUX_PRESET		(1L<<30)
+#define	PCI_CONFIG_3_PCI_POWER			(1L<<31)
+
+#define	GRC_BAR2_CONFIG				0x4e0
+#define	PCI_CONFIG_2_BAR2_SIZE			(0xfL<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_DISABLED		(0L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_64K		(1L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_128K		(2L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_256K		(3L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_512K		(4L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_1M		(5L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_2M		(6L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_4M		(7L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_8M		(8L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_16M		(9L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_32M		(10L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_64M		(11L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_128M		(12L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_256M		(13L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_512M		(14L<<0)
+#define	PCI_CONFIG_2_BAR2_SIZE_1G		(15L<<0)
+#define	PCI_CONFIG_2_BAR2_64ENA			(1L<<4)
+
+#define	PCI_PM_DATA_A					0x410
+#define	PCI_PM_DATA_B					0x414
+#define	PCI_ID_VAL1					0x434
+#define	PCI_ID_VAL2					0x438
+
+#define	MDIO_REG_BANK_CL73_IEEEB0			0x0
+#define	MDIO_CL73_IEEEB0_CL73_AN_CONTROL		0x0
+#define	MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN	0x0200
+#define	MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN		0x1000
+#define	MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST	0x8000
+
+#define	MDIO_REG_BANK_CL73_IEEEB1			0x10
+#define	MDIO_CL73_IEEEB1_AN_ADV1			0x00
+#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE			0x0400
+#define	MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC		0x0800
+#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH		0x0C00
+#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK		0x0C00
+#define	MDIO_CL73_IEEEB1_AN_ADV2			0x01
+#define	MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M		0x0000
+#define	MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX		0x0020
+#define	MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4		0x0040
+#define	MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR		0x0080
+#define	MDIO_CL73_IEEEB1_AN_LP_ADV1			0x03
+#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE		0x0400
+#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC		0x0800
+#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH		0x0C00
+#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK		0x0C00
+
+#define	MDIO_REG_BANK_RX0				0x80b0
+#define	MDIO_RX0_RX_STATUS				0x10
+#define	MDIO_RX0_RX_STATUS_SIGDET			0x8000
+#define	MDIO_RX0_RX_STATUS_RX_SEQ_DONE			0x1000
+#define	MDIO_RX0_RX_EQ_BOOST				0x1c
+#define	MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define	MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define	MDIO_REG_BANK_RX1				0x80c0
+#define	MDIO_RX1_RX_EQ_BOOST				0x1c
+#define	MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define	MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define	MDIO_REG_BANK_RX2				0x80d0
+#define	MDIO_RX2_RX_EQ_BOOST				0x1c
+#define	MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define	MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define	MDIO_REG_BANK_RX3				0x80e0
+#define	MDIO_RX3_RX_EQ_BOOST				0x1c
+#define	MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define	MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define	MDIO_REG_BANK_RX_ALL				0x80f0
+#define	MDIO_RX_ALL_RX_EQ_BOOST				0x1c
+#define	MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define	MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define	MDIO_REG_BANK_TX0				0x8060
+#define	MDIO_TX0_TX_DRIVER				0x17
+#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define	MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
+#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define	MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
+#define	MDIO_TX0_TX_DRIVER_ICBUF1T			1
+
+#define	MDIO_REG_BANK_TX1				0x8070
+#define	MDIO_TX1_TX_DRIVER				0x17
+#define	MDIO_TX1_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define	MDIO_TX1_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define	MDIO_TX1_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define	MDIO_TX1_TX_DRIVER_IDRIVER_SHIFT		8
+#define	MDIO_TX1_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define	MDIO_TX1_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define	MDIO_TX1_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define	MDIO_TX1_TX_DRIVER_IFULLSPD_SHIFT		1
+#define	MDIO_TX1_TX_DRIVER_ICBUF1T			1
+
+#define	MDIO_REG_BANK_TX2				0x8080
+#define	MDIO_TX2_TX_DRIVER				0x17
+#define	MDIO_TX2_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define	MDIO_TX2_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define	MDIO_TX2_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define	MDIO_TX2_TX_DRIVER_IDRIVER_SHIFT		8
+#define	MDIO_TX2_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define	MDIO_TX2_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define	MDIO_TX2_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define	MDIO_TX2_TX_DRIVER_IFULLSPD_SHIFT		1
+#define	MDIO_TX2_TX_DRIVER_ICBUF1T			1
+
+#define	MDIO_REG_BANK_TX3				0x8090
+#define	MDIO_TX3_TX_DRIVER				0x17
+#define	MDIO_TX3_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define	MDIO_TX3_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define	MDIO_TX3_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define	MDIO_TX3_TX_DRIVER_IDRIVER_SHIFT		8
+#define	MDIO_TX3_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define	MDIO_TX3_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define	MDIO_TX3_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define	MDIO_TX3_TX_DRIVER_IFULLSPD_SHIFT		1
+#define	MDIO_TX3_TX_DRIVER_ICBUF1T			1
+
+#define	MDIO_REG_BANK_XGXS_BLOCK0			0x8000
+#define	MDIO_BLOCK0_XGXS_CONTROL			0x10
+
+#define	MDIO_REG_BANK_XGXS_BLOCK1			0x8010
+#define	MDIO_BLOCK1_LANE_CTRL0				0x15
+#define	MDIO_BLOCK1_LANE_CTRL1				0x16
+#define	MDIO_BLOCK1_LANE_CTRL2				0x17
+#define	MDIO_BLOCK1_LANE_PRBS				0x19
+
+#define	MDIO_REG_BANK_XGXS_BLOCK2			0x8100
+#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP			0x10
+#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE		0x8000
+#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE	0x4000
+#define	MDIO_XGXS_BLOCK2_TX_LN_SWAP			0x11
+#define	MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE		0x8000
+#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G		0x14
+#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS	0x0001
+#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS	0x0010
+#define	MDIO_XGXS_BLOCK2_TEST_MODE_LANE			0x15
+
+#define	MDIO_REG_BANK_GP_STATUS				0x8120
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1			0x1B
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE	0x0001
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE	0x0002
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS		0x0004
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS		0x0008
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE	0x0010
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE	0x0020
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE	0x0040
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE	0x0080
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK		0x3f00
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M		0x0000
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M		0x0100
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G		0x0200
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G		0x0300
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G		0x0400
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G		0x0500
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG	0x0600
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4	0x0700
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG	0x0800
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G	0x0900
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G		0x0A00
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G		0x0B00
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G		0x0C00
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX	0x0D00
+#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4	0x0E00
+
+#define	MDIO_REG_BANK_10G_PARALLEL_DETECT		0x8130
+#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS		0x10
+#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK	0x8000
+#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL		0x11
+#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN	0x1
+#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK		0x13
+#define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT		(0xb71<<1)
+
+#define	MDIO_REG_BANK_SERDES_DIGITAL			0x8300
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1			0x10
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE		0x0001
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF		0x0002
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN	0x0004
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT	0x0008
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET		0x0010
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE		0x0020
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2			0x11
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN		0x0001
+#define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR		0x0040
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1			0x14
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX		0x0004
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK		0x0018
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT		3
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G		0x0018
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G		0x0010
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M		0x0008
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M		0x0000
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS2			0x15
+#define	MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED		0x0002
+#define	MDIO_SERDES_DIGITAL_MISC1				0x18
+#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK		0xE000
+#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M		0x0000
+#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M		0x2000
+#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M		0x4000
+#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M		0x6000
+#define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M		0x8000
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL		0x0010
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK		0x000f
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G		0x0000
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G		0x0001
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G		0x0002
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG		0x0003
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4		0x0004
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G		0x0005
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G		0x0006
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G		0x0007
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G		0x0008
+#define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G		0x0009
+
+#define	MDIO_REG_BANK_OVER_1G				0x8320
+#define	MDIO_OVER_1G_DIGCTL_3_4						0x14
+#define	MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK				0xffe0
+#define	MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT				5
+#define	MDIO_OVER_1G_UP1						0x19
+#define	MDIO_OVER_1G_UP1_2_5G						0x0001
+#define	MDIO_OVER_1G_UP1_5G						0x0002
+#define	MDIO_OVER_1G_UP1_6G						0x0004
+#define	MDIO_OVER_1G_UP1_10G						0x0010
+#define	MDIO_OVER_1G_UP1_10GH						0x0008
+#define	MDIO_OVER_1G_UP1_12G						0x0020
+#define	MDIO_OVER_1G_UP1_12_5G						0x0040
+#define	MDIO_OVER_1G_UP1_13G						0x0080
+#define	MDIO_OVER_1G_UP1_15G						0x0100
+#define	MDIO_OVER_1G_UP1_16G						0x0200
+#define	MDIO_OVER_1G_UP2						0x1A
+#define	MDIO_OVER_1G_UP2_IPREDRIVER_MASK				0x0007
+#define	MDIO_OVER_1G_UP2_IDRIVER_MASK					0x0038
+#define	MDIO_OVER_1G_UP2_PREEMPHASIS_MASK				0x03C0
+#define	MDIO_OVER_1G_UP3						0x1B
+#define	MDIO_OVER_1G_UP3_HIGIG2						0x0001
+#define	MDIO_OVER_1G_LP_UP1						0x1C
+#define	MDIO_OVER_1G_LP_UP2						0x1D
+#define	MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK				0x03ff
+#define	MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK				0x0780
+#define	MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT				7
+#define	MDIO_OVER_1G_LP_UP3						0x1E
+
+#define	MDIO_REG_BANK_REMOTE_PHY			0x8330
+#define	MDIO_REMOTE_PHY_MISC_RX_STATUS					0x10
+#define	MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG	0x0010
+#define	MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG	0x0600
+
+#define	MDIO_REG_BANK_BAM_NEXT_PAGE			0x8350
+#define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL				0x10
+#define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE			0x0001
+#define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN			0x0002
+
+#define	MDIO_REG_BANK_CL73_USERB0			0x8370
+#define	MDIO_CL73_USERB0_CL73_UCTRL					0x10
+#define	MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL			0x0002
+#define	MDIO_CL73_USERB0_CL73_USTAT1					0x11
+#define	MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK			0x0100
+#define	MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37		0x0400
+#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1					0x12
+#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN				0x8000
+#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN		0x4000
+#define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN		0x2000
+#define	MDIO_CL73_USERB0_CL73_BAM_CTRL3					0x14
+#define	MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR			0x0001
+
+#define	MDIO_REG_BANK_AER_BLOCK				0xFFD0
+#define	MDIO_AER_BLOCK_AER_REG				0x1E
+
+#define	MDIO_REG_BANK_COMBO_IEEE0			0xFFE0
+#define	MDIO_COMBO_IEEE0_MII_CONTROL			0x10
+#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK			0x2040
+#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10			0x0000
+#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100			0x2000
+#define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000			0x0040
+#define	MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX				0x0100
+#define	MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN				0x0200
+#define	MDIO_COMBO_IEEO_MII_CONTROL_AN_EN				0x1000
+#define	MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK				0x4000
+#define	MDIO_COMBO_IEEO_MII_CONTROL_RESET				0x8000
+#define	MDIO_COMBO_IEEE0_MII_STATUS					0x11
+#define	MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS				0x0004
+#define	MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE			0x0020
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV					0x14
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX			0x0020
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX			0x0040
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK			0x0180
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE			0x0000
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC			0x0080
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC			0x0100
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH			0x0180
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE				0x8000
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1			0x15
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE	0x8000
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK		0x4000
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK	0x0180
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE	0x0000
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH	0x0180
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP	0x0040
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP	0x0020
+/*
+ * WhenthelinkpartnerisinSGMIImode(bit0=1),the
+ * bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
+ * Theotherbitsarereservedandshouldbezero
+ */
+#define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE	0x0001
+
+#define	MDIO_PMA_DEVAD			0x1
+/*ieee*/
+#define	MDIO_PMA_REG_CTRL		0x0
+#define	MDIO_PMA_REG_STATUS		0x1
+#define	MDIO_PMA_REG_10G_CTRL2		0x7
+#define	MDIO_PMA_REG_RX_SD		0xa
+/*bcm*/
+#define	MDIO_PMA_REG_BCM_CTRL		0x0096
+#define	MDIO_PMA_REG_FEC_CTRL		0x00ab
+#define	MDIO_PMA_REG_RX_ALARM_CTRL	0x9000
+#define	MDIO_PMA_REG_LASI_CTRL		0x9002
+#define	MDIO_PMA_REG_RX_ALARM		0x9003
+#define	MDIO_PMA_REG_TX_ALARM		0x9004
+#define	MDIO_PMA_REG_LASI_STATUS	0x9005
+#define	MDIO_PMA_REG_PHY_IDENTIFIER	0xc800
+#define	MDIO_PMA_REG_DIGITAL_CTRL	0xc808
+#define	MDIO_PMA_REG_DIGITAL_STATUS	0xc809
+#define	MDIO_PMA_REG_TX_POWER_DOWN	0xca02
+#define	MDIO_PMA_REG_CMU_PLL_BYPASS	0xca09
+#define	MDIO_PMA_REG_MISC_CTRL		0xca0a
+#define	MDIO_PMA_REG_GEN_CTRL		0xca10
+#define	MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP	0x0188
+#define	MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET		0x018a
+#define	MDIO_PMA_REG_M8051_MSGIN_REG	0xca12
+#define	MDIO_PMA_REG_M8051_MSGOUT_REG	0xca13
+#define	MDIO_PMA_REG_ROM_VER1		0xca19
+#define	MDIO_PMA_REG_ROM_VER2		0xca1a
+#define	MDIO_PMA_REG_EDC_FFE_MAIN	0xca1b
+#define	MDIO_PMA_REG_PLL_BANDWIDTH	0xca1d
+#define	MDIO_PMA_REG_PLL_CTRL		0xca1e
+#define	MDIO_PMA_REG_MISC_CTRL0		0xca23
+#define	MDIO_PMA_REG_LRM_MODE		0xca3f
+#define	MDIO_PMA_REG_CDR_BANDWIDTH	0xca46
+#define	MDIO_PMA_REG_MISC_CTRL1		0xca85
+
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_CTRL		0x8000
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK	0x000c
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE		0x0000
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE	0x0004
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS	0x0008
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED		0x000c
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT	0x8002
+#define	MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR	0x8003
+#define	MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF	0xc820
+#define	MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK	0xff
+#define	MDIO_PMA_REG_8726_TX_CTRL1		0xca01
+#define	MDIO_PMA_REG_8726_TX_CTRL2		0xca05
+
+#define	MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR	0x8005
+#define	MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF	0x8007
+#define	MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK	0xff
+#define	MDIO_PMA_REG_8727_MISC_CTRL		0x8309
+#define	MDIO_PMA_REG_8727_TX_CTRL1		0xca02
+#define	MDIO_PMA_REG_8727_TX_CTRL2		0xca05
+#define	MDIO_PMA_REG_8727_PCS_OPT_CTRL		0xc808
+#define	MDIO_PMA_REG_8727_GPIO_CTRL		0xc80e
+
+#define	MDIO_PMA_REG_8073_CHIP_REV			0xc801
+#define	MDIO_PMA_REG_8073_SPEED_LINK_STATUS		0xc820
+#define	MDIO_PMA_REG_8073_XAUI_WA			0xc841
+
+#define	MDIO_PMA_REG_7101_RESET		0xc000
+#define	MDIO_PMA_REG_7107_LED_CNTL	0xc007
+#define	MDIO_PMA_REG_7101_VER1		0xc026
+#define	MDIO_PMA_REG_7101_VER2		0xc027
+
+#define	MDIO_PMA_REG_8481_PMD_SIGNAL	0xa811
+#define	MDIO_PMA_REG_8481_LED1_MASK	0xa82c
+#define	MDIO_PMA_REG_8481_LED2_MASK	0xa82f
+#define	MDIO_PMA_REG_8481_LED3_MASK	0xa832
+#define	MDIO_PMA_REG_8481_LED3_BLINK	0xa834
+#define	MDIO_PMA_REG_8481_SIGNAL_MASK	0xa835
+#define	MDIO_PMA_REG_8481_LINK_SIGNAL	0xa83b
+
+#define	MDIO_WIS_DEVAD			0x2
+/*bcm*/
+#define	MDIO_WIS_REG_LASI_CNTL		0x9002
+#define	MDIO_WIS_REG_LASI_STATUS	0x9005
+
+#define	MDIO_PCS_DEVAD			0x3
+#define	MDIO_PCS_REG_STATUS		0x0020
+#define	MDIO_PCS_REG_LASI_STATUS	0x9005
+#define	MDIO_PCS_REG_7101_DSP_ACCESS	0xD000
+#define	MDIO_PCS_REG_7101_SPI_MUX	0xD008
+#define	MDIO_PCS_REG_7101_SPI_CTRL_ADDR	0xE12A
+#define	MDIO_PCS_REG_7101_SPI_RESET_BIT	(5)
+#define	MDIO_PCS_REG_7101_SPI_FIFO_ADDR	0xE02A
+#define	MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD	(6)
+#define	MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD		(0xC7)
+#define	MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD	(2)
+#define	MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR		0xE028
+
+#define	MDIO_XS_DEVAD			0x4
+#define	MDIO_XS_PLL_SEQUENCER		0x8000
+#define	MDIO_XS_SFX7101_XGXS_TEST1	0xc00a
+
+#define	MDIO_XS_8706_REG_BANK_RX0	0x80bc
+#define	MDIO_XS_8706_REG_BANK_RX1	0x80cc
+#define	MDIO_XS_8706_REG_BANK_RX2	0x80dc
+#define	MDIO_XS_8706_REG_BANK_RX3	0x80ec
+#define	MDIO_XS_8706_REG_BANK_RXA	0x80fc
+
+#define	MDIO_AN_DEVAD			0x7
+/*ieee*/
+#define	MDIO_AN_REG_CTRL		0x0000
+#define	MDIO_AN_REG_STATUS		0x0001
+#define	MDIO_AN_REG_STATUS_AN_COMPLETE	0x0020
+#define	MDIO_AN_REG_ADV_PAUSE		0x0010
+#define	MDIO_AN_REG_ADV_PAUSE_PAUSE	0x0400
+#define	MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC	0x0800
+#define	MDIO_AN_REG_ADV_PAUSE_BOTH	0x0C00
+#define	MDIO_AN_REG_ADV_PAUSE_MASK	0x0C00
+#define	MDIO_AN_REG_ADV			0x0011
+#define	MDIO_AN_REG_ADV2		0x0012
+#define	MDIO_AN_REG_LP_AUTO_NEG		0x0013
+#define	MDIO_AN_REG_MASTER_STATUS	0x0021
+/*bcm*/
+#define	MDIO_AN_REG_LINK_STATUS		0x8304
+#define	MDIO_AN_REG_CL37_CL73		0x8370
+#define	MDIO_AN_REG_CL37_AN		0xffe0
+#define	MDIO_AN_REG_CL37_FC_LD		0xffe4
+#define	MDIO_AN_REG_CL37_FC_LP		0xffe5
+
+#define	MDIO_AN_REG_8073_2_5G		0x8329
+
+#define	MDIO_AN_REG_8481_LEGACY_MII_CTRL	0xffe0
+#define	MDIO_AN_REG_8481_LEGACY_MII_STATUS	0xffe1
+#define	MDIO_AN_REG_8481_LEGACY_AN_ADV		0xffe4
+#define	MDIO_AN_REG_8481_LEGACY_AN_EXPANSION	0xffe6
+#define	MDIO_AN_REG_8481_1000T_CTRL		0xffe9
+#define	MDIO_AN_REG_8481_EXPANSION_REG_RD_RW	0xfff5
+#define	MDIO_AN_REG_8481_EXPANSION_REG_ACCESS	0xfff7
+#define	MDIO_AN_REG_8481_LEGACY_SHADOW		0xfffc
+
+#define	IGU_FUNC_BASE			0x0400
+
+#define	IGU_ADDR_MSIX			0x0000
+#define	IGU_ADDR_INT_ACK		0x0200
+#define	IGU_ADDR_PROD_UPD		0x0201
+#define	IGU_ADDR_ATTN_BITS_UPD		0x0202
+#define	IGU_ADDR_ATTN_BITS_SET		0x0203
+#define	IGU_ADDR_ATTN_BITS_CLR		0x0204
+#define	IGU_ADDR_COALESCE_NOW		0x0205
+#define	IGU_ADDR_SIMD_MASK		0x0206
+#define	IGU_ADDR_SIMD_NOMASK		0x0207
+#define	IGU_ADDR_MSI_CTL		0x0210
+#define	IGU_ADDR_MSI_ADDR_LO		0x0211
+#define	IGU_ADDR_MSI_ADDR_HI		0x0212
+#define	IGU_ADDR_MSI_DATA		0x0213
+
+#define	IGU_INT_ENABLE			0
+#define	IGU_INT_DISABLE			1
+#define	IGU_INT_NOP			2
+#define	IGU_INT_NOP2			3
+
+#define	COMMAND_REG_INT_ACK		0x0
+#define	COMMAND_REG_PROD_UPD		0x4
+#define	COMMAND_REG_ATTN_BITS_UPD	0x8
+#define	COMMAND_REG_ATTN_BITS_SET	0xc
+#define	COMMAND_REG_ATTN_BITS_CLR	0x10
+#define	COMMAND_REG_COALESCE_NOW	0x14
+#define	COMMAND_REG_SIMD_MASK		0x18
+#define	COMMAND_REG_SIMD_NOMASK		0x1c
+
+#define	IGU_MEM_BASE				0x0000
+
+#define	IGU_MEM_MSIX_BASE			0x0000
+#define	IGU_MEM_MSIX_UPPER			0x007f
+#define	IGU_MEM_MSIX_RESERVED_UPPER		0x01ff
+
+#define	IGU_MEM_PBA_MSIX_BASE			0x0200
+#define	IGU_MEM_PBA_MSIX_UPPER			0x0200
+
+#define	IGU_CMD_BACKWARD_COMP_PROD_UPD		0x0201
+#define	IGU_MEM_PBA_MSIX_RESERVED_UPPER		0x03ff
+
+#define	IGU_CMD_INT_ACK_BASE			0x0400
+#define	IGU_CMD_INT_ACK_UPPER						\
+	(IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
+#define	IGU_CMD_INT_ACK_RESERVED_UPPER		0x04ff
+
+#define	IGU_CMD_E2_PROD_UPD_BASE		0x0500
+#define	IGU_CMD_E2_PROD_UPD_UPPER					\
+	(IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
+#define	IGU_CMD_E2_PROD_UPD_RESERVED_UPPER	0x059f
+
+#define	IGU_CMD_ATTN_BIT_UPD_UPPER		0x05a0
+#define	IGU_CMD_ATTN_BIT_SET_UPPER		0x05a1
+#define	IGU_CMD_ATTN_BIT_CLR_UPPER		0x05a2
+
+#define	IGU_REG_SISR_MDPC_WMASK_UPPER		0x05a3
+#define	IGU_REG_SISR_MDPC_WMASK_LSB_UPPER	0x05a4
+#define	IGU_REG_SISR_MDPC_WMASK_MSB_UPPER	0x05a5
+#define	IGU_REG_SISR_MDPC_WOMASK_UPPER		0x05a6
+
+#define	IGU_REG_RESERVED_UPPER			0x05ff
+
+#define	CDU_REGION_NUMBER_XCM_AG	2
+#define	CDU_REGION_NUMBER_UCM_AG	4
+
+/*
+ *
+ * String-to-compress [31:8] = CID (all 24 bits)
+ * String-to-compress [7:4] = Region
+ * String-to-compress [3:0] = Type
+ */
+#define	CDU_VALID_DATA(_cid,_region, _type)				\
+	(((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
+#define	CDU_CRC8(_cid, _region, _type)					\
+	(calc_crc8(CDU_VALID_DATA(_cid,	_region, _type), 0xff))
+#define	CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)			\
+	(0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
+#define	CDU_RSRVD_VALUE_TYPE_B(_crc, _type)				\
+	(0x80 | ((_type) & 0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
+#define	CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val)	(((_val) & ~0x80)
+
+/*
+ *****************************************************************************
+ * Description:
+ *	   Calculates crc 8 on a word value: polynomial 0-1-2-8
+ *	   Code was translated from Verilog.
+ * Return:
+*****************************************************************************/
+static __inline uint8_t
+calc_crc8(uint32_t data, uint8_t crc)
+{
+	uint8_t	D[32];
+	uint8_t	NewCRC[8];
+	uint8_t	C[8];
+	uint8_t	crc_res;
+	uint8_t	i;
+
+	/* split the data into 31 bits */
+	for (i = 0; i < 32; i++) {
+		D[i] = (uint8_t)(data & 1);
+		data = data >> 1;
+	}
+
+	/* split the crc into 8 bits */
+	for	(i = 0; i < 8; i++) {
+		C[i] = crc & 1;
+		crc = crc >> 1;
+	}
+
+	NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
+	    D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
+	    C[6] ^ C[7];
+	NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
+		D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
+		D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
+		C[6];
+	NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
+		D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
+		C[0] ^ C[1] ^ C[4] ^ C[5];
+	NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
+		D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
+		C[1] ^ C[2] ^ C[5] ^ C[6];
+	NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
+		D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
+		C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
+	NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
+		D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
+		C[3] ^ C[4] ^ C[7];
+	NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
+		D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
+		C[5];
+	NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
+		D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
+		C[6];
+
+	crc_res	= 0;
+	for (i = 0; i < 8; i++)
+		crc_res	|= (NewCRC[i] << i);
+
+	return	(crc_res);
+}
+#endif /* _BXE_REG_H */
+
diff --git a/sys/dev/bxe/bxe_self_test.h b/sys/dev/bxe/bxe_self_test.h
new file mode 100755
index 0000000..4289a85
--- /dev/null
+++ b/sys/dev/bxe/bxe_self_test.h
@@ -0,0 +1,1049 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef _BXE_SELF_TEST_H
+#define	_BXE_SELF_TEST_H
+
+static int idle_chk_errors;
+static int idle_chk_warnings;
+
+#ifdef BXE_DEBUG
+extern uint32_t
+bxe_reg_read32	(struct bxe_softc *, bus_size_t);
+extern void
+bxe_reg_write32	(struct bxe_softc *, bus_size_t, uint32_t);
+#endif
+
+#define	IDLE_CHK_E1			0x1
+#define	IDLE_CHK_E1H			0x2
+
+#define	IDLE_CHK_ERROR			1
+#define	IDLE_CHK_ERROR_NO_TRAFFIC	2
+#define	IDLE_CHK_WARNING		3
+
+#define	CHIP_MASK_CHK(chip_mask)					\
+	(((((chip_mask) & IDLE_CHK_E1) && is_e1) ||			\
+	(((chip_mask) & IDLE_CHK_E1H) && is_e1h)) ? 1 : 0)
+
+#define	CONDITION_CHK(condition, severity, fail_msg, arg_list...) do {	\
+	if (condition) {						\
+		switch (severity) {					\
+		case IDLE_CHK_ERROR:					\
+			BXE_PRINTF("ERROR " fail_msg, ##arg_list);	\
+			idle_chk_errors++;				\
+			break;						\
+		case IDLE_CHK_ERROR_NO_TRAFFIC:				\
+			BXE_PRINTF("WARNING " fail_msg, ##arg_list);	\
+			break;						\
+		case IDLE_CHK_WARNING:					\
+			BXE_PRINTF("INFO " fail_msg, ##arg_list);	\
+			idle_chk_warnings++;				\
+			break;						\
+		}							\
+	}								\
+} while (0)
+
+/* Read one reg and check the condition. */
+#define	IDLE_CHK_1(chip_mask, offset, condition, severity, fail_msg) do { \
+	if (CHIP_MASK_CHK(chip_mask)) {					\
+		val = REG_RD(sc, offset);				\
+		CONDITION_CHK(condition, severity,			\
+		    fail_msg ". Value is 0x%x\n", val);			\
+	}								\
+} while (0)
+
+/* Loop to read one reg and check the condition. */
+#define	IDLE_CHK_2(chip_mask, offset, loop, inc, condition, severity,	\
+	fail_msg) do {							\
+	if (CHIP_MASK_CHK(chip_mask))					\
+		for (int i = 0; i < (loop); i++) {			\
+			val = REG_RD(sc, offset + i * (inc));		\
+			CONDITION_CHK(condition, severity,		\
+			    fail_msg ". Value is 0x%x\n", i, val);	\
+		}							\
+} while (0)
+
+/* Read two regs and check the condition. */
+#define	IDLE_CHK_3(chip_mask, offset1, offset2, condition, severity, 	\
+	fail_msg) do {							\
+	if (CHIP_MASK_CHK(chip_mask)) {					\
+		val1 = REG_RD(sc, offset1);				\
+		val2 = REG_RD(sc, offset2);				\
+		CONDITION_CHK(condition, severity, fail_msg		\
+		    ". Values are 0x%x 0x%x\n", val1, val2);		\
+	}								\
+} while (0)
+
+/* Loop to read two regs and check the condition. */
+#define	IDLE_CHK_4(chip_mask, offset1, offset2, loop, inc, condition,	\
+	severity, fail_msg) do {					\
+	if (CHIP_MASK_CHK(chip_mask))					\
+		for (int i = 0; i < (loop); i++) { 			\
+			val1 = REG_RD(sc, offset1 + i * (inc));		\
+			val2 = (REG_RD(sc, offset2 + i * (inc)) >> 1);	\
+			CONDITION_CHK(condition, severity, fail_msg	\
+			" - LCID %d CID_CAM 0x%x Value is 0x%x\n",	\
+			i, val2, val1);					\
+		} 							\
+} while (0);
+
+/* Read one reg and check according to another reg. */
+#define	IDLE_CHK_5(chip_mask,offset,offset1,offset2,condition,severity,	\
+	fail_msg) do {							\
+	if (CHIP_MASK_CHK(chip_mask))					\
+		if (!REG_RD(sc, offset))				\
+			IDLE_CHK_3(chip_mask, offset1, offset2,		\
+			    condition, severity, fail_msg);		\
+} while (0);
+
+/* Read wide-bus reg and check sub-fields. */
+#define	IDLE_CHK_6(chip_mask, offset, loop, inc, severity)		\
+	bxe_idle_chk6(sc, chip_mask, offset, loop, inc, severity)
+
+/*
+ * Idle check 6.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_idle_chk6(struct bxe_softc *sc, uint32_t chip_mask, uint32_t offset,
+    int loop, int inc, int severity)
+{
+	uint32_t val1, val2;
+	uint32_t rd_ptr, wr_ptr, rd_bank, wr_bank;
+	int i, is_e1, is_e1h;
+
+	is_e1 = CHIP_IS_E1(sc);
+	is_e1h = CHIP_IS_E1H(sc);
+
+	if (!CHIP_MASK_CHK(chip_mask))
+		return;
+
+	for (i = 0; i < loop; i++) {
+		val1 = REG_RD(sc, offset + i*inc);
+		val2 = REG_RD(sc, offset + i*inc + 4);
+		rd_ptr = ((val1 & 0x3FFFFFC0) >> 6);
+		wr_ptr = ((((val1 & 0xC0000000) >> 30) & 0x3) |
+		    ((val2 & 0x3FFFFF) << 2));
+		CONDITION_CHK((rd_ptr != wr_ptr), severity,
+		    "QM: PTRTBL entry %d - rd_ptr is not"
+		    " equal to wr_ptr. Values are 0x%x 0x%x\n",
+		    i, rd_ptr, wr_ptr);
+		rd_bank = ((val1 & 0x30) >> 4);
+		wr_bank = (val1 & 0x03);
+		CONDITION_CHK((rd_bank != wr_bank), severity,
+		    "QM: PTRTBL entry %d - rd_bank is not"
+		    " equal to wr_bank. Values are 0x%x 0x%x\n",
+		    i, rd_bank, wr_bank);
+	}
+}
+
+/* Loop to read wide-bus reg and check according to another reg. */
+#define	IDLE_CHK_7(chip_mask, offset, offset1, offset2, loop, inc,	\
+	condition, severity, fail_msg) do {				\
+	if (CHIP_MASK_CHK(chip_mask))					\
+		for (int i = 0; i < (loop); i++) {			\
+			if (REG_RD(sc, offset + i * 4) == 1) {		\
+				val1 = REG_RD(sc, offset1 + i * (inc));	\
+				val1 = REG_RD(sc, offset1 + i * (inc) +	4); \
+				val1 = ((REG_RD(sc, offset1 + i * (inc)	+ 8) & \
+				    0x00000078) >> 3);			\
+				val2 = (REG_RD(sc, offset2 + i * 4) >> 1); \
+				CONDITION_CHK(condition, severity,	\
+				    fail_msg " - LCID %d CID_CAM 0x%x "	\
+				    "Value is 0x%x\n", i, val2, val1);	\
+			}						\
+		}							\
+} while (0);
+
+/*
+ * Idle check.
+ *
+ * Performs a series of register reads and compares the returned values to
+ * expected values, looking for obvious errors.  The comparisons used here
+ * (IDLE_CHK_*) are machine generated and should not be modifed.
+ *
+ * Returns:
+ *   The number of errors encountered.
+ */
+static int
+bxe_idle_chk(struct bxe_softc *sc)
+{
+	struct ifnet *ifp;
+	uint32_t val, val1, val2;
+	int is_e1, is_e1h;
+
+	idle_chk_errors = 0;
+	idle_chk_warnings = 0;
+	ifp = sc->bxe_ifp;
+	is_e1 = CHIP_IS_E1(sc);
+	is_e1h = CHIP_IS_E1H(sc);
+
+	/* Don't run this code if the inteface hasn't been initialized. */
+	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+		goto bxe_idle_chk_exit;
+
+	BXE_PRINTF(
+	    "------------------------------"
+	    " Idle Check "
+	    "------------------------------\n");
+
+	/* ToDo: Don't run this code is driver is NOT running. */
+
+	/* Perform the idle checks. */
+	IDLE_CHK_1(0x3, 0x2114, ((val & 0x0ff010) != 0), IDLE_CHK_ERROR,
+	    "PCIE: ucorr_err_status is not 0");
+	IDLE_CHK_1(0x3, 0x2114, ((val & 0x100000) != 0), IDLE_CHK_WARNING,
+	    "PCIE: ucorr_err_status - Unsupported request error");
+	IDLE_CHK_1(0x3, 0x2120,
+	    (((val & 0x31c1) != 0x2000) && ((val & 0x31c1) != 0)),
+	    IDLE_CHK_WARNING, "PCIE: corr_err_status is not 0x2000");
+	IDLE_CHK_1(0x3, 0x2814, ((val & ~0x40100) != 0), IDLE_CHK_ERROR,
+	    "PCIE: attentions register is not 0x40100");
+	IDLE_CHK_1(0x2, 0x281c, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR,
+	    "PCIE: attentions register is not 0x40040100");
+	IDLE_CHK_1(0x2, 0x2820, ((val & ~0x40040100) != 0), IDLE_CHK_ERROR,
+	    "PCIE: attentions register is not 0x40040100");
+	IDLE_CHK_1(0x1, PXP2_REG_PGL_EXP_ROM2, (val != 0xffffffff),
+	    IDLE_CHK_WARNING,
+	    "PXP2: There are outstanding read requests. Not all"
+	    " completions have arrived for read requests on tags that"
+	    " are marked with 0");
+	IDLE_CHK_2(0x3, 0x212c, 4, 4, ((val != 0) && (idle_chk_errors > 0)),
+	    IDLE_CHK_WARNING, "PCIE: error packet header %d is not 0");
+
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ0_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ0 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ1_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ1 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ2_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ2 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ3_ENTRY_CNT, (val > 2),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ3 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ4_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ4 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ5_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ5 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ6_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ6 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ7_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ7 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ8_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ8 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ9_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ9 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ10_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ10 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ11_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ11 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ12_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ12 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ13_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ13 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ14_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ14 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ15_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ15 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ16_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ16 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ17_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ17 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ18_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ18 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ19_ENTRY_CNT, (val != 0),
+	    IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ19 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ20_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ20 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ21_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ21 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ22_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ22 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ23_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ23 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ24_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ24 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ25_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ25 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ26_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ26 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ27_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ27 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ28_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ28 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ29_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ29 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ30_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ30 is not empty");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_VQ31_ENTRY_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ31 is not empty");
+
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY, (val != 0),
+	   IDLE_CHK_ERROR, "PXP2: rq_ufifo_num_of_entry is not 0");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_RBC_DONE, (val != 1), IDLE_CHK_ERROR,
+	   "PXP2: rq_rbc_done is not 1");
+	IDLE_CHK_1(0x3, PXP2_REG_RQ_CFG_DONE, (val != 1), IDLE_CHK_ERROR,
+	   "PXP2: rq_cfg_done is not 1");
+	IDLE_CHK_1(0x3, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x1b),
+	   IDLE_CHK_ERROR,
+	   "PXP2: rq_read_credit and rq_write_credit are not 3");
+	IDLE_CHK_1(0x3, PXP2_REG_RD_START_INIT, (val != 1), IDLE_CHK_ERROR,
+	   "PXP2: rd_start_init is not 1");
+	IDLE_CHK_1(0x3, PXP2_REG_RD_INIT_DONE, (val != 1), IDLE_CHK_ERROR,
+	   "PXP2: rd_init_done is not 1");
+
+	IDLE_CHK_3(0x3, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG,
+	   (val1 != (val2-1)), IDLE_CHK_WARNING,
+	   "PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg");
+	IDLE_CHK_3(0x3, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG,
+	   (val1 != val2), IDLE_CHK_WARNING,
+	   "PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg");
+
+	IDLE_CHK_3(0x3, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG,
+	   (val1 < (val2-3)), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PXP2: There are more than two unused SRs");
+	IDLE_CHK_3(0x3, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG,
+	   (val1 < (val2-2)), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PXP2: There are more than two unused blocks");
+
+	IDLE_CHK_1(0x3, PXP2_REG_RD_PORT_IS_IDLE_0, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PXP2: P0 All delivery ports are not idle");
+	IDLE_CHK_1(0x3, PXP2_REG_RD_PORT_IS_IDLE_1, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PXP2: P1 All delivery ports are not idle");
+
+	IDLE_CHK_2(0x3, PXP2_REG_RD_ALMOST_FULL_0, 11, 4, (val != 0),
+	   IDLE_CHK_ERROR, "PXP2: rd_almost_full_%d is not 0");
+
+	IDLE_CHK_1(0x3, PXP2_REG_RD_DISABLE_INPUTS, (val != 0),
+	   IDLE_CHK_ERROR, "PXP2: PSWRD inputs are disabled");
+	IDLE_CHK_1(0x3, PXP2_REG_HST_HEADER_FIFO_STATUS, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PXP2: HST header FIFO status is not 0");
+	IDLE_CHK_1(0x3, PXP2_REG_HST_DATA_FIFO_STATUS, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PXP2: HST data FIFO status is not 0");
+	IDLE_CHK_1(0x3, PXP2_REG_PGL_WRITE_BLOCKED, (val != 0),
+	   IDLE_CHK_ERROR, "PXP2: pgl_write_blocked is not 0");
+	IDLE_CHK_1(0x3, PXP2_REG_PGL_READ_BLOCKED, (val != 0), IDLE_CHK_ERROR,
+	   "PXP2: pgl_read_blocked is not 0");
+	IDLE_CHK_1(0x3, PXP2_REG_PGL_TXW_CDTS, (((val >> 17) & 1) != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PXP2: There is data which is ready");
+
+	IDLE_CHK_1(0x3, PXP_REG_HST_ARB_IS_IDLE, (val != 1), IDLE_CHK_WARNING,
+	   "PXP: HST arbiter is not idle");
+	IDLE_CHK_1(0x3, PXP_REG_HST_CLIENTS_WAITING_TO_ARB, (val != 0),
+	   IDLE_CHK_WARNING,
+	   "PXP: HST one of the clients is waiting for delivery");
+	IDLE_CHK_1(0x2, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS,
+	   (val != 0), IDLE_CHK_WARNING,
+	   "PXP: HST Close the gates: Discarding internal writes");
+	IDLE_CHK_1(0x2, PXP_REG_HST_DISCARD_DOORBELLS_STATUS, (val != 0),
+	   IDLE_CHK_WARNING,
+	   "PXP: HST Close the gates: Discarding doorbells");
+
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 0 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 1 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 2 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 3 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 4 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 5 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C6, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 6 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C7, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 7 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C8, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 8 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C9, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DMAE: command 9 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C10, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 10 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C11, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 11 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C12, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 12 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C13, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 13 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C14, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 14 go is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_GO_C15, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 15 go is not 0");
+
+	IDLE_CHK_1(0x3, CFC_REG_ERROR_VECTOR, (val != 0), IDLE_CHK_ERROR,
+	   "CFC: error vector is not 0");
+	IDLE_CHK_1(0x3, CFC_REG_NUM_LCIDS_ARRIVING, (val != 0),
+	   IDLE_CHK_ERROR, "CFC: number of arriving LCIDs is not 0");
+	IDLE_CHK_1(0x3, CFC_REG_NUM_LCIDS_ALLOC, (val != 0), IDLE_CHK_ERROR,
+	   "CFC: number of alloc LCIDs is not 0");
+	IDLE_CHK_1(0x3, CFC_REG_NUM_LCIDS_LEAVING, (val != 0), IDLE_CHK_ERROR,
+	   "CFC: number of leaving LCIDs is not 0");
+
+	IDLE_CHK_4(0x3, CFC_REG_ACTIVITY_COUNTER, CFC_REG_CID_CAM,
+	   (CFC_REG_ACTIVITY_COUNTER_SIZE >> 2), 4, (val1 > 1),
+	   IDLE_CHK_ERROR, "CFC: AC > 1");
+	IDLE_CHK_7(0x3, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM,
+	   CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16,
+	   (val1 == 3), IDLE_CHK_WARNING,
+	   "CFC: AC is 1, connType is 3");
+	IDLE_CHK_7(0x3, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM,
+	   CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16,
+	   ((val1 != 0) && (val1 != 3)), IDLE_CHK_ERROR,
+	   "CFC: AC is 1, connType is not 0 nor 3");
+
+	IDLE_CHK_2(0x3, QM_REG_QTASKCTR_0, 64, 4, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Q_%d, queue is not empty");
+
+	IDLE_CHK_3(0x3, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0,
+	   (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "QM: VOQ_0, VOQ credit is not equal to initial credit");
+	IDLE_CHK_3(0x3, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1,
+	   (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "QM: VOQ_1, VOQ credit is not equal to initial credit");
+	IDLE_CHK_3(0x3, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4,
+	   (val1 != val2), IDLE_CHK_ERROR,
+	   "QM: VOQ_4, VOQ credit is not equal to initial credit");
+
+	IDLE_CHK_3(0x3, QM_REG_PORT0BYTECRD, QM_REG_BYTECRDINITVAL,
+	   (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "QM: P0 Byte credit is not equal to initial credit");
+	IDLE_CHK_3(0x3, QM_REG_PORT1BYTECRD, QM_REG_BYTECRDINITVAL,
+	   (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "QM: P1 Byte credit is not equal to initial credit");
+
+	IDLE_CHK_1(0x3, CCM_REG_CAM_OCCUP, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "CCM: XX protection CAM is not empty");
+	IDLE_CHK_1(0x3, TCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: XX protection CAM is not empty");
+	IDLE_CHK_1(0x3, UCM_REG_CAM_OCCUP, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "UCM: XX protection CAM is not empty");
+	IDLE_CHK_1(0x3, XCM_REG_CAM_OCCUP, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XCM: XX protection CAM is not empty");
+
+	IDLE_CHK_1(0x3, BRB1_REG_NUM_OF_FULL_BLOCKS, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "BRB1: BRB is not empty");
+
+	IDLE_CHK_1(0x3, CSEM_REG_SLEEP_THREADS_VALID, (val != 0),
+	   IDLE_CHK_ERROR, "CSEM: There are sleeping threads");
+	IDLE_CHK_1(0x3, TSEM_REG_SLEEP_THREADS_VALID, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "TSEM: There are sleeping threads");
+	IDLE_CHK_1(0x3, USEM_REG_SLEEP_THREADS_VALID, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "USEM: There are sleeping threads");
+	IDLE_CHK_1(0x3, XSEM_REG_SLEEP_THREADS_VALID, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XSEM: There are sleeping threads");
+
+	IDLE_CHK_1(0x3, CSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR, "CSEM: External store FIFO is not empty");
+	IDLE_CHK_1(0x3, TSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "TSEM: External store FIFO is not empty");
+	IDLE_CHK_1(0x3, USEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "USEM: External store FIFO is not empty");
+	IDLE_CHK_1(0x3, XSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XSEM: External store FIFO is not empty");
+
+	IDLE_CHK_1(0x3, CSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR, "CSDM: Parser serial FIFO is not empty");
+	IDLE_CHK_1(0x3, TSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "TSDM: Parser serial FIFO is not empty");
+	IDLE_CHK_1(0x3, USDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR, "USDM: Parser serial FIFO is not empty");
+	IDLE_CHK_1(0x3, XSDM_REG_SYNC_PARSER_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR, "XSDM: Parser serial FIFO is not empty");
+
+	IDLE_CHK_1(0x3, CSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+	   "CSDM: Parser SYNC serial FIFO is not empty");
+	IDLE_CHK_1(0x3, TSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+	   "TSDM: Parser SYNC serial FIFO is not empty");
+	IDLE_CHK_1(0x3, USDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+	   "USDM: Parser SYNC serial FIFO is not empty");
+	IDLE_CHK_1(0x3, XSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR,
+	   "XSDM: Parser SYNC serial FIFO is not empty");
+
+	IDLE_CHK_1(0x3, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR,
+	   "CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
+	IDLE_CHK_1(0x3, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR,
+	   "TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
+	IDLE_CHK_1(0x3, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
+	IDLE_CHK_1(0x3, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
+
+	IDLE_CHK_1(0x3, DORQ_REG_DQ_FILL_LVLF, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "DQ: DORQ queue is not empty");
+
+	IDLE_CHK_1(0x3, CFC_REG_CFC_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "CFC: interrupt status is not 0");
+	IDLE_CHK_1(0x3, CDU_REG_CDU_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "CDU: interrupt status is not 0");
+	IDLE_CHK_1(0x3, CCM_REG_CCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "CCM: interrupt status is not 0");
+	IDLE_CHK_1(0x3, TCM_REG_TCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: interrupt status is not 0");
+	IDLE_CHK_1(0x3, UCM_REG_UCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "UCM: interrupt status is not 0");
+	IDLE_CHK_1(0x3, XCM_REG_XCM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: interrupt status is not 0");
+	IDLE_CHK_1(0x3, PBF_REG_PBF_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "PBF: interrupt status is not 0");
+	IDLE_CHK_1(0x3, TM_REG_TM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "TIMERS: interrupt status is not 0");
+	IDLE_CHK_1(0x3, DORQ_REG_DORQ_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "DQ: interrupt status is not 0");
+	IDLE_CHK_1(0x3, SRC_REG_SRC_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "SRCH: interrupt status is not 0");
+	IDLE_CHK_1(0x3, PRS_REG_PRS_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "PRS: interrupt status is not 0");
+	IDLE_CHK_1(0x3, BRB1_REG_BRB1_INT_STS, ((val & ~0xfc00) != 0),
+	   IDLE_CHK_ERROR, "BRB1: interrupt status is not 0");
+	IDLE_CHK_1(0x3, GRCBASE_XPB + PB_REG_PB_INT_STS, (val != 0),
+	   IDLE_CHK_ERROR, "XPB: interrupt status is not 0");
+	IDLE_CHK_1(0x3, GRCBASE_UPB + PB_REG_PB_INT_STS, (val != 0),
+	   IDLE_CHK_ERROR, "UPB: interrupt status is not 0");
+	IDLE_CHK_1(0x3, PXP2_REG_PXP2_INT_STS_0, (val != 0), IDLE_CHK_WARNING,
+	   "PXP2: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x2, PXP2_REG_PXP2_INT_STS_1, (val != 0), IDLE_CHK_WARNING,
+	   "PXP2: interrupt status 1 is not 0");
+	IDLE_CHK_1(0x3, QM_REG_QM_INT_STS, (val != 0), IDLE_CHK_ERROR,
+	   "QM: interrupt status is not 0");
+	IDLE_CHK_1(0x3, PXP_REG_PXP_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+	   "PXP: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, PXP_REG_PXP_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "PXP: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, DORQ_REG_RSPA_CRD_CNT, (val != 2),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "DQ: Credit to XCM is not full");
+	IDLE_CHK_1(0x3, DORQ_REG_RSPB_CRD_CNT, (val != 2), IDLE_CHK_ERROR,
+	   "DQ: Credit to UCM is not full");
+
+	IDLE_CHK_1(0x3, QM_REG_VOQCRDERRREG, (val != 0), IDLE_CHK_ERROR,
+	   "QM: Credit error register is not 0 (byte or credit"
+	   " overflow/underflow)");
+	IDLE_CHK_1(0x3, DORQ_REG_DQ_FULL_ST, (val != 0), IDLE_CHK_ERROR,
+	   "DQ: DORQ queue is full");
+
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0,
+	   ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
+	   "AEU: P0 AFTER_INVERT_1 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0, (val != 0),
+	   IDLE_CHK_ERROR, "AEU: P0 AFTER_INVERT_2 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0,
+	   ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
+	   "AEU: P0 AFTER_INVERT_3 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0,
+	   ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
+	   "AEU: P0 AFTER_INVERT_4 is not 0");
+
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1,
+	   ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
+	   "AEU: P1 AFTER_INVERT_1 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1, (val != 0),
+	   IDLE_CHK_ERROR, "AEU: P1 AFTER_INVERT_2 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1,
+	   ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
+	   "AEU: P1 AFTER_INVERT_3 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1,
+	   ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
+	   "AEU: P1 AFTER_INVERT_4 is not 0");
+
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_1_MCP,
+	   ((val & ~0xcffc) != 0), IDLE_CHK_WARNING,
+	   "AEU: MCP AFTER_INVERT_1 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_2_MCP, (val != 0),
+	   IDLE_CHK_ERROR, "AEU: MCP AFTER_INVERT_2 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_3_MCP,
+	   ((val & ~0xc21b0000) != 0), IDLE_CHK_ERROR,
+	   "AEU: MCP AFTER_INVERT_3 is not 0");
+	IDLE_CHK_1(0x3, MISC_REG_AEU_AFTER_INVERT_4_MCP,
+	   ((val & ~0x801fffff) != 0), IDLE_CHK_ERROR,
+	   "AEU: MCP AFTER_INVERT_4 is not 0");
+
+	IDLE_CHK_5(0x3, PBF_REG_DISABLE_NEW_TASK_PROC_P0, PBF_REG_P0_CREDIT,
+	   PBF_REG_P0_INIT_CRD, (val1 != val2),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PBF: P0 credit is not equal to init_crd");
+	IDLE_CHK_5(0x3, PBF_REG_DISABLE_NEW_TASK_PROC_P1, PBF_REG_P1_CREDIT,
+	   PBF_REG_P1_INIT_CRD, (val1 != val2),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PBF: P1 credit is not equal to init_crd");
+	IDLE_CHK_3(0x3, PBF_REG_P4_CREDIT, PBF_REG_P4_INIT_CRD,
+	   (val1 != val2), IDLE_CHK_ERROR,
+	   "PBF: P4 credit is not equal to init_crd");
+
+	IDLE_CHK_1(0x3, PBF_REG_P0_TASK_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 task_cnt is not 0");
+	IDLE_CHK_1(0x3, PBF_REG_P1_TASK_CNT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 task_cnt is not 0");
+	IDLE_CHK_1(0x3, PBF_REG_P4_TASK_CNT, (val != 0), IDLE_CHK_ERROR,
+	   "PBF: P4 task_cnt is not 0");
+
+	IDLE_CHK_1(0x3, XCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
+	   "XCM: CFC_INIT_CRD is not 1");
+	IDLE_CHK_1(0x3, UCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
+	   "UCM: CFC_INIT_CRD is not 1");
+	IDLE_CHK_1(0x3, TCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR,
+	   "TCM: CFC_INIT_CRD is not 1");
+	IDLE_CHK_1(0x3, CCM_REG_CFC_INIT_CRD, (val != 1),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CFC_INIT_CRD is not 1");
+
+	IDLE_CHK_1(0x3, XCM_REG_XQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
+	   "XCM: XQM_INIT_CRD is not 32");
+	IDLE_CHK_1(0x3, UCM_REG_UQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
+	   "UCM: UQM_INIT_CRD is not 32");
+	IDLE_CHK_1(0x3, TCM_REG_TQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR,
+	   "TCM: TQM_INIT_CRD is not 32");
+	IDLE_CHK_1(0x3, CCM_REG_CQM_INIT_CRD, (val != 32),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CQM_INIT_CRD is not 32");
+
+	IDLE_CHK_1(0x3, XCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR,
+	   "XCM: TM_INIT_CRD is not 4");
+	IDLE_CHK_1(0x3, UCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR,
+	   "UCM: TM_INIT_CRD is not 4");
+
+	IDLE_CHK_1(0x3, XCM_REG_FIC0_INIT_CRD, (val != 64),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: FIC0_INIT_CRD is not 64");
+	IDLE_CHK_1(0x3, UCM_REG_FIC0_INIT_CRD, (val != 64),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC0_INIT_CRD is not 64");
+	IDLE_CHK_1(0x3, TCM_REG_FIC0_INIT_CRD, (val != 64),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC0_INIT_CRD is not 64");
+	IDLE_CHK_1(0x3, CCM_REG_FIC0_INIT_CRD, (val != 64),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC0_INIT_CRD is not 64");
+
+	IDLE_CHK_1(0x3, XCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+	   "XCM: FIC1_INIT_CRD is not 64");
+	IDLE_CHK_1(0x3, UCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+	   "UCM: FIC1_INIT_CRD is not 64");
+	IDLE_CHK_1(0x3, TCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+	   "TCM: FIC1_INIT_CRD is not 64");
+	IDLE_CHK_1(0x3, CCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR,
+	   "CCM: FIC1_INIT_CRD is not 64");
+
+	IDLE_CHK_1(0x1, XCM_REG_XX_FREE, (val != 31), IDLE_CHK_ERROR,
+	   "XCM: XX_FREE is not 31");
+	IDLE_CHK_1(0x2, XCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR,
+	   "XCM: XX_FREE is not 32");
+	IDLE_CHK_1(0x3, UCM_REG_XX_FREE, (val != 27),
+	   IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX_FREE is not 27");
+	IDLE_CHK_1(0x3, TCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR,
+	   "TCM: XX_FREE is not 32");
+	IDLE_CHK_1(0x3, CCM_REG_XX_FREE, (val != 24), IDLE_CHK_ERROR,
+	   "CCM: XX_FREE is not 24");
+
+	IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x18000, (val !=  0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XSEM: FOC0 credit less than initial credit");
+	IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x18040, (val !=  24),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XSEM: FOC1 credit less than initial credit");
+	IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x18080, (val !=  12),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XSEM: FOC2 credit less than initial credit");
+	IDLE_CHK_1(0x3, XSEM_REG_FAST_MEMORY + 0x180C0, (val !=  102),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "XSEM: FOC3 credit less than initial credit");
+
+	IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x18000, (val != 26),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "USEM: FOC0 credit less than initial credit");
+	IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x18040, (val != 78),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "USEM: FOC1 credit less than initial credit");
+	IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x18080, (val != 16),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "USEM: FOC2 credit less than initial credit");
+	IDLE_CHK_1(0x3, USEM_REG_FAST_MEMORY + 0x180C0, (val != 32),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "USEM: FOC3 credit less than initial credit");
+
+	IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x18000, (val != 52),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "TSEM: FOC0 credit less than initial credit");
+	IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x18040, (val != 24),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "TSEM: FOC1 credit less than initial credit");
+	IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x18080, (val != 12),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "TSEM: FOC2 credit less than initial credit");
+	IDLE_CHK_1(0x3, TSEM_REG_FAST_MEMORY + 0x180C0, (val != 32),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "TSEM: FOC3 credit less than initial credit");
+
+	IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x18000, (val != 16),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "CSEM: FOC0 credit less than initial credit");
+	IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x18040, (val != 18),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "CSEM: FOC1 credit less than initial credit");
+	IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x18080, (val != 48),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "CSEM: FOC2 credit less than initial credit");
+	IDLE_CHK_1(0x3, CSEM_REG_FAST_MEMORY + 0x180C0, (val != 14),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "CSEM: FOC3 credit less than initial credit");
+
+	IDLE_CHK_1(0x3, PRS_REG_TSDM_CURRENT_CREDIT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PRS: TSDM current credit is not 0");
+	IDLE_CHK_1(0x3, PRS_REG_TCM_CURRENT_CREDIT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PRS: TCM current credit is not 0");
+	IDLE_CHK_1(0x3, PRS_REG_CFC_LD_CURRENT_CREDIT, (val != 0),
+	   IDLE_CHK_ERROR, "PRS: CFC_LD current credit is not 0");
+	IDLE_CHK_1(0x3, PRS_REG_CFC_SEARCH_CURRENT_CREDIT, (val != 0),
+	   IDLE_CHK_ERROR, "PRS: CFC_SEARCH current credit is not 0");
+	IDLE_CHK_1(0x3, PRS_REG_SRC_CURRENT_CREDIT, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PRS: SRCH current credit is not 0");
+
+	IDLE_CHK_1(0x3, PRS_REG_PENDING_BRB_PRS_RQ, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PRS: PENDING_BRB_PRS_RQ is not 0");
+	IDLE_CHK_2(0x3, PRS_REG_PENDING_BRB_CAC0_RQ, 5, 4, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PRS: PENDING_BRB_CAC%d_RQ is not 0");
+
+	IDLE_CHK_1(0x3, PRS_REG_SERIAL_NUM_STATUS_LSB, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PRS: SERIAL_NUM_STATUS_LSB is not 0");
+	IDLE_CHK_1(0x3, PRS_REG_SERIAL_NUM_STATUS_MSB, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "PRS: SERIAL_NUM_STATUS_MSB is not 0");
+
+	IDLE_CHK_1(0x3, CDU_REG_ERROR_DATA, (val != 0), IDLE_CHK_ERROR,
+	   "CDU: ERROR_DATA is not 0");
+
+	IDLE_CHK_1(0x3, CCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "CCM: STORM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, CCM_REG_CSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "CCM: CSDM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, CCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "CCM: TSEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, CCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "CCM: XSEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, CCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "CCM: USEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, CCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "CCM: PBF declared message length unequal to actual");
+
+	IDLE_CHK_1(0x3, TCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: STORM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, TCM_REG_TSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: TSDM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, TCM_REG_PRS_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: PRS declared message length unequal to actual");
+	IDLE_CHK_1(0x3, TCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: PBF declared message length unequal to actual");
+	IDLE_CHK_1(0x3, TCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: USEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, TCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "TCM: CSEM declared message length unequal to actual");
+
+	IDLE_CHK_1(0x3, UCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "UCM: STORM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, UCM_REG_USDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "UCM: USDM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, UCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "UCM: TSEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, UCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "UCM: CSEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, UCM_REG_XSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "UCM: XSEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, UCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "UCM: DORQ declared message length unequal to actual");
+
+	IDLE_CHK_1(0x3, XCM_REG_STORM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: STORM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_XSDM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: XSDM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_TSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: TSEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_CSEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: CSEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_USEM_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: USEM declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_DORQ_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: DORQ declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_PBF_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: PBF declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_NIG0_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: NIG0 declared message length unequal to actual");
+	IDLE_CHK_1(0x3, XCM_REG_NIG1_LENGTH_MIS, (val != 0), IDLE_CHK_ERROR,
+	   "XCM: NIG1 declared message length unequal to actual");
+
+	IDLE_CHK_1(0x3, QM_REG_XQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+	   "QM: XQM wrc_fifolvl is not 0");
+	IDLE_CHK_1(0x3, QM_REG_UQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+	   "QM: UQM wrc_fifolvl is not 0");
+	IDLE_CHK_1(0x3, QM_REG_TQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+	   "QM: TQM wrc_fifolvl is not 0");
+	IDLE_CHK_1(0x3, QM_REG_CQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR,
+	   "QM: CQM wrc_fifolvl is not 0");
+	IDLE_CHK_1(0x3, QM_REG_QSTATUS_LOW, (val != 0), IDLE_CHK_ERROR,
+	   "QM: QSTATUS_LOW is not 0");
+	IDLE_CHK_1(0x3, QM_REG_QSTATUS_HIGH, (val != 0), IDLE_CHK_ERROR,
+	   "QM: QSTATUS_HIGH is not 0");
+	IDLE_CHK_1(0x3, QM_REG_PAUSESTATE0, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE0 is not 0");
+	IDLE_CHK_1(0x3, QM_REG_PAUSESTATE1, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE1 is not 0");
+	IDLE_CHK_1(0x3, QM_REG_OVFQNUM, (val != 0), IDLE_CHK_ERROR,
+	   "QM: OVFQNUM is not 0");
+	IDLE_CHK_1(0x3, QM_REG_OVFERROR, (val != 0), IDLE_CHK_ERROR,
+	   "QM: OVFERROR is not 0");
+
+	IDLE_CHK_6(0x3, QM_REG_PTRTBL, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC);
+
+	IDLE_CHK_1(0x3, BRB1_REG_BRB1_PRTY_STS, ((val & ~0x8) != 0),
+	   IDLE_CHK_WARNING, "BRB1: parity status is not 0");
+	IDLE_CHK_1(0x3, CDU_REG_CDU_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "CDU: parity status is not 0");
+	IDLE_CHK_1(0x3, CFC_REG_CFC_PRTY_STS, ((val & ~0x2) != 0),
+	   IDLE_CHK_WARNING, "CFC: parity status is not 0");
+	IDLE_CHK_1(0x3, CSDM_REG_CSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "CSDM: parity status is not 0");
+	IDLE_CHK_1(0x3, DBG_REG_DBG_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "DBG: parity status is not 0");
+	IDLE_CHK_1(0x3, DMAE_REG_DMAE_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "DMAE: parity status is not 0");
+	IDLE_CHK_1(0x3, DORQ_REG_DORQ_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "DQ: parity status is not 0");
+	IDLE_CHK_1(0x1, TCM_REG_TCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+	   IDLE_CHK_WARNING, "TCM: parity status is not 0");
+	IDLE_CHK_1(0x2, TCM_REG_TCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "TCM: parity status is not 0");
+	IDLE_CHK_1(0x1, CCM_REG_CCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+	   IDLE_CHK_WARNING, "CCM: parity status is not 0");
+	IDLE_CHK_1(0x2, CCM_REG_CCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "CCM: parity status is not 0");
+	IDLE_CHK_1(0x1, UCM_REG_UCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+	   IDLE_CHK_WARNING, "UCM: parity status is not 0");
+	IDLE_CHK_1(0x2, UCM_REG_UCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "UCM: parity status is not 0");
+	IDLE_CHK_1(0x1, XCM_REG_XCM_PRTY_STS, ((val & ~0x3ffc0) != 0),
+	   IDLE_CHK_WARNING, "XCM: parity status is not 0");
+	IDLE_CHK_1(0x2, XCM_REG_XCM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "XCM: parity status is not 0");
+	IDLE_CHK_1(0x1, HC_REG_HC_PRTY_STS, ((val & ~0x1) != 0),
+	   IDLE_CHK_WARNING, "HC: parity status is not 0");
+	IDLE_CHK_1(0x1, MISC_REG_MISC_PRTY_STS, ((val & ~0x1) != 0),
+	   IDLE_CHK_WARNING, "MISC: parity status is not 0");
+	IDLE_CHK_1(0x3, PRS_REG_PRS_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "PRS: parity status is not 0");
+	IDLE_CHK_1(0x3, PXP_REG_PXP_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "PXP: parity status is not 0");
+	IDLE_CHK_1(0x3, QM_REG_QM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "QM: parity status is not 0");
+	IDLE_CHK_1(0x1, SRC_REG_SRC_PRTY_STS, ((val & ~0x4) != 0),
+	   IDLE_CHK_WARNING, "SRCH: parity status is not 0");
+	IDLE_CHK_1(0x3, TSDM_REG_TSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "TSDM: parity status is not 0");
+	IDLE_CHK_1(0x3, USDM_REG_USDM_PRTY_STS, ((val & ~0x20) != 0),
+	   IDLE_CHK_WARNING, "USDM: parity status is not 0");
+	IDLE_CHK_1(0x3, XSDM_REG_XSDM_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "XSDM: parity status is not 0");
+	IDLE_CHK_1(0x3, GRCBASE_XPB + PB_REG_PB_PRTY_STS, (val != 0),
+	   IDLE_CHK_WARNING, "XPB: parity status is not 0");
+	IDLE_CHK_1(0x3, GRCBASE_UPB + PB_REG_PB_PRTY_STS, (val != 0),
+	   IDLE_CHK_WARNING, "UPB: parity status is not 0");
+
+	IDLE_CHK_1(0x3, CSEM_REG_CSEM_PRTY_STS_0, (val != 0),
+	   IDLE_CHK_WARNING, "CSEM: parity status 0 is not 0");
+	IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0xfff40020) != 0),
+	   IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0");
+	IDLE_CHK_1(0x2, PXP2_REG_PXP2_PRTY_STS_0, ((val & ~0x20) != 0),
+	   IDLE_CHK_WARNING, "PXP2: parity status 0 is not 0");
+	IDLE_CHK_1(0x3, TSEM_REG_TSEM_PRTY_STS_0, (val != 0),
+	   IDLE_CHK_WARNING, "TSEM: parity status 0 is not 0");
+	IDLE_CHK_1(0x3, USEM_REG_USEM_PRTY_STS_0, (val != 0),
+	   IDLE_CHK_WARNING, "USEM: parity status 0 is not 0");
+	IDLE_CHK_1(0x3, XSEM_REG_XSEM_PRTY_STS_0, (val != 0),
+	   IDLE_CHK_WARNING, "XSEM: parity status 0 is not 0");
+
+	IDLE_CHK_1(0x3, CSEM_REG_CSEM_PRTY_STS_1, (val != 0),
+	   IDLE_CHK_WARNING, "CSEM: parity status 1 is not 0");
+	IDLE_CHK_1(0x1, PXP2_REG_PXP2_PRTY_STS_1, ((val & ~0x20) != 0),
+	   IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0");
+	IDLE_CHK_1(0x2, PXP2_REG_PXP2_PRTY_STS_1, (val != 0),
+	   IDLE_CHK_WARNING, "PXP2: parity status 1 is not 0");
+	IDLE_CHK_1(0x3, TSEM_REG_TSEM_PRTY_STS_1, (val != 0),
+	   IDLE_CHK_WARNING, "TSEM: parity status 1 is not 0");
+	IDLE_CHK_1(0x3, USEM_REG_USEM_PRTY_STS_1, (val != 0),
+	   IDLE_CHK_WARNING, "USEM: parity status 1 is not 0");
+	IDLE_CHK_1(0x3, XSEM_REG_XSEM_PRTY_STS_1, (val != 0),
+	   IDLE_CHK_WARNING, "XSEM: parity status 1 is not 0");
+
+	IDLE_CHK_2(0x2, QM_REG_QTASKCTR_EXT_A_0, 64, 4, (val != 0),
+	   IDLE_CHK_ERROR_NO_TRAFFIC,
+	   "QM: Q_EXT_A_%d, queue is not empty");
+	IDLE_CHK_1(0x2, QM_REG_QSTATUS_LOW_EXT_A, (val != 0), IDLE_CHK_ERROR,
+	   "QM: QSTATUS_LOW_EXT_A is not 0");
+	IDLE_CHK_1(0x2, QM_REG_QSTATUS_HIGH_EXT_A, (val != 0), IDLE_CHK_ERROR,
+	   "QM: QSTATUS_HIGH_EXT_A is not 0");
+	IDLE_CHK_1(0x2, QM_REG_PAUSESTATE2, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE2 is not 0");
+	IDLE_CHK_1(0x2, QM_REG_PAUSESTATE3, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE3 is not 0");
+	IDLE_CHK_1(0x2, QM_REG_PAUSESTATE4, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE4 is not 0");
+	IDLE_CHK_1(0x2, QM_REG_PAUSESTATE5, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE5 is not 0");
+	IDLE_CHK_1(0x2, QM_REG_PAUSESTATE6, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE6 is not 0");
+	IDLE_CHK_1(0x2, QM_REG_PAUSESTATE7, (val != 0), IDLE_CHK_ERROR,
+	   "QM: PAUSESTATE7 is not 0");
+	IDLE_CHK_6(0x2, QM_REG_PTRTBL_EXT_A, 64, 8,
+	   IDLE_CHK_ERROR_NO_TRAFFIC);
+
+	IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_OCCURRED, (val != 0),
+	   IDLE_CHK_ERROR, "MISC: system kill occurd;");
+	IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_0, (val != 0),
+	   IDLE_CHK_ERROR,
+	   "MISC: system kill occurd; status_0 register");
+	IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_1, (val != 0),
+	   IDLE_CHK_ERROR,
+	   "MISC: system kill occurd; status_1 register");
+	IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_2, (val != 0),
+	   IDLE_CHK_ERROR,
+	   "MISC: system kill occurd; status_2 register");
+	IDLE_CHK_1(0x2, MISC_REG_AEU_SYS_KILL_STATUS_3, (val != 0),
+	   IDLE_CHK_ERROR,
+	   "MISC: system kill occurd; status_3 register");
+	IDLE_CHK_1(0x2, MISC_REG_PCIE_HOT_RESET, (val != 0), IDLE_CHK_WARNING,
+	   "MISC: pcie_rst_b was asserted without perst assertion");
+
+	IDLE_CHK_1(0x3, NIG_REG_NIG_INT_STS_0, ((val & ~0x300) != 0),
+	   IDLE_CHK_ERROR, "NIG: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, NIG_REG_NIG_INT_STS_0, (val == 0x300),
+	   IDLE_CHK_WARNING,
+	   "NIG: Access to BMAC while not active. If tested on FPGA,"
+	   " ignore this warning.");
+	IDLE_CHK_1(0x3, NIG_REG_NIG_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "NIG: interrupt status 1 is not 0");
+	IDLE_CHK_1(0x2, NIG_REG_NIG_PRTY_STS, ((val & ~0xffc00000) != 0),
+	   IDLE_CHK_WARNING, "NIG: parity status is not 0");
+
+	IDLE_CHK_1(0x3, TSEM_REG_TSEM_INT_STS_0, ((val & ~0x10000000) != 0),
+	   IDLE_CHK_ERROR, "TSEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, TSEM_REG_TSEM_INT_STS_0, (val == 0x10000000),
+	   IDLE_CHK_WARNING, "TSEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, TSEM_REG_TSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "TSEM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, CSEM_REG_CSEM_INT_STS_0, ((val & ~0x10000000) != 0),
+	   IDLE_CHK_ERROR, "CSEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, CSEM_REG_CSEM_INT_STS_0, (val == 0x10000000),
+	   IDLE_CHK_WARNING, "CSEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, CSEM_REG_CSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "CSEM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, USEM_REG_USEM_INT_STS_0, ((val & ~0x10000000) != 0),
+	   IDLE_CHK_ERROR, "USEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, USEM_REG_USEM_INT_STS_0, (val == 0x10000000),
+	   IDLE_CHK_WARNING, "USEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, USEM_REG_USEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "USEM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, XSEM_REG_XSEM_INT_STS_0, ((val & ~0x10000000) != 0),
+	   IDLE_CHK_ERROR, "XSEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, XSEM_REG_XSEM_INT_STS_0, (val == 0x10000000),
+	   IDLE_CHK_WARNING, "XSEM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, XSEM_REG_XSEM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "XSEM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, TSDM_REG_TSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+	   "TSDM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, TSDM_REG_TSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "TSDM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, CSDM_REG_CSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+	   "CSDM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, CSDM_REG_CSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "CSDM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, USDM_REG_USDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+	   "USDM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, USDM_REG_USDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "USDM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x3, XSDM_REG_XSDM_INT_STS_0, (val != 0), IDLE_CHK_ERROR,
+	   "XSDM: interrupt status 0 is not 0");
+	IDLE_CHK_1(0x3, XSDM_REG_XSDM_INT_STS_1, (val != 0), IDLE_CHK_ERROR,
+	   "XSDM: interrupt status 1 is not 0");
+
+	IDLE_CHK_1(0x2, HC_REG_HC_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "HC: parity status is not 0");
+	IDLE_CHK_1(0x2, MISC_REG_MISC_PRTY_STS, (val != 0), IDLE_CHK_WARNING,
+	   "MISC: parity status is not 0");
+	IDLE_CHK_1(0x2, SRC_REG_SRC_PRTY_STS, (val  != 0), IDLE_CHK_WARNING,
+	   "SRCH: parity status is not 0");
+
+	if (idle_chk_errors == 0) {
+		BXE_PRINTF("%s(): Completed successfuly with %d warning(s).\n",
+		    __FUNCTION__, idle_chk_warnings);
+	} else {
+		BXE_PRINTF("%s(): Failed with %d error(s) and %d warning(s)!\n",
+		    __FUNCTION__, idle_chk_errors, idle_chk_warnings);
+	}
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+
+bxe_idle_chk_exit:
+	return (idle_chk_errors);
+}
+
+#endif /* _BXE_SELF_TEST_H */
diff --git a/sys/dev/bxe/dump_e1.h b/sys/dev/bxe/dump_e1.h
new file mode 100755
index 0000000..8b0f959
--- /dev/null
+++ b/sys/dev/bxe/dump_e1.h
@@ -0,0 +1,131 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+uint32_t regs_count_e1=319;
+
+struct reg_addr reg_addrs_e1[319] = {
+	{0x00002000,341}, {0x00002800,103}, {0x00003000,287}, {0x00003800,331},
+	{0x00008800,6}, {0x0000a000,223}, {0x0000a388,1}, {0x0000a398,1},
+	{0x0000a400,69}, {0x0000a518,1}, {0x0000a520,1}, {0x0000a528,1},
+	{0x0000a530,1}, {0x0000a538,1}, {0x0000a540,1}, {0x0000a548,1},
+	{0x0000a550,1}, {0x0000a558,1}, {0x0000a560,1}, {0x0000a568,1},
+	{0x0000a570,1}, {0x0000a580,1}, {0x0000a590,1}, {0x0000a5a0,1},
+	{0x0000a5c0,1}, {0x0000c000,35}, {0x0000c098,1}, {0x0000c0a8,1},
+	{0x0000c100,11}, {0x0000c130,2}, {0x0000c140,2}, {0x0000c160,4},
+	{0x0000c180,4}, {0x0000c1a0,4}, {0x0000c800,4}, {0x00010000,236},
+	{0x000103bc,1}, {0x000103cc,1}, {0x000103dc,1}, {0x00010400,57},
+	{0x000104e8,2}, {0x000104f4,2}, {0x00010500,146}, {0x00010750,2},
+	{0x00010760,2}, {0x00010770,2}, {0x00010780,2}, {0x00010790,2},
+	{0x000107a0,2}, {0x000107b0,2}, {0x000107c0,2}, {0x000107d0,2},
+	{0x000107e0,2}, {0x00010880,2}, {0x00010900,2}, {0x00010c00,2},
+	{0x00011000,2}, {0x00012000,1}, {0x00014000,1}, {0x00020000,170},
+	{0x000202b4,1}, {0x000202c4,1}, {0x00020400,2}, {0x0002040c,8},
+	{0x00020480,1}, {0x00020500,1}, {0x00020600,1}, {0x00028000,24674},
+	{0x00040194,1}, {0x000401a4,1}, {0x00040200,4}, {0x00040400,43},
+	{0x000404b8,1}, {0x000404c8,1}, {0x00040500,2}, {0x00040510,2},
+	{0x00040520,2}, {0x00040530,2}, {0x00040540,2}, {0x00042000,164},
+	{0x0004229c,1}, {0x000422ac,1}, {0x000422bc,1}, {0x00042400,49},
+	{0x000424c8,38}, {0x00042568,2}, {0x00042800,1}, {0x00050000,116},
+	{0x000501dc,1}, {0x000501ec,1}, {0x00050200,2}, {0x0005020c,7},
+	{0x00050240,1}, {0x00050280,1}, {0x00052000,1}, {0x00054000,3328},
+	{0x00058000,8263}, {0x00060128,1}, {0x00060138,1}, {0x00060200,1},
+	{0x00061000,512}, {0x00070000,32768}, {0x000a0000,16384},
+	{0x000c1000,7}, {0x000c1028,1}, {0x000c1038,1}, {0x000c1800,2},
+	{0x000c2000,164}, {0x000c229c,1}, {0x000c22ac,1}, {0x000c22bc,1},
+	{0x000c2400,49}, {0x000c24c8,38}, {0x000c2568,2}, {0x000c2600,1},
+	{0x000c4000,165}, {0x000c42a0,1}, {0x000c42b0,1}, {0x000c42c0,1},
+	{0x000c4400,51}, {0x000c44d0,38}, {0x000c4570,2}, {0x000c4600,1},
+	{0x000d0000,118}, {0x000d01e4,1}, {0x000d01f4,1}, {0x000d0200,2},
+	{0x000d020c,7}, {0x000d0280,1}, {0x000d0300,1}, {0x000d0400,1},
+	{0x000d4000,2560}, {0x000d8000,8306}, {0x000e01d4,1}, {0x000e01e4,1},
+	{0x000e0200,2}, {0x000e020c,8}, {0x000e0280,1}, {0x000e0300,1},
+	{0x000e1000,1}, {0x000e2000,2048}, {0x000f0000,16384}, {0x00101000,12},
+	{0x0010103c,1}, {0x0010104c,1}, {0x00101100,1}, {0x00101800,8},
+	{0x00102000,18}, {0x00102054,1}, {0x00102064,1}, {0x00102080,17},
+	{0x00102400,1}, {0x00103000,26}, {0x00103074,1}, {0x00103084,1},
+	{0x00103094,1}, {0x00103800,8}, {0x00104000,63}, {0x00104108,1},
+	{0x00104118,1}, {0x00104200,17}, {0x00104400,512}, {0x00105000,1024},
+	{0x00108000,33}, {0x00108090,1}, {0x001080a0,1}, {0x00108100,5},
+	{0x00108120,5}, {0x00108200,74}, {0x00108400,74}, {0x00108800,152},
+	{0x00109000,1}, {0x00120000,347}, {0x00120578,1}, {0x00120588,1},
+	{0x00120598,1}, {0x0012080c,65}, {0x00120a00,2}, {0x00122000,2},
+	{0x00140000,114}, {0x001401d4,1}, {0x001401e4,1}, {0x00140200,6},
+	{0x00144000,4}, {0x00148000,4}, {0x0014c000,4}, {0x00150000,4},
+	{0x00154000,4}, {0x00158000,4}, {0x00161000,7}, {0x00161028,1},
+	{0x00161038,1}, {0x00161800,2}, {0x00164000,60}, {0x001640fc,1},
+	{0x0016410c,1}, {0x00164200,1}, {0x00164208,1}, {0x00164210,1},
+	{0x00164218,1}, {0x00164220,1}, {0x00164228,1}, {0x00164230,1},
+	{0x00164238,1}, {0x00164240,1}, {0x00164248,1}, {0x00164250,1},
+	{0x00164258,1}, {0x00164260,1}, {0x00164270,2}, {0x00164280,2},
+	{0x00164800,2}, {0x00165000,2}, {0x00166000,164}, {0x0016629c,1},
+	{0x001662ac,1}, {0x001662bc,1}, {0x00166400,49}, {0x001664c8,38},
+	{0x00166568,2}, {0x00166800,1}, {0x00168000,270}, {0x00168444,1},
+	{0x00168454,1}, {0x00168800,19}, {0x00168900,1}, {0x00168a00,128},
+	{0x0016a000,1536}, {0x0016c000,1536}, {0x00170000,93}, {0x00170180,1},
+	{0x00170190,1}, {0x00170200,4}, {0x00170214,1}, {0x00178000,1},
+	{0x00180000,61}, {0x00180100,1}, {0x00180110,1}, {0x00180120,1},
+	{0x00180130,1}, {0x00180200,58}, {0x00180340,4}, {0x00180400,1},
+	{0x00181000,1024}, {0x001a0000,5632}, {0x001a8000,64},
+	{0x001b1800,128}, {0x001b1c00,128}, {0x001b2000,1}, {0x001b8200,1},
+	{0x001b8240,1}, {0x001b8280,1}, {0x001b82c0,1}, {0x001b8a00,1},
+	{0x001b8a80,1}, {0x001c0000,2}, {0x00200000,65}, {0x00200110,1},
+	{0x00200120,1}, {0x00200130,1}, {0x00200140,1}, {0x00200200,58},
+	{0x00200340,4}, {0x00200400,1}, {0x00202000,2048}, {0x00220000,5632},
+	{0x00228000,64}, {0x00231800,128}, {0x00231c00,128}, {0x00232000,1},
+	{0x00238200,1}, {0x00238240,1}, {0x00238280,1}, {0x002382c0,1},
+	{0x00238a00,1}, {0x00238a80,1}, {0x00240000,2}, {0x00280000,65},
+	{0x00280110,1}, {0x00280120,1}, {0x00280130,1}, {0x00280140,1},
+	{0x00280200,58}, {0x00280340,4}, {0x00280400,1}, {0x00282000,2048},
+	{0x002a0000,5632}, {0x002a8000,64}, {0x002b1800,128}, {0x002b1c00,128},
+	{0x002b2000,1}, {0x002b8200,1}, {0x002b8240,1}, {0x002b8280,1},
+	{0x002b82c0,1}, {0x002b8a00,1}, {0x002b8a80,1}, {0x002c0000,2},
+	{0x00300000,65}, {0x00300110,1}, {0x00300120,1}, {0x00300130,1},
+	{0x00300140,1}, {0x00300200,58}, {0x00300340,4}, {0x00300400,1},
+	{0x00302000,2048}, {0x00320000,5632}, {0x00328000,64},
+	{0x00331800,128}, {0x00331c00,128}, {0x00332000,1}, {0x00338200,1},
+	{0x00338240,1}, {0x00338280,1}, {0x003382c0,1}, {0x00338a00,1},
+	{0x00338a80,1}, {0x00340000,2}};
+
+
+
+uint32_t wregs_count_e1=1;
+
+static uint32_t const_reg0_e1[1] = {0x001b1000};
+
+
+struct wreg_addr wreg_addrs_e1[1] = {{0x001b0c00, 192, 1, const_reg0_e1}};
+
+
+struct hd_param hd_param_e1={0x497e2e43, 0x00040802, 0x0000001f};
+
diff --git a/sys/dev/bxe/dump_e1h.h b/sys/dev/bxe/dump_e1h.h
new file mode 100755
index 0000000..13935cf
--- /dev/null
+++ b/sys/dev/bxe/dump_e1h.h
@@ -0,0 +1,140 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+uint32_t regs_count_e1h=354;
+
+struct reg_addr reg_addrs_e1h[354] = {
+	{0x00002000,341}, {0x00002800,103}, {0x00003000,287}, {0x00003800,331},
+	{0x0000a000,223}, {0x0000a388,1}, {0x0000a398,8}, {0x0000a3c0,3},
+	{0x0000a3d0,1}, {0x0000a3d8,1}, {0x0000a3e0,1}, {0x0000a3e8,1},
+	{0x0000a3f0,1}, {0x0000a3f8,1}, {0x0000a400,69}, {0x0000a518,1},
+	{0x0000a520,1}, {0x0000a528,1}, {0x0000a530,1}, {0x0000a538,1},
+	{0x0000a540,1}, {0x0000a548,1}, {0x0000a550,1}, {0x0000a558,1},
+	{0x0000a560,1}, {0x0000a568,1}, {0x0000a570,1}, {0x0000a580,1},
+	{0x0000a590,1}, {0x0000a5a0,1}, {0x0000a5c0,1}, {0x0000a5e0,1},
+	{0x0000a5e8,1}, {0x0000a5f0,1}, {0x0000a5f8,10}, {0x0000c000,35},
+	{0x0000c098,1}, {0x0000c0a8,1}, {0x0000c100,11}, {0x0000c130,2},
+	{0x0000c140,2}, {0x0000c160,4}, {0x0000c180,4}, {0x0000c1a0,4},
+	{0x0000c800,4}, {0x0000d000,347}, {0x00010000,236}, {0x000103bc,1},
+	{0x000103cc,1}, {0x000103dc,1}, {0x00010400,57}, {0x000104e8,2},
+	{0x000104f4,2}, {0x00010500,146}, {0x00010750,2}, {0x00010760,2},
+	{0x00010770,2}, {0x00010780,2}, {0x00010790,2}, {0x000107a0,2},
+	{0x000107b0,2}, {0x000107c0,2}, {0x000107d0,2}, {0x000107e0,2},
+	{0x00010880,2}, {0x00010900,2}, {0x00010c00,2}, {0x00011000,2},
+	{0x00012000,1}, {0x00014000,1}, {0x00016000,26}, {0x00016070,18},
+	{0x000160c0,27}, {0x00016140,1}, {0x00016160,1}, {0x00016180,2},
+	{0x000161c0,2}, {0x00016204,5}, {0x00018000,1}, {0x00018008,1},
+	{0x00020000,170}, {0x000202b4,1}, {0x000202c4,1}, {0x00020400,2},
+	{0x0002040c,26}, {0x00020480,1}, {0x00020500,1}, {0x00020600,1},
+	{0x00028000,24674}, {0x00040194,1}, {0x000401a4,12}, {0x00040200,4},
+	{0x00040400,43}, {0x000404b8,1}, {0x000404c8,4}, {0x00040500,2},
+	{0x00040510,2}, {0x00040520,2}, {0x00040530,2}, {0x00040540,2},
+	{0x00042000,164}, {0x0004229c,1}, {0x000422ac,1}, {0x000422bc,1},
+	{0x000422d4,5}, {0x00042400,49}, {0x000424c8,38}, {0x00042568,2},
+	{0x00042800,1}, {0x00050000,116}, {0x000501dc,1}, {0x000501ec,7},
+	{0x0005020c,14}, {0x00050280,1}, {0x00052000,1}, {0x00054000,3328},
+	{0x00058000,8263}, {0x00060128,1}, {0x00060138,25}, {0x00060200,1},
+	{0x00061000,512}, {0x00070000,32768}, {0x000a0000,32768},
+	{0x000c1000,7}, {0x000c1028,1}, {0x000c1038,1}, {0x000c1800,2},
+	{0x000c2000,164}, {0x000c229c,1}, {0x000c22ac,1}, {0x000c22bc,1},
+	{0x000c2400,49}, {0x000c24c8,38}, {0x000c2568,2}, {0x000c2600,1},
+	{0x000c4000,165}, {0x000c42a0,1}, {0x000c42b0,1}, {0x000c42c0,1},
+	{0x000c42e0,7}, {0x000c4400,51}, {0x000c44d0,38}, {0x000c4570,2},
+	{0x000c4600,1}, {0x000d0000,118}, {0x000d01e4,1}, {0x000d01f4,1},
+	{0x000d0200,2}, {0x000d020c,25}, {0x000d0280,1}, {0x000d0300,1},
+	{0x000d0400,1}, {0x000d4000,2560}, {0x000d8000,8306}, {0x000e01d4,1},
+	{0x000e01e4,1}, {0x000e0200,2}, {0x000e020c,26}, {0x000e0280,1},
+	{0x000e0300,1}, {0x000e1000,1}, {0x000e2000,2048}, {0x000f0000,16384},
+	{0x00101000,12}, {0x0010103c,1}, {0x0010104c,2}, {0x00101100,1},
+	{0x00101800,8}, {0x00102000,18}, {0x00102054,1}, {0x00102064,1},
+	{0x00102080,17}, {0x001020c8,8}, {0x00102400,1}, {0x00103000,26},
+	{0x00103074,1}, {0x00103084,1}, {0x00103094,6}, {0x00103800,8},
+	{0x00104000,63}, {0x00104108,1}, {0x00104118,1}, {0x00104200,17},
+	{0x00104400,512}, {0x00105000,1024}, {0x00108000,33}, {0x00108090,1},
+	{0x001080a0,1}, {0x001080ac,5}, {0x00108100,5}, {0x00108120,5},
+	{0x00108200,74}, {0x00108400,74}, {0x00108800,152}, {0x00109000,1},
+	{0x00120000,347}, {0x00120578,1}, {0x00120588,1}, {0x00120598,24},
+	{0x00120614,1}, {0x0012061c,30}, {0x0012080c,65}, {0x00120a00,2},
+	{0x00122000,2}, {0x00128000,2}, {0x00140000,114}, {0x001401d4,1},
+	{0x001401e4,1}, {0x00140200,6}, {0x00144000,4}, {0x00148000,4},
+	{0x0014c000,4}, {0x00150000,4}, {0x00154000,4}, {0x00158000,4},
+	{0x0015c000,7}, {0x00161000,7}, {0x00161028,1}, {0x00161038,1},
+	{0x00161800,2}, {0x00164000,60}, {0x001640fc,1}, {0x0016410c,3},
+	{0x00164200,1}, {0x00164208,1}, {0x00164210,1}, {0x00164218,1},
+	{0x00164220,1}, {0x00164228,1}, {0x00164230,1}, {0x00164238,1},
+	{0x00164240,1}, {0x00164248,1}, {0x00164250,1}, {0x00164258,1},
+	{0x00164260,1}, {0x00164270,2}, {0x00164280,2}, {0x00164800,2},
+	{0x00165000,2}, {0x00166000,164}, {0x0016629c,1}, {0x001662ac,1},
+	{0x001662bc,1}, {0x00166400,49}, {0x001664c8,38}, {0x00166568,2},
+	{0x00166800,1}, {0x00168000,270}, {0x00168444,1}, {0x00168454,1},
+	{0x00168800,19}, {0x00168900,1}, {0x00168a00,128}, {0x0016a000,1536},
+	{0x0016c000,1536}, {0x0016e000,16}, {0x0016e100,1}, {0x0016e200,2},
+	{0x0016e400,183}, {0x00170000,93}, {0x00170180,1}, {0x00170190,1},
+	{0x00170200,4}, {0x00170214,1}, {0x00178000,1}, {0x00180000,61},
+	{0x00180100,1}, {0x00180110,1}, {0x00180120,1}, {0x00180130,1},
+	{0x0018013c,2}, {0x00180200,58}, {0x00180340,4}, {0x00180400,1},
+	{0x00181000,1024}, {0x001a0000,16896}, {0x001b1800,128},
+	{0x001b1c00,128}, {0x001b2000,1}, {0x001b2400,64}, {0x001b8200,1},
+	{0x001b8240,1}, {0x001b8280,1}, {0x001b82c0,1}, {0x001b8a00,1},
+	{0x001b8a80,1}, {0x001c0000,2}, {0x00200000,65}, {0x00200110,1},
+	{0x00200120,1}, {0x00200130,1}, {0x00200140,1}, {0x0020014c,2},
+	{0x00200200,58}, {0x00200340,4}, {0x00200400,1}, {0x00202000,2048},
+	{0x00220000,16896}, {0x00231800,128}, {0x00231c00,128}, {0x00232000,1},
+	{0x00232400,64}, {0x00238200,1}, {0x00238240,1}, {0x00238280,1},
+	{0x002382c0,1}, {0x00238a00,1}, {0x00238a80,1}, {0x00240000,2},
+	{0x00280000,65}, {0x00280110,1}, {0x00280120,1}, {0x00280130,1},
+	{0x00280140,1}, {0x0028014c,2}, {0x00280200,58}, {0x00280340,4},
+	{0x00280400,1}, {0x00282000,2048}, {0x002a0000,16896},
+	{0x002b1800,128}, {0x002b1c00,128}, {0x002b2000,1}, {0x002b2400,64},
+	{0x002b8200,1}, {0x002b8240,1}, {0x002b8280,1}, {0x002b82c0,1},
+	{0x002b8a00,1}, {0x002b8a80,1}, {0x002c0000,2}, {0x00300000,65},
+	{0x00300110,1}, {0x00300120,1}, {0x00300130,1}, {0x00300140,1},
+	{0x0030014c,2}, {0x00300200,58}, {0x00300340,4}, {0x00300400,1},
+	{0x00302000,2048}, {0x00320000,16896}, {0x00331800,128},
+	{0x00331c00,128}, {0x00332000,1}, {0x00332400,64}, {0x00338200,1},
+	{0x00338240,1}, {0x00338280,1}, {0x003382c0,1}, {0x00338a00,1},
+	{0x00338a80,1}, {0x00340000,2}};
+
+
+
+uint32_t wregs_count_e1h=1;
+
+static uint32_t const_reg0_e1h[2] = {0x001b1040, 0x001b1000};
+
+
+struct wreg_addr wreg_addrs_e1h[1] = {{0x001b0c00, 256, 2, const_reg0_e1h}};
+
+
+struct hd_param hd_param_e1h={0x497e2efb, 0x00040802, 0x0000001f};
+
diff --git a/sys/dev/bxe/hw_dump_reg_st.h b/sys/dev/bxe/hw_dump_reg_st.h
new file mode 100755
index 0000000..d4019c4
--- /dev/null
+++ b/sys/dev/bxe/hw_dump_reg_st.h
@@ -0,0 +1,80 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef _HW_DUMP_REG_ST_H
+#define	_HW_DUMP_REG_ST_H
+
+#define	BXE_GRCDUMP_BUF_SIZE 	0xE0000
+
+#define	XSTORM_WAITP_ADDRESS    0x2b8a80
+#define	TSTORM_WAITP_ADDRESS    0x2b8a80
+#define	USTORM_WAITP_ADDRESS    0x2b8a80
+#define	CSTORM_WAITP_ADDRESS    0x2b8a80
+#define	TSTORM_CAM_MODE         0x1B1440
+
+/* Register address structure. */
+typedef struct reg_addr {
+	uint32_t	addr;
+	uint32_t	size;
+}*preg_addr;
+
+/* Wide register address structure. */
+typedef struct wreg_addr {
+	uint32_t	addr;
+	uint32_t	size;
+	uint32_t	const_regs_count;
+	uint32_t	* const_regs;
+}*pwreg_addr;
+
+/* Dump header parameters. */
+struct hd_param {
+	uint32_t	time_stamp;
+	uint32_t	diag_ver;
+	uint32_t	grc_dump_ver;
+};
+
+/* Global parameters. */
+extern struct	wreg_addr wreg_addrs_e1[];
+extern struct	reg_addr reg_addrs_e1[];
+extern uint32_t	regs_count_e1;
+extern uint32_t	wregs_count_e1;
+extern struct	hd_param hd_param_e1;
+
+extern struct	wreg_addr wreg_addrs_e1h[];
+extern struct	reg_addr reg_addrs_e1h[];
+extern uint32_t	regs_count_e1h;
+extern uint32_t	wregs_count_e1h;
+extern struct	hd_param hd_param_e1h;
+
+#endif //_HW_DUMP_REG_ST_H
diff --git a/sys/dev/bxe/if_bxe.c b/sys/dev/bxe/if_bxe.c
new file mode 100755
index 0000000..48f158e
--- /dev/null
+++ b/sys/dev/bxe/if_bxe.c
@@ -0,0 +1,17294 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * The following controllers are supported by this driver:
+ *   BCM57710  A1+
+ *   BCM57711  A0+
+ *   BCM57711E A0+
+ *
+ * The following controllers are not supported by this driver:
+ *   BCM57710  A0 (pre-production)
+ *
+ * External PHY References:
+ * ------------------------
+ * BCM8073  - Dual Port 10GBase-KR Ethernet PHY
+ * BCM8705  - 10Gb Ethernet Serial Transceiver
+ * BCM8706  - 10Gb Ethernet LRM PHY
+ * BCM8726  - Dual Port 10Gb Ethernet LRM PHY
+ * BCM8727  - Dual Port 10Gb Ethernet LRM PHY
+ * BCM8481  - Single Port 10GBase-T Ethernet PHY
+ * BCM84823 - Dual Port 10GBase-T Ethernet PHY
+ * SFX7101  - Solarflare 10GBase-T Ethernet PHY
+ *
+ */
+
+#include "opt_bxe.h"
+#include "bxe_include.h"
+#include "if_bxe.h"
+#include "bxe_init.h"
+
+#include "hw_dump_reg_st.h"
+#include "dump_e1.h"
+#include "dump_e1h.h"
+
+#include "bxe_self_test.h"
+
+/* BXE Debug Options */
+#ifdef BXE_DEBUG
+	uint32_t bxe_debug = BXE_WARN;
+
+/*          0 = Never              */
+/*          1 = 1 in 2,147,483,648 */
+/*        256 = 1 in     8,388,608 */
+/*       2048 = 1 in     1,048,576 */
+/*      65536 = 1 in        32,768 */
+/*    1048576 = 1 in         2,048 */
+/*  268435456 =	1 in             8 */
+/*  536870912 = 1 in             4 */
+/* 1073741824 = 1 in             2 */
+
+/* Controls how often to simulate an mbuf allocation failure. */
+int bxe_debug_mbuf_allocation_failure = 0;
+
+/* Controls how often to simulate a DMA mapping failure. */
+int bxe_debug_dma_map_addr_failure = 0;
+
+/* Controls how often to received frame error. */
+int bxe_debug_received_frame_error = 0;
+
+/* Controls how often to simulate a bootcode failure. */
+int bxe_debug_bootcode_running_failure = 0;
+#endif
+
+#define	MDIO_INDIRECT_REG_ADDR	0x1f
+#define	MDIO_SET_REG_BANK(sc, reg_bank)         \
+	bxe_mdio22_write(sc, MDIO_INDIRECT_REG_ADDR, reg_bank)
+
+#define	MDIO_ACCESS_TIMEOUT	1000
+#define	BMAC_CONTROL_RX_ENABLE	2
+
+/* BXE Build Time Options */
+/* #define BXE_NVRAM_WRITE 1 */
+#define	USE_DMAE 1
+
+/*
+ * PCI Device ID Table
+ * Used by bxe_probe() to identify the devices supported by this driver.
+ */
+#define	BXE_DEVDESC_MAX		64
+
+static struct bxe_type bxe_devs[] = {
+	/* BCM57710 Controllers and OEM boards. */
+	{ BRCM_VENDORID, BRCM_DEVICEID_BCM57710, PCI_ANY_ID,  PCI_ANY_ID,
+	    "Broadcom NetXtreme II BCM57710 10GbE" },
+	/* BCM57711 Controllers and OEM boards. */
+	{ BRCM_VENDORID, BRCM_DEVICEID_BCM57711, PCI_ANY_ID,  PCI_ANY_ID,
+	    "Broadcom NetXtreme II BCM57711 10GbE" },
+	/* BCM57711E Controllers and OEM boards. */
+	{ BRCM_VENDORID, BRCM_DEVICEID_BCM57711E, PCI_ANY_ID,  PCI_ANY_ID,
+	    "Broadcom NetXtreme II BCM57711E 10GbE" },
+	{0, 0, 0, 0, NULL}
+};
+
+/*
+ * FreeBSD device entry points.
+ */
+static int  bxe_probe(device_t);
+static int  bxe_attach(device_t);
+static int  bxe_detach(device_t);
+static int  bxe_shutdown(device_t);
+
+static void bxe_print_adapter_info(struct bxe_softc *);
+static void bxe_probe_pci_caps(struct bxe_softc *);
+static void bxe_link_settings_supported(struct bxe_softc *, uint32_t);
+static void bxe_link_settings_requested(struct bxe_softc *);
+static int  bxe_get_function_hwinfo(struct bxe_softc *);
+static void bxe_get_port_hwinfo(struct bxe_softc *);
+static void bxe_get_common_hwinfo(struct bxe_softc *);
+static void bxe_undi_unload(struct bxe_softc *);
+static int  bxe_setup_leading(struct bxe_softc *);
+static int  bxe_stop_leading(struct bxe_softc *);
+static int  bxe_setup_multi(struct bxe_softc *, int);
+static int  bxe_stop_multi(struct bxe_softc *, int);
+static int  bxe_stop_locked(struct bxe_softc *, int);
+static void bxe_init_locked(struct bxe_softc *, int);
+static int  bxe_wait_ramrod(struct bxe_softc *, int, int, int *, int);
+static void bxe_init_str_wr(struct bxe_softc *, uint32_t, const uint32_t *,
+	    uint32_t);
+static void bxe_init_ind_wr(struct bxe_softc *, uint32_t, const uint32_t *,
+	    uint16_t);
+static void bxe_init_wr_64(struct bxe_softc *, uint32_t, const uint32_t *,
+	    uint32_t);
+static void bxe_write_big_buf(struct bxe_softc *, uint32_t, uint32_t);
+static void bxe_init_fill(struct bxe_softc *, uint32_t, int, uint32_t);
+static void bxe_init_block(struct bxe_softc *, uint32_t, uint32_t);
+static void bxe_init(void *);
+static void bxe_release_resources(struct bxe_softc *);
+static void bxe_reg_wr_ind(struct bxe_softc *, uint32_t, uint32_t);
+static uint32_t bxe_reg_rd_ind(struct bxe_softc *, uint32_t);
+static void bxe_post_dmae(struct bxe_softc *, struct dmae_command *, int);
+static void bxe_wb_wr(struct bxe_softc *, int, uint32_t, uint32_t);
+static __inline uint32_t bxe_reg_poll(struct bxe_softc *, uint32_t,
+	    uint32_t, int, int);
+static int  bxe_mc_assert(struct bxe_softc *);
+static void bxe_panic_dump(struct bxe_softc *);
+static void bxe_int_enable(struct bxe_softc *);
+static void bxe_int_disable(struct bxe_softc *);
+
+static int  bxe_nvram_acquire_lock(struct bxe_softc *);
+static int  bxe_nvram_release_lock(struct bxe_softc *);
+static void bxe_nvram_enable_access(struct bxe_softc *);
+static void bxe_nvram_disable_access(struct bxe_softc *);
+static int  bxe_nvram_read_dword	(struct bxe_softc *, uint32_t, uint32_t *,
+	    uint32_t);
+static int  bxe_nvram_read(struct bxe_softc *, uint32_t, uint8_t *, int);
+
+#ifdef BXE_NVRAM_WRITE_SUPPORT
+static int  bxe_nvram_write_dword(struct bxe_softc *, uint32_t, uint32_t,
+	    uint32_t);
+static int  bxe_nvram_write1(struct bxe_softc *, uint32_t, uint8_t *, int);
+static int  bxe_nvram_write(struct bxe_softc *, uint32_t, uint8_t *, int);
+#endif
+
+static int bxe_nvram_test(struct bxe_softc *);
+
+static __inline void bxe_ack_sb(struct bxe_softc *, uint8_t, uint8_t, uint16_t,
+	    uint8_t, uint8_t);
+static __inline uint16_t bxe_update_fpsb_idx(struct bxe_fastpath *);
+static uint16_t bxe_ack_int(struct bxe_softc *);
+static void bxe_sp_event(struct bxe_fastpath *, union eth_rx_cqe *);
+static int  bxe_acquire_hw_lock(struct bxe_softc *, uint32_t);
+static int  bxe_release_hw_lock(struct bxe_softc *, uint32_t);
+static void bxe_acquire_phy_lock(struct bxe_softc *);
+static void bxe_release_phy_lock(struct bxe_softc *);
+static void bxe_pmf_update(struct bxe_softc *);
+static void bxe_init_port_minmax(struct bxe_softc *);
+static void bxe_link_attn(struct bxe_softc *);
+
+static int  bxe_sp_post(struct bxe_softc *, int, int, uint32_t, uint32_t, int);
+static int  bxe_acquire_alr(struct bxe_softc *);
+static void bxe_release_alr(struct bxe_softc *);
+static uint16_t  bxe_update_dsb_idx(struct bxe_softc *);
+static void bxe_attn_int_asserted(struct bxe_softc *, uint32_t);
+static __inline void bxe_attn_int_deasserted0(struct bxe_softc *, uint32_t);
+static __inline void bxe_attn_int_deasserted1(struct bxe_softc *, uint32_t);
+static __inline void bxe_attn_int_deasserted2(struct bxe_softc *, uint32_t);
+static __inline void bxe_attn_int_deasserted3(struct bxe_softc *, uint32_t);
+static void bxe_attn_int_deasserted(struct bxe_softc *, uint32_t);
+static void bxe_attn_int(struct bxe_softc *);
+
+static void bxe_stats_storm_post(struct bxe_softc *);
+static void bxe_stats_init(struct bxe_softc *);
+static void bxe_stats_hw_post(struct bxe_softc *);
+static int  bxe_stats_comp(struct bxe_softc *);
+static void bxe_stats_pmf_update(struct bxe_softc *);
+static void bxe_stats_port_base_init(struct bxe_softc *);
+static void bxe_stats_port_init(struct bxe_softc *);
+static void bxe_stats_func_base_init(struct bxe_softc *);
+static void bxe_stats_func_init(struct bxe_softc *);
+static void bxe_stats_start(struct bxe_softc *);
+static void bxe_stats_pmf_start(struct bxe_softc *);
+static void bxe_stats_restart(struct bxe_softc *);
+static void bxe_stats_bmac_update(struct bxe_softc *);
+static void bxe_stats_emac_update(struct bxe_softc *);
+static int  bxe_stats_hw_update(struct bxe_softc *);
+static int  bxe_stats_storm_update(struct bxe_softc *);
+static void bxe_stats_func_base_update(struct bxe_softc *);
+static void bxe_stats_update(struct bxe_softc *);
+static void bxe_stats_port_stop(struct bxe_softc *);
+static void bxe_stats_stop(struct bxe_softc *);
+static void bxe_stats_do_nothing(struct bxe_softc *);
+static void bxe_stats_handle(struct bxe_softc *, enum bxe_stats_event);
+
+static int  bxe_tx_encap(struct bxe_fastpath *, struct mbuf **);
+static void bxe_tx_start(struct ifnet *);
+static void bxe_tx_start_locked(struct ifnet *, struct bxe_fastpath *);
+static int  bxe_ioctl(struct ifnet *, u_long, caddr_t);
+static __inline int bxe_has_rx_work(struct bxe_fastpath *);
+static __inline int bxe_has_tx_work(struct bxe_fastpath *);
+
+static void bxe_intr_legacy(void *);
+static void bxe_task_sp(void *, int);
+static void bxe_intr_sp(void *);
+static void bxe_task_fp(void *, int);
+static void bxe_intr_fp(void *);
+static void bxe_zero_sb(struct bxe_softc *, int);
+static void bxe_init_sb(struct bxe_softc *, struct host_status_block *,
+	    bus_addr_t, int);
+static void bxe_zero_def_sb(struct bxe_softc *);
+static void bxe_init_def_sb(struct bxe_softc *, struct host_def_status_block *,
+	    bus_addr_t, int);
+static void bxe_update_coalesce(struct bxe_softc *);
+static __inline void bxe_update_rx_prod(struct bxe_softc *,
+	    struct bxe_fastpath *, uint16_t, uint16_t, uint16_t);
+static void bxe_clear_sge_mask_next_elems(struct bxe_fastpath *);
+static __inline void bxe_init_sge_ring_bit_mask(struct bxe_fastpath *);
+static __inline void bxe_free_tpa_pool(struct bxe_fastpath *, int);
+static __inline void bxe_free_rx_sge(struct bxe_softc *, struct bxe_fastpath *,
+	    uint16_t);
+static __inline void bxe_free_rx_sge_range(struct bxe_softc *,
+	    struct bxe_fastpath *, int);
+static struct mbuf *bxe_alloc_mbuf(struct bxe_fastpath *, int);
+static int  bxe_map_mbuf(struct bxe_fastpath *, struct mbuf *, bus_dma_tag_t,
+	    bus_dmamap_t, bus_dma_segment_t *);
+static struct mbuf *bxe_alloc_tpa_mbuf(struct bxe_fastpath *, int, int);
+static int  bxe_alloc_rx_sge(struct bxe_softc *, struct bxe_fastpath *,
+	    uint16_t);
+static void bxe_init_rx_chains(struct bxe_softc *);
+static void bxe_init_tx_chains(struct bxe_softc *);
+static void bxe_free_rx_chains(struct bxe_softc *);
+static void bxe_free_tx_chains(struct bxe_softc *);
+static void bxe_init_sp_ring(struct bxe_softc *);
+static void bxe_init_context(struct bxe_softc *);
+static void bxe_init_ind_table(struct bxe_softc *);
+static void bxe_set_client_config(struct bxe_softc *);
+static void bxe_set_storm_rx_mode(struct bxe_softc *);
+static void bxe_init_internal_common(struct bxe_softc *);
+static void bxe_init_internal_port(struct bxe_softc *);
+
+static void bxe_init_internal_func(struct bxe_softc *);
+static void bxe_init_internal(struct bxe_softc *, uint32_t);
+static void bxe_init_nic(struct bxe_softc *, uint32_t);
+static int  bxe_gunzip_init(struct bxe_softc *);
+static void bxe_lb_pckt(struct bxe_softc *);
+static int  bxe_int_mem_test(struct bxe_softc *);
+static void bxe_enable_blocks_attention (struct bxe_softc *);
+
+static void bxe_init_pxp(struct bxe_softc *);
+static int  bxe_init_common(struct bxe_softc *);
+static int  bxe_init_port(struct bxe_softc *);
+static void bxe_ilt_wr(struct bxe_softc *, uint32_t, bus_addr_t);
+static int  bxe_init_func(struct bxe_softc *);
+static int  bxe_init_hw(struct bxe_softc *, uint32_t);
+static int  bxe_fw_command(struct bxe_softc *, uint32_t);
+static void bxe_dma_free(struct bxe_softc *);
+static void bxe_dmamem_free(struct bxe_softc *, bus_dma_tag_t, caddr_t,
+	    bus_dmamap_t);
+static void bxe_dma_map_addr(void *, bus_dma_segment_t *, int, int);
+static int  bxe_dma_alloc(device_t);
+static int  bxe_dmamem_alloc(struct bxe_softc *, bus_dma_tag_t, bus_dmamap_t,
+	    void *, uint32_t, bus_addr_t *);
+static void bxe_set_mac_addr_e1(struct bxe_softc *, int);
+static void bxe_set_mac_addr_e1h(struct bxe_softc *, int);
+static void bxe_set_rx_mode(struct bxe_softc *);
+static void bxe_reset_func(struct bxe_softc *);
+static void bxe_reset_port(struct bxe_softc *);
+static void bxe_reset_common(struct bxe_softc *);
+static void bxe_reset_chip(struct bxe_softc *, uint32_t);
+static int  bxe_ifmedia_upd(struct ifnet *);
+static void bxe_ifmedia_status(struct ifnet *, struct ifmediareq *);
+static __inline void bxe_update_last_max_sge(struct bxe_fastpath *, uint16_t);
+static void bxe_update_sge_prod(struct bxe_fastpath *,
+	    struct eth_fast_path_rx_cqe *);
+static void bxe_tpa_start(struct bxe_fastpath *, uint16_t, uint16_t, uint16_t);
+static int  bxe_fill_frag_mbuf(struct bxe_softc *, struct bxe_fastpath *,
+	    struct mbuf *, struct eth_fast_path_rx_cqe *, uint16_t);
+static void bxe_tpa_stop(struct bxe_softc *, struct bxe_fastpath *, uint16_t,
+	    int, int, union eth_rx_cqe *, uint16_t);
+static void bxe_rxeof(struct bxe_fastpath *);
+static void bxe_txeof(struct bxe_fastpath *);
+static int  bxe_get_buf(struct bxe_fastpath *, struct mbuf *, uint16_t);
+static void bxe_watchdog(struct bxe_softc *);
+static int  bxe_change_mtu(struct bxe_softc *, int);
+static void bxe_tick(void *);
+static void bxe_add_sysctls(struct bxe_softc *);
+static void bxe_gunzip_end(struct bxe_softc *);
+
+static void bxe_write_dmae_phys_len(struct bxe_softc *, bus_addr_t, uint32_t,
+	    uint32_t);
+
+void bxe_write_dmae(struct bxe_softc *, bus_addr_t, uint32_t, uint32_t);
+void bxe_read_dmae(struct bxe_softc *, uint32_t, uint32_t);
+int  bxe_set_gpio(struct bxe_softc *, int, uint32_t, uint8_t);
+int  bxe_get_gpio(struct bxe_softc *, int, uint8_t);
+int  bxe_set_spio(struct bxe_softc *, int, uint32_t);
+int  bxe_set_gpio_int(struct bxe_softc *, int, uint32_t, uint8_t);
+
+/*
+ * BXE Debug Data Structure Dump Routines
+ */
+
+#ifdef BXE_DEBUG
+static int bxe_sysctl_driver_state(SYSCTL_HANDLER_ARGS);
+static int bxe_sysctl_hw_state(SYSCTL_HANDLER_ARGS);
+static int bxe_sysctl_dump_fw(SYSCTL_HANDLER_ARGS);
+static int bxe_sysctl_dump_cqe_chain(SYSCTL_HANDLER_ARGS);
+static int bxe_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS);
+static int bxe_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS);
+static int bxe_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
+static int bxe_sysctl_breakpoint(SYSCTL_HANDLER_ARGS);
+static void bxe_validate_rx_packet(struct bxe_fastpath *, uint16_t,
+	    union eth_rx_cqe *, struct mbuf *);
+static void bxe_dump_grc(struct bxe_softc *, int);
+static void bxe_dump_enet(struct bxe_softc *,struct mbuf *);
+static void bxe_dump_mbuf (struct bxe_softc *, struct mbuf *);
+static void bxe_dump_tx_mbuf_chain(struct bxe_softc *, int, int);
+static void bxe_dump_rx_mbuf_chain(struct bxe_softc *, int, int);
+static void bxe_dump_pbd_locked(struct bxe_softc *,int,
+	    struct eth_tx_parse_bd *);
+static void bxe_dump_txbd_locked(struct bxe_fastpath *, int,
+	    struct eth_tx_bd *);
+static void bxe_dump_rxbd_locked(struct bxe_fastpath *, int,
+	    struct eth_rx_bd *);
+static void bxe_dump_cqe_locked(struct bxe_fastpath *, int, union eth_rx_cqe *);
+static void bxe_dump_tx_chain(struct bxe_fastpath *, int, int);
+static void bxe_dump_cqe_chain(struct bxe_fastpath *, int, int);
+static void bxe_dump_rx_chain(struct bxe_fastpath *, int, int);
+static void bxe_dump_status_block(struct bxe_softc *);
+static void bxe_dump_stats_block(struct bxe_softc *);
+static void bxe_dump_fp_state(struct bxe_fastpath *);
+static void bxe_dump_port_state_locked(struct bxe_softc *);
+static void bxe_dump_link_vars_state_locked(struct bxe_softc *);
+static void bxe_dump_link_params_state_locked(struct bxe_softc *);
+static void bxe_dump_driver_state(struct bxe_softc *);
+static void bxe_dump_hw_state(struct bxe_softc *);
+static void bxe_dump_fw(struct bxe_softc *);
+static void bxe_decode_mb_msgs(struct bxe_softc *, uint32_t, uint32_t);
+static void bxe_decode_ramrod_cmd(struct bxe_softc *, int);
+static void bxe_breakpoint(struct bxe_softc *);
+#endif
+
+
+#define	BXE_DRIVER_VERSION	"1.5.52_preliminary"
+
+static void bxe_init_e1_firmware(struct bxe_softc *sc);
+static void bxe_init_e1h_firmware(struct bxe_softc *sc);
+
+/*
+ * FreeBSD device dispatch table.
+ */
+static device_method_t bxe_methods[] = {
+	/* Device interface (device_if.h) */
+	DEVMETHOD(device_probe,		bxe_probe),
+	DEVMETHOD(device_attach,	bxe_attach),
+	DEVMETHOD(device_detach,	bxe_detach),
+	DEVMETHOD(device_shutdown,	bxe_shutdown),
+
+	/* Bus interface (bus_if.h) */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
+
+	KOBJMETHOD_END
+};
+
+static driver_t bxe_driver = {
+	"bxe",
+	bxe_methods,
+	sizeof(struct bxe_softc)
+};
+
+static devclass_t bxe_devclass;
+
+MODULE_DEPEND(bxe, pci, 1, 1, 1);
+MODULE_DEPEND(bxe, ether, 1, 1, 1);
+DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0);
+
+/*
+ * Tunable device values
+ */
+SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters");
+/* Allowable values are TRUE (1) or FALSE (0). */
+
+static int bxe_stats_enable = FALSE;
+TUNABLE_INT("hw.bxe.stats_enable", &bxe_stats_enable);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, stats_enable, CTLFLAG_RDTUN, &bxe_stats_enable,
+    0, "stats Enable/Disable");
+
+static int bxe_dcc_enable = FALSE;
+TUNABLE_INT("hw.bxe.dcc_enable", &bxe_dcc_enable);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, dcc_enable, CTLFLAG_RDTUN, &bxe_dcc_enable,
+    0, "dcc Enable/Disable");
+
+/* Allowable values are TRUE (1) or FALSE (0). */
+static int bxe_tso_enable = TRUE;
+TUNABLE_INT("hw.bxe.tso_enable", &bxe_tso_enable);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bxe_tso_enable,
+    0, "TSO Enable/Disable");
+
+/* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ). */
+static int bxe_int_mode = 2;
+TUNABLE_INT("hw.bxe.int_mode", &bxe_int_mode);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, int_mode, CTLFLAG_RDTUN, &bxe_int_mode,
+    0, "Interrupt (MSI-X|MSI|INTx) mode");
+
+/*
+ * Specifies whether the driver should disable Transparent Packet
+ * Aggregation (TPA, also known as LRO).  By default TPA is enabled.
+ *
+ * Allowable values are TRUE (1) or FALSE (0).
+ */
+static int bxe_tpa_enable = FALSE;
+TUNABLE_INT("hw.bxe.tpa_enable", &bxe_tpa_enable);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, tpa_enable, CTLFLAG_RDTUN, &bxe_tpa_enable,
+    0, "TPA Enable/Disable");
+
+
+/*
+ * Specifies the number of queues that will be used when a multi-queue
+ * RSS mode is selected  using bxe_multi_mode below.  Some RSS modes
+ * require additional queue configuration which may conflict with this
+ * setting.  In that case this value will be overriden.
+ *
+ * Allowable values are 0 (Auto) or 1 to MAX_CONTEXT (fixed queue number).
+ */
+static int bxe_queue_count = 0;
+TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN, &bxe_queue_count,
+    0, "Multi-Queue queue count");
+
+/*
+ * ETH_RSS_MODE_DISABLED (0)
+ * Disables all multi-queue/packet sorting algorithms.  Each
+ * received frame is routed to the same receive queue.
+ *
+ * ETH_RSS_MODE_REGULAR (1)
+ * The default mode which assigns incoming frames to receive
+ * queues according to RSS (i.e a 2-tuple match on the source/
+ * destination IP address or a 4-tuple match on the source/
+ * destination IP address and the source/destination TCP port).
+ *
+ */
+static int bxe_multi_mode = ETH_RSS_MODE_DISABLED;
+TUNABLE_INT("hw.bxe.multi_mode", &bxe_multi_mode);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, multi_mode, CTLFLAG_RDTUN, &bxe_multi_mode,
+    0, "Multi-Queue Mode");
+
+static uint32_t bxe_pri_map = 0x0;
+TUNABLE_INT("hw.bxe.pri_map", &bxe_pri_map);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, pri_map, CTLFLAG_RDTUN, &bxe_pri_map,
+    0, "Priority map");
+
+/*
+ * Host interrupt coalescing is controller by these values.
+ * The first frame always causes an interrupt but subsequent
+ * frames are coalesced until the RX/TX ticks timer value
+ * expires and another interrupt occurs.  (Ticks are measured
+ * in microseconds.)
+ */
+static uint32_t bxe_rx_ticks = 25;
+TUNABLE_INT("hw.bxe.rx_ticks", &bxe_rx_ticks);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, &bxe_rx_ticks,
+    0, "Receive ticks");
+
+static uint32_t bxe_tx_ticks = 50;
+TUNABLE_INT("hw.bxe.tx_ticks", &bxe_tx_ticks);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, &bxe_tx_ticks,
+    0, "Transmit ticks");
+
+/*
+ * Allows the PCIe maximum read request size value to be manually
+ * set during initialization rather than automatically determined
+ * by the driver.
+ *
+ * Allowable values are:
+ * -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB)
+ */
+static int bxe_mrrs = -1;
+TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN, &bxe_mrrs,
+    0, "PCIe maximum read request size.");
+
+/*
+ * Allows setting the maximum number of received frames to process
+ * during an interrupt.
+ *
+ * Allowable values are:
+ * -1 (Unlimited), 0 (None), otherwise specifies the number of RX frames.
+ */
+static int bxe_rx_limit = -1;
+TUNABLE_INT("hw.bxe.rx_limit", &bxe_rx_limit);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, rx_limit, CTLFLAG_RDTUN, &bxe_rx_limit,
+    0, "Maximum received frames processed during an interrupt.");
+
+/*
+ * Allows setting the maximum number of transmit frames to process
+ * during an interrupt.
+ *
+ * Allowable values are:
+ * -1 (Unlimited), 0 (None), otherwise specifies the number of TX frames.
+ */
+static int bxe_tx_limit = -1;
+TUNABLE_INT("hw.bxe.tx_limit", &bxe_tx_limit);
+SYSCTL_UINT(_hw_bxe, OID_AUTO, tx_limit, CTLFLAG_RDTUN, &bxe_tx_limit,
+	0, "Maximum transmit frames processed during an interrupt.");
+
+/*
+ * Global variables
+ */
+
+/* 0 is common, 1 is port 0, 2 is port 1. */
+static int load_count[3];
+
+/* Tracks whether MCP firmware is running. */
+static int nomcp;
+
+#ifdef BXE_DEBUG
+/*
+ * A debug version of the 32 bit OS register write function to
+ * capture/display values written to the controller.
+ *
+ * Returns:
+ *   None.
+ */
+void
+bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val)
+{
+
+	if ((offset % 4) != 0) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Warning! Unaligned write to 0x%jX!\n", __FUNCTION__,
+		    (uintmax_t)offset);
+	}
+
+	DBPRINT(sc, BXE_INSANE, "%s(): offset = 0x%jX, val = 0x%08X\n",
+	    __FUNCTION__, (uintmax_t)offset, val);
+
+	bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val);
+}
+
+/*
+ * A debug version of the 16 bit OS register write function to
+ * capture/display values written to the controller.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val)
+{
+
+	if ((offset % 2) != 0) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Warning! Unaligned write to 0x%jX!\n", __FUNCTION__,
+		    (uintmax_t)offset);
+	}
+
+	DBPRINT(sc, BXE_INSANE, "%s(): offset = 0x%jX, val = 0x%04X\n",
+	    __FUNCTION__, (uintmax_t)offset, val);
+
+	bus_space_write_2(sc->bxe_btag, sc->bxe_bhandle, offset, val);
+}
+
+/*
+ * A debug version of the 8 bit OS register write function to
+ * capture/display values written to the controller.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val)
+{
+
+	DBPRINT(sc, BXE_INSANE, "%s(): offset = 0x%jX, val = 0x%02X\n",
+	    __FUNCTION__, (uintmax_t)offset, val);
+
+	bus_space_write_1(sc->bxe_btag, sc->bxe_bhandle, offset, val);
+}
+
+/*
+ * A debug version of the 32 bit OS register read function to
+ * capture/display values read from the controller.
+ *
+ * Returns:
+ *   32bit value read.
+ */
+uint32_t
+bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset)
+{
+	uint32_t val;
+
+	if ((offset % 4) != 0) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Warning! Unaligned read from 0x%jX!\n",
+		    __FUNCTION__, (uintmax_t)offset);
+	}
+
+	val = bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset);
+
+	DBPRINT(sc, BXE_INSANE, "%s(): offset = 0x%jX, val = 0x%08X\n",
+		__FUNCTION__, (uintmax_t)offset, val);
+
+	return (val);
+}
+
+/*
+ * A debug version of the 16 bit OS register read function to
+ * capture/display values read from the controller.
+ *
+ * Returns:
+ *   16bit value read.
+ */
+static uint16_t
+bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset)
+{
+	uint16_t val;
+
+	if ((offset % 2) != 0) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Warning! Unaligned read from 0x%jX!\n",
+		    __FUNCTION__, (uintmax_t)offset);
+	}
+
+	val = bus_space_read_2(sc->bxe_btag, sc->bxe_bhandle, offset);
+
+	DBPRINT(sc, BXE_INSANE, "%s(): offset = 0x%jX, val = 0x%08X\n",
+	    __FUNCTION__, (uintmax_t)offset, val);
+
+	return (val);
+}
+
+
+/*
+ * A debug version of the 8 bit OS register write function to
+ * capture/display values written to the controller.
+ *
+ * Returns:
+ *   8bit value read.
+ */
+static uint8_t
+bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset)
+{
+	uint8_t val = bus_space_read_1(sc->bxe_btag, sc->bxe_bhandle, offset);
+
+	DBPRINT(sc, BXE_INSANE, "%s(): offset = 0x%jX, val = 0x%02X\n",
+		__FUNCTION__, (uintmax_t)offset, val);
+
+	return(val);
+}
+#endif
+
+static void
+bxe_read_mf_cfg(struct bxe_softc *sc)
+{
+	int func, vn;
+
+	for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+		func = 2 * vn + BP_PORT(sc);
+		sc->mf_config[vn] =
+		    SHMEM_RD(sc,mf_cfg.func_mf_config[func].config);
+	}
+}
+
+
+static void
+bxe_e1h_disable(struct bxe_softc *sc)
+{
+	int port;
+
+	port = BP_PORT(sc);
+	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
+	sc->bxe_ifp->if_drv_flags = 0;
+}
+
+static void
+bxe_e1h_enable(struct bxe_softc *sc)
+{
+	int port;
+
+	port = BP_PORT(sc);
+	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
+	sc->bxe_ifp->if_drv_flags = IFF_DRV_RUNNING;
+}
+
+/*
+ * Calculates the sum of vn_min_rates.
+ * It's needed for further normalizing of the min_rates.
+ * Returns:
+ *   sum of vn_min_rates.
+ *     or
+ *   0 - if all the min_rates are 0. In the later case fainess
+ * 	 algorithm should be deactivated. If not all min_rates are
+ * 	 zero then those that are zeroes will be set to 1.
+ */
+static void
+bxe_calc_vn_wsum(struct bxe_softc *sc)
+{
+	uint32_t vn_cfg, vn_min_rate;
+	int all_zero, vn;
+
+	DBENTER(1);
+
+	all_zero = 1;
+	sc->vn_wsum = 0;
+	for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+		vn_cfg = sc->mf_config[vn];
+		vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
+		    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
+		/* Skip hidden vns */
+		if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
+			continue;
+		/* If min rate is zero - set it to 1. */
+		if (!vn_min_rate)
+			vn_min_rate = DEF_MIN_RATE;
+		else
+			all_zero = 0;
+
+		sc->vn_wsum += vn_min_rate;
+	}
+
+	/* ... only if all min rates are zeros - disable fairness */
+	if (all_zero)
+		sc->cmng.flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
+	else
+		sc->cmng.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
+
+	DBEXIT(1);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_vn_minmax(struct bxe_softc *sc, int vn)
+{
+	struct rate_shaping_vars_per_vn m_rs_vn;
+	struct fairness_vars_per_vn m_fair_vn;
+	uint32_t vn_cfg;
+	uint16_t vn_min_rate, vn_max_rate;
+	int func, i;
+
+	vn_cfg = sc->mf_config[vn];
+	func = 2 * vn + BP_PORT(sc);
+
+	DBENTER(1);
+
+	/* If function is hidden - set min and max to zeroes. */
+	if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
+		vn_min_rate = 0;
+		vn_max_rate = 0;
+	} else {
+		vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
+		    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
+		/*
+		 * If fairness is enabled (i.e. not all min rates are zero),
+		 * and if the current min rate is zero, set it to 1.
+		 * This is a requirement of the algorithm.
+		 */
+		if (sc->vn_wsum && (vn_min_rate == 0))
+			vn_min_rate = DEF_MIN_RATE;
+
+		vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
+		    FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
+
+		if (vn_max_rate == 0)
+			return;
+	}
+	DBPRINT(sc, 1,
+	    "%s(): func %d: vn_min_rate = %d, vn_max_rate = %d, wsum = %d.\n",
+	    __FUNCTION__, func, vn_min_rate, vn_max_rate, sc->vn_wsum);
+
+	memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
+	memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
+
+	/* Global VNIC counter - maximal Mbps for this VNIC. */
+	m_rs_vn.vn_counter.rate = vn_max_rate;
+
+	/* Quota - number of bytes transmitted in this period. */
+	m_rs_vn.vn_counter.quota =
+	    (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
+
+	if (sc->vn_wsum) {
+		/*
+		 * Credit for each period of the fairness algorithm.  The
+		 * number of bytes in T_FAIR (the VNIC shares the port rate).
+		 * vn_wsum should not be larger than 10000, thus
+		 * T_FAIR_COEF / (8 * vn_wsum) will always be grater than zero.
+		 */
+		m_fair_vn.vn_credit_delta =
+		    max((uint32_t)(vn_min_rate * (T_FAIR_COEF /
+		    (8 * sc->vn_wsum))),
+		    (uint32_t)(sc->cmng.fair_vars.fair_threshold * 2));
+	}
+
+	func = BP_FUNC(sc);
+
+	/* Store it to internal memory */
+	for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn) / 4; i++)
+		REG_WR(sc, BAR_XSTORM_INTMEM +
+		    XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + (i * 4),
+		    ((uint32_t *)(&m_rs_vn))[i]);
+
+	for (i = 0; i < sizeof(struct fairness_vars_per_vn) / 4; i++)
+		REG_WR(sc, BAR_XSTORM_INTMEM +
+		    XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + (i * 4),
+		    ((uint32_t *)(&m_fair_vn))[i]);
+	DBEXIT(1);
+}
+
+static void
+bxe_congestionmgmt(struct bxe_softc *sc, uint8_t readshm)
+{
+	int vn;
+
+	/* Read mf conf from shmem. */
+	if (readshm)
+		bxe_read_mf_cfg(sc);
+
+	/* Init rate shaping and fairness contexts */
+	bxe_init_port_minmax(sc);
+
+	/* vn_weight_sum and enable fairness if not 0 */
+	bxe_calc_vn_wsum(sc);
+
+	/* calculate and set min-max rate for each vn */
+	for (vn = 0; vn < E1HVN_MAX; vn++)
+		bxe_init_vn_minmax(sc, vn);
+
+	/* Always enable rate shaping and fairness. */
+	sc->cmng.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
+
+	DBPRINT(sc, 1, "rate shaping set\n");
+
+	if (!sc->vn_wsum)
+		DBPRINT(sc, 1,
+		    "All MIN values are zeroes fairness is disabled\n");
+}
+
+static void
+bxe_dcc_event(struct bxe_softc *sc, uint32_t dcc_event)
+{
+	int i, port;
+
+	if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
+		/*
+		 * This is the only place besides the function initialization
+		 * where the sc->bxe_flags can change so it is done without any
+		 * locks
+		 */
+		if (sc->mf_config[BP_E1HVN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
+			DBPRINT(sc, 1, "mf_cfg function disabled\n");
+			sc->bxe_flags = BXE_STATE_DISABLED;
+			bxe_e1h_disable(sc);
+		} else {
+			DBPRINT(sc, 1, "mf_cfg function enabled\n");
+			sc->bxe_flags = BXE_STATE_OPEN;
+			bxe_e1h_enable(sc);
+		}
+		dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
+	}
+	if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
+		port = BP_PORT(sc);
+		bxe_congestionmgmt(sc, TRUE);
+		for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
+			REG_WR(sc, BAR_XSTORM_INTMEM +
+			       XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
+			       ((uint32_t *)(&sc->cmng))[i]);
+		dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
+	}
+
+	/* Report results to MCP */
+	if (dcc_event)
+		bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE);
+	else
+		bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK);
+}
+
+/*
+ * Device probe function.
+ *
+ * Compares the device to the driver's list of supported devices and
+ * reports back to the OS whether this is the right driver for the device.
+ *
+ * Returns:
+ *   BUS_PROBE_DEFAULT on success, positive value on failure.
+ */
+static int
+bxe_probe(device_t dev)
+{
+	struct bxe_softc *sc;
+	struct bxe_type *t;
+	char *descbuf;
+	uint16_t did, sdid, svid, vid;
+
+	sc = device_get_softc(dev);
+	sc->bxe_dev = dev;
+	t = bxe_devs;
+
+	/* Get the data for the device to be probed. */
+	vid  = pci_get_vendor(dev);
+	did  = pci_get_device(dev);
+	svid = pci_get_subvendor(dev);
+	sdid = pci_get_subdevice(dev);
+
+	DBPRINT(sc, BXE_VERBOSE_LOAD,
+	    "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
+	    "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
+
+	/* Look through the list of known devices for a match. */
+	while (t->bxe_name != NULL) {
+		if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
+		    ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
+		    ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
+			descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
+			if (descbuf == NULL)
+				return (ENOMEM);
+
+			/* Print out the device identity. */
+			snprintf(descbuf, BXE_DEVDESC_MAX,
+			    "%s (%c%d) BXE v:%s\n", t->bxe_name,
+			    (((pci_read_config(dev, PCIR_REVID, 4) &
+			    0xf0) >> 4) + 'A'),
+			    (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
+			    BXE_DRIVER_VERSION);
+
+			device_set_desc_copy(dev, descbuf);
+			free(descbuf, M_TEMP);
+			return (BUS_PROBE_DEFAULT);
+		}
+		t++;
+	}
+
+	return (ENXIO);
+}
+
+/*
+ * Prints useful adapter info.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_print_adapter_info(struct bxe_softc *sc)
+{
+
+	DBENTER(BXE_EXTREME_LOAD);
+
+	/* Hardware chip info. */
+	BXE_PRINTF("ASIC (0x%08X); ", sc->common.chip_id);
+	printf("Rev (%c%d); ", (CHIP_REV(sc) >> 12) + 'A',
+	       (CHIP_METAL(sc) >> 4));
+
+	/* Bus info. */
+	printf("Bus (PCIe x%d, ", sc->pcie_link_width);
+	switch (sc->pcie_link_speed) {
+	case 1:
+		printf("2.5Gbps");
+		break;
+	case 2:
+		printf("5Gbps");
+		break;
+	default:
+		printf("Unknown link speed");
+	}
+
+	/* Device features. */
+	printf("); Flags ( ");
+
+	/* Miscellaneous flags. */
+	if (sc->bxe_flags & BXE_USING_MSI_FLAG)
+		printf("MSI ");
+	if (sc->bxe_flags & BXE_USING_MSIX_FLAG)
+		printf("MSI-X ");
+	if (sc->bxe_flags & BXE_SAFC_TX_FLAG)
+		printf("SAFC ");
+	if (TPA_ENABLED(sc))
+		printf("TPA ");
+
+	printf(") Queues (");
+	switch (sc->multi_mode) {
+	case ETH_RSS_MODE_DISABLED:
+		printf("None");
+		break;
+	case ETH_RSS_MODE_REGULAR:
+		printf("RSS");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	/* Firmware versions and device features. */
+	BXE_PRINTF("Firmware (%d.%d.%d); Bootcode (%d.%d.%d)\n",
+	    BCM_5710_FW_MAJOR_VERSION,
+	    BCM_5710_FW_MINOR_VERSION,
+	    BCM_5710_FW_REVISION_VERSION,
+	    (int)((sc->common.bc_ver & 0xff0000) >> 16),
+	    (int)((sc->common.bc_ver & 0x00ff00) >> 8),
+	    (int)((sc->common.bc_ver & 0x0000ff)));
+
+	DBEXIT(BXE_EXTREME_LOAD);
+}
+
+/*
+ * This function determines and allocates the appropriate
+ * interrupt based on system capabilites and user request.
+ *
+ * The user may force a particular interrupt mode, specify
+ * the number of receive queues, specify the method for
+ * distribuitng received frames to receive queues, or use
+ * the default settings which will automatically select the
+ * best supported combination.  In addition, the OS may or
+ * may not support certain combinations of these settings.
+ * This routine attempts to reconcile the settings requested
+ * by the user with the capabilites available from the system
+ * to select the optimal combination of features.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_interrupt_allocate(struct bxe_softc *sc)
+{
+	device_t dev;
+	int i, rid, rc;
+	int msi_count, msi_required, msi_allocated;
+	int msix_count, msix_required, msix_allocated;
+
+	rc = 0;
+	dev = sc->bxe_dev;
+	msi_count = 0;
+	msi_required = 0;
+	msi_allocated = 0;
+	msix_count = 0;
+	msix_required = 0;
+	msix_allocated = 0;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
+
+	/* Assume SAFC not enabled for TX. */
+	sc->bxe_flags &= ~BXE_SAFC_TX_FLAG;
+
+	/* Clear any previous priority queue mappings. */
+	for (i = 0; i < BXE_MAX_PRIORITY; i++)
+		sc->pri_map[i] = 0;
+
+	/*
+	 * Get our starting point for interrupt mode/number of queues.
+	 * We will progressively step down from MSI-X to MSI to INTx
+	 * and reduce the number of receive queues as necessary to
+	 * match the system capabilities.
+	 */
+	sc->multi_mode = bxe_multi_mode;
+	sc->int_mode = bxe_int_mode;
+
+	/*
+	 * Verify the Priority -> Receive Queue mappings.
+	 */
+	if (sc->int_mode > 0) {
+		/* Multi-queue modes require MSI/MSI-X. */
+		switch (sc->multi_mode) {
+		case ETH_RSS_MODE_DISABLED:
+			/* No multi-queue mode requested. */
+			sc->num_queues = 1;
+			break;
+		case ETH_RSS_MODE_REGULAR:
+			if (sc->int_mode > 1) {
+				/*
+				 * Assume we can use MSI-X
+				 * (max of 16 receive queues).
+				 */
+				sc->num_queues = min((bxe_queue_count ?
+				    bxe_queue_count : mp_ncpus), MAX_CONTEXT);
+			} else {
+				/*
+				 * Assume we can use MSI
+				 * (max of 7 receive queues).
+				 */
+				sc->num_queues = min((bxe_queue_count ?
+				    bxe_queue_count : mp_ncpus),
+				    BXE_MSI_VECTOR_COUNT - 1);
+			}
+			break;
+		default:
+			BXE_PRINTF(
+    			    "%s(%d): Unsupported multi_mode parameter (%d), "
+			    "disabling multi-queue support!\n", __FILE__,
+			    __LINE__, sc->multi_mode);
+			sc->multi_mode = ETH_RSS_MODE_DISABLED;
+			sc->num_queues = 1;
+			break;
+		}
+	} else {
+		/* User	has	forced INTx mode. */
+		sc->multi_mode = ETH_RSS_MODE_DISABLED;
+		sc->num_queues = 1;
+	}
+
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+	    "%s(): Requested: int_mode = %d, multi_mode = %d num_queues = %d\n",
+	    __FUNCTION__, sc->int_mode, sc->multi_mode, sc->num_queues);
+
+#ifdef BXE_DEBUG
+	for (i = 0; i < BXE_MAX_PRIORITY; i++) {
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+		    "%s(): sc->pri_map[%d] = %d.\n", __FUNCTION__, i,
+		    sc->pri_map[i]);
+	}
+#endif
+
+	/* Get the number of available MSI/MSI-X interrupts from the OS. */
+	if (sc->int_mode > 0) {
+		if (sc->bxe_cap_flags & BXE_MSIX_CAPABLE_FLAG)
+			msix_count = pci_msix_count(dev);
+
+		if (sc->bxe_cap_flags & BXE_MSI_CAPABLE_FLAG)
+			msi_count = pci_msi_count(dev);
+
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+		    "%s(): %d MSI and %d MSI-X vectors available.\n",
+		    __FUNCTION__, msi_count, msix_count);
+	}
+
+	/* Try allocating MSI-X interrupt resources. */
+	if ((sc->bxe_cap_flags & BXE_MSIX_CAPABLE_FLAG) &&
+	    (sc->int_mode > 1) && (msix_count > 0) &&
+	    (msix_count >= sc->num_queues)) {
+		/* Ask for the necessary number	of MSI-X vectors. */
+		if (sc->num_queues == 1)
+			msix_allocated = msix_required = 2;
+		else
+			msix_allocated = msix_required = sc->num_queues + 1;
+
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+		    "%s(): Requesting %d MSI-X vectors.\n",
+		    __FUNCTION__, msix_required);
+
+		/* BSD resource identifier */
+		rid = 1;
+		if (pci_alloc_msix(dev, &msix_allocated) == 0) {
+			DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+		"%s(): Required/Allocated (%d/%d) MSI-X vector(s).\n",
+			    __FUNCTION__, msix_required, msix_allocated);
+
+			/* Make sure we got all the interrupts we asked for. */
+			if (msix_allocated >= msix_required) {
+				sc->msix_count = msix_required;
+				sc->bxe_flags |= BXE_USING_MSIX_FLAG;
+				msi_count = 0;
+
+				/* Allocate the MSI-X vectors. */
+				for (i = 0; i < msix_required; i++) {
+					sc->bxe_msix_rid[i] = rid + i +
+					    BP_L_ID(sc);
+					sc->bxe_msix_res[i] =
+					    bus_alloc_resource_any(dev,
+					    SYS_RES_IRQ, &sc->bxe_msix_rid[i],
+					    RF_ACTIVE);
+					/* Report any IRQ allocation errors. */
+					if (sc->bxe_msix_res[i] == NULL) {
+						BXE_PRINTF(
+				"%s(%d): Failed to map MSI-X[%d] vector!\n",
+						    __FILE__, __LINE__, (3));
+						rc = ENXIO;
+						goto bxe_interrupt_allocate_exit;
+					}
+				}
+			} else {
+
+				DBPRINT(sc, BXE_WARN,
+				    "%s(): MSI-X allocation failed!\n",
+				    __FUNCTION__);
+
+				/* Release any resources acquired. */
+				pci_release_msi(dev);
+				sc->bxe_flags &= ~BXE_USING_MSIX_FLAG;
+				sc->msix_count = msix_count = 0;
+
+				/* We'll try MSI next. */
+				sc->int_mode = 1;
+			}
+		}
+	}
+
+	/* Try allocating MSI vector resources. */
+	if ((sc->bxe_cap_flags & BXE_MSI_CAPABLE_FLAG) &&
+	    (sc->int_mode > 0) && (msi_count > 0) &&
+	    (msi_count >= sc->num_queues)) {
+		/* Ask for the necessary number	of MSI vectors. */
+		if (sc->num_queues == 1)
+			msi_required = msi_allocated = 1;
+		else
+			msi_required = msi_allocated = BXE_MSI_VECTOR_COUNT;
+
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+		    "%s(): Requesting %d MSI vectors.\n", __FUNCTION__,
+		    msi_required);
+
+		rid = 1;
+		if (pci_alloc_msi(dev, &msi_allocated) == 0) {
+			DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+			    "%s(): Required/Allocated (%d/%d) MSI vector(s).\n",
+			    __FUNCTION__, msi_required, msi_allocated);
+
+			/*
+			 * Make sure we got all the vectors we asked for.
+			 * XXX
+			 * FreeBSD always gives 8 even if we ask for less.
+			 */
+			if (msi_required >= msi_allocated) {
+				sc->msi_count = msi_required;
+				sc->bxe_flags |= BXE_USING_MSI_FLAG;
+				/* Allocate the MSI vectors. */
+				for (i = 0; i < msi_required; i++) {
+					sc->bxe_msi_rid[i] = i + rid;
+					sc->bxe_msi_res[i] =
+					    bus_alloc_resource_any(dev,
+					    SYS_RES_IRQ, &sc->bxe_msi_rid[i],
+					    RF_ACTIVE);
+					/* Report any IRQ allocation errors. */
+					if (sc->bxe_msi_res[i] == NULL) {
+						BXE_PRINTF(
+				"%s(%d): Failed to map MSI vector (%d)!\n",
+						    __FILE__, __LINE__, (i));
+						rc = ENXIO;
+						goto bxe_interrupt_allocate_exit;
+					}
+				}
+			}
+		} else {
+
+			DBPRINT(sc, BXE_WARN, "%s(): MSI allocation failed!\n",
+			    __FUNCTION__);
+
+			/* Release any resources acquired. */
+			pci_release_msi(dev);
+			sc->bxe_flags &= ~BXE_USING_MSI_FLAG;
+			sc->msi_count = msi_count = 0;
+
+			/* We'll try INTx next. */
+			sc->int_mode = 0;
+		}
+	}
+
+	/* Try allocating INTx resources. */
+	if (sc->int_mode == 0) {
+		sc->num_queues = 1;
+		sc->multi_mode = ETH_RSS_MODE_DISABLED;
+
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+		    "%s(): Requesting legacy INTx interrupt.\n",
+		    __FUNCTION__);
+
+		rid = 0;
+		sc->bxe_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+		    RF_SHAREABLE | RF_ACTIVE);
+		/* Report any IRQ allocation errors. */
+		if (sc->bxe_irq_res == NULL) {
+			BXE_PRINTF("%s(%d): PCI map interrupt failed!\n",
+			    __FILE__, __LINE__);
+			rc = ENXIO;
+			goto bxe_interrupt_allocate_exit;
+		}
+		sc->bxe_irq_rid = rid;
+	}
+
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+	    "%s(): Actual: int_mode = %d, multi_mode = %d, num_queues = %d\n",
+	    __FUNCTION__, sc->int_mode, sc->multi_mode, sc->num_queues);
+
+bxe_interrupt_allocate_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
+	return (rc);
+}
+
+static void
+bxe_interrupt_detach(struct bxe_softc *sc)
+{
+	device_t dev;
+	int i;
+
+	dev = sc->bxe_dev;
+	DBENTER(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+	/* Release interrupt resources. */
+	if ((sc->bxe_flags & BXE_USING_MSIX_FLAG) && sc->msix_count) {
+		for (i = 0; i < sc->msix_count; i++) {
+			if (sc->bxe_msix_tag[i] && sc->bxe_msix_res[i])
+				bus_teardown_intr(dev, sc->bxe_msix_res[i],
+				    sc->bxe_msix_tag[i]);
+		}
+	} else if ((sc->bxe_flags & BXE_USING_MSI_FLAG) && sc->msi_count) {
+		for (i = 0; i < sc->msi_count; i++) {
+			if (sc->bxe_msi_tag[i] && sc->bxe_msi_res[i])
+				bus_teardown_intr(dev, sc->bxe_msi_res[i],
+				    sc->bxe_msi_tag[i]);
+		}
+	} else {
+		if (sc->bxe_irq_tag != NULL)
+			bus_teardown_intr(dev, sc->bxe_irq_res,
+			    sc->bxe_irq_tag);
+	}
+}
+
+/*
+ * This function enables interrupts and attachs to the ISR.
+ *
+ * When using multiple MSI/MSI-X vectors the first vector
+ * is used for slowpath operations while all remaining
+ * vectors are used for fastpath operations.  If only a
+ * single MSI/MSI-X vector is used (SINGLE_ISR) then the
+ * ISR must look for both slowpath and fastpath completions.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_interrupt_attach(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	int i, rc;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
+
+	rc = 0;
+
+#ifdef BXE_TASK
+	/* Setup the slowpath deferred task queue. */
+	TASK_INIT(&sc->task, 0, bxe_task_sp, sc);
+	sc->tq = taskqueue_create_fast("bxe_spq", M_NOWAIT,
+		taskqueue_thread_enqueue, &sc->tq);
+	taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s spq",
+		device_get_nameunit(sc->bxe_dev));
+#endif
+
+	/* Setup interrupt handlers. */
+	if (sc->bxe_flags & BXE_USING_MSIX_FLAG) {
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+		    "%s(): Enabling slowpath MSI-X[0] vector.\n",__FUNCTION__);
+		/*
+		 * Setup the interrupt handler.  Note that we pass the
+		 * driver instance to the interrupt handler for the
+		 * slowpath.
+		 */
+		rc = bus_setup_intr(sc->bxe_dev,
+				    sc->bxe_msix_res[0],
+				    INTR_TYPE_NET | INTR_MPSAFE,
+				    NULL,
+				    bxe_intr_sp,
+				    sc,
+				    &sc->bxe_msix_tag[0]);
+
+		if (rc) {
+			BXE_PRINTF(
+			    "%s(%d): Failed to allocate MSI-X[0] vector!\n",
+			    __FILE__, __LINE__);
+			goto bxe_interrupt_attach_exit;
+		}
+
+		/* Now initialize the fastpath vectors. */
+		for (i = 0; i < (sc->num_queues); i++) {
+			fp = &sc->fp[i];
+			DBPRINT(sc,
+				(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+				"%s(): Enabling MSI-X[%d] vector.\n",
+				__FUNCTION__, i + 1);
+			/*
+			 * Setup the interrupt handler. Note that we pass the
+			 * fastpath context to the interrupt handler in this
+			 * case. Also the first msix_res was used by the sp.
+			 */
+			rc = bus_setup_intr(sc->bxe_dev,
+					    sc->bxe_msix_res[i + 1],
+					    INTR_TYPE_NET | INTR_MPSAFE,
+					    NULL,
+					    bxe_intr_fp,
+					    fp,
+					    &sc->bxe_msix_tag[i + 1]
+					    );
+
+			if (rc) {
+			    BXE_PRINTF(
+			    "%s(%d): Failed to allocate MSI-X[%d] vector!\n",
+			    __FILE__, __LINE__, (i + 1));
+			    goto bxe_interrupt_attach_exit;
+			}
+#ifdef BXE_TASK
+			TASK_INIT(&fp->task, 0, bxe_task_fp, fp);
+			fp->tq = taskqueue_create_fast("bxe_fpq", M_NOWAIT,
+				taskqueue_thread_enqueue, &fp->tq);
+			taskqueue_start_threads(&fp->tq, 1, PI_NET, "%s fpq",
+				device_get_nameunit(sc->bxe_dev));
+#endif
+			fp->state = BXE_FP_STATE_IRQ;
+		}
+	} else if (sc->bxe_flags & BXE_USING_MSI_FLAG) {
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+			"%s(): Enabling slowpath MSI[0] vector.\n",
+			__FUNCTION__);
+		/*
+		 * Setup the interrupt handler.  Note that we pass the driver
+		 * instance to the interrupt handler for the slowpath.
+		 */
+		rc = bus_setup_intr(sc->bxe_dev,sc->bxe_msi_res[0],
+				    INTR_TYPE_NET | INTR_MPSAFE,
+				    NULL,
+				    bxe_intr_sp,
+				    sc,
+				    &sc->bxe_msi_tag[0]
+				    );
+
+		if (rc) {
+			BXE_PRINTF(
+			    "%s(%d): Failed to allocate MSI[0] vector!\n",
+			    __FILE__, __LINE__);
+			goto bxe_interrupt_attach_exit;
+		}
+
+		/* Now initialize the fastpath vectors. */
+		for (i = 0; i < (sc->num_queues); i++) {
+			fp = &sc->fp[i];
+			DBPRINT(sc,
+				(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+				"%s(): Enabling MSI[%d] vector.\n",
+				__FUNCTION__, i + 1);
+			/*
+			 * Setup the interrupt handler.  Note that we pass the
+			 * fastpath context to the interrupt handler in this
+			 * case.
+			 */
+			rc = bus_setup_intr(sc->bxe_dev,
+					    sc->bxe_msi_res[i + 1],
+					    INTR_TYPE_NET | INTR_MPSAFE,
+					    NULL,
+					    bxe_intr_fp,
+					    fp,
+					    &sc->bxe_msi_tag[i + 1]
+					    );
+
+			if (rc) {
+				BXE_PRINTF(
+				"%s(%d): Failed to allocate MSI[%d] vector!\n",
+				__FILE__, __LINE__, (i + 1));
+				goto bxe_interrupt_attach_exit;
+			}
+#ifdef BXE_TASK
+			TASK_INIT(&fp->task, 0, bxe_task_fp, fp);
+			fp->tq = taskqueue_create_fast("bxe_fpq", M_NOWAIT,
+					taskqueue_thread_enqueue, &fp->tq);
+			taskqueue_start_threads(&fp->tq, 1, PI_NET, "%s fpq",
+				device_get_nameunit(sc->bxe_dev));
+#endif
+		}
+
+	} else {
+#ifdef BXE_TASK
+		fp = &sc->fp[0];
+#endif
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
+			"%s(): Enabling INTx interrupts.\n", __FUNCTION__);
+
+		/*
+		 * Setup the interrupt handler.  Note that we pass the
+		 * driver instance to the interrupt handler which
+		 * will handle both the slowpath and fastpath.
+		 */
+		rc = bus_setup_intr(sc->bxe_dev,sc->bxe_irq_res,
+		    INTR_TYPE_NET | INTR_MPSAFE,
+		    NULL,
+		    bxe_intr_legacy,
+		    sc,
+		    &sc->bxe_irq_tag);
+
+		if (rc) {
+			BXE_PRINTF("%s(%d): Failed to allocate interrupt!\n",
+				   __FILE__, __LINE__);
+			goto bxe_interrupt_attach_exit;
+		}
+#ifdef BXE_TASK
+		TASK_INIT(&fp->task, 0, bxe_task_fp, fp);
+		fp->tq = taskqueue_create_fast("bxe_fpq", M_NOWAIT,
+					       taskqueue_thread_enqueue,
+					       &fp->tq
+					       );
+		taskqueue_start_threads(&fp->tq, 1, PI_NET, "%s fpq",
+					device_get_nameunit(sc->bxe_dev)
+					);
+#endif
+	}
+
+bxe_interrupt_attach_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
+	return (rc);
+}
+
+
+/*
+ * PCI Capabilities Probe Function.
+ *
+ * Walks the PCI capabiites list for the device to find what features are
+ * supported.  These capabilites may be enabled/disabled by firmware so it's
+ * best to walk the list rather than hard code any values.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_probe_pci_caps(struct bxe_softc *sc)
+{
+	device_t dev;
+	uint32_t reg;
+	uint16_t link_status;
+
+	dev = sc->bxe_dev;
+	DBENTER(BXE_EXTREME_LOAD);
+
+	/* Check if PCI Power Management capability is enabled. */
+	if (pci_find_extcap(dev, PCIY_PMG, &reg) == 0) {
+		if (reg != 0) {
+			DBPRINT(sc, BXE_EXTREME_LOAD,
+				"%s(): Found PM capability at 0x%04X\n",
+				__FUNCTION__, reg);
+			sc->pm_cap = reg;
+		}
+	}
+
+	/* Check if PCIe capability is enabled. */
+	if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
+		if (reg != 0) {
+			link_status = pci_read_config(dev, reg + 0x12, 2);
+
+			DBPRINT(sc, BXE_EXTREME_LOAD,
+				"%s(): Found PCIe capability at 0x%04X\n",
+				__FUNCTION__, reg);
+
+			/* Handle PCIe 2.0 workarounds for the 57710. */
+			if (CHIP_IS_E1(sc)) {
+				/* Workaround for 57710 errata E4_57710_27462. */
+				sc->pcie_link_speed =
+					(REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
+
+				/* Workaround for 57710 errata E4_57710_27488. */
+				sc->pcie_link_width = (link_status >> 4) & 0x3f;
+				if (sc->pcie_link_speed > 1)
+					sc->pcie_link_width =
+						((link_status >> 4) & 0x3f) >> 1;
+
+			} else {
+
+				sc->pcie_link_speed = link_status & 0xf;
+				sc->pcie_link_width = (link_status >> 4) & 0x3f;
+
+			}
+
+			sc->bxe_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
+			sc->pcie_cap = reg;
+		}
+	}
+
+
+	/* Check if MSI capability is enabled. */
+	if (pci_find_extcap(dev, PCIY_MSI, &reg) == 0) {
+		if (reg != 0) {
+			DBPRINT(sc, BXE_EXTREME_LOAD,
+				"%s(): Found MSI capability at 0x%04X\n",
+				__FUNCTION__, reg);
+			sc->bxe_cap_flags |= BXE_MSI_CAPABLE_FLAG;
+		}
+	}
+
+	/* Check if MSI-X capability is enabled. */
+	if (pci_find_extcap(dev, PCIY_MSIX, &reg) == 0) {
+		if (reg != 0) {
+			DBPRINT(sc, BXE_EXTREME_LOAD,
+				"%s(): Found MSI-X capability at 0x%04X\n",
+				__FUNCTION__, reg);
+			sc->bxe_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
+		}
+	}
+
+	DBEXIT(BXE_EXTREME_LOAD);
+}
+
+static void
+bxe_init_e1_firmware(struct bxe_softc *sc)
+{
+	INIT_OPS(sc)                  = (struct raw_op *)init_ops_e1;
+	INIT_DATA(sc)                 = (const uint32_t *)init_data_e1;
+	INIT_OPS_OFFSETS(sc)          = (const uint16_t *)init_ops_offsets_e1;
+	INIT_TSEM_INT_TABLE_DATA(sc)  = tsem_int_table_data_e1;
+	INIT_TSEM_PRAM_DATA(sc)       = tsem_pram_data_e1;
+	INIT_USEM_INT_TABLE_DATA(sc)  = usem_int_table_data_e1;
+	INIT_USEM_PRAM_DATA(sc)       = usem_pram_data_e1;
+	INIT_XSEM_INT_TABLE_DATA(sc)  = xsem_int_table_data_e1;
+	INIT_XSEM_PRAM_DATA(sc)       = xsem_pram_data_e1;
+	INIT_CSEM_INT_TABLE_DATA(sc)  = csem_int_table_data_e1;
+	INIT_CSEM_PRAM_DATA(sc)       = csem_pram_data_e1;
+}
+
+static void
+bxe_init_e1h_firmware(struct bxe_softc *sc)
+{
+	INIT_OPS(sc)                  = (struct raw_op *)init_ops_e1h;
+	INIT_DATA(sc)                 = (const uint32_t *)init_data_e1h;
+	INIT_OPS_OFFSETS(sc)          = (const uint16_t *)init_ops_offsets_e1h;
+	INIT_TSEM_INT_TABLE_DATA(sc)  = tsem_int_table_data_e1h;
+	INIT_TSEM_PRAM_DATA(sc)       = tsem_pram_data_e1h;
+	INIT_USEM_INT_TABLE_DATA(sc)  = usem_int_table_data_e1h;
+	INIT_USEM_PRAM_DATA(sc)       = usem_pram_data_e1h;
+	INIT_XSEM_INT_TABLE_DATA(sc)  = xsem_int_table_data_e1h;
+	INIT_XSEM_PRAM_DATA(sc)       = xsem_pram_data_e1h;
+	INIT_CSEM_INT_TABLE_DATA(sc)  = csem_int_table_data_e1h;
+	INIT_CSEM_PRAM_DATA(sc)       = csem_pram_data_e1h;
+}
+
+static int
+bxe_init_firmware(struct bxe_softc *sc)
+{
+	if (CHIP_IS_E1(sc))
+		bxe_init_e1_firmware(sc);
+	else if (CHIP_IS_E1H(sc))
+		bxe_init_e1h_firmware(sc);
+	else {
+		BXE_PRINTF("Unsupported chip revision\n");
+		return (ENXIO);
+	}
+	return (0);
+}
+
+/*
+ * Device attach function.
+ *
+ * Allocates device resources, performs secondary chip identification,
+ * resets and initializes the hardware, and initializes driver instance
+ * variables.
+ *
+ * Returns:
+ *   0 = Success, Positive value on failure.
+ */
+static int
+bxe_attach(device_t dev)
+{
+	struct bxe_softc *sc;
+	struct ifnet *ifp;
+	int rid, rc;
+
+	sc = device_get_softc(dev);
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	sc->bxe_dev = dev;
+	sc->bxe_unit = device_get_unit(dev);
+	sc->bxe_func = pci_get_function(dev);
+	sc->bxe_flags = 0;
+	sc->state = BXE_STATE_CLOSED;
+	rc = 0;
+
+	/* Initialize mutexes. */
+	BXE_CORE_LOCK_INIT(sc, device_get_nameunit(dev));
+	BXE_SP_LOCK_INIT(sc, "bxe_sp_lock");
+	BXE_DMAE_LOCK_INIT(sc, "bxe_dmae_lock");
+	BXE_PHY_LOCK_INIT(sc, "bxe_phy_lock");
+	BXE_FWMB_LOCK_INIT(sc, "bxe_fwmb_lock");
+	BXE_PRINT_LOCK_INIT(sc, "bxe_print_lock");
+
+	/* Prepare the tick routine. */
+	callout_init(&sc->bxe_tick_callout, CALLOUT_MPSAFE);
+	ifmedia_init(&sc->bxe_ifmedia, IFM_IMASK, bxe_ifmedia_upd,
+	     bxe_ifmedia_status);
+	ifmedia_add(&sc->bxe_ifmedia, IFM_ETHER | IFM_10G_CX4, 0, NULL);
+	ifmedia_add(&sc->bxe_ifmedia, IFM_ETHER | IFM_10G_CX4 | IFM_FDX, 0,
+	    NULL);
+	ifmedia_add(&sc->bxe_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
+	ifmedia_set(&sc->bxe_ifmedia, IFM_ETHER | IFM_AUTO);
+	sc->bxe_ifmedia.ifm_media = sc->bxe_ifmedia.ifm_cur->ifm_media;
+
+	/* Enable bus master capability */
+	pci_enable_busmaster(dev);
+
+	/*
+	 * Allocate PCI memory resources for BAR0.
+	 * This includes device registers and internal
+	 * processor memory.
+	 */
+	rid = PCIR_BAR(0);
+	sc->bxe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+		&rid, RF_ACTIVE);
+	if (sc->bxe_res == NULL) {
+		BXE_PRINTF("%s(%d):PCI BAR0 memory allocation failed\n",
+			__FILE__, __LINE__);
+		rc = ENXIO;
+		goto bxe_attach_fail;
+	}
+
+	/* Get OS resource handles for BAR0 memory. */
+	sc->bxe_btag    = rman_get_bustag(sc->bxe_res);
+	sc->bxe_bhandle = rman_get_bushandle(sc->bxe_res);
+	sc->bxe_vhandle = (vm_offset_t) rman_get_virtual(sc->bxe_res);
+
+	/*
+	 * Allocate PCI memory resources for BAR2.
+	 * Doorbell (DB) memory.
+	 */
+	rid = PCIR_BAR(2);
+	sc->bxe_db_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+		&rid, RF_ACTIVE);
+	if (sc->bxe_db_res == NULL) {
+		BXE_PRINTF("%s(%d): PCI BAR2 memory allocation failed\n",
+			__FILE__, __LINE__);
+		rc = ENXIO;
+		goto bxe_attach_fail;
+	}
+
+	/* Get OS resource handles for BAR2 memory. */
+	sc->bxe_db_btag    = rman_get_bustag(sc->bxe_db_res);
+	sc->bxe_db_bhandle = rman_get_bushandle(sc->bxe_db_res);
+	sc->bxe_db_vhandle = (vm_offset_t) rman_get_virtual(sc->bxe_db_res);
+
+	/* Put indirect address registers into a sane state. */
+	pci_write_config(sc->bxe_dev, PCICFG_GRC_ADDRESS,
+		PCICFG_VENDOR_ID_OFFSET, 4);
+	REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(sc) * 16, 0);
+	REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(sc) * 16, 0);
+	REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(sc) * 16, 0);
+	REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(sc) * 16, 0);
+
+	/* Get hardware info from shared memory and validate data. */
+	if (bxe_get_function_hwinfo(sc)) {
+		DBPRINT(sc, BXE_WARN, "%s(): Failed to get hardware info!\n",
+			__FUNCTION__);
+		rc = ENODEV;
+		goto bxe_attach_fail;
+	}
+
+	/* Set init arrays */
+	rc = bxe_init_firmware(sc);
+	if (rc) {
+		BXE_PRINTF("Error loading firmware\n");
+		goto bxe_attach_fail;
+	}
+
+
+#ifdef BXE_DEBUG
+
+	/* Allocate a memory buffer for grcdump output.*/
+	sc->grcdump_buffer = malloc(BXE_GRCDUMP_BUF_SIZE, M_TEMP, M_NOWAIT);
+	if (sc->grcdump_buffer == NULL) {
+		/* Failure is OK, just print a message and continue attach. */
+		BXE_PRINTF("Failed to allocate grcdump memory buffer!\n");
+	}
+#endif
+
+	/* Check that NVRAM contents are valid.*/
+	if (bxe_nvram_test(sc)) {
+		DBPRINT(sc, BXE_WARN, "%s(): Failed NVRAM test!\n",
+			__FUNCTION__);
+		rc = ENODEV;
+		goto bxe_attach_fail;
+	}
+
+	/* Allocate the appropriate interrupts.*/
+	if (bxe_interrupt_allocate(sc)) {
+		BXE_PRINTF("%s(%d): Interrupt allocation failed!\n",
+			__FILE__, __LINE__);
+		rc = ENODEV;
+		goto bxe_attach_fail;
+	}
+
+	/* Useful for accessing unconfigured devices (i.e. factory diags).*/
+	if (nomcp)
+		sc->bxe_flags |= BXE_NO_MCP_FLAG;
+
+	/* If bootcode is not running only initialize port 0. */
+	if (nomcp && BP_PORT(sc)) {
+		BXE_PRINTF(
+		    "Second device disabled (no bootcode), exiting...\n");
+		rc = ENODEV;
+		goto bxe_attach_fail;
+	}
+
+	/* Check if PXE/UNDI is still active and unload it. */
+	if (!BP_NOMCP(sc))
+		bxe_undi_unload(sc);
+
+	/* Set TPA flag. */
+	if (bxe_tpa_enable){
+		sc->bxe_flags |= BXE_TPA_ENABLE_FLAG;
+	}else
+		sc->bxe_flags &= ~BXE_TPA_ENABLE_FLAG;
+
+	/* Select the PCIe maximum read request size. */
+	if (bxe_mrrs > 3)
+		sc->mrrs = 3;
+	else
+		sc->mrrs = bxe_mrrs;
+
+	/* Select the RX and TX ring sizes */
+	sc->tx_ring_size = USABLE_TX_BD;
+	sc->rx_ring_size = USABLE_RX_BD;
+
+	/* Assume receive IP/TCP/UDP checksum is enabled. */
+	sc->rx_csum = 1;
+
+	/* Select the host coalescing tick count values. */
+	sc->tx_ticks = bxe_tx_ticks;
+	sc->rx_ticks = bxe_rx_ticks;
+
+	/* Disable WoL. */
+	sc->wol = 0;
+
+	/* Allocate DMA memory resources. */
+	if (bxe_dma_alloc(sc->bxe_dev)) {
+		BXE_PRINTF("%s(%d): DMA allocation failed!\n",
+			__FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_attach_fail;
+	}
+
+	/* Allocate a FreeBSD ifnet structure. */
+	ifp = sc->bxe_ifp = if_alloc(IFT_ETHER);
+	if (ifp == NULL) {
+		BXE_PRINTF("%s(%d): Interface allocation failed!\n",
+			__FILE__, __LINE__);
+		rc = ENXIO;
+		goto bxe_attach_fail;
+	}
+
+	/* Initialize the FreeBSD ifnet interface. */
+	ifp->if_softc = sc;
+	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = bxe_ioctl;
+	ifp->if_start = bxe_tx_start;
+#ifdef FreeBSD8_0
+	ifp->if_timer = 0;
+#endif
+	ifp->if_init = bxe_init;
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_hwassist = BXE_IF_HWASSIST;
+	ifp->if_capabilities = BXE_IF_CAPABILITIES;
+	ifp->if_capenable = ifp->if_capabilities;
+	ifp->if_baudrate = IF_Gbps(10UL);
+
+	/* Assume a standard 1500 byte MTU size for mbuf allocations. */
+	sc->mbuf_alloc_size  = MCLBYTES;
+	ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size;
+
+	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
+	IFQ_SET_READY(&ifp->if_snd);
+
+	/* Attach to the Ethernet interface list. */
+	ether_ifattach(ifp, sc->link_params.mac_addr);
+
+	/* Attach the interrupts to the interrupt handlers. */
+	if (bxe_interrupt_attach(sc)) {
+		BXE_PRINTF("%s(%d): Interrupt allocation failed!\n", __FILE__,
+		    __LINE__);
+		goto bxe_attach_fail;
+	}
+
+	/* Print important adapter info for the user. */
+	bxe_print_adapter_info(sc);
+
+	/* Add the supported sysctls to the kernel. */
+	bxe_add_sysctls(sc);
+
+bxe_attach_fail:
+	if (rc != 0)
+		bxe_detach(dev);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	return(rc);
+}
+
+
+/*
+ * Supported link settings.
+ *
+ * Examines hardware configuration present in NVRAM and
+ * determines the link settings that are supported between
+ * the external PHY and the switch.
+ *
+ * Returns:
+ *   None.
+ *
+ * Side effects:
+ * 	 Sets sc->port.supported
+ *	 Sets sc->link_params.phy_addr
+ */
+static void
+bxe_link_settings_supported(struct bxe_softc *sc, uint32_t switch_cfg)
+{
+	uint32_t ext_phy_type;
+	int port;
+
+	DBENTER(BXE_VERBOSE_PHY);
+	DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): switch_cfg = 0x%08X\n",
+		__FUNCTION__, switch_cfg);
+
+	port = BP_PORT(sc);
+	/* Get the link	settings supported by the external PHY. */
+	switch (switch_cfg) {
+	case SWITCH_CFG_1G:
+		ext_phy_type =
+		    SERDES_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
+
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+		    "%s(): 1G switch w/ ext_phy_type = "
+		    "0x%08X\n", __FUNCTION__, ext_phy_type);
+
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): 1G Direct.\n",
+			    __FUNCTION__);
+
+			sc->port.supported |=
+			    (SUPPORTED_10baseT_Half |
+			     SUPPORTED_10baseT_Full |
+			     SUPPORTED_100baseT_Half |
+			     SUPPORTED_100baseT_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_2500baseX_Full |
+			     SUPPORTED_TP |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+			DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): 1G 5482\n",
+				__FUNCTION__);
+
+			sc->port.supported |=
+			    (SUPPORTED_10baseT_Half |
+			     SUPPORTED_10baseT_Full |
+			     SUPPORTED_100baseT_Half |
+			     SUPPORTED_100baseT_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_TP |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		default:
+			BXE_PRINTF(
+			    "%s(%d): BAD External PHY NVRAM config data "
+			    "(0x%08X).\n",
+			    __FILE__, __LINE__,
+			    sc->link_params.ext_phy_config);
+			goto bxe_link_settings_supported_exit;
+		}
+
+		sc->port.phy_addr =
+		    REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + (port * 0x10));
+
+		DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): phy_addr = 0x%08X\n",
+		    __FUNCTION__, sc->port.phy_addr);
+		break;
+
+	case SWITCH_CFG_10G:
+		ext_phy_type =
+		    XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
+
+		DBPRINT(
+		    sc, BXE_VERBOSE_PHY,
+		    "%s(): 10G switch w/ ext_phy_type = 0x%08X\n",
+		    __FUNCTION__, ext_phy_type);
+
+		switch (ext_phy_type) {
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "%s(): 10G switch w/ direct connect.\n",
+			    __FUNCTION__);
+
+			sc->port.supported |=
+			    (SUPPORTED_10baseT_Half |
+			     SUPPORTED_10baseT_Full |
+			     SUPPORTED_100baseT_Half |
+			     SUPPORTED_100baseT_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_2500baseX_Full |
+			     SUPPORTED_10000baseT_Full |
+			     SUPPORTED_TP |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "ext_phy_type 0x%x (8072)\n",ext_phy_type);
+
+			sc->port.supported |=
+			    (SUPPORTED_10000baseT_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+			DBPRINT(sc,
+			    BXE_VERBOSE_PHY,"ext_phy_type 0x%x (8073)\n",
+			    ext_phy_type);
+
+			sc->port.supported |=
+			    (SUPPORTED_10000baseT_Full |
+			     SUPPORTED_2500baseX_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "%s(): 10G switch w/ 8705.\n",__FUNCTION__);
+
+			sc->port.supported |=
+			    (SUPPORTED_10000baseT_Full |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "%s(): 10G switch w/ 8706.\n",
+			    __FUNCTION__);
+
+			sc->port.supported |=
+			    (SUPPORTED_10000baseT_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+			DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "%s(): 10G switch w/ 8726.\n",
+			    __FUNCTION__);
+
+			sc->port.supported |=
+			    (SUPPORTED_10000baseT_Full |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+			DBPRINT(sc, BXE_VERBOSE_PHY,"ext_phy_type 0x%x (8727)\n",
+			    ext_phy_type);
+
+			sc->port.supported |=
+			    (SUPPORTED_10000baseT_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_FIBRE |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+			 DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "%s(): 10G switch w/ SFX7101.\n",
+			    __FUNCTION__);
+
+			sc->port.supported |=
+			    (SUPPORTED_10000baseT_Full |
+			     SUPPORTED_TP |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+			 DBPRINT(sc, BXE_VERBOSE_PHY,
+			    "ext_phy_type 0x%x (BCM8481)\n",
+			    ext_phy_type);
+
+			sc->port.supported |=
+			    (SUPPORTED_10baseT_Half |
+			     SUPPORTED_10baseT_Full |
+			     SUPPORTED_100baseT_Half |
+			     SUPPORTED_100baseT_Full |
+			     SUPPORTED_1000baseT_Full |
+			     SUPPORTED_10000baseT_Full |
+			     SUPPORTED_TP |
+			     SUPPORTED_Autoneg |
+			     SUPPORTED_Pause |
+			     SUPPORTED_Asym_Pause);
+			break;
+
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
+			DBPRINT(sc, BXE_WARN,
+			    "%s(): 10G XGXS PHY failure detected.\n",
+			    __FUNCTION__);
+			break;
+
+		default:
+			BXE_PRINTF(
+			    "%s(%d): BAD External PHY NVRAM config data "
+			    "(0x%08X).\n", __FILE__, __LINE__,
+			    sc->link_params.ext_phy_config);
+			goto bxe_link_settings_supported_exit;
+		}
+
+		sc->port.phy_addr =
+		    REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR +(port * 0x18));
+		break;
+
+	default:
+		DBPRINT(sc, BXE_WARN, "%s(): BAD switch configuration "
+		    "(link_config = 0x%08X)\n", __FUNCTION__,
+		    sc->port.link_config);
+		goto bxe_link_settings_supported_exit;
+	}
+
+	sc->link_params.phy_addr = sc->port.phy_addr;
+
+	/* Mask out unsupported speeds according to NVRAM. */
+	if ((sc->link_params.speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) == 0)
+		sc->port.supported &= ~SUPPORTED_10baseT_Half;
+
+	if ((sc->link_params.speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) == 0)
+		sc->port.supported &= ~SUPPORTED_10baseT_Full;
+
+	if ((sc->link_params.speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) == 0)
+		sc->port.supported &= ~SUPPORTED_100baseT_Half;
+
+	if ((sc->link_params.speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) == 0)
+		sc->port.supported &= ~SUPPORTED_100baseT_Full;
+
+	if ((sc->link_params.speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) == 0)
+		sc->port.supported &= ~(SUPPORTED_1000baseT_Half |
+			SUPPORTED_1000baseT_Full);
+
+	if ((sc->link_params.speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) == 0)
+		sc->port.supported &= ~SUPPORTED_2500baseX_Full;
+
+	if ((sc->link_params.speed_cap_mask &
+	    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) == 0)
+		sc->port.supported &= ~SUPPORTED_10000baseT_Full;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "%s(): Supported link settings = 0x%b\n", __FUNCTION__,
+	    sc->port.supported, BXE_SUPPORTED_PRINTFB);
+
+bxe_link_settings_supported_exit:
+
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+/*
+ * Requested link settings.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_link_settings_requested(struct bxe_softc *sc)
+{
+	uint32_t ext_phy_type;
+	DBENTER(BXE_VERBOSE_PHY);
+
+	sc->link_params.req_duplex = MEDIUM_FULL_DUPLEX;
+
+	switch (sc->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
+
+	case PORT_FEATURE_LINK_SPEED_AUTO:
+		if (sc->port.supported & SUPPORTED_Autoneg) {
+			sc->link_params.req_line_speed |= SPEED_AUTO_NEG;
+			sc->port.advertising = sc->port.supported;
+		} else {
+			ext_phy_type = XGXS_EXT_PHY_TYPE(
+			    sc->link_params.ext_phy_config);
+
+			if ((ext_phy_type ==
+			     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
+			    (ext_phy_type ==
+			     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
+				/* Force 10G, no autonegotiation. */
+				sc->link_params.req_line_speed = SPEED_10000;
+				sc->port.advertising =
+				    ADVERTISED_10000baseT_Full |
+				    ADVERTISED_FIBRE;
+				break;
+			}
+
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - Autoneg not supported!\n",
+			    __FUNCTION__, sc->port.link_config);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	case PORT_FEATURE_LINK_SPEED_10M_FULL:
+		if (sc->port.supported & SUPPORTED_10baseT_Full) {
+			sc->link_params.req_line_speed = SPEED_10;
+			sc->port.advertising = ADVERTISED_10baseT_Full |
+				ADVERTISED_TP;
+		} else {
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - speed_cap_mask 0x%08X\n",
+			    __FUNCTION__, sc->port.link_config,
+			    sc->link_params.speed_cap_mask);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	case PORT_FEATURE_LINK_SPEED_10M_HALF:
+		if (sc->port.supported & SUPPORTED_10baseT_Half) {
+			sc->link_params.req_line_speed = SPEED_10;
+			sc->link_params.req_duplex = MEDIUM_HALF_DUPLEX;
+			sc->port.advertising = ADVERTISED_10baseT_Half |
+				ADVERTISED_TP;
+		} else {
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
+			    __FUNCTION__, sc->port.link_config,
+			    sc->link_params.speed_cap_mask);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	case PORT_FEATURE_LINK_SPEED_100M_FULL:
+		if (sc->port.supported & SUPPORTED_100baseT_Full) {
+			sc->link_params.req_line_speed = SPEED_100;
+			sc->port.advertising = ADVERTISED_100baseT_Full |
+				ADVERTISED_TP;
+		} else {
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
+			    __FUNCTION__, sc->port.link_config,
+			    sc->link_params.speed_cap_mask);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	case PORT_FEATURE_LINK_SPEED_100M_HALF:
+		if (sc->port.supported & SUPPORTED_100baseT_Half) {
+			sc->link_params.req_line_speed = SPEED_100;
+			sc->link_params.req_duplex = MEDIUM_HALF_DUPLEX;
+			sc->port.advertising = ADVERTISED_100baseT_Half |
+				ADVERTISED_TP;
+		} else {
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
+			    __FUNCTION__, sc->port.link_config,
+			    sc->link_params.speed_cap_mask);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	case PORT_FEATURE_LINK_SPEED_1G:
+		if (sc->port.supported & SUPPORTED_1000baseT_Full) {
+			sc->link_params.req_line_speed = SPEED_1000;
+			sc->port.advertising = ADVERTISED_1000baseT_Full |
+				ADVERTISED_TP;
+		} else {
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
+			    __FUNCTION__, sc->port.link_config,
+			    sc->link_params.speed_cap_mask);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	case PORT_FEATURE_LINK_SPEED_2_5G:
+		if (sc->port.supported & SUPPORTED_2500baseX_Full) {
+			sc->link_params.req_line_speed = SPEED_2500;
+			sc->port.advertising = ADVERTISED_2500baseX_Full |
+				ADVERTISED_TP;
+		} else {
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
+			    __FUNCTION__, sc->port.link_config,
+			    sc->link_params.speed_cap_mask);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	case PORT_FEATURE_LINK_SPEED_10G_CX4:
+	case PORT_FEATURE_LINK_SPEED_10G_KX4:
+	case PORT_FEATURE_LINK_SPEED_10G_KR:
+		if (sc->port.supported & SUPPORTED_10000baseT_Full) {
+			sc->link_params.req_line_speed = SPEED_10000;
+			sc->port.advertising = ADVERTISED_10000baseT_Full |
+			    ADVERTISED_FIBRE;
+		} else {
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): NVRAM config error. Invalid "
+			    "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
+			    __FUNCTION__, sc->port.link_config,
+			    sc->link_params.speed_cap_mask);
+			goto bxe_link_settings_requested_exit;
+		}
+		break;
+	default:
+		DBPRINT(sc, BXE_FATAL, "%s(): NVRAM config error. BAD link "
+		    "speed - link_config = 0x%08X\n", __FUNCTION__,
+		    sc->port.link_config);
+		sc->link_params.req_line_speed = 0;
+		sc->port.advertising = sc->port.supported;
+		break;
+	}
+
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "%s(): req_line_speed = %d, req_duplex = %d\n",
+	    __FUNCTION__, sc->link_params.req_line_speed,
+	    sc->link_params.req_duplex);
+
+	sc->link_params.req_flow_ctrl =
+	    sc->port.link_config & PORT_FEATURE_FLOW_CONTROL_MASK;
+
+	if ((sc->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
+	    !(sc->port.supported & SUPPORTED_Autoneg))
+		sc->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY,
+		"%s(): req_flow_ctrl = 0x%08X, advertising = 0x%08X\n",
+		__FUNCTION__, sc->link_params.req_flow_ctrl,
+		sc->port.advertising);
+
+bxe_link_settings_requested_exit:
+
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+
+/*
+ * Get function specific hardware configuration.
+ *
+ * Multiple function devices such as the BCM57711E have configuration
+ * information that is specific to each PCIe function of the controller.
+ * The number of PCIe functions is not necessarily the same as the number
+ * of Ethernet ports supported by the device.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure
+ */
+static int
+bxe_get_function_hwinfo(struct bxe_softc *sc)
+{
+	uint32_t mac_hi, mac_lo, val;
+	int func, rc;
+
+	DBENTER(BXE_VERBOSE_LOAD);
+
+	rc = 0;
+	func = BP_FUNC(sc);
+
+	/* Get the common hardware configuration first. */
+	bxe_get_common_hwinfo(sc);
+
+	/* Assume no outer VLAN/multi-function support. */
+	sc->e1hov = sc->e1hmf = 0;
+
+	/* Get config info for mf enabled devices. */
+	if (CHIP_IS_E1H(sc)) {
+		sc->mf_config[BP_E1HVN(sc)] =
+		    SHMEM_RD(sc, mf_cfg.func_mf_config[func].config);
+		val = (SHMEM_RD(sc, mf_cfg.func_mf_config[func].e1hov_tag) &
+		    FUNC_MF_CFG_E1HOV_TAG_MASK);
+		if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
+			sc->e1hov = (uint16_t) val;
+			sc->e1hmf = 1;
+		} else {
+			if (BP_E1HVN(sc)) {
+				rc = EPERM;
+				goto bxe_get_function_hwinfo_exit;
+			}
+		}
+	}
+
+	if (!BP_NOMCP(sc)) {
+		bxe_get_port_hwinfo(sc);
+		sc->fw_seq = SHMEM_RD(sc, func_mb[func].drv_mb_header) &
+		    DRV_MSG_SEQ_NUMBER_MASK;
+	}
+
+
+	/*
+	 * Fetch the factory configured MAC address for multi function
+	 * devices. If this is not a multi-function device then the MAC
+	 * address was already read in the bxe_get_port_hwinfo() routine.
+	 * The MAC addresses used by the port are not the same as the MAC
+	 * addressed used by the function.
+	 */
+	if (IS_E1HMF(sc)) {
+		mac_hi = SHMEM_RD(sc, mf_cfg.func_mf_config[func].mac_upper);
+		mac_lo = SHMEM_RD(sc, mf_cfg.func_mf_config[func].mac_lower);
+
+		if ((mac_lo == 0) && (mac_hi == 0)) {
+			BXE_PRINTF("%s(%d): Invalid Ethernet address!\n",
+				__FILE__, __LINE__);
+		} else {
+			sc->link_params.mac_addr[0] = (u_char)(mac_hi >> 8);
+			sc->link_params.mac_addr[1] = (u_char)(mac_hi);
+			sc->link_params.mac_addr[2] = (u_char)(mac_lo >> 24);
+			sc->link_params.mac_addr[3] = (u_char)(mac_lo >> 16);
+			sc->link_params.mac_addr[4] = (u_char)(mac_lo >> 8);
+			sc->link_params.mac_addr[5] = (u_char)(mac_lo);
+		}
+	}
+
+
+bxe_get_function_hwinfo_exit:
+	DBEXIT(BXE_VERBOSE_LOAD);
+	return(rc);
+}
+
+
+/*
+ * Get port specific hardware configuration.
+ *
+ * Multiple port devices such as the BCM57710 have configuration
+ * information that is specific to each Ethernet port of the
+ * controller.  This function reads that configuration
+ * information from the bootcode's shared memory and saves it
+ * for future use.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_get_port_hwinfo(struct bxe_softc *sc)
+{
+	int i, port;
+	uint32_t val, mac_hi, mac_lo;
+
+	DBENTER(BXE_VERBOSE_LOAD);
+
+	port = BP_PORT(sc);
+	sc->link_params.sc = sc;
+	sc->link_params.port = port;
+
+	/* Fetch several configuration values from bootcode shared memory. */
+	sc->link_params.lane_config =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
+	sc->link_params.ext_phy_config =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
+
+	if (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config) ==
+	    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
+		sc->link_params.ext_phy_config &=
+		    ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+		sc->link_params.ext_phy_config |=
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
+		sc->link_params.feature_config_flags |=
+		    FEATURE_CONFIG_BCM8727_NOC;
+	}
+
+	sc->link_params.speed_cap_mask =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
+	sc->port.link_config =
+	    SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
+
+
+	/* Read the XGXS RX/TX preemphasis values. */
+	for (i = 0; i < 2; i++) {
+		val = SHMEM_RD(sc,
+		    dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
+		sc->link_params.xgxs_config_rx[i << 1] = ((val >> 16) & 0xffff);
+		sc->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
+
+		val = SHMEM_RD(sc,
+		    dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
+		sc->link_params.xgxs_config_tx[i << 1] = ((val >> 16) & 0xffff);
+		sc->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
+	}
+
+	/* Fetch the device configured link settings. */
+	sc->link_params.switch_cfg = sc->port.link_config &
+	    PORT_FEATURE_CONNECTED_SWITCH_MASK;
+
+	bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
+	bxe_link_settings_requested(sc);
+
+	mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
+	mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
+
+	if (mac_lo == 0 && mac_hi == 0) {
+		BXE_PRINTF("%s(%d): No Ethernet address programmed on the "
+		    "controller!\n", __FILE__, __LINE__);
+	} else {
+		sc->link_params.mac_addr[0] = (u_char)(mac_hi >> 8);
+		sc->link_params.mac_addr[1] = (u_char)(mac_hi);
+		sc->link_params.mac_addr[2] = (u_char)(mac_lo >> 24);
+		sc->link_params.mac_addr[3] = (u_char)(mac_lo >> 16);
+		sc->link_params.mac_addr[4] = (u_char)(mac_lo >> 8);
+		sc->link_params.mac_addr[5] = (u_char)(mac_lo);
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD);
+}
+
+
+/*
+ * Get common hardware configuration.
+ *
+ * Multiple port devices such as the BCM57710 have configuration
+ * information that is specific to each Ethernet port of the controller.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_get_common_hwinfo(struct bxe_softc *sc)
+{
+	uint32_t val;
+
+	DBENTER(BXE_VERBOSE_LOAD);
+
+	/* Get the chip revision. */
+	sc->common.chip_id = sc->link_params.chip_id =
+	    ((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
+	    ((REG_RD(sc, MISC_REG_CHIP_REV) & 0x000f) << 12) |
+	    ((REG_RD(sc, MISC_REG_CHIP_METAL) & 0xff) << 4) |
+	    ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf));
+
+	DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): chip_id = 0x%08X.\n",
+	    __FUNCTION__, sc->common.chip_id);
+
+	val = (REG_RD(sc, 0x2874) & 0x55);
+	if ((sc->common.chip_id & 0x1) ||
+	    (CHIP_IS_E1(sc) && val) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
+		sc->bxe_flags |= BXE_ONE_PORT_FLAG;
+		DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): Single port device.\n",
+		    __FUNCTION__);
+	}
+
+	/* Identify enabled PCI capabilites (PCIe, MSI-X, etc.). */
+	bxe_probe_pci_caps(sc);
+
+	/* Get the NVRAM size. */
+	val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
+	sc->common.flash_size = (NVRAM_1MB_SIZE <<
+	    (val & MCPR_NVM_CFG4_FLASH_SIZE));
+
+	DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): flash_size = 0x%08x (%dKB)\n",
+	    __FUNCTION__, sc->common.flash_size,(sc->common.flash_size >> 10));
+
+	/* Find the shared memory base address. */
+	sc->common.shmem_base = sc->link_params.shmem_base =
+	    REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
+	sc->common.shmem2_base = REG_RD(sc, MISC_REG_GENERIC_CR_0);
+	DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): shmem_base = 0x%08X\n",
+	    __FUNCTION__, sc->common.shmem_base);
+
+	/* Make sure the shared memory address is valid. */
+	if (!sc->common.shmem_base ||
+	    (sc->common.shmem_base < 0xA0000) ||
+	    (sc->common.shmem_base > 0xC0000)) {
+
+		DBPRINT(sc, BXE_FATAL, "%s(): MCP is not active!\n",
+		    __FUNCTION__);
+		sc->bxe_flags |= BXE_NO_MCP_FLAG;
+		goto bxe_get_common_hwinfo_exit;
+	}
+
+	/* Make sure the shared memory contents are valid. */
+	val = SHMEM_RD(sc, validity_map[BP_PORT(sc)]);
+	if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
+	    (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
+		BXE_PRINTF("Invalid NVRAM-Bad validity signature!\n");
+		goto bxe_get_common_hwinfo_exit;
+	}
+
+	/* Read the device configuration from shared memory. */
+	sc->common.hw_config =
+	    SHMEM_RD(sc, dev_info.shared_hw_config.config);
+	sc->link_params.hw_led_mode = ((sc->common.hw_config &
+	    SHARED_HW_CFG_LED_MODE_MASK) >> SHARED_HW_CFG_LED_MODE_SHIFT);
+
+	/* Check if we need to override the preemphasis values. */
+	sc->link_params.feature_config_flags = 0;
+	val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
+	if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
+		sc->link_params.feature_config_flags |=
+		    FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
+	else
+		sc->link_params.feature_config_flags &=
+		    ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
+
+	/* In multifunction mode, we can't support WoL on a VN. */
+	if (BP_E1HVN(sc) == 0) {
+		val = REG_RD(sc, PCICFG_OFFSET + PCICFG_PM_CAPABILITY);
+		sc->bxe_flags |= (val & PCICFG_PM_CAPABILITY_PME_IN_D3_COLD) ?
+			0 : BXE_NO_WOL_FLAG;
+	} else
+		sc->bxe_flags |= BXE_NO_WOL_FLAG;
+
+	DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): %sWoL capable\n", __FUNCTION__,
+		(sc->bxe_flags & BXE_NO_WOL_FLAG) ? "Not " : "");
+
+	/* Check bootcode version */
+	sc->common.bc_ver = ((SHMEM_RD(sc, dev_info.bc_rev)) >> 8);
+	if (sc->common.bc_ver < MIN_BXE_BC_VER) {
+		BXE_PRINTF("Warning: This driver needs bootcode 0x%08X "
+			"but found 0x%08X, please upgrade!\n", MIN_BXE_BC_VER,
+			sc->common.bc_ver);
+		goto bxe_get_common_hwinfo_exit;
+	}
+
+bxe_get_common_hwinfo_exit:
+	DBEXIT(BXE_VERBOSE_LOAD);
+}
+
+
+/*
+ * Remove traces of PXE boot by forcing UNDI driver unload.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_undi_unload(struct bxe_softc *sc)
+{
+	uint32_t reset_code, swap_en, swap_val, val;
+	int func;
+
+	DBENTER(BXE_VERBOSE_LOAD);
+
+	/* Check if there is any driver already loaded */
+	val = REG_RD(sc, MISC_REG_UNPREPARED);
+	if (val == 0x1) {
+
+		/* Check if it is the UNDI driver. */
+		bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_UNDI);
+		val = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
+		if (val == 0x7) {
+			reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+			func = BP_FUNC(sc);
+
+			DBPRINT(sc, BXE_WARN,
+			    "%s(): UNDI is active! Resetting the device.\n",
+			    __FUNCTION__);
+
+			/* Clear the UNDI indication. */
+			REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
+
+			/* Try to unload UNDI on port 0. */
+			sc->bxe_func = 0;
+			sc->fw_seq = (SHMEM_RD(sc,
+			    func_mb[sc->bxe_func].drv_mb_header) &
+			    DRV_MSG_SEQ_NUMBER_MASK);
+			reset_code = bxe_fw_command(sc, reset_code);
+
+			/* Check if UNDI is active on port 1. */
+			if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
+
+				/* Send "done" for previous unload. */
+				bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
+
+				/* Now unload on port 1. */
+				sc->bxe_func = 1;
+				sc->fw_seq = (SHMEM_RD(sc,
+				    func_mb[sc->bxe_func].drv_mb_header) &
+				    DRV_MSG_SEQ_NUMBER_MASK);
+
+				reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+				bxe_fw_command(sc, reset_code);
+			}
+
+			/* It's	now safe to release the lock. */
+			bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_UNDI);
+
+			REG_WR(sc, (BP_PORT(sc) ? HC_REG_CONFIG_1 :
+				HC_REG_CONFIG_0), 0x1000);
+
+			REG_WR(sc, (BP_PORT(sc) ?
+			    NIG_REG_LLH1_BRB1_DRV_MASK :
+			    NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
+
+			REG_WR(sc, (BP_PORT(sc) ?
+			    NIG_REG_LLH1_BRB1_NOT_MCP :
+			    NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
+
+			/* Clear AEU. */
+			REG_WR(sc, (BP_PORT(sc) ?
+			    MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+			    MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
+
+			DELAY(10000);
+
+			/* Save NIG port swap information. */
+			swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
+			swap_en = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
+
+			/* Reset the controller. */
+			REG_WR(sc, GRCBASE_MISC +
+			    MISC_REGISTERS_RESET_REG_1_CLEAR, 0xd3ffffff);
+			REG_WR(sc, GRCBASE_MISC +
+			    MISC_REGISTERS_RESET_REG_2_CLEAR, 0x00001403);
+
+			/* Take the NIG out of reset and restore swap values.*/
+			REG_WR(sc, GRCBASE_MISC +
+			    MISC_REGISTERS_RESET_REG_1_SET,
+			    MISC_REGISTERS_RESET_REG_1_RST_NIG);
+			REG_WR(sc, NIG_REG_PORT_SWAP, swap_val);
+			REG_WR(sc, NIG_REG_STRAP_OVERRIDE, swap_en);
+
+			/* Send completion message to the MCP. */
+			bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
+
+			/*
+			 * Restore our function and firmware sequence counter.
+			 */
+			sc->bxe_func = func;
+			sc->fw_seq = (SHMEM_RD(sc,
+			    func_mb[sc->bxe_func].drv_mb_header) &
+			    DRV_MSG_SEQ_NUMBER_MASK);
+		} else
+			bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_UNDI);
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD);
+}
+
+
+/*
+ * Device detach function.
+ *
+ * Stops the controller, resets the controller, and releases resources.
+ *
+ * Returns:
+ *   0 on success, positive value on failure.
+ */
+static int
+bxe_detach(device_t dev)
+{
+	struct bxe_softc *sc;
+	struct ifnet *ifp;
+#ifdef BXE_TASK
+	struct bxe_fastpath *fp;
+	int i;
+#endif
+
+	sc = device_get_softc(dev);
+	DBENTER(BXE_VERBOSE_RESET);
+
+	ifp = sc->bxe_ifp;
+	if (ifp != NULL && ifp->if_vlantrunk != NULL) {
+		BXE_PRINTF("Cannot detach while VLANs are in use.\n");
+		return(EBUSY);
+	}
+
+	/* Stop and reset the controller if it was open. */
+	if (sc->state != BXE_STATE_CLOSED) {
+		BXE_CORE_LOCK(sc);
+		bxe_stop_locked(sc, UNLOAD_CLOSE);
+		BXE_CORE_UNLOCK(sc);
+	}
+
+#ifdef BXE_TASK
+	/* Free the OS taskqueue resources. */
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+
+		if (fp->tq) {
+			taskqueue_drain(fp->tq, &fp->task);
+			taskqueue_free(fp->tq);
+		}
+	}
+
+	if (sc->tq) {
+		taskqueue_drain(sc->tq, &sc->task);
+		taskqueue_free(sc->tq);
+	}
+#endif
+	/* Release the network interface. */
+	if (ifp != NULL)
+		ether_ifdetach(ifp);
+	ifmedia_removeall(&sc->bxe_ifmedia);
+	/* Release all remaining resources. */
+	bxe_release_resources(sc);
+	pci_disable_busmaster(dev);
+
+	return(0);
+}
+
+
+/*
+ * Setup a leading connection for the controller.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_setup_leading(struct bxe_softc *sc)
+{
+	int rc;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+
+	/* Reset IGU state for the leading connection. */
+	bxe_ack_sb(sc, sc->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+	/* Post a PORT_SETUP ramrod and wait for completion. */
+	bxe_sp_post(sc, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
+
+	/* Wait for the ramrod to complete on the leading connection. */
+	rc = bxe_wait_ramrod(sc, BXE_STATE_OPEN, 0, &(sc->state), 1);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+	return (rc);
+}
+
+
+/*
+ * Stop the leading connection on the controller.
+ *
+ * Returns:
+ *   None.
+ */
+static int
+bxe_stop_leading(struct bxe_softc *sc)
+{
+	uint16_t dsb_sp_prod_idx;
+	int rc, timeout;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+
+	/* Send the ETH_HALT ramrod. */
+	sc->fp[0].state = BXE_FP_STATE_HALTING;
+	bxe_sp_post(sc,RAMROD_CMD_ID_ETH_HALT, 0, 0, sc->fp[0].cl_id, 0);
+
+	/* Poll for the ETH_HALT ramrod on the leading connection. */
+	rc = bxe_wait_ramrod(sc, BXE_FP_STATE_HALTED, 0, &(sc->fp[0].state), 1);
+	if (rc)
+		goto bxe_stop_leading_exit;
+
+	dsb_sp_prod_idx = *sc->dsb_sp_prod;
+
+	/*
+	 * Now that the connection is in the
+	 * HALTED state send PORT_DELETE ramrod.
+	 */
+	bxe_sp_post(sc, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
+
+	/*
+	 * Wait for completion.  This can take a * long time if the other port
+	 * is busy. Give the command some time to complete but don't wait for a
+	 * completion since there's nothing we can do.
+	 */
+	timeout = 500;
+	while (dsb_sp_prod_idx == *sc->dsb_sp_prod) {
+		if (!timeout) {
+			DBPRINT(sc, BXE_FATAL, "%s(): Timeout waiting for "
+			    "PORT_DEL ramrod completion!\n", __FUNCTION__);
+			rc = EBUSY;
+			break;
+		}
+		timeout--;
+		DELAY(1000);
+		rmb();
+	}
+
+	/* Update the adapter and connection states. */
+	sc->state = BXE_STATE_CLOSING_WAIT4_UNLOAD;
+	sc->fp[0].state = BXE_FP_STATE_CLOSED;
+
+bxe_stop_leading_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+	return(rc);
+}
+
+/*
+ * Setup a client connection when using multi-queue/RSS.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static int
+bxe_setup_multi(struct bxe_softc *sc, int index)
+{
+	struct bxe_fastpath *fp;
+	int rc;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+
+	fp = &sc->fp[index];
+	/* Reset IGU state. */
+	bxe_ack_sb(sc, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+	/* Post a CLIENT_SETUP ramrod. */
+	fp->state = BXE_FP_STATE_OPENING;
+	bxe_sp_post(sc, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, fp->cl_id, 0);
+
+	/* Wait for the ramrod to complete. */
+	rc = bxe_wait_ramrod(sc, BXE_FP_STATE_OPEN, index, &(fp->state), 1);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+	return(rc);
+}
+
+/*
+ * Stop a client connection.
+ *
+ * Stops an individual client connection on the device.  Use
+ * bxe_stop_leading() for the first/default connection.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_stop_multi(struct bxe_softc *sc, int index)
+{
+	struct bxe_fastpath *fp;
+	int rc;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+
+	fp = &sc->fp[index];
+	/* Halt the client connection. */
+	fp->state = BXE_FP_STATE_HALTING;
+	bxe_sp_post(sc, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0);
+
+	/* Wait for the ramrod completion. */
+	rc = bxe_wait_ramrod(sc, BXE_FP_STATE_HALTED, index, &(fp->state), 1);
+	if (rc){
+	BXE_PRINTF("halted failed \n");
+		goto bxe_stop_multi_exit;
+	}
+	/* Delete the CFC entry. */
+	bxe_sp_post(sc, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
+
+	/* Poll for the ramrod completion. */
+	rc = bxe_wait_ramrod(sc, BXE_FP_STATE_CLOSED, index, &(fp->state), 1);
+
+bxe_stop_multi_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+	return(rc);
+}
+
+/*
+ * Hardware lock for shared, dual-port PHYs.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_acquire_phy_lock(struct bxe_softc *sc)
+{
+	uint32_t ext_phy_type;
+
+	DBENTER(BXE_VERBOSE_PHY);
+
+	ext_phy_type = XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
+	switch(ext_phy_type){
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+			bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
+			break;
+		default:
+			break;
+	}
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+/*
+ * Hardware unlock for shared, dual-port PHYs.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_release_phy_lock(struct bxe_softc *sc)
+{
+	uint32_t ext_phy_type;
+
+	DBENTER(BXE_VERBOSE_PHY);
+	ext_phy_type = XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
+	switch(ext_phy_type){
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+			bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
+			break;
+		default:
+			break;
+	}
+
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe__link_reset(struct bxe_softc *sc)
+{
+	DBENTER(BXE_VERBOSE_PHY);
+
+	if (!BP_NOMCP(sc)) {
+		bxe_acquire_phy_lock(sc);
+		bxe_link_reset(&sc->link_params, &sc->link_vars, 1);
+		bxe_release_phy_lock(sc);
+	} else {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Bootcode is not running, not resetting link!\n",
+		    __FUNCTION__);
+	}
+
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+/*
+ * Stop the controller.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static int
+bxe_stop_locked(struct bxe_softc *sc, int unload_mode)
+{
+	struct ifnet *ifp;
+	struct mac_configuration_cmd *config;
+	struct bxe_fastpath *fp;
+	uint32_t reset_code;
+	uint32_t emac_base, val;
+	uint8_t entry, *mac_addr;
+	int count, i, port, rc;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+	ifp = sc->bxe_ifp;
+	port = BP_PORT(sc),
+	reset_code = 0;
+	rc = 0;
+
+	/* Stop the periodic tick. */
+	callout_stop(&sc->bxe_tick_callout);
+
+	sc->state = BXE_STATE_CLOSING_WAIT4_HALT;
+
+	/* Stop receiving all types of Ethernet traffic. */
+	sc->rx_mode = BXE_RX_MODE_NONE;
+	bxe_set_storm_rx_mode(sc);
+
+	/* Tell the stack the driver is stopped and TX queue is full. */
+	if (ifp != NULL)
+		ifp->if_drv_flags = 0;
+
+	/* Tell the bootcode to stop watching for a heartbeat. */
+	SHMEM_WR(sc, func_mb[BP_FUNC(sc)].drv_pulse_mb,
+	    (DRV_PULSE_ALWAYS_ALIVE | sc->fw_drv_pulse_wr_seq));
+	/* Stop the statistics updates. */
+	bxe_stats_handle(sc, STATS_EVENT_STOP);
+
+	/* Wait until all TX fastpath tasks have completed. */
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+
+		count = 1000;
+		while (bxe_has_tx_work(fp)) {
+
+			bxe_txeof(fp);
+
+			if (count == 0) {
+				BXE_PRINTF(
+			"%s(%d): Timeout wating for fp[%d] to complete.\n",
+				    __FILE__, __LINE__, i);
+				break;
+			}
+			count--;
+			DELAY(1000);
+			rmb();
+		}
+	}
+
+	/* Wait until all slowpath tasks have completed. */
+	count = 1000;
+	while ((sc->spq_left != MAX_SPQ_PENDING) && count--)
+		DELAY(1000);
+
+	/* Disable Interrupts */
+	bxe_int_disable(sc);
+
+	DELAY(1000);
+	/* Clear the MAC addresses. */
+	if (CHIP_IS_E1(sc)) {
+		config = BXE_SP(sc, mcast_config);
+		bxe_set_mac_addr_e1(sc, 0);
+
+		for (i = 0; i < config->hdr.length; i++)
+			CAM_INVALIDATE(config->config_table[i]);
+
+		config->hdr.length = i;
+		config->hdr.offset = BXE_MAX_MULTICAST * (1 + port);
+		config->hdr.client_id = BP_CL_ID(sc);
+		config->hdr.reserved1 = 0;
+
+		bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+		    U64_HI(BXE_SP_MAPPING(sc, mcast_config)),
+		    U64_LO(BXE_SP_MAPPING(sc, mcast_config)), 0);
+	} else {
+		REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
+		bxe_set_mac_addr_e1h(sc, 0);
+		for (i = 0; i < MC_HASH_SIZE; i++)
+			REG_WR(sc, MC_HASH_OFFSET(sc, i), 0);
+		REG_WR(sc, MISC_REG_E1HMF_MODE, 0);
+	}
+	/* Determine if any WoL settings needed. */
+	if (unload_mode == UNLOAD_NORMAL)
+		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+	else if (sc->bxe_flags & BXE_NO_WOL_FLAG) {
+		/* Driver initiated WoL is disabled, use OOB WoL settings. */
+		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
+		if (CHIP_IS_E1H(sc))
+			REG_WR(sc, MISC_REG_E1HMF_MODE, 0);
+	} else if (sc->wol) {
+		emac_base = BP_PORT(sc) ?  GRCBASE_EMAC0 : GRCBASE_EMAC1;
+		mac_addr = sc->link_params.mac_addr;
+		entry = (BP_E1HVN(sc) + 1) * 8;
+		val = (mac_addr[0] << 8) | mac_addr[1];
+		EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry, val);
+		val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
+		    (mac_addr[4] << 8) | mac_addr[5];
+		EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
+		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
+	} else {
+		/* Prevent WoL. */
+		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+	}
+	/* Stop all non-leading client connections. */
+	for (i = 1; i < sc->num_queues; i++) {
+		if (bxe_stop_multi(sc, i)){
+			BXE_PRINTF("multi failed \n");
+			goto bxe_stop_locked_exit;
+		}
+	}
+	/* Stop the leading client connection. */
+	rc = bxe_stop_leading(sc);
+	if (rc) {
+#ifdef BXE_DEBUG
+		if ((sc->state != BXE_STATE_CLOSING_WAIT4_UNLOAD) ||
+		    (sc->fp[0].state != BXE_FP_STATE_CLOSED)) {
+			BXE_PRINTF(
+			    "%s(): Failed to close leading connection!\n",
+			    __FUNCTION__);
+		}
+#endif
+	}
+
+	DELAY(10000);
+
+bxe_stop_locked_exit:
+
+	if (BP_NOMCP(sc)) {
+		DBPRINT(sc, BXE_INFO,
+		    "%s(): Old No MCP load counts:  %d, %d, %d\n", __FUNCTION__,
+		    load_count[0], load_count[1], load_count[2]);
+
+		load_count[0]--;
+		load_count[1 + port]--;
+		DBPRINT(sc, BXE_INFO,
+		    "%s(): New No MCP load counts:  %d, %d, %d\n", __FUNCTION__,
+		    load_count[0], load_count[1], load_count[2]);
+
+		if (load_count[0] == 0)
+			reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
+		else if (load_count[1 + BP_PORT(sc)] == 0)
+			reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
+		else
+			reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
+	} else {
+		/* Tell MCP driver unload is complete. */
+		reset_code = bxe_fw_command(sc, reset_code);
+	}
+
+	if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
+	    (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
+		bxe__link_reset(sc);
+
+	DELAY(10000);
+
+	/* Reset the chip */
+	bxe_reset_chip(sc, reset_code);
+
+	DELAY(10000);
+
+	/* Report UNLOAD_DONE to MCP */
+	if (!BP_NOMCP(sc))
+		bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
+	sc->port.pmf = 0;
+
+	/* Free RX chains and buffers. */
+	bxe_free_rx_chains(sc);
+
+	/* Free TX chains and buffers. */
+	bxe_free_tx_chains(sc);
+
+	sc->state = BXE_STATE_CLOSED;
+
+	bxe_ack_int(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |BXE_VERBOSE_UNLOAD);
+	return(rc);
+}
+
+
+/*
+ * Device shutdown function.
+ *
+ * Stops and resets the controller.
+ *
+ * Returns:
+ *   Nothing
+ */
+static int
+bxe_shutdown(device_t dev)
+{
+	struct bxe_softc *sc;
+
+	sc = device_get_softc(dev);
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+
+	BXE_CORE_LOCK(sc);
+	bxe_stop_locked(sc, UNLOAD_NORMAL);
+	BXE_CORE_UNLOCK(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+	return (0);
+}
+
+/*
+ * Prints out link speed and duplex setting to console.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_link_report(struct bxe_softc *sc)
+{
+	uint32_t line_speed;
+	uint16_t vn_max_rate;
+
+	DBENTER(BXE_VERBOSE_PHY);
+
+	if (sc->link_vars.link_up) {
+		/* Report the link status change to OS. */
+		if (sc->state == BXE_STATE_OPEN)
+			if_link_state_change(sc->bxe_ifp, LINK_STATE_UP);
+		line_speed = sc->link_vars.line_speed;
+		if (IS_E1HMF(sc)){
+			vn_max_rate = ((sc->mf_config[BP_E1HVN(sc)] &
+			    FUNC_MF_CFG_MAX_BW_MASK) >>
+			    FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
+			if (vn_max_rate < line_speed)
+				line_speed = vn_max_rate;
+		}
+
+		BXE_PRINTF("Link is up, %d Mbps, ", line_speed);
+
+		if (sc->link_vars.duplex == MEDIUM_FULL_DUPLEX)
+			printf("full duplex");
+		else
+			printf("half duplex");
+		if (sc->link_vars.flow_ctrl) {
+			if (sc->link_vars.flow_ctrl & FLOW_CTRL_RX) {
+				printf(", receive ");
+				if (sc->link_vars.flow_ctrl & FLOW_CTRL_TX)
+					printf("& transmit ");
+			} else
+				printf(", transmit ");
+			printf("flow control ON");
+		}
+		printf("\n");
+	} else {
+		/* Report the link down */
+		BXE_PRINTF("Link is down.\n");
+		if_link_state_change(sc->bxe_ifp, LINK_STATE_DOWN);
+	}
+
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe__link_status_update(struct bxe_softc *sc)
+{
+	DBENTER(BXE_VERBOSE_PHY);
+
+	if (bxe_stats_enable == FALSE || sc->state != BXE_STATE_OPEN)
+		return;
+
+	bxe_link_status_update(&sc->link_params, &sc->link_vars);
+
+	if (sc->link_vars.link_up)
+		bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
+	else
+		bxe_stats_handle(sc, STATS_EVENT_STOP);
+	bxe_read_mf_cfg(sc);
+	/* Indicate link status. */
+	bxe_link_report(sc);
+
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+/*
+ * Calculate flow control to advertise during autonegotiation.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_calc_fc_adv(struct bxe_softc *sc)
+{
+	DBENTER(BXE_EXTREME_PHY);
+
+	switch (sc->link_vars.ieee_fc &
+	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
+
+	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
+		sc->port.advertising &= ~(ADVERTISED_Asym_Pause |
+		    ADVERTISED_Pause);
+		break;
+
+	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
+		sc->port.advertising |= (ADVERTISED_Asym_Pause |
+		    ADVERTISED_Pause);
+		break;
+
+	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
+		sc->port.advertising |= ADVERTISED_Asym_Pause;
+		break;
+
+	default:
+		sc->port.advertising &= ~(ADVERTISED_Asym_Pause |
+		    ADVERTISED_Pause);
+		break;
+	}
+
+	DBEXIT(BXE_EXTREME_PHY);
+}
+
+
+
+/*
+ *
+ * Returns:
+ *
+ */
+static uint8_t
+bxe_initial_phy_init(struct bxe_softc *sc)
+{
+	uint8_t rc;
+
+	DBENTER(BXE_VERBOSE_PHY);
+
+	rc = 0;
+	if (!BP_NOMCP(sc)) {
+
+		/*
+		 * It is recommended to turn off RX flow control for 5771x
+		 * when using jumbo frames for better performance.
+		 */
+		if (!IS_E1HMF(sc) & (sc->mbuf_alloc_size > 5000))
+			sc->link_params.req_fc_auto_adv = FLOW_CTRL_TX;
+		else
+			sc->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
+
+		bxe_acquire_phy_lock(sc);
+		rc = bxe_phy_init(&sc->link_params, &sc->link_vars);
+		bxe_release_phy_lock(sc);
+
+		bxe_calc_fc_adv(sc);
+		if (sc->link_vars.link_up) {
+		    bxe_stats_handle(sc,STATS_EVENT_LINK_UP);
+		    bxe_link_report(sc);
+		}
+
+	} else {
+		DBPRINT(sc, 1,
+		    "%s(): Bootcode is not running, not initializing link!\n",
+		    __FUNCTION__);
+		rc = EINVAL;
+	}
+
+	DBEXIT(BXE_VERBOSE_PHY);
+	return (rc);
+}
+
+
+
+/*
+ * Handles controller initialization.
+ *
+ * Must be called from a locked routine.  Since this code
+ * may be called from the OS it does not provide a return
+ * error value and must clean-up it's own mess.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_init_locked(struct bxe_softc *sc, int load_mode)
+{
+	struct ifnet *ifp;
+	uint32_t load_code;
+	int i, port;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	BXE_CORE_LOCK_ASSERT(sc);
+
+	ifp = sc->bxe_ifp;
+	/* Skip if we're in panic mode. */
+	if (sc->panic) {
+		DBPRINT(sc, BXE_WARN, "%s(): Panic mode enabled, exiting!\n",
+		    __FUNCTION__);
+		goto bxe_init_locked_exit;
+	}
+
+	/* Check if the driver is still running and bail out if it is. */
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Init called while driver is running!\n",
+		    __FUNCTION__);
+		goto bxe_init_locked_exit;
+	}
+
+	/*
+	 * Send LOAD_REQUEST command to MCP.
+	 * The MCP will return the type of LOAD
+	 * the driver should perform.
+	 * - If it is the first port to be initialized
+	 *   then all common blocks should be initialized.
+	 * - If it is not the first port to be initialized
+	 *   then don't do the common block initialization.
+	 */
+	sc->state = BXE_STATE_OPENING_WAIT4_LOAD;
+
+	if (BP_NOMCP(sc)) {
+		port = BP_PORT(sc);
+
+		DBPRINT(sc, BXE_INFO,
+		    "%s(): Old No MCP load counts:  %d, %d, %d\n",
+		    __FUNCTION__,
+		    load_count[0], load_count[1], load_count[2]);
+
+		load_count[0]++;
+		load_count[1 + port]++;
+
+		DBPRINT(sc, BXE_INFO,
+		    "%s(): New No MCP load counts:  %d, %d, %d\n",
+		    __FUNCTION__,
+		    load_count[0], load_count[1], load_count[2]);
+
+		/* No MCP to tell us what to do. */
+		if (load_count[0] == 1)
+			load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
+		else if (load_count[1 + port] == 1)
+			load_code = FW_MSG_CODE_DRV_LOAD_PORT;
+		else
+			load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
+
+	} else {
+		/* Ask the MCP what type of initialization we need to do. */
+		load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ);
+
+		if ((load_code == 0) ||
+		    (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED)) {
+			DBPRINT(sc, (BXE_WARN_LOAD | BXE_WARN_RESET),
+			    "%s(): Bootcode refused load request.!\n",
+			    __FUNCTION__);
+			goto bxe_init_locked_failed1;
+		}
+	}
+
+	/* Keep track of whether we are controlling the port. */
+	if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
+	    (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
+		sc->port.pmf = 1;
+	else
+		sc->port.pmf = 0;
+
+	/* Block any interrupts until we're ready. */
+	sc->intr_sem = 1;
+
+	/* Initialize hardware. */
+	if (bxe_init_hw(sc, load_code)){
+		BXE_PRINTF("HW init failed, aborting\n");
+		goto bxe_init_locked_failed1;
+	}
+
+	/* Calculate and save the Ethernet MTU size. */
+	sc->port.ether_mtu = ifp->if_mtu + ETHER_HDR_LEN +
+	    (ETHER_VLAN_ENCAP_LEN * 2) + ETHER_CRC_LEN + 4;
+
+	/* Setup the mbuf allocation size for RX frames. */
+	if (sc->port.ether_mtu <= MCLBYTES)
+		sc->mbuf_alloc_size = MCLBYTES;
+	else if (sc->port.ether_mtu <= PAGE_SIZE)
+		sc->mbuf_alloc_size = PAGE_SIZE;
+	else
+		sc->mbuf_alloc_size = MJUM9BYTES;
+
+
+	DBPRINT(sc, BXE_INFO,
+	    "%s(): mbuf_alloc_size = %d, max_frame_size = %d\n", __FUNCTION__,
+	    sc->mbuf_alloc_size, sc->port.ether_mtu);
+
+	/* Setup NIC internals and enable interrupts. */
+	bxe_init_nic(sc, load_code);
+
+	if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) &&
+	    (sc->common.shmem2_base)){
+		if (bxe_dcc_enable) {
+			BXE_PRINTF(" setting dcc support\n");
+			SHMEM2_WR(sc, dcc_support,
+			    (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
+			     SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
+		}
+	}
+
+	/* Tell MCP that driver load is done. */
+	if (!BP_NOMCP(sc)) {
+		load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE);
+		if (!load_code) {
+			BXE_PRINTF("%s(%d): Driver load failed! No MCP "
+			    "response to LOAD_DONE!\n", __FILE__, __LINE__);
+			goto bxe_init_locked_failed2;
+		}
+	}
+
+	sc->state = BXE_STATE_OPENING_WAIT4_PORT;
+
+	/* Enable ISR for PORT_SETUP ramrod. */
+	sc->intr_sem = 0;
+
+	/* Setup the leading connection for the controller. */
+	if (bxe_setup_leading(sc))
+		DBPRINT(sc, 1, "%s(): Initial PORT_SETUP ramrod failed. "
+		    "State is not OPEN!\n", __FUNCTION__);
+
+
+	if (CHIP_IS_E1H(sc)) {
+		if (sc->mf_config[BP_E1HVN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
+			BXE_PRINTF("Multi-function mode is disabled\n");
+			/* sc->state = BXE_STATE_DISABLED; */
+		}
+		/* Setup additional client connections for RSS/multi-queue */
+		if (sc->state == BXE_STATE_OPEN) {
+			for (i = 1; i < sc->num_queues; i++) {
+				if (bxe_setup_multi(sc, i)) {
+					DBPRINT(sc, 1,
+		"%s(): fp[%d] CLIENT_SETUP ramrod failed! State not OPEN!\n",
+					    __FUNCTION__, i);
+					goto bxe_init_locked_failed4;
+				}
+			}
+		}
+	}
+
+	DELAY(5000);
+	bxe_int_enable(sc);
+	DELAY(5000);
+	/* Initialize statistics. */
+	bxe_stats_init(sc);
+	DELAY(1000);
+
+	/* Load our MAC address. */
+	bcopy(IF_LLADDR(sc->bxe_ifp), sc->link_params.mac_addr, ETHER_ADDR_LEN);
+
+	if (CHIP_IS_E1(sc))
+		bxe_set_mac_addr_e1(sc, 1);
+	else
+		bxe_set_mac_addr_e1h(sc, 1);
+
+
+	DELAY(1000);
+
+	/* Perform PHY initialization for the primary port. */
+	if (sc->port.pmf)
+		bxe_initial_phy_init(sc);
+
+	DELAY(1000);
+
+	/* Start fastpath. */
+	switch (load_mode) {
+	case LOAD_NORMAL:
+	case LOAD_OPEN:
+		/* Initialize the receive filters. */
+		bxe_set_rx_mode(sc);
+		break;
+
+	case LOAD_DIAG:
+		/* Initialize the receive filters. */
+		bxe_set_rx_mode(sc);
+		sc->state = BXE_STATE_DIAG;
+		break;
+
+	default:
+		DBPRINT(sc, BXE_WARN, "%s(): Unknown load mode (%d)!\n",
+		    __FUNCTION__, load_mode);
+		break;
+	}
+
+	if (!sc->port.pmf)
+		bxe__link_status_update(sc);
+
+	DELAY(1000);
+	/* Tell the stack the driver is running and the TX queue is open. */
+	ifp->if_drv_flags = IFF_DRV_RUNNING;
+
+	/* Schedule our periodic timer tick. */
+	callout_reset(&sc->bxe_tick_callout, hz, bxe_tick, sc);
+	/* Everything went OK, go ahead and exit. */
+	goto bxe_init_locked_exit;
+	/* Try and gracefully shutdown the device because of a failure. */
+/* Try and gracefully shutdown the device because of a failure. */
+bxe_init_locked_failed4:
+
+	for (i = 1; i < sc->num_queues; i++)
+		bxe_stop_multi(sc, i);
+
+	bxe_stop_leading(sc);
+
+	bxe_stats_handle(sc, STATS_EVENT_STOP);
+
+bxe_init_locked_failed2:
+
+	bxe_int_disable(sc);
+
+bxe_init_locked_failed1:
+
+	if (!BP_NOMCP(sc)) {
+		bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE);
+		bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
+		bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
+	}
+	sc->port.pmf = 0;
+
+	DBPRINT(sc, BXE_INFO, "%s(): Initialization failed!\n", __FUNCTION__);
+
+bxe_init_locked_exit:
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Ramrod wait function.
+ *
+ * Waits for a ramrod command to complete.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure
+ */
+static int
+bxe_wait_ramrod(struct bxe_softc *sc, int state, int idx, int *state_p,
+    int poll)
+{
+	int rc, timeout;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+
+	DBPRINT(sc, BXE_VERBOSE_RAMROD, "%s(): %s for state 0x%08X on fp[%d], "
+	    "currently 0x%08X.\n", __FUNCTION__, poll ? "Polling" : "Waiting",
+	    state, idx, *state_p);
+
+	rc = 0;
+	timeout = 5000;
+	while (timeout) {
+
+		/* Manually check for the completion. */
+		if (poll) {
+			bxe_rxeof(sc->fp);
+			/*
+			 * Some commands don't use the leading client
+			 * connection.
+			 */
+			if (idx)
+				bxe_rxeof(&sc->fp[idx]);
+		}
+
+		/* State may be changed by bxe_sp_event(). */
+		mb();
+		if (*state_p == state)
+			goto bxe_wait_ramrod_exit;
+
+		timeout--;
+
+		/* Pause 1ms before checking again. */
+		DELAY(1000);
+	}
+
+	/* We timed out polling for a completion. */
+	DBPRINT(sc, 1, "%s(): Timeout %s for state 0x%08X on fp[%d]. "
+	    "Got 0x%x instead\n", __FUNCTION__, poll ? "polling" : "waiting",
+	    state, idx, *state_p);
+
+	rc = EBUSY;
+
+bxe_wait_ramrod_exit:
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+	return (rc);
+}
+
+/*
+ *
+ *
+ */
+static void
+bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr,
+    uint32_t addr, uint32_t len)
+{
+	int dmae_wr_max, offset;
+	DBENTER(BXE_VERBOSE_LOAD);
+
+	dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
+	offset = 0;
+	while (len > dmae_wr_max) {
+		bxe_write_dmae(sc, phys_addr + offset, addr + offset,
+		    dmae_wr_max);
+		offset += dmae_wr_max * 4;
+		len -= dmae_wr_max;
+	}
+	bxe_write_dmae(sc, phys_addr + offset, addr + offset, len);
+	DBEXIT(BXE_VERBOSE_LOAD);
+
+}
+
+
+
+#define	INIT_MEM_WR(block, reg, part, hw, data, reg_off, len) \
+	bxe_init_str_wr(sc, GRCBASE_##block + reg + reg_off * 4, data, len)
+
+
+/*
+ * Write a block of data to a range of registers.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_str_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
+    uint32_t len)
+{
+	uint32_t i;
+	for (i = 0; i < len; i++)
+		REG_WR(sc, addr + i * 4, data[i]);
+}
+
+/*
+ * Write a block of data to a range of registers using indirect access.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_ind_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
+    uint16_t len)
+{
+	uint32_t i;
+	for (i = 0; i < len; i++)
+		REG_WR_IND(sc, addr + i * 4, data[i]);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_write_big_buf(struct bxe_softc *sc, uint32_t addr, uint32_t len)
+{
+	DBENTER(BXE_VERBOSE_LOAD);
+#ifdef USE_DMAE
+	if (sc->dmae_ready)
+		bxe_write_dmae_phys_len(sc, sc->gunzip_mapping,	addr, len);
+	else
+		bxe_init_str_wr(sc, addr, sc->gunzip_buf, len);
+#else
+	bxe_init_str_wr(sc, addr, sc->gunzip_buf, len);
+#endif
+
+	DBEXIT(BXE_VERBOSE_LOAD);
+}
+
+/*
+ * Fill areas of device memory with the specified value.
+ *
+ * Generally used to clear a small area of device memory prior to writing
+ * firmware to STORM memory or writing STORM firmware to device memory.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_fill(struct bxe_softc *sc, uint32_t addr, int fill, uint32_t len)
+{
+	uint32_t cur_len, i, leftovers, length;
+
+	DBENTER(BXE_VERBOSE_LOAD);
+
+	length = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
+	leftovers = length / 4;
+	memset(sc->gunzip_buf, fill, length);
+
+	for (i = 0; i < len; i += leftovers) {
+		cur_len = min(leftovers, len - i);
+		bxe_write_big_buf(sc, addr + i * 4, cur_len);
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_wr_64(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
+    uint32_t len64)
+{
+	uint64_t data64, *pdata;
+	uint32_t buf_len32, cur_len, len;
+	int i;
+
+	buf_len32 = FW_BUF_SIZE / 4;
+	len = len64 * 2;
+	/* 64 bit value is in a blob: first low DWORD, then high DWORD. */
+	data64 = HILO_U64((*(data + 1)), (*data));
+	len64 = min((uint32_t)(FW_BUF_SIZE / 8), len64);
+	for (i = 0; i < len64; i++) {
+		pdata = ((uint64_t *)(sc->gunzip_buf)) + i;
+		*pdata = data64;
+	}
+
+	for (i = 0; i < len; i += buf_len32) {
+		cur_len = min(buf_len32, len - i);
+		bxe_write_big_buf(sc, addr + i*4, cur_len);
+	}
+}
+
+
+/*
+ * There are different blobs for each PRAM section. In addition, each
+ * blob write operation is divided into multiple, smaller write
+ * operations in order to decrease the amount of physically contiguous
+ * buffer memory needed. Thus, when we select a blob, the address may
+ * be with some offset from the beginning of PRAM section. The same
+ * holds for the INT_TABLE sections.
+ */
+
+#define	IF_IS_INT_TABLE_ADDR(base, addr) \
+	if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
+
+#define	IF_IS_PRAM_ADDR(base, addr) \
+	if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+
+static const uint8_t *
+bxe_sel_blob(struct bxe_softc *sc, uint32_t addr, const uint8_t *data)
+{
+
+	IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
+		data = INIT_TSEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
+			data = INIT_CSEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
+			data = INIT_USEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
+			data = INIT_XSEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
+			data = INIT_TSEM_PRAM_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
+			data = INIT_CSEM_PRAM_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
+			data = INIT_USEM_PRAM_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
+			data = INIT_XSEM_PRAM_DATA(sc);
+
+	return (data);
+
+}
+
+static void
+bxe_write_big_buf_wb(struct bxe_softc *sc, uint32_t addr, uint32_t len)
+{
+	if (sc->dmae_ready)
+		bxe_write_dmae_phys_len(sc, sc->gunzip_mapping, addr, len);
+	else
+		bxe_init_ind_wr(sc, addr, sc->gunzip_buf, len);
+}
+
+
+#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
+	do { \
+		memcpy(sc->gunzip_buf, data, (len32)*4); \
+		bxe_write_big_buf_wb(sc, addr, len32); \
+	} while (0)
+
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_wr_wb(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
+    uint32_t len)
+{
+	const uint32_t *old_data;
+
+	DBENTER(BXE_VERBOSE_LOAD);
+	old_data = data;
+	data = (const uint32_t *)bxe_sel_blob(sc, addr, (const uint8_t *)data);
+	if (sc->dmae_ready) {
+		if (old_data != data)
+			VIRT_WR_DMAE_LEN(sc, data, addr, len, 1);
+		else
+			VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
+	} else
+		bxe_init_ind_wr(sc, addr, data, len);
+
+	DBEXIT(BXE_VERBOSE_LOAD);
+}
+
+static void
+bxe_init_wr_zp(struct bxe_softc *sc, uint32_t addr, uint32_t len,
+    uint32_t blob_off)
+{
+	BXE_PRINTF("%s(): Compressed FW is not supported yet. "
+	    "ERROR: address:0x%x len:0x%x bloboffset:0x%x\n", __FUNCTION__,
+	    addr, len, blob_off);
+}
+
+/*
+ * Initialize blocks of the device.
+ *
+ * This routine basically performs bulk register programming for different
+ * blocks within the controller.  The file bxe_init_values.h contains a
+ * series of register access operations (read, write, fill, etc.) as well
+ * as a BLOB of data to initialize multiple blocks within the controller.
+ * Block initialization may be supported by all controllers or by specific
+ * models only.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
+{
+	union init_op *op;
+	const uint32_t *data, *data_base;
+	uint32_t i, op_type, addr, len;
+	uint16_t op_end, op_start;
+	int hw_wr;
+
+	op_start = INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
+	    STAGE_START)];
+	op_end = INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage, STAGE_END)];
+	/* If empty block */
+	if (op_start == op_end)
+		return;
+
+	hw_wr = OP_WR_ASIC;
+
+	data_base = INIT_DATA(sc);
+
+	for (i = op_start; i < op_end; i++) {
+
+		op = (union init_op *)&(INIT_OPS(sc)[i]);
+
+		op_type = op->str_wr.op;
+		addr = op->str_wr.offset;
+		len = op->str_wr.data_len;
+		data = data_base + op->str_wr.data_off;
+
+		/* HW/EMUL specific */
+		if ((op_type > OP_WB) && (op_type == hw_wr))
+			op_type = OP_WR;
+
+		switch (op_type) {
+		case OP_RD:
+			REG_RD(sc, addr);
+			break;
+		case OP_WR:
+			REG_WR(sc, addr, op->write.val);
+			break;
+		case OP_SW:
+			bxe_init_str_wr(sc, addr, data, len);
+			break;
+		case OP_WB:
+			bxe_init_wr_wb(sc, addr, data, len);
+			break;
+		case OP_SI:
+			bxe_init_ind_wr(sc, addr, data, len);
+			break;
+		case OP_ZR:
+			bxe_init_fill(sc, addr, 0, op->zero.len);
+			break;
+		case OP_ZP:
+			bxe_init_wr_zp(sc, addr, len, op->str_wr.data_off);
+			break;
+		case OP_WR_64:
+			bxe_init_wr_64(sc, addr, data, len);
+			break;
+		default:
+			/* happens whenever an op is of a diff HW */
+			break;
+		}
+	}
+}
+
+/*
+ * Handles controller initialization when called from an unlocked routine.
+ * ifconfig calls this function.
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init(void *xsc)
+{
+	struct bxe_softc *sc;
+
+	sc = xsc;
+	DBENTER(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+
+	BXE_CORE_LOCK(sc);
+	bxe_init_locked(sc, LOAD_NORMAL);
+	BXE_CORE_UNLOCK(sc);
+
+	DBEXIT(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+}
+
+/*
+ * Release all resources used by the driver.
+ *
+ * Releases all resources acquired by the driver including interrupts,
+ * interrupt handler, interfaces, mutexes, and DMA memory.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_release_resources(struct bxe_softc *sc)
+{
+	device_t dev;
+	int i;
+
+	DBENTER(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+
+	dev = sc->bxe_dev;
+
+	/* Release interrupt resources. */
+	bxe_interrupt_detach(sc);
+	if ((sc->bxe_flags & BXE_USING_MSIX_FLAG) && sc->msix_count) {
+
+		for (i = 0; i < sc->msix_count; i++) {
+			DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
+			    BXE_VERBOSE_INTR), "%s(): Releasing MSI-X[%d] "
+			    "vector.\n", __FUNCTION__, i);
+			if (sc->bxe_msix_res[i] && sc->bxe_msix_rid[i])
+				bus_release_resource(dev, SYS_RES_IRQ,
+				    sc->bxe_msix_rid[i], sc->bxe_msix_res[i]);
+		}
+
+		pci_release_msi(dev);
+
+	} else if ((sc->bxe_flags & BXE_USING_MSI_FLAG) && sc->msi_count) {
+
+		for (i = 0; i < sc->msi_count; i++) {
+			DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
+			    BXE_VERBOSE_INTR), "%s(): Releasing MSI[%d] "
+			    "vector.\n", __FUNCTION__, i);
+			if (sc->bxe_msi_res[i] && sc->bxe_msi_rid[i])
+				bus_release_resource(dev, SYS_RES_IRQ,
+				    sc->bxe_msi_rid[i], sc->bxe_msi_res[i]);
+		}
+
+		pci_release_msi(dev);
+
+	} else {
+
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
+		    BXE_VERBOSE_INTR), "%s(): Releasing legacy interrupt.\n",
+		    __FUNCTION__);
+		if (sc->bxe_irq_res != NULL)
+			bus_release_resource(dev, SYS_RES_IRQ, sc->bxe_irq_rid,
+			    sc->bxe_irq_res);
+	}
+
+	/* Free the DMA memory */
+	bxe_dma_free(sc);
+
+	/* Release the PCIe BAR0 mapped memory */
+	if (sc->bxe_res != NULL) {
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+		    "%s(): Releasing PCI BAR0 memory.\n", __FUNCTION__);
+		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
+		    sc->bxe_res);
+	}
+
+	/* Release the PCIe BAR2 mapped memory */
+	if (sc->bxe_db_res != NULL) {
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+		    "%s(): Releasing PCI BAR2 memory.\n", __FUNCTION__);
+		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2),
+		    sc->bxe_db_res);
+	}
+
+	/* Release the FreeBSD interface. */
+	if (sc->bxe_ifp != NULL)
+		if_free(sc->bxe_ifp);
+
+	BXE_CORE_LOCK_DESTROY(sc);
+	BXE_SP_LOCK_DESTROY(sc);
+	BXE_DMAE_LOCK_DESTROY(sc);
+	BXE_PHY_LOCK_DESTROY(sc);
+	BXE_FWMB_LOCK_DESTROY(sc);
+	BXE_PRINT_LOCK_DESTROY(sc);
+}
+
+
+/*
+ * Indirect register write.
+ *
+ * Writes NetXtreme II registers using an index/data register pair in PCI
+ * configuration space.  Using this mechanism avoids issues with posted
+ * writes but is much slower than memory-mapped I/O.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t offset, uint32_t val)
+{
+	DBPRINT(sc, BXE_INSANE, "%s(); offset = 0x%08X, val = 0x%08X\n",
+		__FUNCTION__, offset, val);
+
+	pci_write_config(sc->bxe_dev, PCICFG_GRC_ADDRESS, offset, 4);
+	pci_write_config(sc->bxe_dev, PCICFG_GRC_DATA, val, 4);
+
+	/* Return to a safe address. */
+	pci_write_config(sc->bxe_dev, PCICFG_GRC_ADDRESS,
+	    PCICFG_VENDOR_ID_OFFSET, 4);
+}
+
+
+/*
+ * Indirect register read.
+ *
+ * Reads NetXtreme II registers using an index/data register pair in PCI
+ * configuration space.  Using this mechanism avoids issues with posted
+ * reads but is much slower than memory-mapped I/O.
+ *
+ * Returns:
+ *   The value of the register.
+ */
+static uint32_t
+bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t offset)
+{
+	uint32_t val;
+
+	pci_write_config(sc->bxe_dev, PCICFG_GRC_ADDRESS, offset, 4);
+	val = pci_read_config(sc->bxe_dev, PCICFG_GRC_DATA, 4);
+
+	/* Return to a safe address. */
+	pci_write_config(sc->bxe_dev, PCICFG_GRC_ADDRESS,
+	    PCICFG_VENDOR_ID_OFFSET, 4);
+
+	DBPRINT(sc, BXE_INSANE, "%s(); offset = 0x%08X, val = 0x%08X\n",
+	    __FUNCTION__, offset, val);
+	return (val);
+}
+
+
+
+static uint32_t dmae_reg_go_c[] = {
+	DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
+	DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
+	DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
+	DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
+};
+
+
+/*
+ * Copy DMAE command into memory and start the command.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx)
+{
+	uint32_t cmd_offset;
+	int i;
+	cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
+
+	for (i = 0; i < (sizeof(struct dmae_command) / 4); i++) {
+		REG_WR(sc, cmd_offset + i * 4, *(((uint32_t *)dmae) + i));
+		DBPRINT(sc, BXE_INSANE, "%s(): DMAE cmd[%d].%d : 0x%08X\n",
+		    __FUNCTION__, idx, i, cmd_offset + i * 4);
+	}
+
+	/* Kick off the command. */
+	REG_WR(sc, dmae_reg_go_c[idx], 1);
+}
+
+
+/*
+ * Perform a DMAE write to device memory.
+ *
+ * Some of the registers on the 577XX controller are 128bits wide.  It is
+ * required that when accessing those registers that they be written
+ * atomically and that no intervening bus acceses to the device occur.
+ * This could be handled by a lock held across all driver instances for
+ * the device or it can be handled by performing a DMA operation when
+ * writing to the device.  This code implements the latter.
+ *
+ * Returns:
+ *   None.
+ */
+void
+bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, uint32_t dst_addr,
+    uint32_t len32)
+{
+	struct dmae_command dmae;
+	uint32_t *data, *wb_comp;
+	int timeout;
+
+	DBENTER(BXE_INSANE_REGS);
+
+	DBPRINT(sc, BXE_EXTREME_REGS,
+	    "%s(): host addr = 0x%jX, device addr = 0x%08X, length = %d.\n",
+	    __FUNCTION__, (uintmax_t)dma_addr, dst_addr, (int)len32);
+
+	wb_comp = BXE_SP(sc, wb_comp);
+	/* Fall back to indirect access if DMAE is not ready. */
+	if (!sc->dmae_ready) {
+		data = BXE_SP(sc, wb_data[0]);
+
+		DBPRINT(sc, 1, "%s(): DMAE not ready, using indirect.\n",
+		    __FUNCTION__);
+
+		bxe_init_ind_wr(sc, dst_addr, data, len32);
+		goto bxe_write_dmae_exit;
+	}
+
+	memset(&dmae, 0, sizeof(struct dmae_command));
+
+	dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+	    DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+	dmae.src_addr_lo = U64_LO(dma_addr);
+	dmae.src_addr_hi = U64_HI(dma_addr);
+	dmae.dst_addr_lo = dst_addr >> 2;
+	dmae.dst_addr_hi = 0;
+	dmae.len = len32;
+	dmae.comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
+	dmae.comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
+	dmae.comp_val = BXE_WB_COMP_VAL;
+
+	BXE_DMAE_LOCK(sc);
+
+	*wb_comp = 0;
+
+	bxe_post_dmae(sc, &dmae, INIT_DMAE_C(sc));
+
+	DELAY(5);
+
+	timeout = 4000;
+	while (*wb_comp != BXE_WB_COMP_VAL) {
+		if (!timeout) {
+			DBPRINT(sc, 1,
+			"%s(): DMAE timeout (dst_addr = 0x%08X, len = %d)!\n",
+			    __FUNCTION__, dst_addr, len32);
+			break;
+		}
+		timeout--;
+		DELAY(5);
+	}
+
+	BXE_DMAE_UNLOCK(sc);
+
+bxe_write_dmae_exit:
+	DBEXIT(BXE_INSANE_REGS);
+}
+
+
+/*
+* Perform a DMAE read from to device memory.
+*
+ * Some of the registers on the 577XX controller are 128bits wide.  It is
+ * required that when accessing those registers that they be read
+ * atomically and that no intervening bus acceses to the device occur.
+ * This could be handled by a lock held across all driver instances for
+ * the device or it can be handled by performing a DMA operation when
+ * reading from the device.  This code implements the latter.
+*
+* Returns:
+*   None.
+*/
+void
+bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr,
+    uint32_t len32)
+{
+	struct dmae_command dmae;
+	uint32_t *data, *wb_comp;
+	int i, timeout;
+
+	DBENTER(BXE_INSANE);
+
+	wb_comp = BXE_SP(sc, wb_comp);
+	/* Fall back to indirect access if DMAE is not ready. */
+	if (!sc->dmae_ready) {
+		data = BXE_SP(sc, wb_data[0]);
+
+		DBPRINT(sc, 1, "%s(): DMAE not ready, using indirect.\n",
+		    __FUNCTION__);
+
+		for (i = 0; i < len32; i++)
+			data[i] = bxe_reg_rd_ind(sc, src_addr + i * 4);
+
+		goto bxe_read_dmae_exit;
+	}
+
+	memset(&dmae, 0, sizeof(struct dmae_command));
+
+	dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+	    DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+
+	dmae.src_addr_lo = src_addr >> 2;
+	dmae.src_addr_hi = 0;
+	dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
+	dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
+	dmae.len = len32;
+	dmae.comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
+	dmae.comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
+	dmae.comp_val = BXE_WB_COMP_VAL;
+
+	BXE_DMAE_LOCK(sc);
+
+	memset(BXE_SP(sc, wb_data[0]), 0, sizeof(uint32_t) * 4);
+	*wb_comp = 0;
+
+	bxe_post_dmae(sc, &dmae, INIT_DMAE_C(sc));
+
+	DELAY(5);
+
+	timeout = 200;
+	while (*wb_comp != BXE_WB_COMP_VAL) {
+		if (!timeout) {
+			DBPRINT(sc, 1,
+			"%s(): DMAE timeout (src_addr = 0x%08X, len = %d)!\n",
+			    __FUNCTION__, src_addr, len32);
+			break;
+		}
+		timeout--;
+		DELAY(5);
+	}
+
+	BXE_DMAE_UNLOCK(sc);
+
+bxe_read_dmae_exit:
+	DBEXIT(BXE_INSANE);
+}
+
+/*
+ * DMAE write wrapper.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_wb_wr(struct bxe_softc *sc, int reg, uint32_t val_hi, uint32_t val_lo)
+{
+	uint32_t wb_write[2];
+
+	wb_write[0] = val_hi;
+	wb_write[1] = val_lo;
+	REG_WR_DMAE(sc, reg, wb_write, 2);
+}
+
+
+
+/*
+ * Poll a register waiting for a value.
+ *
+ * Returns:
+ *   The last read register value.
+ */
+static __inline
+uint32_t bxe_reg_poll(struct bxe_softc *sc, uint32_t reg, uint32_t expected,
+    int ms, int wait)
+{
+	uint32_t val;
+
+	do {
+		val = REG_RD(sc, reg);
+		if (val == expected)
+			break;
+		ms -= wait;
+		DELAY(wait * 1000);
+
+	} while (ms > 0);
+
+	return (val);
+}
+
+
+/*
+ * Microcode assert display.
+ *
+ * This function walks through each STORM processor and prints out a
+ * listing of all asserts currently in effect.  Useful for post-mortem
+ * debugging.
+ *
+ * Returns:
+ *   The number of asserts detected.
+ */
+static int
+bxe_mc_assert(struct bxe_softc *sc)
+{
+	uint32_t row0, row1, row2, row3;
+	char last_idx;
+	int i, rc;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	rc = 0;
+	/* XSTORM */
+	last_idx = REG_RD8(sc, BAR_XSTORM_INTMEM +
+	    XSTORM_ASSERT_LIST_INDEX_OFFSET);
+
+	if (last_idx)
+		DBPRINT(sc, BXE_FATAL, "DATA XSTORM_ASSERT_LIST_INDEX 0x%x\n",
+		    last_idx);
+
+	/* Print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 = REG_RD(sc, BAR_XSTORM_INTMEM +
+		    XSTORM_ASSERT_LIST_OFFSET(i));
+		row1 = REG_RD(sc, BAR_XSTORM_INTMEM +
+		    XSTORM_ASSERT_LIST_OFFSET(i) + 4);
+		row2 = REG_RD(sc, BAR_XSTORM_INTMEM +
+		    XSTORM_ASSERT_LIST_OFFSET(i) + 8);
+		row3 = REG_RD(sc, BAR_XSTORM_INTMEM +
+		    XSTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			DBPRINT(sc, BXE_FATAL, "DATA XSTORM_ASSERT_INDEX %d = "
+			    "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
+			    row1, row0);
+			rc++;
+		} else
+			break;
+	}
+
+	/* TSTORM */
+	last_idx = REG_RD8(sc, BAR_TSTORM_INTMEM +
+	    TSTORM_ASSERT_LIST_INDEX_OFFSET);
+
+	if (last_idx)
+		DBPRINT(sc, BXE_FATAL, "DATA TSTORM_ASSERT_LIST_INDEX 0x%x\n",
+			last_idx);
+
+	/* Print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 = REG_RD(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_ASSERT_LIST_OFFSET(i));
+		row1 = REG_RD(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_ASSERT_LIST_OFFSET(i) + 4);
+		row2 = REG_RD(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_ASSERT_LIST_OFFSET(i) + 8);
+		row3 = REG_RD(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			DBPRINT(sc, BXE_FATAL, "DATA TSTORM_ASSERT_INDEX %d = "
+			    "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
+			    row1, row0);
+			rc++;
+		} else
+			break;
+	}
+
+	/* CSTORM */
+	last_idx = REG_RD8(sc, BAR_CSTORM_INTMEM +
+	    CSTORM_ASSERT_LIST_INDEX_OFFSET);
+
+	if (last_idx)
+		DBPRINT(sc, BXE_FATAL, "DATA CSTORM_ASSERT_LIST_INDEX 0x%x\n",
+		    last_idx);
+
+	/* Print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 = REG_RD(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_ASSERT_LIST_OFFSET(i));
+		row1 = REG_RD(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_ASSERT_LIST_OFFSET(i) + 4);
+		row2 = REG_RD(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_ASSERT_LIST_OFFSET(i) + 8);
+		row3 = REG_RD(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			DBPRINT(sc, BXE_FATAL, "DATA CSTORM_ASSERT_INDEX %d = "
+			    "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
+			    row1, row0);
+			rc++;
+		} else
+			break;
+	}
+
+	/* USTORM */
+	last_idx = REG_RD8(sc, BAR_USTORM_INTMEM +
+	    USTORM_ASSERT_LIST_INDEX_OFFSET);
+
+	if (last_idx)
+		DBPRINT(sc, BXE_FATAL, "DATA USTORM_ASSERT_LIST_INDEX 0x%x\n",
+		    last_idx);
+
+	/* Print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 = REG_RD(sc, BAR_USTORM_INTMEM +
+		    USTORM_ASSERT_LIST_OFFSET(i));
+		row1 = REG_RD(sc, BAR_USTORM_INTMEM +
+		    USTORM_ASSERT_LIST_OFFSET(i) + 4);
+		row2 = REG_RD(sc, BAR_USTORM_INTMEM +
+		    USTORM_ASSERT_LIST_OFFSET(i) + 8);
+		row3 = REG_RD(sc, BAR_USTORM_INTMEM +
+		    USTORM_ASSERT_LIST_OFFSET(i) + 12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			DBPRINT(sc, BXE_FATAL, "DATA USTORM_ASSERT_INDEX %d = "
+			    "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
+			    row1, row0);
+			rc++;
+		} else
+			break;
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+	return (rc);
+}
+
+
+/*
+ * Perform a panic dump.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_panic_dump(struct bxe_softc *sc)
+{
+	DBENTER(BXE_FATAL);
+
+	sc->stats_state = STATS_STATE_DISABLED;
+
+	BXE_PRINTF("---------- Begin crash dump ----------\n");
+
+	/* Idle	check is run twice to verify the controller has	stopped. */
+	bxe_idle_chk(sc); bxe_idle_chk(sc);
+	bxe_mc_assert(sc);
+#ifdef BXE_DEBUG
+	bxe_breakpoint(sc);
+#endif
+
+	BXE_PRINTF("----------  End crash dump  ----------\n");
+
+	DBEXIT(BXE_FATAL);
+}
+
+
+/*
+ * Enables interrupt generation.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_int_enable(struct bxe_softc *sc)
+{
+	uint32_t hc_addr, val;
+	int port;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	port = BP_PORT(sc);
+	hc_addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
+	val = REG_RD(sc, hc_addr);
+	if (sc->bxe_flags & BXE_USING_MSIX_FLAG) {
+		if (sc->msix_count == 1) {
+
+			/* Single interrupt, multiple queues.*/
+			DBPRINT(sc, BXE_VERBOSE_INTR,
+		"%s(): Setting host coalescing registers for MSI-X (SIMQ).\n",
+			    __FUNCTION__);
+
+			/* Clear INTx. */
+			val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
+
+			/* Enable single ISR mode, MSI/MSI-X, and attention messages. */
+			val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+			    HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+			    HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+		} else {
+
+			/* Multiple interrupts, multiple queues.*/
+			DBPRINT(sc, BXE_VERBOSE_INTR,
+		"%s(): Setting host coalescing registers for MSI-X (MIMQ).\n",
+			    __FUNCTION__);
+
+			/* Clear single ISR mode and INTx. */
+			val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+			    HC_CONFIG_0_REG_INT_LINE_EN_0);
+
+			/* Enable MSI/MSI-X and attention messages. */
+			val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+    			    HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+		}
+
+	} else if (sc->bxe_flags & BXE_USING_MSI_FLAG) {
+
+		if (sc->msi_count == 1) {
+
+			/* Single interrupt, multiple queues.*/
+			DBPRINT(sc, BXE_VERBOSE_INTR,
+		"%s(): Setting host coalescing registers for MSI (SIMQ).\n",
+			    __FUNCTION__);
+
+			/* Clear INTx. */
+			val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
+
+			/* Enable single ISR mode, MSI/MSI-X, and attention
+			 * messages.
+			 */
+			val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+			    HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+			    HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+		} else {
+			/* Multiple interrupts, multiple queues.*/
+			DBPRINT(sc, BXE_VERBOSE_INTR,
+			    "%s(): Setting host coalescing registers for"
+			    "MSI (MIMQ).\n",
+			    __FUNCTION__);
+
+			/* Clear single ISR mode and INTx. */
+			val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+			    HC_CONFIG_0_REG_INT_LINE_EN_0);
+
+			/* Enable MSI/MSI-X and attention messages. */
+			val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+			    HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+		}
+	} else {
+		/* Single interrupt, single queue. */
+		DBPRINT(sc, BXE_VERBOSE_INTR,
+		    "%s(): Setting host coalescing registers for INTA#.\n",
+		    __FUNCTION__);
+
+		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0   |
+		    HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+		    HC_CONFIG_0_REG_INT_LINE_EN_0     |
+		    HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+		REG_WR(sc, hc_addr, val);
+
+		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
+	}
+
+	/* Write the interrupt mode to the host coalescing block. */
+	REG_WR(sc, hc_addr, val);
+
+	if (CHIP_IS_E1H(sc)) {
+
+		/* Init leading/trailing edge attention generation. */
+		if (IS_E1HMF(sc)) {
+			val = (0xee0f | (1 << (BP_E1HVN(sc) + 4)));
+
+			/*
+			 * Check if this driver instance is the port
+			 * master function.
+			 */
+			if (sc->port.pmf)
+				/* Enable nig & GPIO3 attentions. */
+				val |= 0x1100;
+		} else
+			val = 0xffff;
+
+		REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
+		REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+
+/*
+ * Disables interrupt generation.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_int_disable(struct bxe_softc *sc)
+{
+	uint32_t hc_addr, val;
+	int port;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	port = BP_PORT(sc);
+	hc_addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
+	val = REG_RD(sc, hc_addr);
+
+	val &= ~(HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+	    HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+
+	REG_WR(sc, hc_addr, val);
+
+	if (REG_RD(sc, hc_addr)!= val) {
+		DBPRINT(sc, BXE_WARN, "%s(): BUG! Returned value from IGU "
+		    "doesn't match value written (0x%08X).\n",
+		    __FUNCTION__, val);
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+#define	BXE_CRC32_RESIDUAL	0xdebb20e3
+
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_nvram_acquire_lock(struct bxe_softc *sc)
+{
+	uint32_t val;
+	int i, port, rc;
+
+	DBENTER(BXE_VERBOSE_NVRAM);
+
+	port = BP_PORT(sc);
+	rc = 0;
+	val = 0;
+
+	/* Acquire the NVRAM lock. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
+	    (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
+
+	for (i = 0; i < NVRAM_TIMEOUT_COUNT * 10; i++) {
+		val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
+		if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
+			break;
+
+		DELAY(5);
+	}
+
+	if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
+		DBPRINT(sc, BXE_WARN, "%s(): Cannot acquire NVRAM lock!\n",
+		    __FUNCTION__);
+		rc = EBUSY;
+	}
+
+	DBEXIT(BXE_VERBOSE_NVRAM);
+	return (rc);
+}
+
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_nvram_release_lock(struct bxe_softc *sc)
+{
+	uint32_t val;
+	int i, port, rc;
+
+	DBENTER(BXE_VERBOSE_NVRAM);
+
+	port = BP_PORT(sc);
+	rc = 0;
+	val = 0;
+
+	/* Release the NVRAM lock. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
+	    (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
+
+	for (i = 0; i < NVRAM_TIMEOUT_COUNT * 10; i++) {
+		val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
+		if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
+			break;
+
+		DELAY(5);
+	}
+
+	if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
+		DBPRINT(sc, BXE_WARN, "%s(): Cannot release NVRAM lock!\n",
+		    __FUNCTION__);
+		rc = EBUSY;
+	}
+
+	DBEXIT(BXE_VERBOSE_NVRAM);
+	return (rc);
+}
+
+/*
+ * Returns:
+ *   None.
+ */
+static void
+bxe_nvram_enable_access(struct bxe_softc *sc)
+{
+	uint32_t val;
+
+	DBENTER(BXE_VERBOSE_NVRAM);
+
+	val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
+
+	/* Enable both bits, even on read */
+	REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
+	    (val | MCPR_NVM_ACCESS_ENABLE_EN |
+	     MCPR_NVM_ACCESS_ENABLE_WR_EN));
+
+	DBEXIT(BXE_VERBOSE_NVRAM);
+}
+
+/*
+ * Returns:
+ *   None.
+ */
+static void
+bxe_nvram_disable_access(struct bxe_softc *sc)
+{
+	uint32_t val;
+
+	DBENTER(BXE_VERBOSE_NVRAM);
+
+	val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
+
+	/* Disable both bits, even after read. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
+	    (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
+	    MCPR_NVM_ACCESS_ENABLE_WR_EN)));
+
+	DBEXIT(BXE_VERBOSE_NVRAM);
+}
+
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_nvram_read_dword(struct bxe_softc *sc, uint32_t offset, uint32_t *ret_val,
+    uint32_t cmd_flags)
+{
+	uint32_t val;
+	int i, rc;
+
+	DBENTER(BXE_INSANE_NVRAM);
+
+	/* Build the command word. */
+	cmd_flags |= MCPR_NVM_COMMAND_DOIT;
+
+	/* Need to clear DONE bit separately. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
+
+	/* Address within the NVRAM to read. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
+		(offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
+
+	/* Issue a read command. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
+
+	/* Wait for completion. */
+	*ret_val = 0;
+	rc = EBUSY;
+	for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
+		DELAY(5);
+		val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
+
+		if (val & MCPR_NVM_COMMAND_DONE) {
+			val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
+			val = htobe32(val);
+			*ret_val = val;
+			rc = 0;
+			break;
+		}
+	}
+
+	DBPRINT(sc, BXE_INSANE_NVRAM, "%s(): Read 0x%08X from offset 0x%08X.\n",
+	    __FUNCTION__, *ret_val, offset);
+	DBEXIT(BXE_INSANE_NVRAM);
+	return (rc);
+}
+
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_nvram_read(struct bxe_softc *sc, uint32_t offset, uint8_t *ret_buf,
+    int buf_size)
+{
+	uint32_t cmd_flags, val;
+	int rc;
+
+	DBENTER(BXE_EXTREME_NVRAM);
+
+	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
+		DBPRINT(sc, BXE_WARN, "%s(): Unaligned address or invalid "
+		    "buffer for NVRAM read (offset = 0x%08X, buf_size = %d)!\n",
+		    __FUNCTION__, offset, buf_size);
+		rc = EINVAL;
+		goto bxe_nvram_read_exit;
+	}
+
+	if (offset + buf_size > sc->common.flash_size) {
+		DBPRINT(sc, BXE_WARN, "%s(): Read extends beyond the end of "
+		    "the NVRAM (offset (0x%08X) + buf_size (%d) > flash_size "
+		    "(0x%08X))!\n", __FUNCTION__, offset, buf_size,
+		    sc->common.flash_size);
+		rc = EINVAL;
+		goto bxe_nvram_read_exit;
+	}
+
+	rc = bxe_nvram_acquire_lock(sc);
+	if (rc)
+		goto bxe_nvram_read_exit;
+
+	bxe_nvram_enable_access(sc);
+
+	/* Read the first word(s). */
+	cmd_flags = MCPR_NVM_COMMAND_FIRST;
+	while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
+		rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
+		memcpy(ret_buf, &val, 4);
+
+		/* Advance to the next DWORD. */
+		offset += sizeof(uint32_t);
+		ret_buf += sizeof(uint32_t);
+		buf_size -= sizeof(uint32_t);
+		cmd_flags = 0;
+	}
+
+	/* Read the final word. */
+	if (rc == 0) {
+		cmd_flags |= MCPR_NVM_COMMAND_LAST;
+		rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
+		memcpy(ret_buf, &val, 4);
+	}
+
+	/* Disable access to NVRAM interface. */
+	bxe_nvram_disable_access(sc);
+	bxe_nvram_release_lock(sc);
+
+bxe_nvram_read_exit:
+	DBEXIT(BXE_EXTREME_NVRAM);
+	return (rc);
+}
+
+#ifdef BXE_NVRAM_WRITE_SUPPORT
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_nvram_write_dword(struct bxe_softc *sc, uint32_t offset, uint32_t val,
+uint32_t cmd_flags)
+{
+	int i, rc;
+
+	DBENTER(BXE_VERBOSE_NVRAM);
+
+	/* Build the command word. */
+	cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
+
+	/* Need to clear DONE bit separately. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
+
+	/* Write the data. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
+
+	/* Address to write within the NVRAM. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
+		(offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
+
+	/* Issue the write command. */
+	REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
+
+	/* Wait for completion. */
+	rc = EBUSY;
+	for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
+		DELAY(5);
+		val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
+		if (val & MCPR_NVM_COMMAND_DONE) {
+			rc = 0;
+			break;
+		}
+	}
+
+	DBEXIT(BXE_VERBOSE_NVRAM);
+	return (rc);
+}
+
+#define	BYTE_OFFSET(offset)		(8 * (offset & 0x03))
+
+/*
+ * Returns:
+ *
+ */
+static int
+bxe_nvram_write1(struct bxe_softc *sc, uint32_t offset, uint8_t *data_buf,
+    int buf_size)
+{
+	uint32_t align_offset, cmd_flags, val;
+	int rc;
+
+	DBENTER(BXE_VERBOSE_NVRAM);
+
+	if (offset + buf_size > sc->common.flash_size) {
+		DBPRINT(sc, BXE_WARN, "%s(): Write extends beyond the end of "
+		    "the NVRAM (offset (0x%08X) + buf_size (%d) > flash_size "
+		    "(0x%08X))!\n", __FUNCTION__, offset, buf_size,
+		    sc->common.flash_size);
+		rc = EINVAL;
+		goto bxe_nvram_write1_exit;
+	}
+
+	/* request access to nvram interface */
+	rc = bxe_nvram_acquire_lock(sc);
+	if (rc)
+		goto bxe_nvram_write1_exit;
+
+	/* Enable access to the NVRAM interface. */
+	bxe_nvram_enable_access(sc);
+
+	cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
+	align_offset = (offset & ~0x03);
+	rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
+
+	if (rc == 0) {
+		val &= ~(0xff << BYTE_OFFSET(offset));
+		val |= (*data_buf << BYTE_OFFSET(offset));
+
+		val = be32toh(val);
+		rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
+	}
+
+	/* Disable access to the NVRAM interface. */
+	bxe_nvram_disable_access(sc);
+	bxe_nvram_release_lock(sc);
+
+bxe_nvram_write1_exit:
+	DBEXIT(BXE_VERBOSE_NVRAM);
+	return (rc);
+}
+
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_nvram_write(struct bxe_softc *sc, uint32_t offset, uint8_t *data_buf,
+    int buf_size)
+{
+	uint32_t cmd_flags, val, written_so_far;
+	int rc;
+
+	rc = 0;
+
+	if (buf_size == 1)
+		return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
+
+	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
+		DBPRINT(sc, BXE_WARN, "%s(): Unaligned address or invalid "
+		    "buffer for NVRAM write "
+		    "(offset = 0x%08X, buf_size = %d)!\n", __FUNCTION__,
+		    offset, buf_size);
+		rc = EINVAL;
+		goto bxe_nvram_write_exit;
+	}
+
+	if (offset + buf_size > sc->common.flash_size) {
+		DBPRINT(sc, BXE_WARN, "%s(): Write extends beyond the end of "
+		    "the NVRAM (offset (0x%08X) + buf_size (%d) > flash_size "
+		    "(0x%08X))!\n", __FUNCTION__, offset, buf_size,
+		    sc->common.flash_size);
+		rc = EINVAL;
+		goto bxe_nvram_write_exit;
+	}
+
+	/* Request access to NVRAM interface. */
+	rc = bxe_nvram_acquire_lock(sc);
+	if (rc)
+		goto bxe_nvram_write_exit;
+
+	/* Enable access to the NVRAM interface. */
+	bxe_nvram_enable_access(sc);
+
+	written_so_far = 0;
+	cmd_flags = MCPR_NVM_COMMAND_FIRST;
+	while ((written_so_far < buf_size) && (rc == 0)) {
+		if (written_so_far == (buf_size - sizeof(uint32_t)))
+			cmd_flags |= MCPR_NVM_COMMAND_LAST;
+		else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
+			cmd_flags |= MCPR_NVM_COMMAND_LAST;
+		else if ((offset % NVRAM_PAGE_SIZE) == 0)
+			cmd_flags |= MCPR_NVM_COMMAND_FIRST;
+
+		memcpy(&val, data_buf, 4);
+
+		rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
+
+		/* Advance to the next DWORD. */
+		offset += sizeof(uint32_t);
+		data_buf += sizeof(uint32_t);
+		written_so_far += sizeof(uint32_t);
+		cmd_flags = 0;
+	}
+
+	/* Disable access to the NVRAM interface. */
+	bxe_nvram_disable_access(sc);
+	bxe_nvram_release_lock(sc);
+
+bxe_nvram_write_exit:
+	DBEXIT(BXE_VERBOSE_NVRAM);
+	return (rc);
+}
+#endif
+
+/*
+ * This function validates NVRAM content by reading spcific
+ * regions and validating that the NVRAM checksum matches the
+ * actual content.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_nvram_test(struct bxe_softc *sc)
+{
+	static const struct {
+		int offset;
+		int size;
+	} nvram_tbl[] = {
+		{     0,  0x14 }, /* bootstrap area*/
+		{  0x14,  0xec }, /* directory area */
+		{ 0x100, 0x350 }, /* manuf_info */
+		{ 0x450,  0xf0 }, /* feature_info */
+		{ 0x640,  0x64 }, /* upgrade_key_info */
+		{ 0x708,  0x70 }, /* manuf_key_info */
+		{     0,     0 }
+	};
+	uint32_t magic, csum, buf[0x350 / 4];
+	uint8_t *data;
+	int i, rc;
+
+	DBENTER(BXE_VERBOSE_NVRAM);
+
+	data = (uint8_t *) buf;
+
+	/* Read the DWORD at offset 0 in NVRAM. */
+	rc = bxe_nvram_read(sc, 0, data, 4);
+	if (rc) {
+		BXE_PRINTF("%s(%d): Error (%d) returned reading NVRAM!\n",
+		    __FILE__, __LINE__, rc);
+		goto bxe_nvram_test_exit;
+	}
+
+	/* Make sure we found our magic value. */
+	magic = be32toh(buf[0]);
+	if (magic != 0x669955aa) {
+		BXE_PRINTF("%s(%d): Invalid magic value (0x%08x) found!\n",
+		    __FILE__, __LINE__, magic);
+		rc = ENODEV;
+		goto bxe_nvram_test_exit;
+	}
+
+	/* Read through each region in NVRAM and validate the checksum. */
+	for (i = 0; nvram_tbl[i].size; i++) {
+		DBPRINT(sc, BXE_VERBOSE_NVRAM, "%s(): Testing NVRAM region %d, "
+		    "starting offset = %d, length = %d\n", __FUNCTION__, i,
+		    nvram_tbl[i].offset, nvram_tbl[i].size);
+
+		rc = bxe_nvram_read(sc, nvram_tbl[i].offset, data,
+			nvram_tbl[i].size);
+		if (rc) {
+			BXE_PRINTF("%s(%d): Error (%d) returned reading NVRAM "
+			    "region %d!\n", __FILE__, __LINE__, rc, i);
+			goto bxe_nvram_test_exit;
+		}
+
+		csum = ether_crc32_le(data, nvram_tbl[i].size);
+		if (csum != BXE_CRC32_RESIDUAL) {
+			BXE_PRINTF("%s(%d): Checksum error (0x%08X) for NVRAM "
+			    "region %d!\n", __FILE__, __LINE__, csum, i);
+			rc = ENODEV;
+			goto bxe_nvram_test_exit;
+		}
+	}
+
+bxe_nvram_test_exit:
+	DBEXIT(BXE_VERBOSE_NVRAM);
+	return (rc);
+}
+
+/*
+ * Acknowledge status block and modify interrupt mode.
+ *
+ * Returns:
+ *   None.
+ */
+static __inline void
+bxe_ack_sb(struct bxe_softc *sc, uint8_t sb_id, uint8_t storm, uint16_t index,
+    uint8_t int_mode, uint8_t update)
+{
+	struct igu_ack_register igu_ack;
+	uint32_t hc_addr;
+
+	DBPRINT(sc, BXE_VERBOSE_INTR, "%s(): sb_id = %d, storm = %d, "
+	    "index = %d, int_mode = %d, update = %d.\n", __FUNCTION__, sb_id,
+	    storm, index, int_mode, update);
+
+	hc_addr = (HC_REG_COMMAND_REG + BP_PORT(sc) * 32 + COMMAND_REG_INT_ACK);
+	igu_ack.status_block_index = index;
+	igu_ack.sb_id_and_flags =
+	    ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
+	    (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
+	    (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
+	    (int_mode << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
+
+	rmb();
+
+	DBPRINT(sc, BXE_VERBOSE_INTR,
+	    "%s(): Writing 0x%08X to HC addr 0x%08X\n", __FUNCTION__,
+	    (*(uint32_t *) &igu_ack), hc_addr);
+
+	REG_WR(sc, hc_addr, (*(uint32_t *) &igu_ack));
+	wmb();
+}
+
+/*
+ * Update fastpath status block index.
+ *
+ * Returns:
+ *   0
+ */
+static __inline uint16_t
+bxe_update_fpsb_idx(struct bxe_fastpath *fp)
+{
+	struct host_status_block *fpsb;
+	uint16_t rc;
+
+	fpsb = fp->status_block;
+	rc = 0;
+
+	rmb();
+
+	/* Check for any CSTORM transmit completions. */
+	if (fp->fp_c_idx != le16toh(fpsb->c_status_block.status_block_index)) {
+		fp->fp_c_idx = le16toh(fpsb->c_status_block.status_block_index);
+		rc |= 0x1;
+	}
+
+	/* Check for any USTORM receive completions. */
+	if (fp->fp_u_idx != le16toh(fpsb->u_status_block.status_block_index)) {
+		fp->fp_u_idx = le16toh(fpsb->u_status_block.status_block_index);
+		rc |= 0x2;
+	}
+
+	return (rc);
+}
+
+/*
+ * Acknowledge interrupt.
+ *
+ * Returns:
+ *   Interrupt value read from IGU.
+ */
+static uint16_t
+bxe_ack_int(struct bxe_softc *sc)
+{
+	uint32_t hc_addr, result;
+
+	hc_addr = HC_REG_COMMAND_REG + BP_PORT(sc) * 32 + COMMAND_REG_SIMD_MASK;
+	result = REG_RD(sc, hc_addr);
+	DBPRINT(sc, BXE_INSANE_INTR, "%s(): Read 0x%08X from HC addr 0x%08X\n",
+	    __FUNCTION__, result, hc_addr);
+
+	return (result);
+}
+
+/*
+ * Slowpath event handler.
+ *
+ * Checks that a ramrod completion occurs while	the
+ * controller is in the proper state.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_sp_event(struct bxe_fastpath *fp, union eth_rx_cqe *rr_cqe)
+{
+	struct bxe_softc *sc;
+	int cid, command;
+
+	sc = fp->sc;
+	DBENTER(BXE_VERBOSE_RAMROD);
+
+	cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+	command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+	DBPRINT(sc, BXE_VERBOSE_RAMROD, "%s(): CID = %d, ramrod command = %d, "
+	    "device state = 0x%08X, fp[%d].state = 0x%08X, type = %d\n",
+	    __FUNCTION__, cid, command, sc->state, fp->index, fp->state,
+	    rr_cqe->ramrod_cqe.ramrod_type);
+
+	/* Free up an entry on the slowpath queue. */
+	sc->spq_left++;
+
+	/* Handle ramrod commands that completed on a client connection. */
+	if (fp->index) {
+		/* Check for a completion for the current state. */
+		switch (command | fp->state) {
+		case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BXE_FP_STATE_OPENING):
+			DBPRINT(sc, BXE_VERBOSE_RAMROD,
+			    "%s(): Completed fp[%d] CLIENT_SETUP Ramrod.\n",
+			    __FUNCTION__, cid);
+			fp->state = BXE_FP_STATE_OPEN;
+			break;
+		case (RAMROD_CMD_ID_ETH_HALT | BXE_FP_STATE_HALTING):
+			DBPRINT(sc, BXE_VERBOSE_RAMROD,
+			    "%s(): Completed fp[%d] ETH_HALT ramrod\n",
+			    __FUNCTION__, cid);
+			fp->state = BXE_FP_STATE_HALTED;
+			break;
+		default:
+			DBPRINT(sc, BXE_VERBOSE_RAMROD,
+			    "%s(): Unexpected microcode reply (%d) while "
+			    "in state 0x%04X!\n", __FUNCTION__, command,
+			    fp->state);
+		}
+
+		goto bxe_sp_event_exit;
+	}
+
+	/* Handle ramrod commands that completed on the leading connection. */
+	switch (command | sc->state) {
+	case (RAMROD_CMD_ID_ETH_PORT_SETUP | BXE_STATE_OPENING_WAIT4_PORT):
+		DBPRINT(sc, BXE_VERBOSE_RAMROD,
+		    "%s(): Completed PORT_SETUP ramrod.\n", __FUNCTION__);
+		sc->state = BXE_STATE_OPEN;
+		break;
+	case (RAMROD_CMD_ID_ETH_HALT | BXE_STATE_CLOSING_WAIT4_HALT):
+		DBPRINT(sc, BXE_VERBOSE_RAMROD,
+		    "%s(): Completed ETH_HALT ramrod.\n", __FUNCTION__);
+		sc->state = BXE_STATE_CLOSING_WAIT4_DELETE;
+		fp->state = BXE_FP_STATE_HALTED;
+		break;
+	case (RAMROD_CMD_ID_ETH_CFC_DEL | BXE_STATE_CLOSING_WAIT4_HALT):
+		DBPRINT(sc, BXE_VERBOSE_RAMROD,
+		    "%s(): Completed fp[%d] ETH_CFC_DEL ramrod.\n",
+		    __FUNCTION__, cid);
+		sc->fp[cid].state = BXE_FP_STATE_CLOSED;
+		break;
+	case (RAMROD_CMD_ID_ETH_SET_MAC | BXE_STATE_OPEN):
+		DBPRINT(sc, BXE_VERBOSE_RAMROD,
+		    "%s(): Completed ETH_SET_MAC ramrod in STATE_OPEN state.\n",
+		    __FUNCTION__);
+		break;
+	case (RAMROD_CMD_ID_ETH_SET_MAC | BXE_STATE_CLOSING_WAIT4_HALT):
+		DBPRINT(sc, BXE_VERBOSE_RAMROD,
+		    "%s(): Completed ETH_SET_MAC ramrod in "
+		    "CLOSING_WAIT4_HALT state.\n", __FUNCTION__);
+		break;
+	default:
+		DBPRINT(sc, BXE_FATAL, "%s(): Unexpected microcode reply (%d)! "
+		    "State is 0x%08X\n", __FUNCTION__, command, sc->state);
+	}
+
+bxe_sp_event_exit:
+	/* Force bxe_wait_ramrod() to see the change. */
+	mb();
+	DBEXIT(BXE_VERBOSE_RAMROD);
+}
+
+/*
+ * Lock access to a hardware resource using controller arbitration
+ * register.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_acquire_hw_lock(struct bxe_softc *sc, uint32_t resource)
+{
+	uint32_t hw_lock_control_reg, lock_status, resource_bit;
+	uint8_t func;
+	int cnt, rc;
+
+	DBENTER(BXE_VERBOSE_MISC);
+	DBPRINT(sc, BXE_VERBOSE, "%s(): Locking resource 0x%08X\n",
+	    __FUNCTION__, resource);
+
+	func = BP_FUNC(sc);
+	resource_bit = 1 << resource;
+	rc = 0;
+
+	hw_lock_control_reg = ((func <= 5) ?
+	    (MISC_REG_DRIVER_CONTROL_1 + func * 8) :
+	    (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8));
+
+	/* Validating that the resource is within range. */
+	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
+		DBPRINT(sc, BXE_INFO, "%s(): Resource is out of range! "
+		    "resource(0x%08X) > HW_LOCK_MAX_RESOURCE_VALUE(0x%08X)\n",
+		    __FUNCTION__, resource, HW_LOCK_MAX_RESOURCE_VALUE);
+		rc = EINVAL;
+		goto bxe_acquire_hw_lock_exit;
+	}
+
+	/* Validating that the resource is not already taken. */
+	lock_status = REG_RD(sc, hw_lock_control_reg);
+	if (lock_status & resource_bit) {
+		DBPRINT(sc, BXE_INFO, "%s(): Failed to acquire lock! "
+		    "lock_status = 0x%08X, resource_bit = 0x%08X\n",
+		    __FUNCTION__, lock_status, resource_bit);
+		rc = EEXIST;
+		goto bxe_acquire_hw_lock_exit;
+	}
+
+	/* Try for 5 seconds every 5ms. */
+	for (cnt = 0; cnt < 1000; cnt++) {
+		/* Try to acquire the lock. */
+		REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
+		lock_status = REG_RD(sc, hw_lock_control_reg);
+
+		if (lock_status & resource_bit)
+			goto bxe_acquire_hw_lock_exit;
+		DELAY(5000);
+	}
+
+	DBPRINT(sc, BXE_INFO, "%s(): Timeout!\n", __FUNCTION__);
+	rc = EAGAIN;
+
+bxe_acquire_hw_lock_exit:
+	DBEXIT(BXE_VERBOSE_MISC);
+	return (rc);
+}
+
+/*
+ * Unlock access to a hardware resource using controller arbitration
+ * register.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_release_hw_lock(struct bxe_softc *sc, uint32_t resource)
+{
+	uint32_t hw_lock_control_reg, lock_status, resource_bit;
+	uint8_t func;
+	int rc;
+
+	DBENTER(BXE_VERBOSE_MISC);
+	DBPRINT(sc, BXE_VERBOSE, "%s(): Unlocking resource 0x%08X\n",
+		__FUNCTION__, resource);
+
+	resource_bit = 1 << resource;
+	func = BP_FUNC(sc);
+	rc = 0;
+	/* Validating that the resource is within range */
+	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
+		DBPRINT(sc, BXE_INFO, "%s(): Resource is out of range! "
+		    "resource(0x%08X) > HW_LOCK_MAX_RESOURCE_VALUE(0x%08X)\n",
+		    __FUNCTION__, resource, HW_LOCK_MAX_RESOURCE_VALUE);
+		rc = EINVAL;
+		goto bxe_release_hw_lock_exit;
+	}
+
+	/* Find the register for the resource lock. */
+	hw_lock_control_reg = ((func <= 5) ?
+	    (MISC_REG_DRIVER_CONTROL_1 + func * 8) :
+	    (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8));
+
+	/* Validating that the resource is currently taken */
+	lock_status = REG_RD(sc, hw_lock_control_reg);
+	if (!(lock_status & resource_bit)) {
+		DBPRINT(sc, BXE_INFO, "%s(): The resource is not currently "
+		    "locked! lock_status = 0x%08X, resource_bit = 0x%08X\n",
+		    __FUNCTION__, lock_status, resource_bit);
+		rc = EFAULT;
+		goto bxe_release_hw_lock_exit;
+	}
+
+	/* Free the hardware lock. */
+	REG_WR(sc, hw_lock_control_reg, resource_bit);
+
+bxe_release_hw_lock_exit:
+	DBEXIT(BXE_VERBOSE_MISC);
+	return (rc);
+}
+
+int
+bxe_get_gpio(struct bxe_softc *sc, int gpio_num, uint8_t port)
+{
+	uint32_t gpio_mask, gpio_reg;
+	int gpio_port, gpio_shift, value;
+
+	/* The GPIO should be swapped if swap register is set and active */
+	gpio_port = (REG_RD(sc, NIG_REG_PORT_SWAP) && REG_RD(sc,
+	    NIG_REG_STRAP_OVERRIDE)) ^ port;
+	gpio_shift = gpio_num +
+	    (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
+	gpio_mask = 1 << gpio_shift;
+
+	if (gpio_num > MISC_REGISTERS_GPIO_3) {
+		BXE_PRINTF("Invalid GPIO %d\n", gpio_num);
+		return (-EINVAL);
+	}
+
+	/* read GPIO value */
+	gpio_reg = REG_RD(sc, MISC_REG_GPIO);
+
+	/* get the requested pin value */
+	if ((gpio_reg & gpio_mask) == gpio_mask)
+		value = 1;
+	else
+		value = 0;
+
+	DBPRINT(sc, BXE_VERBOSE_PHY, "pin %d  value 0x%x\n", gpio_num, value);
+
+	return (value);
+}
+
+/*
+ * Sets the state of a General Purpose I/O (GPIO).
+ *
+ * Returns:
+ *   None.
+ */
+int
+bxe_set_gpio(struct bxe_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
+{
+	uint32_t gpio_reg, gpio_mask;
+	int gpio_port, gpio_shift, rc;
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	/* The GPIO should be swapped if swap register is set and active. */
+	gpio_port = (REG_RD(sc, NIG_REG_PORT_SWAP) && REG_RD(sc,
+	    NIG_REG_STRAP_OVERRIDE)) ^ port;
+	gpio_shift = gpio_num +
+	    (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
+	gpio_mask = (1 << gpio_shift);
+	rc = 0;
+
+	if (gpio_num > MISC_REGISTERS_GPIO_3) {
+		DBPRINT(sc, BXE_FATAL, "%s(): Invalid GPIO (%d)!\n",
+		    __FUNCTION__, gpio_num);
+		rc = EINVAL;
+		goto bxe_set_gpio_exit;
+	}
+
+	/* Make sure no one else is trying to use the GPIO. */
+	rc = bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+	if (rc) {
+		DBPRINT(sc, BXE_WARN, "%s(): Can't acquire GPIO lock!\n",
+		    __FUNCTION__);
+		goto bxe_set_gpio_exit;
+	}
+
+	/* Read GPIO and mask all but the float bits. */
+	gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
+
+	switch (mode) {
+	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
+		DBPRINT(sc, BXE_VERBOSE, "%s(): Set GPIO %d (shift %d) -> "
+		    "output low\n", __FUNCTION__, gpio_num, gpio_shift);
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
+		break;
+	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
+		DBPRINT(sc, BXE_VERBOSE, "%s(): Set GPIO %d (shift %d) -> "
+		    "output high\n", __FUNCTION__, gpio_num, gpio_shift);
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
+		break;
+	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
+		DBPRINT(sc, BXE_VERBOSE, "%s(): Set GPIO %d (shift %d) -> "
+		    "input\n", __FUNCTION__, gpio_num, gpio_shift);
+		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+		break;
+	default:
+		DBPRINT(sc, BXE_FATAL, "%s(): Unknown GPIO mode (0x%08X)!\n",
+		    __FUNCTION__, mode);
+		break;
+	}
+
+	REG_WR(sc, MISC_REG_GPIO, gpio_reg);
+	rc = bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+	if (rc) {
+		DBPRINT(sc, BXE_WARN, "%s(): Can't release GPIO lock!\n",
+		    __FUNCTION__);
+	}
+
+bxe_set_gpio_exit:
+	DBEXIT(BXE_VERBOSE_MISC);
+	return (rc);
+}
+
+int
+bxe_set_gpio_int(struct bxe_softc *sc, int gpio_num, uint32_t mode,
+    uint8_t port)
+{
+	uint32_t gpio_mask, gpio_reg;
+	int gpio_port, gpio_shift;
+
+	/* The GPIO should be swapped if swap register is set and active */
+	gpio_port = (REG_RD(sc, NIG_REG_PORT_SWAP) && REG_RD(sc,
+	    NIG_REG_STRAP_OVERRIDE)) ^ port;
+	gpio_shift = gpio_num +
+	    (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
+	gpio_mask = (1 << gpio_shift);
+	if (gpio_num > MISC_REGISTERS_GPIO_3) {
+		BXE_PRINTF("Invalid GPIO %d\n", gpio_num);
+		return (-EINVAL);
+	}
+
+	bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+	/* read GPIO int */
+	gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
+
+	switch (mode) {
+	case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Clear GPIO INT %d (shift %d) -> "
+		    "output low\n", gpio_num, gpio_shift);
+		/* clear SET and set CLR */
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
+		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
+		break;
+	case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
+		DBPRINT(sc, BXE_VERBOSE_PHY, "Set GPIO INT %d (shift %d) -> "
+		    "output high\n", gpio_num, gpio_shift);
+		/* clear CLR and set SET */
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
+		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
+		break;
+	default:
+		break;
+	}
+
+	REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
+	bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+
+	return (0);
+}
+
+/*
+ * Sets the state of a Shared Purpose I/O (SPIO).
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+int
+bxe_set_spio(struct bxe_softc *sc, int spio_num, uint32_t mode)
+{
+	uint32_t spio_reg, spio_mask;
+	int rc;
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	rc = 0;
+	spio_mask = 1 << spio_num;
+
+	/* Validate the SPIO. */
+	if ((spio_num < MISC_REGISTERS_SPIO_4) ||
+	    (spio_num > MISC_REGISTERS_SPIO_7)) {
+		DBPRINT(sc, BXE_FATAL, "%s(): Invalid SPIO (%d)!\n",
+		    __FUNCTION__, spio_num);
+		rc = EINVAL;
+		goto bxe_set_spio_exit;
+	}
+
+	rc = bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
+	if (rc) {
+		DBPRINT(sc, BXE_WARN, "%s(): Can't acquire SPIO lock!\n",
+		    __FUNCTION__);
+		goto bxe_set_spio_exit;
+	}
+
+	/* Read SPIO and mask all but the float bits. */
+	spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
+
+	switch (mode) {
+	case MISC_REGISTERS_SPIO_OUTPUT_LOW :
+		DBPRINT(sc, BXE_INFO, "%s(): Set SPIO %d -> output low\n",
+		    __FUNCTION__, spio_num);
+		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
+		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
+		break;
+	case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
+		DBPRINT(sc, BXE_INFO,  "%s(): Set SPIO %d -> output high\n",
+		    __FUNCTION__, spio_num);
+		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
+		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
+		break;
+	case MISC_REGISTERS_SPIO_INPUT_HI_Z:
+		DBPRINT(sc, BXE_INFO, "%s(): Set SPIO %d -> input\n",
+		    __FUNCTION__, spio_num);
+		spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
+		break;
+	default:
+		DBPRINT(sc, BXE_FATAL, "%s(): Unknown SPIO mode (0x%08X)!\n",
+		    __FUNCTION__, mode);
+		break;
+	}
+
+	REG_WR(sc, MISC_REG_SPIO, spio_reg);
+	rc = bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
+	if (rc) {
+		DBPRINT(sc, BXE_WARN, "%s(): Can't release SPIO lock!\n",
+		    __FUNCTION__);
+	}
+
+bxe_set_spio_exit:
+	DBEXIT(BXE_VERBOSE_MISC);
+	return (rc);
+}
+
+/*
+ * When the 57711E is operating in multi-function mode, the controller
+ * must be configured to arbitrate TX between multiple VNICs.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_port_minmax(struct bxe_softc *sc)
+{
+	uint32_t fair_periodic_timeout_usec, r_param, t_fair;
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	r_param = sc->link_vars.line_speed / 8;
+
+	memset(&(sc->cmng.rs_vars), 0,
+	    sizeof(struct rate_shaping_vars_per_port));
+	memset(&(sc->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
+
+	/* 100 usec in SDM ticks = 25 since each tick is 4 usec. */
+	sc->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
+	/*
+	 * This is the threshold below which no timer arming will occur.
+	 * We use a coefficient of 1, 25 so that the threshold is a
+	 * little bigger that real time to compensate for timer
+	 * in-accuracy.
+	 */
+	sc->cmng.rs_vars.rs_threshold = (RS_PERIODIC_TIMEOUT_USEC *
+	    r_param * 5) / 4;
+	/* Resolution of fairness timer. */
+	fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
+
+	/* For 10G it is 1000us, for 1G it is 10000us. */
+	t_fair = T_FAIR_COEF / sc->link_vars.line_speed;
+	/* This is the threshold where we won't arm the timer
+	   anymore. */
+	sc->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
+	/*
+	 * Multiply by 1e3/8 to get bytes/msec. We don't want the
+	 * credits to pass a credit of the T_FAIR*FAIR_MEM (algorithm
+	 * resolution)
+	 */
+	sc->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
+	/* Since each tick is 4 us. */
+	sc->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
+
+	DBEXIT(BXE_VERBOSE_MISC);
+}
+
+
+/*
+ * This function is called when a link interrupt is generated
+ * and configures the controller for the new link state.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_link_attn(struct bxe_softc *sc)
+{
+	struct host_port_stats *pstats;
+	uint32_t pause_enabled;
+	int func, i, port, vn;
+
+	DBENTER(BXE_VERBOSE_PHY);
+
+	/* Make sure that we are synced with the current statistics. */
+	bxe_stats_handle(sc, STATS_EVENT_STOP);
+
+	bxe_link_update(&sc->link_params, &sc->link_vars);
+
+	if (sc->link_vars.link_up) {
+		if (CHIP_IS_E1H(sc)) {
+			port = BP_PORT(sc);
+			pause_enabled = 0;
+
+			if (sc->link_vars.flow_ctrl & FLOW_CTRL_TX)
+				pause_enabled = 1;
+
+			REG_WR(sc, BAR_USTORM_INTMEM +
+			    USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
+			    pause_enabled);
+		}
+
+		if (sc->link_vars.mac_type == MAC_TYPE_BMAC) {
+			pstats = BXE_SP(sc, port_stats);
+			/* Reset old BMAC statistics. */
+			memset(&(pstats->mac_stx[0]), 0,
+			    sizeof(struct mac_stx));
+		}
+
+		if ((sc->state == BXE_STATE_OPEN) ||
+		    (sc->state == BXE_STATE_DISABLED))
+			bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
+	}
+
+	/* Report the new link status. */
+	bxe_link_report(sc);
+
+	/* Need additional handling for multi-function devices. */
+	if (IS_E1HMF(sc)) {
+		port = BP_PORT(sc);
+		if (sc->link_vars.link_up) {
+			if (bxe_dcc_enable) {
+				bxe_congestionmgmt(sc, TRUE);
+				/* Store in internal memory. */
+				for (i = 0; i <
+				    sizeof(struct cmng_struct_per_port) / 4;
+				    i++) {
+					REG_WR(sc, BAR_XSTORM_INTMEM +
+				XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + (i*4),
+					    ((uint32_t *)(&sc->cmng))[i]);
+				}
+			}
+		}
+		for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+			/* Don't send an attention to ourselves. */
+			if (vn == BP_E1HVN(sc))
+				continue;
+			func = ((vn << 1) | port);
+			/*
+			 * Send an attention to other drivers on the same port.
+			 */
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
+			    (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
+		}
+	}
+
+	DBEXIT(BXE_VERBOSE_PHY);
+}
+
+/*
+ * Sets the driver instance as the port management function (PMF).
+ *
+ * This is only used on "multi-function" capable devices such as the
+ * 57711E and initializes the controller so that the PMF driver instance
+ * can interact with other driver instances that may be operating on
+ * the same Ethernet port.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_pmf_update(struct bxe_softc *sc)
+{
+	uint32_t val;
+	int port;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	/* Record that this driver instance is managing the port. */
+	sc->port.pmf = 1;
+	DBPRINT(sc, BXE_INFO, "%s(): Enabling port management function.\n",
+	    __FUNCTION__);
+
+	/* Enable NIG attention. */
+	port = BP_PORT(sc);
+	val = (0xff0f | (1 << (BP_E1HVN(sc) + 4)));
+	REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
+	REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
+
+	bxe_stats_handle(sc, STATS_EVENT_PMF);
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/* 8073 Download definitions */
+/* spi Parameters.*/
+#define	SPI_CTRL_1_L	0xC000
+#define	SPI_CTRL_1_H	0xC002
+#define	SPI_CTRL_2_L	0xC400
+#define	SPI_CTRL_2_H	0xC402
+#define	SPI_TXFIFO	0xD000
+#define	SPI_RXFIFO	0xD400
+
+/* Input Command Messages.*/
+/*
+ * Write CPU/SPI Control Regs, followed by Count And CPU/SPI Controller
+ * Reg add/data pairs.
+ */
+#define	WR_CPU_CTRL_REGS	0x11
+/*
+ * Read CPU/SPI Control Regs, followed by Count and CPU/SPI Controller
+ * Register Add.
+ */
+#define	RD_CPU_CTRL_REGS	0xEE
+/*
+ * Write CPU/SPI Control Regs Continously, followed by Count and
+ * CPU/SPI Controller Reg addr and data's.
+ */
+#define	WR_CPU_CTRL_FIFO	0x66
+/* Output Command Messages.*/
+#define	DONE			0x4321
+
+/* SPI Controller Commands (known As messages).*/
+#define	MSGTYPE_HWR	0x40
+#define	MSGTYPE_HRD	0x80
+#define	WRSR_OPCODE	0x01
+#define	WR_OPCODE	0x02
+#define	RD_OPCODE	0x03
+#define	WRDI_OPCODE	0x04
+#define	RDSR_OPCODE	0x05
+#define	WREN_OPCODE	0x06
+#define	WR_BLOCK_SIZE	0x40	/* Maximum 64 Bytes Writes.*/
+
+/*
+ * Post a slowpath command.
+ *
+ * A slowpath command is used to propogate a configuration change through
+ * the controller in a controlled manner, allowing each STORM processor and
+ * other H/W blocks to phase in the change.  The commands sent on the
+ * slowpath are referred to as ramrods.  Depending on the ramrod used the
+ * completion of the ramrod will occur in different ways.  Here's a
+ * breakdown of ramrods and how they complete:
+ *
+ * RAMROD_CMD_ID_ETH_PORT_SETUP
+ *   Used to setup the leading connection on a port.  Completes on the
+ *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
+ *
+ * RAMROD_CMD_ID_ETH_CLIENT_SETUP
+ *   Used to setup an additional connection on a port.  Completes on the
+ *   RCQ of the multi-queue/RSS connection being initialized.
+ *
+ * RAMROD_CMD_ID_ETH_STAT_QUERY
+ *   Used to force the storm processors to update the statistics database
+ *   in host memory.  This ramrod is send on the leading connection CID and
+ *   completes as an index increment of the CSTORM on the default status
+ *   block.
+ *
+ * RAMROD_CMD_ID_ETH_UPDATE
+ *   Used to update the state of the leading connection, usually to udpate
+ *   the RSS indirection table.  Completes on the RCQ of the leading
+ *   connection. (Not currently used under FreeBSD until OS support becomes
+ *   available.)
+ *
+ * RAMROD_CMD_ID_ETH_HALT
+ *   Used when tearing down a connection prior to driver unload.  Completes
+ *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
+ *   use this on the leading connection.
+ *
+ * RAMROD_CMD_ID_ETH_SET_MAC
+ *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
+ *   the RCQ of the leading connection.
+ *
+ * RAMROD_CMD_ID_ETH_CFC_DEL
+ *   Used when tearing down a conneciton prior to driver unload.  Completes
+ *   on the RCQ of the leading connection (since the current connection
+ *   has been completely removed from controller memory).
+ *
+ * RAMROD_CMD_ID_ETH_PORT_DEL
+ *   Used to tear down the leading connection prior to driver unload,
+ *   typically fp[0].  Completes as an index increment of the CSTORM on the
+ *   default status block.
+ *
+ * RAMROD_CMD_ID_ETH_FORWARD_SETUP
+ *   Used for connection offload.  Completes on the RCQ of the multi-queue
+ *   RSS connection that is being offloaded.  (Not currently used under
+ *   FreeBSD.)
+ *
+ * There can only be one command pending per function.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_sp_post(struct bxe_softc *sc, int command, int cid, uint32_t data_hi,
+    uint32_t data_lo, int common)
+{
+	int func, rc;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+
+	DBRUNMSG(BXE_VERBOSE_RAMROD, bxe_decode_ramrod_cmd(sc, command));
+
+	DBPRINT(sc, BXE_VERBOSE_RAMROD, "%s(): cid = %d, data_hi = 0x%08X, "
+	    "data_low = 0x%08X, remaining spq entries = %d\n", __FUNCTION__,
+	    cid, data_hi, data_lo, sc->spq_left);
+
+	rc = 0;
+	/* Skip all slowpath commands if the driver has panic'd. */
+	if (sc->panic) {
+		rc = EIO;
+		goto bxe_sp_post_exit;
+	}
+
+	BXE_SP_LOCK(sc);
+
+	/* We are limited to 8 slowpath commands. */
+	if (!sc->spq_left) {
+		BXE_PRINTF("%s(%d): Slowpath queue is full!\n", __FILE__,
+		    __LINE__);
+		bxe_panic_dump(sc);
+		rc = EBUSY;
+		goto bxe_sp_post_exit;
+	}
+
+	/* Encode the CID with the command. */
+	sc->spq_prod_bd->hdr.conn_and_cmd_data =
+	    htole32(((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid)));
+	sc->spq_prod_bd->hdr.type = htole16(ETH_CONNECTION_TYPE);
+
+	if (common)
+		sc->spq_prod_bd->hdr.type |=
+		    htole16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
+
+	/* Point the hardware at the new configuration data. */
+	sc->spq_prod_bd->data.mac_config_addr.hi = htole32(data_hi);
+	sc->spq_prod_bd->data.mac_config_addr.lo = htole32(data_lo);
+
+	/* Reduce the number of available slots for slowpath commands. */
+	sc->spq_left--;
+
+	/* Manage the end of the ring. */
+	if (sc->spq_prod_bd == sc->spq_last_bd) {
+		sc->spq_prod_bd = sc->spq;
+		sc->spq_prod_idx = 0;
+		DBPRINT(sc, BXE_VERBOSE, "%s(): End of slowpath queue.\n",
+		    __FUNCTION__);
+	} else {
+		sc->spq_prod_bd++;
+		sc->spq_prod_idx++;
+	}
+
+	func = BP_FUNC(sc);
+	/* Kick off the slowpath command. */
+	REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
+	    sc->spq_prod_idx);
+
+bxe_sp_post_exit:
+	BXE_SP_UNLOCK(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
+
+	return (rc);
+}
+
+/*
+ * Acquire the MCP access lock.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_acquire_alr(struct bxe_softc *sc)
+{
+	uint32_t val;
+	int i, rc, retries;
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	rc = 0;
+	retries = 100;
+	/* Acquire lock using mcpr_access_lock SPLIT register. */
+	for (i = 0; i < retries * 10; i++) {
+		val = 1UL << 31;
+		REG_WR(sc, GRCBASE_MCP + 0x9c, val);
+		val = REG_RD(sc, GRCBASE_MCP + 0x9c);
+
+		if (val & (1L << 31))
+			break;
+
+		DELAY(5000);
+	}
+
+	if (!(val & (1L << 31))) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Cannot acquire MCP split access lock.\n",
+		    __FUNCTION__);
+		rc = EBUSY;
+	}
+
+	DBEXIT(BXE_VERBOSE_MISC);
+	return (rc);
+}
+
+
+/*
+ * Release the MCP access lock.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_release_alr(struct bxe_softc* sc)
+{
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
+
+	DBEXIT(BXE_VERBOSE_MISC);
+}
+
+/*
+ * Update driver's copies of the values in the host default status block.
+ *
+ * Returns:
+ *   Bitmap indicating changes to the block.
+ */
+static __inline uint16_t
+bxe_update_dsb_idx(struct bxe_softc *sc)
+{
+	struct host_def_status_block *dsb;
+	uint16_t rc;
+
+	rc = 0;
+	dsb = sc->def_status_block;
+	/* Read memory barrier since block is written by hardware. */
+	rmb();
+
+	if (sc->def_att_idx !=
+	    le16toh(dsb->atten_status_block.attn_bits_index)) {
+		sc->def_att_idx =
+		    le16toh(dsb->atten_status_block.attn_bits_index);
+		rc |= 0x1;
+	}
+
+	if (sc->def_c_idx !=
+	    le16toh(dsb->c_def_status_block.status_block_index)) {
+		sc->def_c_idx =
+		    le16toh(dsb->c_def_status_block.status_block_index);
+		rc |= 0x2;
+	}
+
+	if (sc->def_u_idx !=
+	    le16toh(dsb->u_def_status_block.status_block_index)) {
+		sc->def_u_idx =
+		    le16toh(dsb->u_def_status_block.status_block_index);
+		rc |= 0x4;
+	}
+
+	if (sc->def_x_idx !=
+	    le16toh(dsb->x_def_status_block.status_block_index)) {
+		sc->def_x_idx =
+		    le16toh(dsb->x_def_status_block.status_block_index);
+		rc |= 0x8;
+	}
+
+	if (sc->def_t_idx !=
+	    le16toh(dsb->t_def_status_block.status_block_index)) {
+		sc->def_t_idx =
+		    le16toh(dsb->t_def_status_block.status_block_index);
+		rc |= 0x10;
+	}
+
+	return (rc);
+}
+
+/*
+ * Handle any attentions that have been newly asserted.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_attn_int_asserted(struct bxe_softc *sc, uint32_t asserted)
+{
+	uint32_t aeu_addr, hc_addr, nig_int_mask_addr;
+	uint32_t aeu_mask, nig_mask;
+	int port, rc;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	port = BP_PORT(sc);
+	hc_addr = (HC_REG_COMMAND_REG + port * 32 + COMMAND_REG_ATTN_BITS_SET);
+	aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
+	nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
+	    NIG_REG_MASK_INTERRUPT_PORT0;
+	nig_mask = 0;
+
+	if (sc->attn_state & asserted)
+		BXE_PRINTF("%s(%d): IGU ERROR!\n", __FILE__, __LINE__);
+
+	rc = bxe_acquire_hw_lock(sc,
+		HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+	if (rc) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Failed to acquire attention lock for port %d!\n",
+		    __FUNCTION__, port);
+		goto bxe_attn_int_asserted_exit;
+	}
+
+	aeu_mask = REG_RD(sc, aeu_addr);
+	DBPRINT(sc, BXE_VERBOSE_INTR,
+	    "%s(): aeu_mask = 0x%08X, newly asserted = 0x%08X\n", __FUNCTION__,
+	    aeu_mask, asserted);
+
+	aeu_mask &= ~(asserted & 0xff);
+	DBPRINT(sc, BXE_VERBOSE_INTR, "%s(): new mask = 0x%08X\n", __FUNCTION__,
+	    aeu_mask);
+	REG_WR(sc, aeu_addr, aeu_mask);
+
+	rc = bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+	if (rc) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Failed to release attention lock!\n", __FUNCTION__);
+		goto bxe_attn_int_asserted_exit;
+	}
+
+	DBPRINT(sc, BXE_VERBOSE_INTR, "%s(): attn_state = 0x%08X\n",
+	    __FUNCTION__, sc->attn_state);
+
+	sc->attn_state |= asserted;
+	DBPRINT(sc, BXE_VERBOSE_INTR, "%s(): new attn_state = 0x%08X\n",
+	    __FUNCTION__, sc->attn_state);
+
+	if (asserted & ATTN_HARD_WIRED_MASK) {
+		if (asserted & ATTN_NIG_FOR_FUNC) {
+			bxe_acquire_phy_lock(sc);
+
+			/* Save NIG interrupt mask. */
+			nig_mask = REG_RD(sc, nig_int_mask_addr);
+			REG_WR(sc, nig_int_mask_addr, 0);
+
+			bxe_link_attn(sc);
+		}
+
+		if (asserted & ATTN_SW_TIMER_4_FUNC)
+			DBPRINT(sc, BXE_WARN, "%s(): ATTN_SW_TIMER_4_FUNC!\n",
+			    __FUNCTION__);
+
+		if (asserted & GPIO_2_FUNC)
+			DBPRINT(sc, BXE_WARN, "%s(): GPIO_2_FUNC!\n",
+			    __FUNCTION__);
+
+		if (asserted & GPIO_3_FUNC)
+			DBPRINT(sc, BXE_WARN, "%s(): GPIO_3_FUNC!\n",
+			    __FUNCTION__);
+
+		if (asserted & GPIO_4_FUNC)
+			DBPRINT(sc, BXE_WARN, "%s(): GPIO_4_FUNC!\n",
+			    __FUNCTION__);
+
+		if (port == 0) {
+			if (asserted & ATTN_GENERAL_ATTN_1) {
+				DBPRINT(sc, BXE_WARN,
+				    "%s(): ATTN_GENERAL_ATTN_1!\n",
+				    __FUNCTION__);
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
+			}
+
+			if (asserted & ATTN_GENERAL_ATTN_2) {
+				DBPRINT(sc, BXE_WARN,
+				    "%s(): ATTN_GENERAL_ATTN_2!\n",
+				    __FUNCTION__);
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
+			}
+
+			if (asserted & ATTN_GENERAL_ATTN_3) {
+				DBPRINT(sc, BXE_WARN,
+				    "%s(): ATTN_GENERAL_ATTN_3!\n",
+				    __FUNCTION__);
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
+			}
+		} else {
+			if (asserted & ATTN_GENERAL_ATTN_4) {
+				DBPRINT(sc, BXE_WARN,
+				    "%s(): ATTN_GENERAL_ATTN_4!\n",
+				    __FUNCTION__);
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
+			}
+
+			if (asserted & ATTN_GENERAL_ATTN_5) {
+				DBPRINT(sc, BXE_WARN,
+				    "%s(): ATTN_GENERAL_ATTN_5!\n",
+				    __FUNCTION__);
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
+			}
+			if (asserted & ATTN_GENERAL_ATTN_6) {
+				DBPRINT(sc, BXE_WARN,
+				    "%s(): ATTN_GENERAL_ATTN_6!\n",
+				    __FUNCTION__);
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
+			}
+		}
+	}
+
+	DBPRINT(sc, BXE_VERBOSE_INTR,
+	    "%s(): Writing 0x%08X to HC addr 0x%08X\n", __FUNCTION__,
+	    asserted, hc_addr);
+	REG_WR(sc, hc_addr, asserted);
+
+	/* Now set back the NIG mask. */
+	if (asserted & ATTN_NIG_FOR_FUNC) {
+		REG_WR(sc, nig_int_mask_addr, nig_mask);
+		bxe_release_phy_lock(sc);
+	}
+
+bxe_attn_int_asserted_exit:
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/*
+ * Handle any attentions that have been newly deasserted.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_attn_int_deasserted0(struct bxe_softc *sc, uint32_t attn)
+{
+	uint32_t val, swap_val, swap_override;
+	int port, reg_offset;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	port = BP_PORT(sc);
+	reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
+
+	/* Handle SPIO5 attention. */
+	if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
+		val = REG_RD(sc, reg_offset);
+		val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
+		REG_WR(sc, reg_offset, val);
+
+		DBPRINT(sc, BXE_FATAL, "%s(): SPIO5 H/W attention!\n",
+		    __FUNCTION__);
+		/* Fan failure attention */
+		switch (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config)) {
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+			/*
+			 * SPIO5 is used on A1022G boards to indicate
+			 * fan failure.  Shutdown the controller and
+			 * associated PHY to avoid damage.
+			 */
+
+			/* Low power mode is controled by GPIO 2. */
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
+				MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+			/* PHY reset is controled by GPIO 1. */
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1,
+				MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+			break;
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
+			/*
+			 * The PHY reset is controlled by GPIO 1.
+			 * Fake the port number to cancel the swap done in
+			 * set_gpio().
+			 */
+			swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
+			swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
+			port = (swap_val && swap_override) ^ 1;
+			bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1,
+			    MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
+			break;
+		default:
+			break;
+		}
+
+		/* Mark the failure. */
+		sc->link_params.ext_phy_config &=
+		    ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+		sc->link_params.ext_phy_config |=
+		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
+		SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
+		    sc->link_params.ext_phy_config);
+		/* Log the failure */
+		BXE_PRINTF("A fan failure has caused the driver to shutdown "
+		    "the device to prevent permanent damage.\n");
+	}
+
+	if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
+	    AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
+		bxe_acquire_phy_lock(sc);
+		bxe_handle_module_detect_int(&sc->link_params);
+		bxe_release_phy_lock(sc);
+	}
+
+	/* Checking for an assert on the zero block */
+	if (attn & HW_INTERRUT_ASSERT_SET_0) {
+		val = REG_RD(sc, reg_offset);
+		val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
+		REG_WR(sc, reg_offset, val);
+
+		BXE_PRINTF(
+		    "%s(%d): FATAL hardware block attention (set0 = 0x%08X)!\n",
+		    __FILE__, __LINE__,
+		    (attn & (uint32_t)HW_INTERRUT_ASSERT_SET_0));
+
+		bxe_panic_dump(sc);
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/*
+ * Handle any attentions that have been newly deasserted.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_attn_int_deasserted1(struct bxe_softc *sc, uint32_t attn)
+{
+	uint32_t val;
+	int port, reg_offset;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
+		val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
+
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): Doorbell hardware attention (0x%08X).\n",
+		    __FUNCTION__, val);
+
+		/* DORQ discard attention */
+		if (val & 0x2)
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): FATAL doorbell queue error!\n",
+			    __FUNCTION__);
+	}
+
+	if (attn & HW_INTERRUT_ASSERT_SET_1) {
+		port = BP_PORT(sc);
+		reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
+		    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1;
+
+		val = REG_RD(sc, reg_offset);
+		val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
+		REG_WR(sc, reg_offset, val);
+
+		BXE_PRINTF(
+		    "%s(%d): FATAL hardware block attention (set1 = 0x%08X)!\n",
+		    __FILE__, __LINE__,
+		    (attn & (uint32_t)HW_INTERRUT_ASSERT_SET_1));
+
+		bxe_panic_dump(sc);
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/*
+ * Handle any attentions that have been newly deasserted.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_attn_int_deasserted2(struct bxe_softc *sc, uint32_t attn)
+{
+	uint32_t val;
+	int port, reg_offset;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
+		val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
+
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): CFC hardware attention (0x%08X).\n", __FUNCTION__,
+		    val);
+
+		/* CFC error attention. */
+		if (val & 0x2)
+			DBPRINT(sc, BXE_FATAL, "%s(): FATAL CFC error!\n",
+			    __FUNCTION__);
+	}
+
+	if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
+		val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
+
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): PXP hardware attention (0x%08X).\n", __FUNCTION__,
+		    val);
+
+		/* RQ_USDMDP_FIFO_OVERFLOW */
+		if (val & 0x18000)
+			DBPRINT(sc, BXE_FATAL, "%s(): FATAL PXP error!\n",
+			    __FUNCTION__);
+	}
+
+	if (attn & HW_INTERRUT_ASSERT_SET_2) {
+		port = BP_PORT(sc);
+		reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
+		    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2;
+
+		val = REG_RD(sc, reg_offset);
+		val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
+		REG_WR(sc, reg_offset, val);
+
+		BXE_PRINTF("%s(%d): FATAL hardware block attention (set2 = "
+		    "0x%08X)! port=%d, val written=0x%x attn=0x%x\n", __FILE__,
+		    __LINE__, (attn & (uint32_t)HW_INTERRUT_ASSERT_SET_2),
+		    port, val, attn);
+
+		bxe_panic_dump(sc);
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/*
+ * Handle any attentions that have been newly deasserted.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_attn_int_deasserted3(struct bxe_softc *sc, uint32_t attn)
+{
+	uint32_t val;
+	int func;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
+		/* Look for any port assertions. */
+		if (attn & BXE_PMF_LINK_ASSERT) {
+			/*
+			 * We received a message from the driver instance
+			 * that is managing the Ethernet port (link up/down).
+			 * Go ahead and handle it.
+			 */
+			func = BP_FUNC(sc);
+
+			DBPRINT(sc, BXE_INFO,
+			    "%s(): Received link attention from PMF.\n",
+			    __FUNCTION__);
+
+			/* Clear the attention. */
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
+			sc->mf_config[BP_E1HVN(sc)] =
+			    SHMEM_RD(sc,
+			    mf_cfg.func_mf_config[(sc->bxe_func & 1)].config);
+			val = SHMEM_RD(sc, func_mb[func].drv_status);
+			if (bxe_dcc_enable) {
+				if (val & DRV_STATUS_DCC_EVENT_MASK)
+					bxe_dcc_event(sc,
+					    val & DRV_STATUS_DCC_EVENT_MASK);
+			}
+			bxe__link_status_update(sc);
+
+			if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
+				bxe_pmf_update(sc);
+		/* Look for any microcode assertions. */
+		} else if (attn & BXE_MC_ASSERT_BITS) {
+			DBPRINT(sc, BXE_FATAL, "%s(): Microcode assert!\n",
+			    __FUNCTION__);
+
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
+
+			bxe_panic_dump(sc);
+
+		/* Look for any bootcode assertions. */
+		} else if (attn & BXE_MCP_ASSERT) {
+			DBPRINT(sc, BXE_FATAL, "%s(): Bootcode assert!\n",
+				__FUNCTION__);
+
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
+
+			DBRUN(bxe_dump_fw(sc));
+		} else
+			DBPRINT(sc, BXE_FATAL,
+			    "%s(): Unknown hardware assertion "
+			    "(attn = 0x%08X)!\n", __FUNCTION__, attn);
+	}
+
+	/* Look for any hardware latched attentions. */
+	if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): Latched attention 0x%08X (masked)!\n", __FUNCTION__,
+		    attn);
+
+		/* Check if a GRC register access timeout occurred. */
+		if (attn & BXE_GRC_TIMEOUT) {
+			val = CHIP_IS_E1H(sc) ? REG_RD(sc,
+			    MISC_REG_GRC_TIMEOUT_ATTN) : 0;
+
+			DBPRINT(sc, BXE_WARN,
+			    "%s(): GRC timeout for register 0x%08X!\n",
+			    __FUNCTION__, val);
+		}
+
+		/* Check if a GRC reserved register was accessed. */
+		if (attn & BXE_GRC_RSV) {
+			val = CHIP_IS_E1H(sc) ? REG_RD(sc,
+			    MISC_REG_GRC_RSV_ATTN) : 0;
+
+			DBPRINT(sc, BXE_WARN,
+			    "%s(): GRC register 0x%08X is reserved!\n",
+			    __FUNCTION__, val);
+		}
+
+		REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/*
+ * Handle any attentions that have been newly deasserted.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_attn_int_deasserted(struct bxe_softc *sc, uint32_t deasserted)
+{
+	struct attn_route attn;
+	struct attn_route group_mask;
+	uint32_t val, reg_addr, aeu_mask;
+	int index, port;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	/*
+	 * Need to take HW lock because MCP or other port might also try
+	 * to handle this event.
+	 */
+	bxe_acquire_alr(sc);
+
+	port = BP_PORT(sc);
+	/* Get the current attention signal bits. */
+	attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
+	attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
+	attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
+	attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
+	DBPRINT(sc, BXE_VERBOSE,
+	    "%s(): attention = 0x%08X 0x%08X 0x%08X 0x%08X\n", __FUNCTION__,
+	    attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
+
+	/*
+	 * Compare the current attention bits to each attention group
+	 * to see if anyone has registered this attention.
+	 */
+	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
+		if (deasserted & (1 << index)) {
+			group_mask = sc->attn_group[index];
+
+			DBPRINT(sc, 1, /*BXE_EXTREME_INTR,*/
+			    "%s(): group[%02d] = 0x%08X 0x%08X 0x%08x 0X%08x\n",
+			    __FUNCTION__, index, group_mask.sig[0],
+			    group_mask.sig[1], group_mask.sig[2],
+			    group_mask.sig[3]);
+
+			/* Handle any registered attentions. */
+			bxe_attn_int_deasserted3(sc,
+			    attn.sig[3] & group_mask.sig[3]);
+			bxe_attn_int_deasserted1(sc,
+			    attn.sig[1] & group_mask.sig[1]);
+			bxe_attn_int_deasserted2(sc,
+			    attn.sig[2] & group_mask.sig[2]);
+			bxe_attn_int_deasserted0(sc,
+			    attn.sig[0] & group_mask.sig[0]);
+
+			if ((attn.sig[0] & group_mask.sig[0] &
+			    HW_PRTY_ASSERT_SET_0) ||
+			    (attn.sig[1] & group_mask.sig[1] &
+			    HW_PRTY_ASSERT_SET_1) ||
+			    (attn.sig[2] & group_mask.sig[2] &
+			    HW_PRTY_ASSERT_SET_2))
+				BXE_PRINTF("%s(%d): FATAL hardware block "
+				    "parity attention!\n", __FILE__, __LINE__);
+		}
+	}
+
+	bxe_release_alr(sc);
+
+	reg_addr = (HC_REG_COMMAND_REG + port * 32 + COMMAND_REG_ATTN_BITS_CLR);
+
+	val = ~deasserted;
+	DBPRINT(sc, BXE_VERBOSE_INTR,
+	    "%s(): About to mask 0x%08X at HC addr 0x%08X\n", __FUNCTION__,
+	    deasserted, reg_addr);
+	REG_WR(sc, reg_addr, val);
+
+	if (~sc->attn_state & deasserted)
+		DBPRINT(sc, BXE_FATAL, "%s(): IGU Bug!\n", __FUNCTION__);
+
+	reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
+
+	bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+	aeu_mask = REG_RD(sc, reg_addr);
+
+	DBPRINT(sc, BXE_EXTREME_INTR,
+	    "%s(): Current aeu_mask = 0x%08X, newly deasserted = 0x%08X\n",
+	    __FUNCTION__, aeu_mask, deasserted);
+	aeu_mask |= (deasserted & 0xff);
+	DBPRINT(sc, BXE_EXTREME_INTR, "%s(): New aeu_mask = 0x%08X\n",
+	    __FUNCTION__, aeu_mask);
+
+	REG_WR(sc, reg_addr, aeu_mask);
+	bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+
+	DBPRINT(sc, BXE_EXTREME_INTR, "%s(): Current attn_state = 0x%08X\n",
+	    __FUNCTION__, sc->attn_state);
+	sc->attn_state &= ~deasserted;
+	DBPRINT(sc, BXE_EXTREME_INTR, "%s(): New attn_state = 0x%08X\n",
+	    __FUNCTION__, sc->attn_state);
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/*
+ * Handle interrupts caused by internal attentions (everything else other
+ * than RX, TX, and link state changes).
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_attn_int(struct bxe_softc* sc)
+{
+	uint32_t attn_ack, attn_bits, attn_state;
+	uint32_t asserted, deasserted;
+
+	DBENTER(BXE_VERBOSE_INTR);
+
+	attn_bits = le32toh(sc->def_status_block->atten_status_block.attn_bits);
+	attn_ack =
+	    le32toh(sc->def_status_block->atten_status_block.attn_bits_ack);
+	attn_state = sc->attn_state;
+	asserted = attn_bits & ~attn_ack & ~attn_state;
+	deasserted = ~attn_bits &  attn_ack &  attn_state;
+
+	/* Make sure we're in a sane state. */
+	if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
+	    BXE_PRINTF("%s(%d): Bad attention state!\n",
+	    	__FILE__, __LINE__);
+
+	/* Handle any attentions that are newly asserted. */
+	if (asserted) {
+		DBPRINT(sc, BXE_VERBOSE_INTR,
+		    "%s(): attn_state = 0x%08X, attn_bits = 0x%08X, "
+		    "attn_ack = 0x%08X, asserted = 0x%08X\n", __FUNCTION__,
+		    attn_state, attn_bits, attn_ack, asserted);
+		bxe_attn_int_asserted(sc, asserted);
+	}
+
+	/* Handle any attentions that are newly deasserted. */
+	if (deasserted) {
+		DBPRINT(sc, BXE_VERBOSE_INTR,
+		    "%s(): attn_state = 0x%08X, attn_bits = 0x%08X, "
+		    "attn_ack = 0x%08X, deasserted = 0x%08X\n", __FUNCTION__,
+		    attn_state, attn_bits, attn_ack, deasserted);
+		bxe_attn_int_deasserted(sc, deasserted);
+	}
+
+	DBEXIT(BXE_VERBOSE_INTR);
+}
+
+/* sum[hi:lo] += add[hi:lo] */
+#define	ADD_64(s_hi, a_hi, s_lo, a_lo) do {			\
+	s_lo += a_lo;						\
+	s_hi += a_hi + (s_lo < a_lo) ? 1 : 0;			\
+} while (0)
+
+/* Subtraction = minuend -= subtrahend */
+#define	SUB_64(m_hi, s_hi, m_lo, s_lo)				\
+	do {							\
+		DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo);	\
+	} while (0)
+
+
+/* difference = minuend - subtrahend */
+#define	DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) do {	\
+	if (m_lo < s_lo) {					\
+		/* underflow */					\
+		d_hi = m_hi - s_hi;				\
+		if (d_hi > 0) {					\
+			/* we can 'loan' 1 */			\
+			d_hi--;					\
+			d_lo = m_lo + (UINT_MAX - s_lo) + 1;	\
+		} else {					\
+			/* m_hi <= s_hi */			\
+			d_hi = 0;				\
+			d_lo = 0;				\
+		}						\
+	} else {						\
+		/* m_lo >= s_lo */				\
+		if (m_hi < s_hi) {				\
+			d_hi = 0;				\
+			d_lo = 0;				\
+		} else {					\
+			/* m_hi >= s_hi */			\
+			d_hi = m_hi - s_hi;			\
+			d_lo = m_lo - s_lo;			\
+		}						\
+	}							\
+} while (0)
+
+#define	UPDATE_STAT64(s, t) do {				\
+	DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi,\
+	    diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo);	\
+	pstats->mac_stx[0].t##_hi = new->s##_hi;		\
+	pstats->mac_stx[0].t##_lo = new->s##_lo;		\
+	ADD_64(pstats->mac_stx[1].t##_hi, diff.hi,		\
+	    pstats->mac_stx[1].t##_lo, diff.lo);		\
+} while (0)
+
+#define	UPDATE_STAT64_NIG(s, t) do {				\
+	DIFF_64(diff.hi, new->s##_hi, old->s##_hi,		\
+	    diff.lo, new->s##_lo, old->s##_lo);			\
+	ADD_64(estats->t##_hi, diff.hi,				\
+	    estats->t##_lo, diff.lo);				\
+} while (0)
+
+/* sum[hi:lo] += add */
+#define	ADD_EXTEND_64(s_hi, s_lo, a) do {			\
+	s_lo += a;						\
+	s_hi += (s_lo < a) ? 1 : 0;				\
+} while (0)
+
+#define	UPDATE_EXTEND_STAT(s) do {				\
+	ADD_EXTEND_64(pstats->mac_stx[1].s##_hi,		\
+	    pstats->mac_stx[1].s##_lo, new->s);			\
+} while (0)
+
+#define	UPDATE_EXTEND_TSTAT(s, t) do {				\
+	diff = (tclient->s) - (old_tclient->s);	\
+	old_tclient->s = (tclient->s);				\
+	ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff);	\
+} while (0)
+
+#define	UPDATE_EXTEND_XSTAT(s, t) do {				\
+	diff = xclient->s - old_xclient->s;	\
+	old_xclient->s = xclient->s;				\
+	ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff);	\
+} while (0)
+
+#define	UPDATE_EXTEND_USTAT(s, t) do {				\
+	diff = uclient->s - old_uclient->s;	\
+	old_uclient->s = uclient->s;				\
+	ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff);	\
+} while (0)
+
+#define	SUB_EXTEND_64(m_hi, m_lo, s)do {			\
+	SUB_64(m_hi, 0, m_lo, s);				\
+} while (0)
+
+#define	SUB_EXTEND_USTAT(s, t)do {				\
+	diff = (uclient->s) - (old_uclient->s);	\
+	SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff);	\
+} while (0)
+
+
+
+
+#ifdef __i386__
+#define	BITS_PER_LONG	32
+#else /*Only support x86_64(AMD64 and EM64T)*/
+#define	BITS_PER_LONG	64
+#endif
+
+static __inline long
+bxe_hilo(uint32_t *hiref)
+{
+	uint32_t lo;
+
+	lo = *(hiref + 1);
+#if (BITS_PER_LONG == 64)
+	uint32_t hi = *hiref;
+	return (HILO_U64(hi, lo));
+#else
+	return (lo);
+#endif
+}
+
+/*
+ * Request the STORM statistics by posting a slowpath ramrod.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_storm_post(struct bxe_softc *sc)
+{
+	struct eth_query_ramrod_data ramrod_data = {0};
+	int rc;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	if (!sc->stats_pending) {
+		ramrod_data.drv_counter = sc->stats_counter++;
+		ramrod_data.collect_port = sc->port.pmf ? 1 : 0;
+		ramrod_data.ctr_id_vector = (1 << BP_CL_ID(sc));
+
+		rc = bxe_sp_post(sc, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
+		    ((uint32_t *)&ramrod_data)[1],
+		    ((uint32_t *)&ramrod_data)[0], 0);
+
+		if (rc == 0) {
+			/* Stats ramrod has it's own slot on the SPQ. */
+			sc->spq_left++;
+			sc->stats_pending = 1;
+		}
+	}
+
+	DBEXIT(BXE_INSANE_STATS);
+}
+
+static void
+bxe_stats_port_base_init(struct bxe_softc *sc)
+{
+	uint32_t *stats_comp;
+	struct dmae_command *dmae;
+
+	if (!sc->port.pmf || !sc->port.port_stx) {
+		BXE_PRINTF("%s(%d): Bug!\n", __FILE__, __LINE__);
+		return;
+	}
+
+	stats_comp = BXE_SP(sc, stats_comp);
+
+	sc->executer_idx = 0;  /* dmae clients */
+
+	dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+			DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+			DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+			(BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+			(BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+	dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
+	dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
+	dmae->dst_addr_lo = sc->port.port_stx >> 2;
+	dmae->dst_addr_hi = 0;
+	dmae->len = sizeof(struct host_port_stats) >> 2;
+	dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_val = DMAE_COMP_VAL;
+
+	*stats_comp = 0;
+	bxe_stats_hw_post(sc);
+	bxe_stats_comp(sc);
+}
+
+static void
+bxe_stats_func_base_init(struct bxe_softc *sc)
+{
+	int port, func;
+	int vn, vn_max;
+	uint32_t func_stx;
+
+	port = BP_PORT(sc);
+	func_stx = sc->func_stx;
+	vn_max = IS_E1HMF(sc) ? E1HVN_MAX : E1VN_MAX;
+
+	for (vn = VN_0; vn < vn_max; vn++) {
+		func = 2*vn + port;
+		sc->func_stx = SHMEM_RD(sc, func_mb[func].fw_mb_param);
+		bxe_stats_func_init(sc);
+		bxe_stats_hw_post(sc);
+		bxe_stats_comp(sc);
+	}
+
+	sc->func_stx = func_stx;
+}
+
+static void
+bxe_stats_func_base_update(struct bxe_softc *sc)
+{
+	uint32_t *stats_comp;
+	struct dmae_command *dmae;
+
+	dmae = &sc->stats_dmae;
+	stats_comp = BXE_SP(sc, stats_comp);
+
+	sc->executer_idx = 0;
+	memset(dmae, 0, sizeof(struct dmae_command));
+
+	dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+			DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+			DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+			(BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+			(BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+	dmae->src_addr_lo = sc->func_stx >> 2;
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats_base));
+	dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats_base));
+	dmae->len = sizeof(struct host_func_stats) >> 2;
+	dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_val = DMAE_COMP_VAL;
+
+	*stats_comp = 0;
+	bxe_stats_hw_post(sc);
+	bxe_stats_comp(sc);
+}
+
+
+/*
+ * Initialize statistics.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_stats_init(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	int func, i, port;
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	if (bxe_stats_enable == FALSE)
+	    return;
+
+	port = BP_PORT(sc);
+	func = BP_FUNC(sc);
+	sc->executer_idx  = 0;
+	sc->stats_counter = 0;
+	sc->stats_pending = 0;
+
+	/* Fetch the offset of port statistics in shared memory. */
+	if (BP_NOMCP(sc)){
+		sc->port.port_stx = 0;
+		sc->func_stx = 0;
+	} else{
+		sc->port.port_stx = SHMEM_RD(sc, port_mb[port].port_stx);
+		sc->func_stx = SHMEM_RD(sc, func_mb[func].fw_mb_param);
+	}
+	/* If this is still 0 then no management firmware running. */
+	DBPRINT(sc, BXE_VERBOSE_STATS, "%s(): sc->port.port_stx = 0x%08X\n",
+	    __FUNCTION__, sc->port.port_stx);
+
+	/* port stats */
+	memset(&(sc->port.old_nig_stats), 0, sizeof(struct nig_stats));
+	sc->port.old_nig_stats.brb_discard = REG_RD(sc,
+	    NIG_REG_STAT0_BRB_DISCARD + port * 0x38);
+	sc->port.old_nig_stats.brb_truncate = REG_RD(sc,
+	    NIG_REG_STAT0_BRB_TRUNCATE + port * 0x38);
+	REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port * 0x50,
+	    &(sc->port.old_nig_stats.egress_mac_pkt0_lo), 2);
+	REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port * 0x50,
+	    &(sc->port.old_nig_stats.egress_mac_pkt1_lo), 2);
+
+	/* function stats */
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		/* Clear function statistics memory. */
+		memset(&fp->old_tclient, 0,
+		    sizeof(struct tstorm_per_client_stats));
+		memset(&fp->old_uclient, 0,
+		    sizeof(struct ustorm_per_client_stats));
+		memset(&fp->old_xclient, 0,
+		    sizeof(struct xstorm_per_client_stats));
+		memset(&fp->eth_q_stats, 0, sizeof(struct bxe_q_stats));
+	}
+
+	sc->stats_state = STATS_STATE_DISABLED;
+
+	/* Init port statistics if we're the port management function. */
+	if (sc->port.pmf) {
+		/* Port_stx are in 57710 when ncsi presnt & always in 57711.*/
+		if (sc->port.port_stx)
+			bxe_stats_port_base_init(sc);
+		if (sc->func_stx)
+			bxe_stats_func_base_init(sc);
+	} else if (sc->func_stx)
+		bxe_stats_func_base_update(sc);
+
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_hw_post(struct bxe_softc *sc)
+{
+	struct dmae_command *dmae;
+	uint32_t *stats_comp;
+	int loader_idx;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	dmae = &sc->stats_dmae;
+	stats_comp = BXE_SP(sc, stats_comp);
+	*stats_comp = DMAE_COMP_VAL;
+
+	if (sc->executer_idx) {
+		loader_idx = PMF_DMAE_C(sc);
+
+		memset(dmae, 0, sizeof(struct dmae_command));
+
+		dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+		    DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
+		    DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+		    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+		    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+		    (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+		    (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+
+		dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, dmae[0]));
+		dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, dmae[0]));
+		dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
+		    sizeof(struct dmae_command) * (loader_idx + 1)) >> 2;
+		dmae->dst_addr_hi = 0;
+		dmae->len = sizeof(struct dmae_command) >> 2;
+
+		if (CHIP_IS_E1(sc))
+			dmae->len--;
+
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+
+		*stats_comp = 0;
+		bxe_post_dmae(sc, dmae, loader_idx);
+
+	} else if (sc->func_stx) {
+		*stats_comp = 0;
+		bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
+	}
+
+	DBEXIT(BXE_INSANE_STATS);
+}
+
+/*
+ *
+ * Returns:
+ *   1
+ */
+static int
+bxe_stats_comp(struct bxe_softc *sc)
+{
+	uint32_t *stats_comp;
+	int cnt;
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	stats_comp = BXE_SP(sc, stats_comp);
+	cnt = 10;
+	while (*stats_comp != DMAE_COMP_VAL) {
+		if (!cnt) {
+			BXE_PRINTF("%s(%d): Timeout waiting for statistics "
+			    "completions.\n", __FILE__, __LINE__);
+			break;
+		}
+		cnt--;
+		DELAY(1000);
+	}
+
+	DBEXIT(BXE_VERBOSE_STATS);
+	return (1);
+}
+
+/*
+ * Initialize port statistics.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_pmf_update(struct bxe_softc *sc)
+{
+	struct dmae_command *dmae;
+	uint32_t opcode, *stats_comp;
+	int loader_idx;
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	stats_comp = BXE_SP(sc, stats_comp);
+	loader_idx = PMF_DMAE_C(sc);
+
+	/* We shouldn't be here if any of the following are false. */
+	if (!IS_E1HMF(sc) || !sc->port.pmf || !sc->port.port_stx) {
+		DBPRINT(sc, BXE_WARN, "%s(): Bug!\n", __FUNCTION__);
+		goto bxe_stats_pmf_update_exit;
+	}
+
+	sc->executer_idx = 0;
+
+	opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+	    DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+
+	dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
+	dmae->src_addr_lo = sc->port.port_stx >> 2;
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
+	dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
+	dmae->len = DMAE_LEN32_RD_MAX;
+	dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+	dmae->comp_addr_hi = 0;
+	dmae->comp_val = 1;
+
+	dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
+	dmae->src_addr_lo = (sc->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats) +
+	    DMAE_LEN32_RD_MAX * 4);
+	dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats) +
+	    DMAE_LEN32_RD_MAX * 4);
+	dmae->len = (sizeof(struct host_port_stats) >> 2) -
+	    DMAE_LEN32_RD_MAX;
+	dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_val = DMAE_COMP_VAL;
+
+	*stats_comp = 0;
+	bxe_stats_hw_post(sc);
+	bxe_stats_comp(sc);
+
+bxe_stats_pmf_update_exit:
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ * Prepare the DMAE parameters required for port statistics.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_port_init(struct bxe_softc *sc)
+{
+	struct dmae_command *dmae;
+	uint32_t mac_addr, opcode, *stats_comp;
+	int loader_idx, port, vn;
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	port = BP_PORT(sc);
+	vn = BP_E1HVN(sc);
+	loader_idx = PMF_DMAE_C(sc);
+	stats_comp = BXE_SP(sc, stats_comp);
+
+	/* Sanity check. */
+	if (!sc->link_vars.link_up || !sc->port.pmf) {
+		BXE_PRINTF("%s(%d): Bug!\n", __FILE__, __LINE__);
+		goto bxe_stats_port_init_exit;
+	}
+
+	sc->executer_idx = 0;
+
+	/* Setup statistics reporting to MCP. */
+	opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+	    DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (vn << DMAE_CMD_E1HVN_SHIFT));
+
+	/* Setup the DMA for port statistics. */
+	if (sc->port.port_stx) {
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
+		dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
+		dmae->dst_addr_lo = sc->port.port_stx >> 2;
+		dmae->dst_addr_hi = 0;
+		dmae->len = sizeof(struct host_port_stats) >> 2;
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+	}
+
+	/* Setup the DMA for function statistics. */
+	if (sc->func_stx) {
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats));
+		dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats));
+		dmae->dst_addr_lo = sc->func_stx >> 2;
+		dmae->dst_addr_hi = 0;
+		dmae->len = sizeof(struct host_func_stats) >> 2;
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+	}
+
+	/* Setup statistics reporting for the MAC. */
+	opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+	    DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (vn << DMAE_CMD_E1HVN_SHIFT));
+
+	if (sc->link_vars.mac_type == MAC_TYPE_BMAC) {
+		/* Enable statistics for the BMAC. */
+
+		mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
+			NIG_REG_INGRESS_BMAC0_MEM);
+
+		/* Setup BMAC TX statistics (TX_STAT_GTPKT .. TX_STAT_GTBYT). */
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = (mac_addr +
+		    BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
+		dmae->src_addr_hi = 0;
+		dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats));
+		dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats));
+		dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
+		    BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+
+		/* Setup BMAC RX statistcs (RX_STAT_GR64 .. RX_STAT_GRIPJ). */
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = (mac_addr +
+		    BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
+		dmae->src_addr_hi = 0;
+		dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats) +
+		    offsetof(struct bmac_stats, rx_stat_gr64_lo));
+		dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats) +
+		    offsetof(struct bmac_stats, rx_stat_gr64_lo));
+		dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
+		    BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+
+	} else if (sc->link_vars.mac_type == MAC_TYPE_EMAC) {
+		/* Enable statistics for the EMAC. */
+
+		mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
+
+		/* Setup EMAC RX statistics. */
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_RX_STAT_AC) >> 2;
+		dmae->src_addr_hi = 0;
+		dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats));
+		dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats));
+		dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+
+		/* Setup additional EMAC RX statistics. */
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = (mac_addr +
+		    EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
+		dmae->src_addr_hi = 0;
+		dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats) +
+		    offsetof(struct emac_stats, rx_stat_falsecarriererrors));
+		dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats) +
+		    offsetof(struct emac_stats, rx_stat_falsecarriererrors));
+		dmae->len = 1;
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+
+		/* Setup EMAC TX statistics. */
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_TX_STAT_AC) >> 2;
+		dmae->src_addr_hi = 0;
+		dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats) +
+		    offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
+		dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats) +
+		    offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
+		dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
+		dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+	} else {
+		DBPRINT(sc, BXE_WARN, "%s(): Undefined MAC type.\n",
+		    __FUNCTION__);
+	}
+
+	/* Enable NIG statistics. */
+	dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = opcode;
+	dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
+	    NIG_REG_STAT0_BRB_DISCARD) >> 2;
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, nig_stats));
+	dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, nig_stats));
+	dmae->len = (sizeof(struct nig_stats) - 4 * sizeof(uint32_t)) >> 2;
+	dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+	dmae->comp_addr_hi = 0;
+	dmae->comp_val = 1;
+
+	dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = opcode;
+	dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
+	    NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, nig_stats) +
+	    offsetof(struct nig_stats, egress_mac_pkt0_lo));
+	dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, nig_stats) +
+	    offsetof(struct nig_stats, egress_mac_pkt0_lo));
+	dmae->len = (2 * sizeof(uint32_t)) >> 2;
+	dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+	dmae->comp_addr_hi = 0;
+	dmae->comp_val = 1;
+
+	dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+	    DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (vn << DMAE_CMD_E1HVN_SHIFT));
+	dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
+	    NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, nig_stats) +
+	    offsetof(struct nig_stats, egress_mac_pkt1_lo));
+	dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, nig_stats) +
+	    offsetof(struct nig_stats, egress_mac_pkt1_lo));
+	dmae->len = (2 * sizeof(uint32_t)) >> 2;
+	dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_val = DMAE_COMP_VAL;
+
+	/* Clear the statistics completion value. */
+	*stats_comp = 0;
+
+bxe_stats_port_init_exit:
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ * Prepare the DMAE parameters required for function statistics.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_func_init(struct bxe_softc *sc)
+{
+	struct dmae_command *dmae;
+	uint32_t *stats_comp;
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	dmae = &sc->stats_dmae;
+	stats_comp = BXE_SP(sc, stats_comp);
+
+	if (!sc->func_stx) {
+		BXE_PRINTF("%s(%d): Bug!\n", __FILE__, __LINE__);
+		goto bxe_stats_func_init_exit;
+	}
+
+	sc->executer_idx = 0;
+	memset(dmae, 0, sizeof(struct dmae_command));
+
+	/* Setup the DMA for function statistics. */
+	dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+	    DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+
+	dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats));
+	dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats));
+	dmae->dst_addr_lo = sc->func_stx >> 2;
+	dmae->dst_addr_hi = 0;
+	dmae->len = sizeof(struct host_func_stats) >> 2;
+	dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
+	dmae->comp_val = DMAE_COMP_VAL;
+
+	*stats_comp = 0;
+
+bxe_stats_func_init_exit:
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_start(struct bxe_softc *sc)
+{
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	if (sc->port.pmf)
+		bxe_stats_port_init(sc);
+
+	else if (sc->func_stx)
+		bxe_stats_func_init(sc);
+
+	bxe_stats_hw_post(sc);
+	bxe_stats_storm_post(sc);
+
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_pmf_start(struct bxe_softc *sc)
+{
+	DBENTER(BXE_VERBOSE_STATS);
+
+	bxe_stats_comp(sc);
+	bxe_stats_pmf_update(sc);
+	bxe_stats_start(sc);
+
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_restart(struct bxe_softc *sc)
+{
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	bxe_stats_comp(sc);
+	bxe_stats_start(sc);
+
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_bmac_update(struct bxe_softc *sc)
+{
+	struct bmac_stats *new;
+	struct host_port_stats *pstats;
+	struct bxe_eth_stats *estats;
+	struct regpair diff;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	new = BXE_SP(sc, mac_stats.bmac_stats);
+	pstats = BXE_SP(sc, port_stats);
+	estats = &sc->eth_stats;
+
+	UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
+	UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
+	UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
+	UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
+	UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
+	UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
+	UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
+	UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
+	UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
+	UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
+	UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
+	UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
+	UPDATE_STAT64(tx_stat_gt127, tx_stat_etherstatspkts65octetsto127octets);
+	UPDATE_STAT64(tx_stat_gt255,
+	    tx_stat_etherstatspkts128octetsto255octets);
+	UPDATE_STAT64(tx_stat_gt511,
+	    tx_stat_etherstatspkts256octetsto511octets);
+	UPDATE_STAT64(tx_stat_gt1023,
+	    tx_stat_etherstatspkts512octetsto1023octets);
+	UPDATE_STAT64(tx_stat_gt1518,
+	    tx_stat_etherstatspkts1024octetsto1522octets);
+	UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
+	UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
+	UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
+	UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
+	UPDATE_STAT64(tx_stat_gterr,
+	    tx_stat_dot3statsinternalmactransmiterrors);
+	UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
+
+	estats->pause_frames_received_hi =
+	    pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
+	estats->pause_frames_received_lo =
+	    pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
+
+	estats->pause_frames_sent_hi =
+	    pstats->mac_stx[1].tx_stat_outxoffsent_hi;
+	estats->pause_frames_sent_lo =
+	    pstats->mac_stx[1].tx_stat_outxoffsent_lo;
+
+	DBEXIT(BXE_INSANE_STATS);
+}
+
+/*
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_emac_update(struct bxe_softc *sc)
+{
+	struct emac_stats *new;
+	struct host_port_stats *pstats;
+	struct bxe_eth_stats *estats;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	new = BXE_SP(sc, mac_stats.emac_stats);
+	pstats = BXE_SP(sc, port_stats);
+	estats = &sc->eth_stats;
+
+	UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
+	UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
+	UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
+	UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
+	UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
+	UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
+	UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
+	UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
+	UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
+	UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
+	UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
+	UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
+	UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
+	UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
+	UPDATE_EXTEND_STAT(tx_stat_outxonsent);
+	UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
+	UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
+	UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
+	UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
+	UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
+	UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
+	UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
+	UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
+	UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
+
+	estats->pause_frames_received_hi =
+	    pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
+	estats->pause_frames_received_lo =
+	    pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
+	ADD_64(estats->pause_frames_received_hi,
+       pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
+       estats->pause_frames_received_lo,
+       pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
+
+	estats->pause_frames_sent_hi =
+	    pstats->mac_stx[1].tx_stat_outxonsent_hi;
+	estats->pause_frames_sent_lo =
+	    pstats->mac_stx[1].tx_stat_outxonsent_lo;
+	ADD_64(estats->pause_frames_sent_hi,
+	    pstats->mac_stx[1].tx_stat_outxoffsent_hi,
+	    estats->pause_frames_sent_lo,
+	    pstats->mac_stx[1].tx_stat_outxoffsent_lo);
+
+	DBEXIT(BXE_INSANE_STATS);
+}
+
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_stats_hw_update(struct bxe_softc *sc)
+{
+	struct nig_stats *new, *old;
+	struct host_port_stats *pstats;
+	struct bxe_eth_stats *estats;
+	struct regpair diff;
+	uint32_t nig_timer_max;
+	int rc;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	rc = 0;
+	new = BXE_SP(sc, nig_stats);
+	old = &(sc->port.old_nig_stats);
+	pstats = BXE_SP(sc, port_stats);
+	estats = &sc->eth_stats;
+
+	/* Update statistics for the active MAC. */
+	if (sc->link_vars.mac_type == MAC_TYPE_BMAC)
+		bxe_stats_bmac_update(sc);
+	else if (sc->link_vars.mac_type == MAC_TYPE_EMAC)
+		bxe_stats_emac_update(sc);
+	else {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Statistics updated by DMAE but no MAC is active!\n",
+		    __FUNCTION__);
+		rc = EINVAL;
+		goto bxe_stats_hw_update_exit;
+	}
+
+	/* Now update the hardware (NIG) statistics. */
+	ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
+	    new->brb_discard - old->brb_discard);
+	ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
+	    new->brb_truncate - old->brb_truncate);
+
+	UPDATE_STAT64_NIG(egress_mac_pkt0,
+	    etherstatspkts1024octetsto1522octets);
+	UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
+
+	memcpy(old, new, sizeof(struct nig_stats));
+
+	memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
+	    sizeof(struct mac_stx));
+	estats->brb_drop_hi = pstats->brb_drop_hi;
+	estats->brb_drop_lo = pstats->brb_drop_lo;
+
+	pstats->host_port_stats_start = ++pstats->host_port_stats_end;
+
+	nig_timer_max = SHMEM_RD(sc, port_mb[BP_PORT(sc)].stat_nig_timer);
+	if (nig_timer_max != estats->nig_timer_max) {
+		estats->nig_timer_max = nig_timer_max;
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): NIG timer reached max value (%u)!\n", __FUNCTION__,
+		    estats->nig_timer_max);
+	}
+
+bxe_stats_hw_update_exit:
+	DBEXIT(BXE_INSANE_STATS);
+	return (rc);
+}
+
+/*
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_stats_storm_update(struct bxe_softc *sc)
+{
+	int rc, i, cl_id;
+	struct eth_stats_query *stats;
+	struct host_func_stats *fstats;
+	struct tstorm_per_port_stats *tport;
+	struct tstorm_per_client_stats *tclient;
+	struct ustorm_per_client_stats *uclient;
+	struct xstorm_per_client_stats *xclient;
+	struct tstorm_per_client_stats *old_tclient;
+	struct ustorm_per_client_stats *old_uclient;
+	struct xstorm_per_client_stats *old_xclient;
+	struct bxe_eth_stats *estats;
+	struct bxe_q_stats *qstats;
+	struct bxe_fastpath * fp;
+	uint32_t diff;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	rc = 0;
+	stats = BXE_SP(sc, fw_stats);
+	tport = &stats->tstorm_common.port_statistics;
+
+	fstats = BXE_SP(sc, func_stats);
+	memcpy(&(fstats->total_bytes_received_hi),
+	    &(BXE_SP(sc, func_stats_base)->total_bytes_received_hi),
+	    sizeof(struct host_func_stats) - 2*sizeof(uint32_t));
+
+	diff = 0;
+	estats = &sc->eth_stats;
+	estats->no_buff_discard_hi = 0;
+	estats->no_buff_discard_lo = 0;
+	estats->error_bytes_received_hi = 0;
+	estats->error_bytes_received_lo = 0;
+/*	estats->etherstatsoverrsizepkts_hi = 0;
+	estats->etherstatsoverrsizepkts_lo = 0;
+*/
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		cl_id = fp->cl_id;
+		tclient = &stats->tstorm_common.client_statistics[cl_id];
+		uclient = &stats->ustorm_common.client_statistics[cl_id];
+		xclient = &stats->xstorm_common.client_statistics[cl_id];
+		old_tclient = &fp->old_tclient;
+		old_uclient = &fp->old_uclient;
+		old_xclient = &fp->old_xclient;
+		qstats = &fp->eth_q_stats;
+
+		/* Are STORM statistics valid? */
+		if ((uint16_t)(le16toh(tclient->stats_counter) + 1) !=
+		    sc->stats_counter) {
+			DBPRINT(sc, BXE_WARN, "%s(): Stats not updated by TSTORM "
+			    "(tstorm counter (%d) != stats_counter (%d))!\n",
+			    __FUNCTION__, tclient->stats_counter, sc->stats_counter);
+			rc = 1;
+			goto bxe_stats_storm_update_exit;
+		}
+
+		if ((uint16_t)(le16toh(uclient->stats_counter) + 1) !=
+		    sc->stats_counter) {
+			DBPRINT(sc, BXE_WARN, "%s(): Stats not updated by USTORM "
+			    "(ustorm counter (%d) != stats_counter (%d))!\n",
+			    __FUNCTION__, uclient->stats_counter, sc->stats_counter);
+			rc = 2;
+			goto bxe_stats_storm_update_exit;
+		}
+
+		if ((uint16_t)(le16toh(xclient->stats_counter) + 1) !=
+			sc->stats_counter) {
+			DBPRINT(sc, BXE_WARN, "%s(): Stats not updated by XSTORM "
+			    "(xstorm counter (%d) != stats_counter (%d))!\n",
+			    __FUNCTION__, xclient->stats_counter, sc->stats_counter);
+			rc = 3;
+			goto bxe_stats_storm_update_exit;
+		}
+
+		qstats->total_bytes_received_hi =
+		    (tclient->rcv_broadcast_bytes.hi);
+		qstats->total_bytes_received_lo =
+		    le32toh(tclient->rcv_broadcast_bytes.lo);
+
+		ADD_64(qstats->total_bytes_received_hi,
+		    le32toh(tclient->rcv_multicast_bytes.hi),
+		    qstats->total_bytes_received_lo,
+		    le32toh(tclient->rcv_multicast_bytes.lo));
+
+		ADD_64(qstats->total_bytes_received_hi,
+		    le32toh(tclient->rcv_unicast_bytes.hi),
+		    qstats->total_bytes_received_lo,
+		    le32toh(tclient->rcv_unicast_bytes.lo));
+
+		SUB_64(qstats->total_bytes_received_hi,
+		    le32toh(uclient->bcast_no_buff_bytes.hi),
+		    qstats->total_bytes_received_lo,
+		    le32toh(uclient->bcast_no_buff_bytes.lo));
+
+		SUB_64(qstats->total_bytes_received_hi,
+		    le32toh(uclient->mcast_no_buff_bytes.hi),
+		    qstats->total_bytes_received_lo,
+		    le32toh(uclient->mcast_no_buff_bytes.lo));
+
+		SUB_64(qstats->total_bytes_received_hi,
+		    le32toh(uclient->ucast_no_buff_bytes.hi),
+		    qstats->total_bytes_received_lo,
+		    le32toh(uclient->ucast_no_buff_bytes.lo));
+
+		qstats->valid_bytes_received_hi =
+		    qstats->total_bytes_received_hi;
+		qstats->valid_bytes_received_lo =
+		    qstats->total_bytes_received_lo;
+
+		qstats->error_bytes_received_hi =
+		    le32toh(tclient->rcv_error_bytes.hi);
+		qstats->error_bytes_received_lo =
+		    le32toh(tclient->rcv_error_bytes.lo);
+
+		ADD_64(qstats->total_bytes_received_hi,
+		    qstats->error_bytes_received_hi,
+		    qstats->total_bytes_received_lo,
+		    qstats->error_bytes_received_lo);
+
+		UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
+		    total_unicast_packets_received);
+		UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
+		    total_multicast_packets_received);
+		UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
+		    total_broadcast_packets_received);
+/*		UPDATE_EXTEND_TSTAT(packets_too_big_discard,
+        	    etherstatsoverrsizepkts);
+*/
+		UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
+
+		SUB_EXTEND_USTAT(ucast_no_buff_pkts,
+		    total_unicast_packets_received);
+		SUB_EXTEND_USTAT(mcast_no_buff_pkts,
+		    total_multicast_packets_received);
+		SUB_EXTEND_USTAT(bcast_no_buff_pkts,
+		    total_broadcast_packets_received);
+		UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
+		UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
+		UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
+
+		qstats->total_bytes_transmitted_hi =
+		    (xclient->unicast_bytes_sent.hi);
+		qstats->total_bytes_transmitted_lo =
+		    (xclient->unicast_bytes_sent.lo);
+
+		ADD_64(qstats->total_bytes_transmitted_hi,
+		    (xclient->multicast_bytes_sent.hi),
+		    qstats->total_bytes_transmitted_lo,
+		    (xclient->multicast_bytes_sent.lo));
+
+		ADD_64(qstats->total_bytes_transmitted_hi,
+		    (xclient->broadcast_bytes_sent.hi),
+		    qstats->total_bytes_transmitted_lo,
+		    (xclient->broadcast_bytes_sent.lo));
+
+		UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
+		    total_unicast_packets_transmitted);
+
+		UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
+		    total_multicast_packets_transmitted);
+
+		UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
+		    total_broadcast_packets_transmitted);
+
+		old_tclient->checksum_discard = tclient->checksum_discard;
+		old_tclient->ttl0_discard = tclient->ttl0_discard;
+
+		ADD_64(fstats->total_bytes_received_hi,
+		    qstats->total_bytes_received_hi,
+		    fstats->total_bytes_received_lo,
+		    qstats->total_bytes_received_lo);
+		ADD_64(fstats->total_bytes_transmitted_hi,
+		    qstats->total_bytes_transmitted_hi,
+		    fstats->total_bytes_transmitted_lo,
+		    qstats->total_bytes_transmitted_lo);
+		ADD_64(fstats->total_unicast_packets_received_hi,
+		    qstats->total_unicast_packets_received_hi,
+		    fstats->total_unicast_packets_received_lo,
+		    qstats->total_unicast_packets_received_lo);
+		ADD_64(fstats->total_multicast_packets_received_hi,
+		    qstats->total_multicast_packets_received_hi,
+		    fstats->total_multicast_packets_received_lo,
+		    qstats->total_multicast_packets_received_lo);
+		ADD_64(fstats->total_broadcast_packets_received_hi,
+		    qstats->total_broadcast_packets_received_hi,
+		    fstats->total_broadcast_packets_received_lo,
+		    qstats->total_broadcast_packets_received_lo);
+		ADD_64(fstats->total_unicast_packets_transmitted_hi,
+		    qstats->total_unicast_packets_transmitted_hi,
+		    fstats->total_unicast_packets_transmitted_lo,
+		    qstats->total_unicast_packets_transmitted_lo);
+		ADD_64(fstats->total_multicast_packets_transmitted_hi,
+		    qstats->total_multicast_packets_transmitted_hi,
+		    fstats->total_multicast_packets_transmitted_lo,
+		    qstats->total_multicast_packets_transmitted_lo);
+		ADD_64(fstats->total_broadcast_packets_transmitted_hi,
+		    qstats->total_broadcast_packets_transmitted_hi,
+		    fstats->total_broadcast_packets_transmitted_lo,
+		    qstats->total_broadcast_packets_transmitted_lo);
+		ADD_64(fstats->valid_bytes_received_hi,
+		    qstats->valid_bytes_received_hi,
+		    fstats->valid_bytes_received_lo,
+		    qstats->valid_bytes_received_lo);
+
+		ADD_64(estats->error_bytes_received_hi,
+		    qstats->error_bytes_received_hi,
+		    estats->error_bytes_received_lo,
+		    qstats->error_bytes_received_lo);
+
+		ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
+		    estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
+	}
+
+	ADD_64(fstats->total_bytes_received_hi,
+	    estats->rx_stat_ifhcinbadoctets_hi,
+	    fstats->total_bytes_received_lo,
+	    estats->rx_stat_ifhcinbadoctets_lo);
+
+	memcpy(estats, &(fstats->total_bytes_received_hi),
+	    sizeof(struct host_func_stats) - 2*sizeof(uint32_t));
+
+	ADD_64(estats->error_bytes_received_hi,
+	    estats->rx_stat_ifhcinbadoctets_hi,
+	    estats->error_bytes_received_lo,
+	    estats->rx_stat_ifhcinbadoctets_lo);
+
+	if (sc->port.pmf) {
+		estats->mac_filter_discard =
+		    le32toh(tport->mac_filter_discard);
+		estats->xxoverflow_discard =
+		    le32toh(tport->xxoverflow_discard);
+		estats->brb_truncate_discard =
+		    le32toh(tport->brb_truncate_discard);
+		estats->mac_discard = le32toh(tport->mac_discard);
+	}
+
+	fstats->host_func_stats_start = ++fstats->host_func_stats_end;
+
+	sc->stats_pending = 0;
+
+bxe_stats_storm_update_exit:
+
+	DBEXIT(BXE_INSANE_STATS);
+	return(rc);
+}
+
+/*
+ * Copy the controller maintained statistics over to the OS.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_net_update(struct bxe_softc *sc)
+{
+	struct tstorm_per_client_stats *old_tclient;
+	struct bxe_eth_stats *estats;
+	struct ifnet *ifp;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	old_tclient = &sc->fp[0].old_tclient;
+	estats = &sc->eth_stats;
+	ifp = sc->bxe_ifp;
+
+	/*
+	 * Update the OS interface statistics from
+	 * the hardware statistics.
+	 */
+
+	ifp->if_collisions =
+	    (u_long) estats->tx_stat_dot3statssinglecollisionframes_lo +
+	    (u_long) estats->tx_stat_dot3statsmultiplecollisionframes_lo +
+	    (u_long) estats->tx_stat_dot3statslatecollisions_lo +
+	    (u_long) estats->tx_stat_dot3statsexcessivecollisions_lo;
+
+	ifp->if_ierrors =
+	    (u_long) old_tclient->checksum_discard +
+	    (u_long) estats->no_buff_discard_lo +
+	    (u_long) estats->mac_discard +
+	    (u_long) estats->rx_stat_etherstatsundersizepkts_lo +
+	    (u_long) estats->jabber_packets_received +
+	    (u_long) estats->brb_drop_lo +
+	    (u_long) estats->brb_truncate_discard +
+	    (u_long) estats->rx_stat_dot3statsfcserrors_lo +
+	    (u_long) estats->rx_stat_dot3statsalignmenterrors_lo +
+	    (u_long) estats->xxoverflow_discard;
+
+	ifp->if_oerrors =
+	    (u_long) estats->tx_stat_dot3statslatecollisions_lo +
+	    (u_long) estats->tx_stat_dot3statsexcessivecollisions_lo +
+	    (u_long) estats->tx_stat_dot3statsinternalmactransmiterrors_lo;
+
+	ifp->if_ipackets =
+	    bxe_hilo(&estats->total_unicast_packets_received_hi) +
+	    bxe_hilo(&estats->total_multicast_packets_received_hi) +
+	    bxe_hilo(&estats->total_broadcast_packets_received_hi);
+
+	ifp->if_opackets =
+	    bxe_hilo(&estats->total_unicast_packets_transmitted_hi) +
+	    bxe_hilo(&estats->total_multicast_packets_transmitted_hi) +
+	    bxe_hilo(&estats->total_broadcast_packets_transmitted_hi);
+
+	DBEXIT(BXE_INSANE_STATS);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_update(struct bxe_softc *sc)
+{
+	uint32_t *stats_comp;
+	int update;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	stats_comp = BXE_SP(sc, stats_comp);
+	update = 0;
+
+	/* Make sure the statistics DMAE update has completed. */
+	if (*stats_comp != DMAE_COMP_VAL)
+		goto bxe_stats_update_exit;
+
+	/* Check for any hardware statistics updates. */
+	if (sc->port.pmf)
+		update = (bxe_stats_hw_update(sc) == 0);
+
+	/* Check for any STORM statistics updates. */
+	update |= (bxe_stats_storm_update(sc) == 0);
+
+	/* If we got updated hardware statistics then update the OS. */
+	if (update)
+		bxe_stats_net_update(sc);
+	else {
+		/* Check if any statistics updates are pending. */
+		if (sc->stats_pending) {
+			/* The update hasn't completed, keep waiting. */
+			sc->stats_pending++;
+
+			/* Have we been waiting for too long? */
+			if (sc->stats_pending >= 3) {
+				BXE_PRINTF(
+				    "%s(%d): Failed to get statistics after "
+				    "3 tries!\n", __FILE__, __LINE__);
+				bxe_panic_dump(sc);
+				goto bxe_stats_update_exit;
+			}
+		}
+	}
+
+	/* Kickoff the next statistics request. */
+	bxe_stats_hw_post(sc);
+	bxe_stats_storm_post(sc);
+
+bxe_stats_update_exit:
+	DBEXIT(BXE_INSANE_STATS);
+}
+
+/*
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_port_stop(struct bxe_softc *sc)
+{
+	struct dmae_command *dmae;
+	uint32_t opcode, *stats_comp;
+	int loader_idx;
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	stats_comp = BXE_SP(sc, stats_comp);
+	loader_idx = PMF_DMAE_C(sc);
+	sc->executer_idx = 0;
+
+	opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+	    DMAE_CMD_C_ENABLE |
+	    DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+	    DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+	    DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+	    (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
+	    (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
+
+	if (sc->port.port_stx) {
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+
+		if (sc->func_stx)
+			dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
+		else
+			dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
+
+		dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
+		dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
+		dmae->dst_addr_lo = sc->port.port_stx >> 2;
+		dmae->dst_addr_hi = 0;
+		dmae->len = sizeof(struct host_port_stats) >> 2;
+
+		if (sc->func_stx) {
+			dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+			dmae->comp_addr_hi = 0;
+			dmae->comp_val = 1;
+		} else {
+			dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc,
+			    stats_comp));
+			dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc,
+			    stats_comp));
+			dmae->comp_val = DMAE_COMP_VAL;
+
+			*stats_comp = 0;
+		}
+	}
+
+	if (sc->func_stx) {
+		dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
+		dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
+		dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats));
+		dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats));
+		dmae->dst_addr_lo = sc->func_stx >> 2;
+		dmae->dst_addr_hi = 0;
+		dmae->len = sizeof(struct host_func_stats) >> 2;
+		dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
+		dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
+		dmae->comp_val = DMAE_COMP_VAL;
+
+		*stats_comp = 0;
+	}
+
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_stop(struct bxe_softc *sc)
+{
+	int update;
+
+	DBENTER(BXE_VERBOSE_STATS);
+
+	update = 0;
+	/* Wait for any pending completions. */
+	bxe_stats_comp(sc);
+
+	if (sc->port.pmf)
+		update = (bxe_stats_hw_update(sc) == 0);
+
+	update |= (bxe_stats_storm_update(sc) == 0);
+
+	if (update) {
+		bxe_stats_net_update(sc);
+
+		if (sc->port.pmf)
+			bxe_stats_port_stop(sc);
+
+		bxe_stats_hw_post(sc);
+		bxe_stats_comp(sc);
+	}
+
+	DBEXIT(BXE_VERBOSE_STATS);
+}
+
+/*
+ * A dummy function to fill in the statistics state transition table.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_do_nothing(struct bxe_softc *sc)
+{
+
+}
+
+static const struct {
+	void (*action)(struct bxe_softc *sc);
+	enum bxe_stats_state next_state;
+} bxe_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
+    /* State   Event  */
+    {
+    /* DISABLED	PMF	*/ {bxe_stats_pmf_update,	STATS_STATE_DISABLED},
+    /*		LINK_UP	*/ {bxe_stats_start,		STATS_STATE_ENABLED},
+    /*		UPDATE	*/ {bxe_stats_do_nothing,	STATS_STATE_DISABLED},
+    /*		STOP	*/ {bxe_stats_do_nothing,	STATS_STATE_DISABLED}
+    },
+
+    {
+    /* ENABLED	PMF	*/ {bxe_stats_pmf_start,	STATS_STATE_ENABLED},
+    /*		LINK_UP	*/ {bxe_stats_restart,		STATS_STATE_ENABLED},
+    /*		UPDATE	*/ {bxe_stats_update,		STATS_STATE_ENABLED},
+    /*		STOP	*/ {bxe_stats_stop,		STATS_STATE_DISABLED}
+    }
+};
+
+/*
+ * Move to the next state of the statistics state machine.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_stats_handle(struct bxe_softc *sc, enum bxe_stats_event event)
+{
+	enum bxe_stats_state state;
+
+	DBENTER(BXE_INSANE_STATS);
+
+	state = sc->stats_state;
+#ifdef BXE_DEBUG
+	if (event != STATS_EVENT_UPDATE)
+		DBPRINT(sc, BXE_VERBOSE_STATS,
+		    "%s(): Current state = %d, event = %d.\n", __FUNCTION__,
+		    state, event);
+#endif
+
+	bxe_stats_stm[state][event].action(sc);
+	sc->stats_state = bxe_stats_stm[state][event].next_state;
+
+#ifdef BXE_DEBUG
+	if (event != STATS_EVENT_UPDATE)
+		DBPRINT(sc, BXE_VERBOSE_STATS, "%s(): New state = %d.\n",
+		    __FUNCTION__, sc->stats_state);
+#endif
+
+	DBEXIT(BXE_INSANE_STATS);
+}
+
+/*
+ * bxe_chktso_window()
+ * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
+ * Check that (13 total bds - 3bds) = 10 bd window >= MSS.
+ * The window: 3 bds are = 1 (for headers BD) + 2 (for PBD and last BD)
+ * The headers comes in a seperate bd in FreeBSD. So 13-3=10.
+ * returns 1 to defrag, 0 if OK.
+ */
+static int
+bxe_chktso_window(struct bxe_softc* sc, int nsegs, bus_dma_segment_t *segs,
+    struct mbuf *m0)
+{
+	uint32_t num_wnds, wnd_size, wnd_sum;
+	int32_t frag_idx, wnd_idx;
+	unsigned short lso_mss;
+	int defrag;
+
+	defrag = 0;
+	wnd_sum = 0;
+	wnd_size = 10;
+	num_wnds = nsegs - wnd_size;
+	lso_mss = htole16(m0->m_pkthdr.tso_segsz);
+
+	/*
+	 * Total Header lengths Eth+IP+TCP in 1st FreeBSD mbuf so
+	 * calculate the first window sum of data skip the first
+	 * assuming it is the header in FreeBSD.
+	 */
+	for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++)
+		wnd_sum += htole16(segs[frag_idx].ds_len);
+
+	/* Chk the first 10 bd window size */
+	if (wnd_sum < lso_mss)
+		return (defrag = 1);
+
+	/* Run through the windows */
+	for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
+		/* Subtract the 1st mbuf->m_len of the last wndw(-header). */
+		wnd_sum	-= htole16(segs[wnd_idx+1].ds_len);
+		/* Add the next mbuf len to the len of our new window. */
+		wnd_sum +=  htole16(segs[frag_idx].ds_len);
+		if (wnd_sum < lso_mss) {
+			defrag = 1;
+			break;
+		}
+	}
+
+	return (defrag);
+}
+
+/*
+ * bxe_tx_encap()
+ * Encapsultes an mbuf cluster into the bxe tx_bd chain structure and
+ * makes the memory visible to the controller.
+ *
+ * If an mbuf is submitted to this routine and cannot be given to the
+ * controller (e.g. it has too many fragments) then the function may free
+ * the mbuf and return to the caller.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure
+ *   Note the side effect that an mbuf may be freed if it causes a problem.
+ */
+static int
+bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
+{
+	bus_dma_segment_t segs[32];
+	bus_dmamap_t map;
+	struct mbuf *m0;
+	struct eth_tx_parse_bd *pbd;
+	struct eth_tx_bd *tx_data_bd;
+	struct eth_tx_bd *tx_total_pkt_size_bd;
+	struct eth_tx_start_bd *tx_start_bd;
+	uint16_t etype, bd_prod, pkt_prod, total_pkt_size;
+	uint8_t mac_type;
+	int i, e_hlen, error, nsegs, rc, nbds, vlan_off, ovlan;
+	struct bxe_softc *sc;
+
+	sc = fp->sc;
+	DBENTER(BXE_VERBOSE_SEND);
+
+	rc = 0;
+	nbds = 0;
+	ovlan = 0;
+	vlan_off = 0;
+	total_pkt_size = 0;
+
+	m0 = *m_head;
+
+	tx_total_pkt_size_bd = NULL;
+	tx_start_bd = NULL;
+	tx_data_bd = NULL;
+	pbd = NULL;
+
+	pkt_prod = fp->tx_pkt_prod;
+	bd_prod = TX_BD(fp->tx_bd_prod);
+
+	mac_type = UNICAST_ADDRESS;
+
+#ifdef BXE_DEBUG
+	int debug_prod;
+	DBRUN(debug_prod = bd_prod);
+#endif
+
+	/* Map the mbuf into the next open DMAable memory. */
+	map = fp->tx_mbuf_map[TX_BD(pkt_prod)];
+	error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, map, m0,
+	    segs, &nsegs, BUS_DMA_NOWAIT);
+	do{
+	/* Handle any mapping errors. */
+		if(__predict_false(error)){
+			if (error == ENOMEM) {
+				rc = ENOMEM;
+			}else if (error == EFBIG) {
+				m0 = m_defrag(*m_head, M_DONTWAIT);
+				if (m0 == NULL) {
+					rc = ENOBUFS;
+				} else {
+				/* Defrag was successful, try mapping again.*/
+					*m_head = m0;
+					error =
+					    bus_dmamap_load_mbuf_sg(
+						fp->tx_mbuf_tag, map, m0,
+						segs, &nsegs, BUS_DMA_NOWAIT);
+				}
+			}else {
+				rc = error;
+			}
+			break;
+		}
+		/*
+		 * Now that we know how many buffer descriptors	are required to
+		 * send the frame, check whether we have enough transmit BD's
+		 * to do the job.  Make sure we have enough room for a parsing
+		 * BD too.
+		 */
+		if (__predict_false((nsegs + 2) >
+		    (USABLE_TX_BD - fp->used_tx_bd))) {
+			bus_dmamap_unload(fp->tx_mbuf_tag, map);
+			rc = ENOBUFS;
+			break;
+		}
+		/* Now make sure it fits in the pkt window */
+		if (nsegs > 12) {
+		/* The mbuf has more segments than the controller can handle.
+		 * Try to defrag the mbuf if there are too many
+		 * segments.  If it can't be defragged then
+		 * drop the frame, log an error, and exit.
+		 * An alternative would be to use a bounce buffer.
+		 */
+			if(m0->m_pkthdr.csum_flags & CSUM_TSO){
+				if (! bxe_chktso_window(sc,nsegs,segs,m0))
+					/* Send it */
+					break;
+			}
+			/* Defrag for non tso and if tso needs it */
+			m0 = m_defrag(*m_head, M_DONTWAIT);
+			if (m0 == NULL) {
+				rc = ENOBUFS;
+				break;
+			}
+			/* Defrag was successful, try mapping again. */
+			*m_head = m0;
+			error =
+			    bus_dmamap_load_mbuf_sg(
+				fp->tx_mbuf_tag, map, m0,
+				segs, &nsegs, BUS_DMA_NOWAIT);
+			/* Handle any mapping errors. */
+			if (__predict_false(error)) {
+				if(error == ENOMEM) {
+					/* This is a recoverable error,
+					 * try again later.
+					 */
+					rc = ENOMEM;
+				} else {
+					/* The frame can't be defragged,
+					 *  drop it.
+					 */
+					rc = error;
+				}
+				break;
+			}
+			/* Last try */
+			if (m0->m_pkthdr.csum_flags & CSUM_TSO){
+				if (bxe_chktso_window(sc,nsegs,segs,m0))
+					rc = ENOBUFS;
+			} else if (nsegs > 12 ){
+				rc = ENOBUFS;
+			}
+		}
+	}while (0);
+
+    /* Check for errors */
+	if (rc){
+		if(rc == ENOMEM){
+			/* Recoverable try again later  */
+			BXE_PRINTF("%s(%d): Error mapping mbuf into TX chain"
+			   "returning pkt to queue\n",__FILE__, __LINE__);
+		}else{
+			fp->soft_tx_errors++;
+			DBRUN(fp->tx_mbuf_alloc--);
+			m_freem(*m_head);
+			*m_head = NULL;
+			BXE_PRINTF("%s(%d): Error mapping mbuf into TX chain"
+			    "Frame dropped \n",__FILE__, __LINE__);
+		}
+		return (rc);
+	}
+
+	/* We're committed to sending the frame, update the counter. */
+	fp->tx_pkt_prod++;
+
+	/* set flag according to packet type (UNICAST_ADDRESS is default)*/
+		if (m0->m_flags & M_BCAST)
+			mac_type = BROADCAST_ADDRESS;
+		else if (m0->m_flags & M_MCAST)
+			mac_type = MULTICAST_ADDRESS;
+
+	/* Prepare the first transmit BD for the mbuf(Get a link from the chain). */
+	tx_start_bd = &fp->tx_bd_chain[TX_PAGE(bd_prod)][TX_IDX(bd_prod)].start_bd;
+
+	tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
+	tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
+	tx_start_bd->nbytes  = htole16(segs[0].ds_len);
+	total_pkt_size += tx_start_bd->nbytes;
+	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
+	tx_start_bd->general_data =
+		(mac_type << ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
+
+	tx_start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
+
+	nbds = nsegs + 1;  /* Add 1 for parsing bd. Assuming nseg > 0  */
+	tx_start_bd->nbd = htole16(nbds);
+
+	if (m0->m_flags & M_VLANTAG) {
+//		vlan_off += ETHER_VLAN_ENCAP_LEN;
+		tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
+		tx_start_bd->vlan = htole16(m0->m_pkthdr.ether_vtag);
+		DBPRINT(sc, BXE_VERBOSE_SEND, "%s(): Inserting VLAN tag %d\n",
+			__FUNCTION__, m0->m_pkthdr.ether_vtag);
+	}
+	else
+		/*
+		 * In cases where the VLAN tag is not used the firmware
+		 * expects to see a packet counter in the VLAN tag field
+		 * Failure to do so will cause an assertion which will
+		 * stop the controller.
+		 */
+		tx_start_bd->vlan = htole16(pkt_prod);
+
+	/* Add a parsing BD from the chain. The parsing bd is always added,
+	 * however, it is only used for tso & chksum.
+	 */
+	bd_prod = TX_BD(NEXT_TX_BD(bd_prod));
+	pbd = (struct eth_tx_parse_bd *)
+		   &fp->tx_bd_chain[TX_PAGE(bd_prod)][TX_IDX(bd_prod)].parse_bd;
+	memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
+
+	/* Gather all info about the packet and add to pbd */
+	if (m0->m_pkthdr.csum_flags) {
+		struct ether_vlan_header *eh;
+		struct ip *ip = NULL;
+		struct tcphdr *th = NULL;
+		uint16_t flags = 0;
+		struct udphdr *uh = NULL;
+
+		/* Map the Ethernet header to find the type & header length. */
+		eh = mtod(m0, struct ether_vlan_header *);
+
+		/* Handle VLAN encapsulation if present. */
+		if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
+			etype = ntohs(eh->evl_proto);
+			e_hlen = ETHER_HDR_LEN + vlan_off;
+		} else {
+			etype = ntohs(eh->evl_encap_proto);
+			e_hlen = ETHER_HDR_LEN;
+		}
+
+		/* Set the Ethernet header length in 16 bit words. */
+		pbd->global_data = (e_hlen + ovlan) >> 1;
+		pbd->global_data |= ((m0->m_flags & M_VLANTAG) << ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT);
+
+		switch (etype) {
+		case ETHERTYPE_IP:{
+			/* if mbuf's len < 20bytes, the ip_hdr is in next mbuf*/
+			if (m0->m_len < sizeof(struct ip))
+				ip = (struct ip *)m0->m_next->m_data;
+			else
+				ip = (struct ip *)(m0->m_data + e_hlen);
+
+			/* Calculate IP header length (16 bit words). */
+			pbd->ip_hlen = (ip->ip_hl << 1);
+
+			/* Calculate enet + IP header length (16 bit words). */
+			pbd->total_hlen = pbd->ip_hlen + (e_hlen >> 1);
+
+			if (m0->m_pkthdr.csum_flags & CSUM_IP) {
+				DBPRINT(sc, BXE_EXTREME_SEND, "%s(): IP checksum "
+					"enabled.\n", __FUNCTION__);
+				DBRUN(sc->debug_ip_csum_offload_frames++);
+				flags |= ETH_TX_BD_FLAGS_IP_CSUM;
+			}
+
+			/* Handle any checksums requested by the stack. */
+			if ((m0->m_pkthdr.csum_flags & CSUM_TCP)||
+				(m0->m_pkthdr.csum_flags & CSUM_TSO)){
+
+				/* Perform TCP checksum offload. */
+				DBPRINT(sc, BXE_EXTREME_SEND, "%s(): TCP checksum "
+					"enabled.\n", __FUNCTION__);
+
+				/* Get the TCP header. */
+				th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
+
+				/* Add the TCP checksum offload flag. */
+				flags |= ETH_TX_BD_FLAGS_L4_CSUM;
+				DBRUN(sc->debug_tcp_csum_offload_frames++);
+
+				/* Update the enet + IP + TCP header length. */
+				pbd->total_hlen += (uint16_t)(th->th_off << 1);
+
+				/* Get the pseudo header checksum. */
+				pbd->tcp_pseudo_csum = ntohs(th->th_sum);
+			} else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
+				/*
+				 * The hardware doesn't actually support UDP checksum
+				 * offload but we can fake it by doing TCP checksum
+				 * offload and factoring out the extra bytes that are
+				 * different between the TCP header and the UDP header.
+				 * calculation will begin 10 bytes before the actual
+				 * start of the UDP header.  To work around this we
+				 * need to calculate the checksum of the 10 bytes
+				 * before the UDP header and factor that out of the
+				 * UDP pseudo header checksum before asking the H/W
+				 * to calculate the full UDP checksum.
+				 */
+				uint16_t tmp_csum;
+				uint32_t *tmp_uh;
+
+				/* This value is 10. */
+				uint8_t fix = (uint8_t) (offsetof(struct tcphdr, th_sum) -
+					(int) offsetof(struct udphdr, uh_sum));
+
+				/* Perform UDP checksum offload. */
+				DBPRINT(sc, BXE_EXTREME_SEND, "%s(): UDP checksum "
+					"enabled.\n", __FUNCTION__);
+
+				/* Add the TCP checksum offload flag for UDP frames too. */
+				flags |= ETH_TX_BD_FLAGS_L4_CSUM;
+				DBRUN(sc->debug_udp_csum_offload_frames++);
+				pbd->global_data |= ETH_TX_PARSE_BD_UDP_CS_FLG;
+
+				/* Get a pointer to the UDP header. */
+				uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
+
+				/* Set a pointer 10 bytes before the actual UDP header. */
+ 					tmp_uh = (uint32_t *)((uint8_t *)uh - fix);
+
+				/*
+				 * Calculate a pseudo header checksum over the 10 bytes
+				 * before the UDP header.
+				 */
+				tmp_csum = in_pseudo(ntohl(*tmp_uh),
+					ntohl(*(tmp_uh + 1)),
+					ntohl((*(tmp_uh + 2)) & 0x0000FFFF));
+
+				/* Update the enet + IP + UDP header length. */
+				pbd->total_hlen += (sizeof(struct udphdr) >> 1);
+				pbd->tcp_pseudo_csum = ~in_addword(uh->uh_sum, ~tmp_csum);
+			}
+
+			/* Update the flags settings for VLAN/Offload. */
+			tx_start_bd->bd_flags.as_bitfield |= flags;
+
+			break;
+		}
+		case ETHERTYPE_IPV6:
+			BXE_PRINTF("%s(%d): IPv6 checksum offload not "
+				"supported!.\n", __FILE__, __LINE__);
+			break;
+
+		default:
+			BXE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
+				__FILE__, __LINE__);
+		}
+
+		/* Setup the Parsing BD with TSO specific info */
+		if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
+
+			uint16_t hdr_len = pbd->total_hlen << 1;
+
+			DBPRINT(sc, BXE_EXTREME_SEND, "%s(): TSO is enabled.\n",__FUNCTION__);
+
+			tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
+
+			DBRUN(sc->debug_tso_offload_frames++);
+ 			if (__predict_false(tx_start_bd->nbytes > hdr_len)) {
+				/*
+				 * Split the first BD into 2 BDs to make the
+				 * FW job easy...
+				 */
+				tx_start_bd->nbd++;
+				DBPRINT(sc, 1, /*BXE_EXTREME_SEND,*/
+					"%s(): TSO split headr size is %d (%x:%x) nbds %d\n",
+					__FUNCTION__, tx_start_bd->nbytes, tx_start_bd->addr_hi,
+					tx_start_bd->addr_lo, nbds);
+
+	bd_prod = TX_BD(NEXT_TX_BD(bd_prod));
+
+				/* Get a new transmit BD (after the pbd) and fill it. */
+				tx_data_bd = &fp->tx_bd_chain[TX_PAGE(bd_prod)][TX_IDX(bd_prod)].reg_bd;
+				tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hdr_len));
+				tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hdr_len));
+				tx_data_bd->nbytes = htole16(segs[0].ds_len) - hdr_len;
+
+				/*
+				 * This indicates that the transmit BD
+				 * has no individual mapping and the
+				 * FW ignores this flag in a BD that is
+				 * not marked with the start flag.
+				 */
+
+				DBPRINT(sc, BXE_EXTREME_SEND, "%s(): TSO split data "
+					"size is %d (%x:%x)\n", __FUNCTION__,
+					tx_data_bd->nbytes, tx_data_bd->addr_hi, tx_data_bd->addr_lo);
+			}
+
+			/*
+			 * For TSO the controller needs the following info:
+			 * MSS, tcp_send_seq, ip_id, and tcp_pseudo_csum.
+			 */
+			pbd->lso_mss = htole16(m0->m_pkthdr.tso_segsz);
+			pbd->tcp_send_seq = ntohl(th->th_seq);
+			pbd->tcp_flags = th->th_flags;
+			pbd->ip_id = ntohs(ip->ip_id);
+
+			pbd->tcp_pseudo_csum = ntohs(in_pseudo(ip->ip_src.s_addr,
+								   ip->ip_dst.s_addr, htons(IPPROTO_TCP)));
+
+			pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
+		}
+	}
+
+	/* Prepare Remaining BDs. Start_tx_bd contains first seg(frag). */
+	for (i = 1; i < nsegs ; i++) {
+		bd_prod = TX_BD(NEXT_TX_BD(bd_prod));
+		tx_data_bd = &fp->tx_bd_chain[TX_PAGE(bd_prod)][TX_IDX(bd_prod)].reg_bd;
+		tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
+		tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
+		tx_data_bd->nbytes = htole16(segs[i].ds_len);
+		if (tx_total_pkt_size_bd == NULL)
+			tx_total_pkt_size_bd = tx_data_bd;
+		total_pkt_size += tx_data_bd->nbytes;
+	}
+
+	if(tx_total_pkt_size_bd != NULL)
+		tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
+
+	/* Update bd producer index value for next tx */
+	bd_prod = TX_BD(NEXT_TX_BD(bd_prod));
+/*
+BXE_PRINTF("tx_start_bd: addrlo:0x%x, addrhi:0x%x, nbytes:0x%x, bitfield:0x%x, gendata:0x%x, nbd:0x%x\n",
+tx_start_bd->addr_lo,
+tx_start_bd->addr_hi,
+tx_start_bd->nbytes,
+tx_start_bd->bd_flags.as_bitfield,
+tx_start_bd->general_data,
+tx_start_bd->nbd );
+
+bxe_dump_mbuf(sc, m0);
+*/
+	DBRUNMSG(BXE_EXTREME_SEND, bxe_dump_tx_chain(fp, debug_prod, nbds));
+
+	/*
+	 * Ensure that the mbuf pointer for this
+	 * transmission is placed at the array index
+	 * of the last descriptor in this chain.
+	 * This is done because a single map is used
+	 * for all segments of the mbuf and we don't
+	 * want to unload the map before all of the
+	 * segments have been freed.
+	 */
+	fp->tx_mbuf_ptr[TX_BD(pkt_prod)] = m0;
+
+	fp->used_tx_bd += nbds;
+
+	/*
+	 * Ring the tx doorbell, counting the next
+	 * bd if the packet contains or ends with it.
+	 */
+	if(TX_IDX(bd_prod) < nbds)
+		nbds++;
+
+//BXE_PRINTF("nsegs:%d, tpktsz:0x%x\n",nsegs, total_pkt_size) ;
+
+	/*
+	 * Update the buffer descriptor producer count and the packet
+	 * producer count in doorbell data memory (eth_tx_db_data) then
+	 * ring the doorbell.
+	 */
+/*	fp->hw_tx_prods->bds_prod =
+		htole16(le16toh(fp->hw_tx_prods->bds_prod) + nbds);
+*/
+
+
+//pci_read_config(sc->bxe_dev, PCIR_REVID, 4);
+
+	/* Don't allow reordering of writes for nbd and packets. */
+	mb();
+/*
+	fp->hw_tx_prods->packets_prod =
+		htole32(le32toh(fp->hw_tx_prods->packets_prod) + 1);
+*/
+//	DOORBELL(sc, fp->index, 0);
+
+//	BXE_PRINTF("doorbell: nbd %d  bd %u  index %d\n", nbds, bd_prod, fp->index);
+
+	fp->tx_db.data.prod += nbds;
+	/* Producer points to the next free tx_bd at this point. */
+	fp->tx_bd_prod = bd_prod;
+
+	DOORBELL(sc, fp->index, fp->tx_db.raw);
+
+
+	DBRUN(fp->tx_pkts++);
+
+	/* Prevent speculative reads from getting ahead of the status block. */
+	bus_space_barrier(sc->bxe_btag, sc->bxe_bhandle, 0, 0,
+		BUS_SPACE_BARRIER_READ);
+
+	/* Prevent speculative reads from getting ahead of the status block. */
+	bus_space_barrier(sc->bxe_db_btag, sc->bxe_db_bhandle, 0, 0,
+		BUS_SPACE_BARRIER_READ);
+//pci_read_config(sc->bxe_dev, PCIR_REVID, 4);
+
+	DBEXIT(BXE_VERBOSE_SEND);
+	return(rc);
+}
+
+/*
+ * Transmit dispatch routine.
+ *
+ * This routine acts as a dispatcher, deciding which TX chain will be used
+ * to send an outgoing frame and then adding the frame to that chain. It is
+ * called by the OS when it's ready to transmit a frame.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_tx_start(struct ifnet *ifp)
+{
+	struct bxe_softc *sc;
+	struct bxe_fastpath *fp;
+	int fp_index;
+
+	sc = ifp->if_softc;
+	DBENTER(BXE_EXTREME_SEND);
+
+	fp_index = 0;
+
+	/* Exit if there's no link. */
+	if (!sc->link_vars.link_up) {
+		DBPRINT(sc, BXE_VERBOSE_SEND,
+		    "%s(): No link, ignoring transmit request.\n",
+		    __FUNCTION__);
+		goto bxe_tx_start_exit;
+	}
+
+	/* Exit if the transmit queue is full. */
+	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+		IFF_DRV_RUNNING) {
+		DBPRINT(sc, BXE_VERBOSE_SEND, "%s(): Driver running but "
+		    "transmit queue full, ignoring transmit request.\n",
+		    __FUNCTION__);
+		goto bxe_tx_start_exit;
+	}
+
+	/* Set the TX queue for the frame. */
+	fp = &sc->fp[fp_index];
+
+	BXE_CORE_LOCK(sc);
+	bxe_tx_start_locked(ifp, fp);
+	BXE_CORE_UNLOCK(sc);
+
+bxe_tx_start_exit:
+	DBEXIT(BXE_EXTREME_SEND);
+}
+
+/*
+ * Main transmit routine.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_tx_start_locked(struct ifnet *ifp, struct bxe_fastpath *fp)
+{
+	struct bxe_softc *sc;
+	struct mbuf *m;
+	int tx_count;
+
+	sc = fp->sc;
+	DBENTER(BXE_EXTREME_SEND);
+
+	m = NULL;
+	tx_count = 0;
+
+ 	/* Keep adding entries while there are frames to send. */
+	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
+
+		/* Check for any frames to send. */
+		IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
+		if (__predict_false(m == NULL))
+			break;
+
+		/* The transmit mbuf now belongs to us, keep track of it. */
+		DBRUN(fp->tx_mbuf_alloc++);
+
+		/*
+		 * Pack the data into the transmit ring. If we
+		 * don't have room, place the mbuf back at the
+		 * head of the TX queue, set the OACTIVE flag,
+		 * and wait for the NIC to drain the chain.
+		 */
+		if (__predict_false(bxe_tx_encap(fp, &m))) {
+			/* Very Bad Frames(tm) may have been dropped. */
+			if (m != NULL) {
+				/*
+				 * Mark the TX queue as full and return
+				 * the frame.
+				 */
+				ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+				IFQ_DRV_PREPEND(&ifp->if_snd, m);
+				DBRUN(fp->tx_mbuf_alloc--);
+				sc->eth_stats.driver_xoff++;
+			} else {
+
+			}
+
+			/* Stop looking for more work. */
+			break;
+		}
+
+		/* The transmit frame was enqueued successfully. */
+		tx_count++;
+
+		/* Send a copy of the frame to any BPF listeners. */
+		BPF_MTAP(ifp, m);
+	}
+
+	/* No TX packets were dequeued. */
+	if (tx_count == 0) {
+		DBPRINT(sc, BXE_INFO_SEND,
+		    "%s(): No packets were dequeued on fp[%d].\n", __FUNCTION__,
+		    fp->index);
+		goto bxe_tx_start_locked_exit;
+	}
+
+	/* Reset the TX watchdog timeout timer. */
+	sc->watchdog_timer = BXE_TX_TIMEOUT;
+
+bxe_tx_start_locked_exit:
+	DBEXIT(BXE_EXTREME_SEND);
+}
+
+/*
+ * Handles any IOCTL calls from the operating system.
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+	struct bxe_softc *sc;
+	struct ifreq *ifr;
+	int error, mask, reinit;
+
+	sc = ifp->if_softc;
+	DBENTER(BXE_EXTREME_MISC);
+
+	ifr = (struct ifreq *)data;
+	error = 0;
+	reinit = 0;
+
+	switch (command) {
+	case SIOCSIFMTU:
+		/* Set the MTU. */
+		DBPRINT(sc, BXE_EXTREME_MISC, "%s(): Received SIOCSIFMTU\n",
+		    __FUNCTION__);
+
+		/* Check that the MTU setting is supported. */
+		if ((ifr->ifr_mtu < BXE_MIN_MTU) ||
+			(ifr->ifr_mtu > BXE_JUMBO_MTU)) {
+			DBPRINT(sc, BXE_WARN, "%s(): Unsupported MTU "
+			    "(%d < %d < %d)!\n", __FUNCTION__, BXE_MIN_MTU,
+			    ifr->ifr_mtu, BXE_JUMBO_MTU);
+			error = EINVAL;
+			break;
+		}
+
+		BXE_CORE_LOCK(sc);
+		ifp->if_mtu = ifr->ifr_mtu;
+		bxe_change_mtu(sc, ifp->if_drv_flags & IFF_DRV_RUNNING);
+		BXE_CORE_UNLOCK(sc);
+		break;
+	case SIOCSIFFLAGS:
+		/* Toggle the interface state up or down. */
+		DBPRINT(sc, BXE_EXTREME_MISC, "%s(): Received SIOCSIFFLAGS\n",
+		    __FUNCTION__);
+
+		BXE_CORE_LOCK(sc);
+
+		/* Check if the interface is up. */
+		if (ifp->if_flags & IFF_UP) {
+			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+				/*
+				 * Change the promiscuous/multicast flags as
+				 * necessary.
+				 */
+				bxe_set_rx_mode(sc);
+			} else {
+				/* Start the HW */
+				bxe_init_locked(sc, LOAD_NORMAL);
+			}
+		} else {
+			/*
+			 * The interface is down.  Check if the driver is
+			 * running.
+			 */
+			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+				bxe_stop_locked(sc, UNLOAD_NORMAL);
+		}
+		BXE_CORE_UNLOCK(sc);
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		/* Add/Delete multicast addresses. */
+		DBPRINT(sc, BXE_EXTREME_MISC,
+		    "%s(): Received SIOCADDMULTI/SIOCDELMULTI\n", __FUNCTION__);
+
+		BXE_CORE_LOCK(sc);
+
+		/* Don't bother unless the driver's running. */
+		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+			bxe_set_rx_mode(sc);
+
+		BXE_CORE_UNLOCK(sc);
+		break;
+	case SIOCSIFMEDIA:
+	case SIOCGIFMEDIA:
+		/* Set/Get Interface media */
+		DBPRINT(sc, BXE_EXTREME_MISC,
+		    "%s(): Received SIOCSIFMEDIA/SIOCGIFMEDIA\n", __FUNCTION__);
+		error = ifmedia_ioctl(ifp, ifr, &sc->bxe_ifmedia, command);
+		break;
+	case SIOCSIFCAP:
+		/* Set interface capability */
+
+		/* Find out which capabilities have changed. */
+		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+		DBPRINT(sc, BXE_VERBOSE_MISC,
+		    "%s(): Received SIOCSIFCAP (mask = 0x%08X)\n", __FUNCTION__,
+		    (uint32_t)mask);
+
+		BXE_CORE_LOCK(sc);
+
+		/* Toggle the LRO capabilites enable flag. */
+		if (mask & IFCAP_LRO) {
+			ifp->if_capenable ^= IFCAP_LRO;
+			sc->bxe_flags ^= BXE_TPA_ENABLE_FLAG;
+			DBPRINT(sc, BXE_INFO_MISC,
+			    "%s(): Toggling LRO (bxe_flags = 0x%08X).\n",
+			    __FUNCTION__, sc->bxe_flags);
+			reinit = 1;
+		}
+
+		/* Toggle the TX checksum capabilites enable flag. */
+		if (mask & IFCAP_TXCSUM) {
+			DBPRINT(sc, BXE_VERBOSE_MISC,
+			    "%s(): Toggling IFCAP_TXCSUM.\n", __FUNCTION__);
+
+			ifp->if_capenable ^= IFCAP_TXCSUM;
+
+			if (IFCAP_TXCSUM & ifp->if_capenable)
+				ifp->if_hwassist = BXE_IF_HWASSIST;
+			else
+				ifp->if_hwassist = 0;
+		}
+
+		/* Toggle the RX checksum capabilities enable flag. */
+		if (mask & IFCAP_RXCSUM) {
+			DBPRINT(sc, BXE_VERBOSE_MISC,
+			    "%s(): Toggling IFCAP_RXCSUM.\n", __FUNCTION__);
+
+			ifp->if_capenable ^= IFCAP_RXCSUM;
+
+			if (IFCAP_RXCSUM & ifp->if_capenable)
+				ifp->if_hwassist = BXE_IF_HWASSIST;
+			else
+				ifp->if_hwassist = 0;
+		}
+
+		/* Toggle VLAN_MTU capabilities enable flag. */
+		if (mask & IFCAP_VLAN_MTU) {
+			BXE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n",
+			    __FILE__, __LINE__);
+			error = EINVAL;
+		}
+
+		/* Toggle VLANHWTAG capabilities enabled flag. */
+		if (mask & IFCAP_VLAN_HWTAGGING) {
+			BXE_PRINTF(
+			    "%s(%d): Changing VLAN_HWTAGGING not supported!\n",
+			    __FILE__, __LINE__);
+			error = EINVAL;
+		}
+
+		/* Toggle TSO4 capabilities enabled flag. */
+		if (mask & IFCAP_TSO4) {
+			DBPRINT(sc, BXE_VERBOSE_MISC,
+			    "%s(): Toggling IFCAP_TSO4.\n", __FUNCTION__);
+
+			ifp->if_capenable ^= IFCAP_TSO4;
+		}
+
+		/* Toggle TSO6 capabilities enabled flag. */
+		if (mask & IFCAP_TSO6) {
+			DBPRINT(sc, BXE_VERBOSE_MISC,
+			    "%s(): Toggling IFCAP_TSO6.\n", __FUNCTION__);
+
+			ifp->if_capenable ^= IFCAP_TSO6;
+		}
+
+		/* Handle any other capabilities. */
+		if (mask & ~(IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU |
+		    IFCAP_RXCSUM | IFCAP_TXCSUM)) {
+			BXE_PRINTF("%s(%d): Unsupported capability!\n",
+			    __FILE__, __LINE__);
+			error = EINVAL;
+		}
+
+		/* Handle any other capabilities. */
+		if (mask & ~(IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU |
+			IFCAP_RXCSUM | IFCAP_TXCSUM)) {
+			BXE_PRINTF("%s(%d): Unsupported capability!\n",
+				__FILE__, __LINE__);
+			error = EINVAL;
+		}
+
+		/* Restart the controller with the new capabilities. */
+		if (reinit) {
+			bxe_stop_locked(sc, UNLOAD_NORMAL);
+			bxe_init_locked(sc, LOAD_NORMAL);
+		}
+
+		BXE_CORE_UNLOCK(sc);
+		break;
+	default:
+		/* We don't know how to handle the IOCTL, pass it on. */
+		error = ether_ioctl(ifp, command, data);
+		break;
+	}
+
+	DBEXIT(BXE_EXTREME_MISC);
+
+	return (error);
+}
+
+/*
+ * Gets the current value of the RX Completion Consumer index
+ * from the fastpath status block, updates it as necessary if
+ * it is pointing to a "Next Page" entry, and returns it to the
+ * caller.
+ *
+ * Returns:
+ * 	 The adjusted value of *fp->rx_cons_sb.
+ */
+static __inline uint16_t
+bxe_rx_comp_cons(struct bxe_fastpath *fp)
+{
+	volatile uint16_t rx_cons_sb = 0;
+
+	rmb();
+	rx_cons_sb = (volatile uint16_t)le16toh(*fp->rx_cons_sb);
+
+	/*
+	 * It is valid for the hardware's copy of the completion
+	 * consumer index to be pointing at a "Next Page" entry in
+	 * the completion chain but the driver prefers to assume
+	 * that it is pointing at the next available CQE so we
+	 * need to adjust the value accordingly.
+	 */
+	if ((rx_cons_sb & TOTAL_RCQ_ENTRIES_PER_PAGE) ==
+		TOTAL_RCQ_ENTRIES_PER_PAGE)
+		rx_cons_sb++;
+
+	return (rx_cons_sb);
+}
+
+static __inline int
+bxe_has_tx_work(struct bxe_fastpath *fp)
+{
+
+	rmb();
+	return (((fp->tx_pkt_prod != le16toh(*fp->tx_cons_sb)) || \
+	    (fp->tx_pkt_prod != fp->tx_pkt_cons)));
+}
+
+/*
+ * Checks if there are any received frames to process on the
+ * completion queue.
+ *
+ * Returns:
+ * 	 0 = No received frames pending, !0 = Received frames
+ * 	 pending
+ */
+static __inline int
+bxe_has_rx_work(struct bxe_fastpath *fp)
+{
+
+	rmb();
+	return (bxe_rx_comp_cons(fp) != fp->rx_comp_cons);
+}
+
+/*
+ * Slowpath task entry point.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_task_sp(void *xsc, int pending)
+{
+	struct bxe_softc *sc;
+	uint32_t sp_status;
+
+	sc = xsc;
+	DBENTER(BXE_EXTREME_INTR);
+
+	DBPRINT(sc, BXE_EXTREME_INTR, "%s(): pending = %d.\n", __FUNCTION__,
+	    pending);
+
+	/* Check for the source of the interrupt. */
+	sp_status = bxe_update_dsb_idx(sc);
+
+	/* Handle any hardware attentions. */
+	if (sp_status & 0x1) {
+		bxe_attn_int(sc);
+		sp_status &= ~0x1;
+	}
+
+	/* CSTORM event asserted (query_stats, port delete ramrod, etc.). */
+	if (sp_status & 0x2) {
+		sc->stats_pending = 0;
+		sp_status &= ~0x2;
+	}
+
+	/* Check for other weirdness. */
+	if (sp_status != 0) {
+		DBPRINT(sc, BXE_WARN, "%s(): Unexpected slowpath interrupt "
+		    "(sp_status = 0x%04X)!\n", __FUNCTION__, sp_status);
+	}
+
+	/* Acknowledge the xSTORM tags and enable slowpath interrupts. */
+	bxe_ack_sb(sc, DEF_SB_ID, ATTENTION_ID, le16toh(sc->def_att_idx),
+	    IGU_INT_NOP, 1);
+	bxe_ack_sb(sc, DEF_SB_ID, USTORM_ID, le16toh(sc->def_u_idx),
+	    IGU_INT_NOP, 1);
+	bxe_ack_sb(sc, DEF_SB_ID, CSTORM_ID, le16toh(sc->def_c_idx),
+	    IGU_INT_NOP, 1);
+	bxe_ack_sb(sc, DEF_SB_ID, XSTORM_ID, le16toh(sc->def_x_idx),
+	    IGU_INT_NOP, 1);
+	bxe_ack_sb(sc, DEF_SB_ID, TSTORM_ID, le16toh(sc->def_t_idx),
+	    IGU_INT_ENABLE, 1);
+
+	DBEXIT(BXE_EXTREME_INTR);
+}
+
+
+/*
+ * Legacy interrupt entry point.
+ *
+ * Verifies that the controller generated the interrupt and
+ * then calls a separate routine to handle the various
+ * interrupt causes: link, RX, and TX.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_intr_legacy(void *xsc)
+{
+	struct bxe_softc *sc;
+	struct bxe_fastpath *fp;
+	uint32_t mask, fp_status;
+
+	sc = xsc;
+	fp = &sc->fp[0];
+
+	/* Don't handle any interrupts if we're not ready. */
+	if (__predict_false(sc->intr_sem != 0))
+		goto bxe_intr_legacy_exit;
+
+	/* Bail out if the interrupt wasn't generated by our hardware. */
+	fp_status = bxe_ack_int(sc);
+	if (fp_status == 0)
+		goto bxe_intr_legacy_exit;
+
+	/* Need to weed out calls due to shared interrupts. */
+	DBENTER(BXE_EXTREME_INTR);
+
+	/* Handle the fastpath interrupt. */
+	/*
+	 * sb_id = 0 for ustorm, 1 for cstorm.
+	 * The bits returned from ack_int() are 0-15,
+	 * bit 0=attention status block
+	 * bit 1=fast path status block
+	 * A mask of 0x2 or more = tx/rx event
+	 * A mask of 1 = slow path event
+	 */
+
+	mask = (0x2 << fp->sb_id);
+	DBPRINT(sc, BXE_EXTREME_INTR,
+	    "%s(): fp_status = 0x%08X, mask = 0x%08X\n", __FUNCTION__,
+	    fp_status, mask);
+
+	/* CSTORM event means fastpath completion. */
+	if (fp_status & mask) {
+		/* This interrupt must be ours, disable further interrupts. */
+		bxe_ack_sb(sc, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
+#ifdef BXE_TASK
+		taskqueue_enqueue(fp->tq, &fp->task);
+#else
+		bxe_task_fp((void *)fp, 0);
+#endif
+		/* Clear this event from the status flags. */
+		fp_status &= ~mask;
+	}
+
+	/* Handle all slow path interrupts and attentions */
+	if (fp_status & 0x1) {
+		/* Acknowledge and disable further slowpath interrupts. */
+		bxe_ack_sb(sc, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
+#ifdef BXE_TASK
+		/* Schedule the slowpath task. */
+		taskqueue_enqueue(sc->tq, &sc->task);
+#else
+		bxe_task_sp(xsc, 0);
+#endif
+		/* Clear this event from the status flags. */
+		fp_status &= ~0x1;
+	}
+
+#ifdef BXE_DEBUG
+	if (fp_status) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Unexpected fastpath status (fp_status = 0x%08X)!\n",
+		    __FUNCTION__, fp_status);
+	}
+#endif
+
+	DBEXIT(BXE_EXTREME_INTR);
+
+bxe_intr_legacy_exit:
+	return;
+}
+
+/*
+ * Slowpath interrupt entry point.
+ *
+ * Acknowledge the interrupt and schedule a slowpath task.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_intr_sp(void *xsc)
+{
+	struct bxe_softc *sc;
+
+	sc = xsc;
+	DBENTER(BXE_EXTREME_INTR);
+
+	/* Don't handle any interrupts if we're not ready. */
+	if (__predict_false(sc->intr_sem != 0))
+		goto bxe_intr_sp_exit;
+
+	/* Acknowledge and disable further slowpath interrupts. */
+	bxe_ack_sb(sc, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
+
+#ifdef BXE_TASK
+	/* Schedule the slowpath task. */
+	taskqueue_enqueue(sc->tq, &sc->task);
+#else
+	bxe_task_sp(xsc, 0);
+#endif
+
+bxe_intr_sp_exit:
+	DBEXIT(BXE_EXTREME_INTR);
+}
+
+/*
+ * Fastpath interrupt entry point.
+ *
+ * Acknowledge the interrupt and schedule a fastpath task.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_intr_fp (void *xfp)
+{
+	struct bxe_fastpath *fp;
+	struct bxe_softc *sc;
+
+	fp = xfp;
+	sc = fp->sc;
+
+	DBENTER(BXE_EXTREME_INTR);
+
+	DBPRINT(sc, BXE_EXTREME_INTR,
+	    "%s(%d): MSI-X vector on fp[%d].sb_id = %d\n", __FUNCTION__, curcpu,	    fp->index, fp->sb_id);
+
+	/* Don't handle any interrupts if we're not ready. */
+	if (__predict_false(sc->intr_sem != 0))
+		goto bxe_intr_fp_exit;
+
+	/* Disable further interrupts. */
+	bxe_ack_sb(sc, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
+#ifdef BXE_TASK
+	taskqueue_enqueue(fp->tq, &fp->task);
+#else
+	bxe_task_fp (xfp, 0);
+#endif
+
+bxe_intr_fp_exit:
+	DBEXIT(BXE_EXTREME_INTR);
+}
+
+/*
+ * Fastpath task entry point.
+ *
+ * Handle any pending transmit or receive events.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_task_fp (void *xfp, int pending)
+{
+	struct bxe_fastpath *fp;
+	struct bxe_softc *sc;
+
+	fp = xfp;
+	sc = fp->sc;
+
+	DBENTER(BXE_EXTREME_INTR);
+
+	DBPRINT(sc, BXE_EXTREME_INTR, "%s(): pending = %d.\n", __FUNCTION__,
+	    pending);
+
+	DBPRINT(sc, BXE_EXTREME_INTR, "%s(%d): FP task on fp[%d].sb_id = %d\n",
+	    __FUNCTION__, curcpu, fp->index, fp->sb_id);
+
+	/* Update the fast path indices */
+	bxe_update_fpsb_idx(fp);
+
+	/* Service any completed TX frames. */
+	if (bxe_has_tx_work(fp)) {
+		BXE_CORE_LOCK(sc);
+		bxe_txeof(fp);
+		BXE_CORE_UNLOCK(sc);
+	}
+
+	/* Service any completed RX frames. */
+	rmb();
+	bxe_rxeof(fp);
+
+	/* Acknowledge the fastpath status block indices. */
+	bxe_ack_sb(sc, fp->sb_id, USTORM_ID, fp->fp_u_idx, IGU_INT_NOP, 1);
+	bxe_ack_sb(sc, fp->sb_id, CSTORM_ID, fp->fp_c_idx, IGU_INT_ENABLE, 1);
+
+	DBEXIT(BXE_EXTREME_INTR);
+}
+
+/*
+ * Clears the fastpath (per-queue) status block.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_zero_sb(struct bxe_softc *sc, int sb_id)
+{
+	int port;
+
+	port = BP_PORT(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+	    "%s(): Clearing sb_id = %d on port %d.\n", __FUNCTION__, sb_id,
+	    port);
+
+	/* "CSTORM" */
+	bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
+	    CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
+	    CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
+	bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
+	    CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
+	    CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+}
+
+/*
+ * Initialize the fastpath (per queue) status block.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_init_sb(struct bxe_softc *sc, struct host_status_block *sb,
+    bus_addr_t mapping, int sb_id)
+{
+	uint64_t section;
+	int func, index, port;
+
+	port = BP_PORT(sc);
+	func = BP_FUNC(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR),
+		 "%s():	Initializing sb_id = %d on port %d, function %d.\n",
+		__FUNCTION__, sb_id, port, func);
+
+	/* Setup the USTORM status block. */
+	section = ((uint64_t)mapping) + offsetof(struct host_status_block,
+	    u_status_block);
+	sb->u_status_block.status_block_id = sb_id;
+
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section));
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
+	    U64_HI(section));
+	REG_WR8(sc, BAR_CSTORM_INTMEM + FP_USB_FUNC_OFF +
+	    CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
+
+	for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
+		REG_WR16(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 0x1);
+
+	/* Setup the CSTORM status block. */
+	section = ((uint64_t)mapping) + offsetof(struct host_status_block,
+	    c_status_block);
+	sb->c_status_block.status_block_id = sb_id;
+
+	/* Write the status block address to CSTORM. Order is important! */
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
+	    U64_HI(section));
+	REG_WR8(sc, BAR_CSTORM_INTMEM + FP_CSB_FUNC_OFF +
+	    CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
+
+	for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
+		REG_WR16(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 0x1);
+
+	/* Enable interrupts. */
+	bxe_ack_sb(sc, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+}
+
+/*
+ * Clears the default status block.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_zero_def_sb(struct bxe_softc *sc)
+{
+	int func;
+
+	func = BP_FUNC(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR),
+	    "%s(): Clearing default status block on function %d.\n",
+	    __FUNCTION__, func);
+
+	/* Fill the STORM's copy of the default status block with 0. */
+	bxe_init_fill(sc, TSEM_REG_FAST_MEMORY +
+	    TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+	    sizeof(struct tstorm_def_status_block) / 4);
+	bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
+	    CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
+	    sizeof(struct cstorm_def_status_block_u) / 4);
+	bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
+	    CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
+	    sizeof(struct cstorm_def_status_block_c) / 4);
+	bxe_init_fill(sc, XSEM_REG_FAST_MEMORY +
+	    XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+	    sizeof(struct xstorm_def_status_block) / 4);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+}
+
+/*
+ * Initialize default status block.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_init_def_sb(struct bxe_softc *sc, struct host_def_status_block *def_sb,
+    bus_addr_t mapping, int sb_id)
+{
+	uint64_t section;
+	int func, index, port, reg_offset, val;
+
+	port = BP_PORT(sc);
+	func = BP_FUNC(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR),
+	   "%s(): Initializing default status block on port %d, function %d.\n",
+	   __FUNCTION__, port, func);
+
+	/* Setup the default status block (DSB). */
+	section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
+	    atten_status_block);
+	def_sb->atten_status_block.status_block_id = sb_id;
+	sc->attn_state = 0;
+	sc->def_att_idx = 0;
+
+	/*
+	 * Read routing configuration for attn signal
+	 * output of groups. Currently, only groups
+	 * 0 through 3 are wired.
+	 */
+	reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
+
+	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
+		sc->attn_group[index].sig[0] = REG_RD(sc, reg_offset +
+		    0x10 * index);
+		sc->attn_group[index].sig[1] = REG_RD(sc, reg_offset +
+		    0x10 * index + 0x4);
+		sc->attn_group[index].sig[2] = REG_RD(sc, reg_offset +
+		    0x10 * index + 0x8);
+		sc->attn_group[index].sig[3] = REG_RD(sc, reg_offset +
+		    0x10 * index + 0xc);
+
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
+		    BXE_VERBOSE_INTR),
+		    "%s(): attn_group[%d] = 0x%08X 0x%08X 0x%08x 0X%08x\n",
+		    __FUNCTION__, index, sc->attn_group[index].sig[0],
+		    sc->attn_group[index].sig[1], sc->attn_group[index].sig[2],
+		    sc->attn_group[index].sig[3]);
+	}
+
+	reg_offset = port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
+
+	REG_WR(sc, reg_offset, U64_LO(section));
+	REG_WR(sc, reg_offset + 4, U64_HI(section));
+
+	reg_offset = port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0;
+
+	val = REG_RD(sc, reg_offset);
+	val |= sb_id;
+	REG_WR(sc, reg_offset, val);
+
+	/* USTORM */
+	section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
+	    u_def_status_block);
+	def_sb->u_def_status_block.status_block_id = sb_id;
+	sc->def_u_idx = 0;
+
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section));
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4), U64_HI(section));
+	REG_WR8(sc, BAR_CSTORM_INTMEM + DEF_USB_FUNC_OFF +
+	    CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
+
+	for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
+		REG_WR16(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
+
+	/* CSTORM */
+	section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
+	    c_def_status_block);
+	def_sb->c_def_status_block.status_block_id = sb_id;
+	sc->def_c_idx = 0;
+
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
+	REG_WR(sc, BAR_CSTORM_INTMEM +
+	    ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4), U64_HI(section));
+	REG_WR8(sc, BAR_CSTORM_INTMEM + DEF_CSB_FUNC_OFF +
+	    CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
+
+	for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
+		REG_WR16(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
+
+	/* TSTORM */
+	section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
+	    t_def_status_block);
+	def_sb->t_def_status_block.status_block_id = sb_id;
+	sc->def_t_idx = 0;
+
+	REG_WR(sc, BAR_TSTORM_INTMEM +
+	    TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
+	REG_WR(sc, BAR_TSTORM_INTMEM +
+	    ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section));
+	REG_WR8(sc, BAR_TSTORM_INTMEM + DEF_TSB_FUNC_OFF +
+	    TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
+
+	for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
+		REG_WR16(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+
+	/* XSTORM */
+	section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
+	    x_def_status_block);
+	def_sb->x_def_status_block.status_block_id = sb_id;
+	sc->def_x_idx = 0;
+
+	REG_WR(sc, BAR_XSTORM_INTMEM +
+	    XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
+	REG_WR(sc, BAR_XSTORM_INTMEM +
+	    ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section));
+	REG_WR8(sc, BAR_XSTORM_INTMEM + DEF_XSB_FUNC_OFF +
+	    XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
+
+	for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
+		REG_WR16(sc, BAR_XSTORM_INTMEM +
+		    XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+
+	sc->stats_pending = 0;
+	sc->set_mac_pending = 0;
+
+	bxe_ack_sb(sc, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
+}
+
+/*
+ * Update interrupt coalescing parameters.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_update_coalesce(struct bxe_softc *sc)
+{
+	int i, port, sb_id;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	port = BP_PORT(sc);
+	/* Cycle through each fastpath queue and set the coalescing values. */
+	for (i = 0; i < sc->num_queues; i++) {
+		sb_id = sc->fp[i].sb_id;
+
+		/* Receive interrupt coalescing is done on USTORM. */
+		REG_WR8(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
+		    U_SB_ETH_RX_CQ_INDEX), sc->rx_ticks / (BXE_BTR * 4));
+
+		REG_WR16(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
+		    U_SB_ETH_RX_CQ_INDEX),
+		    (sc->rx_ticks / (BXE_BTR * 4)) ? 0 : 1);
+
+		/* Transmit interrupt coalescing is done on CSTORM. */
+		REG_WR8(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
+		    C_SB_ETH_TX_CQ_INDEX), sc->tx_ticks / (BXE_BTR * 4));
+		REG_WR16(sc, BAR_CSTORM_INTMEM +
+		    CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
+		    C_SB_ETH_TX_CQ_INDEX),
+		    (sc->tx_ticks / (BXE_BTR * 4)) ? 0 : 1);
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Free memory buffers from the TPA pool.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_free_tpa_pool(struct bxe_fastpath *fp, int last)
+{
+	struct bxe_softc *sc;
+	int j;
+
+	sc = fp->sc;
+#ifdef BXE_DEBUG
+	int tpa_pool_max;
+
+	tpa_pool_max = CHIP_IS_E1H(sc) ? ETH_MAX_AGGREGATION_QUEUES_E1H :
+	    ETH_MAX_AGGREGATION_QUEUES_E1;
+	DBRUNIF((last > tpa_pool_max), DBPRINT(sc, BXE_FATAL,
+	    "%s(): Index value out of range (%d > %d)!\n", __FUNCTION__, last,
+	    tpa_pool_max));
+#endif
+
+	if (!(TPA_ENABLED(sc)))
+		return;
+
+	for (j = 0; j < last; j++) {
+		if (fp->rx_mbuf_tag) {
+			if (fp->tpa_mbuf_map[j] != NULL) {
+				bus_dmamap_sync(fp->rx_mbuf_tag,
+				    fp->tpa_mbuf_map[j], BUS_DMASYNC_POSTREAD);
+				bus_dmamap_unload(fp->rx_mbuf_tag,
+				    fp->tpa_mbuf_map[j]);
+			}
+
+			if (fp->tpa_mbuf_ptr[j] != NULL) {
+				m_freem(fp->tpa_mbuf_ptr[j]);
+				DBRUN(fp->tpa_mbuf_alloc--);
+				fp->tpa_mbuf_ptr[j] = NULL;
+			} else {
+				DBPRINT(sc, BXE_FATAL,
+				    "%s(): TPA bin %d empty on free!\n",
+				    __FUNCTION__, j);
+			}
+		}
+	}
+}
+
+/*
+ * Free an entry in the receive scatter gather list.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_free_rx_sge(struct bxe_softc *sc, struct bxe_fastpath *fp, uint16_t index)
+{
+	struct eth_rx_sge *sge;
+
+	sge = &fp->rx_sge_chain[RX_SGE_PAGE(index)][RX_SGE_IDX(index)];
+	/* Skip "next page" elements */
+	if (!sge)
+		return;
+
+	if (fp->rx_sge_buf_tag) {
+		if (fp->rx_sge_buf_map[index]) {
+			bus_dmamap_sync(fp->rx_sge_buf_tag,
+			    fp->rx_sge_buf_map[index], BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(fp->rx_sge_buf_tag,
+			    fp->rx_sge_buf_map[index]);
+		}
+
+		if (fp->rx_sge_buf_ptr[index]) {
+			DBRUN(fp->sge_mbuf_alloc--);
+			m_freem(fp->rx_sge_buf_ptr[index]);
+			fp->rx_sge_buf_ptr[index] = NULL;
+		}
+
+		sge->addr_hi = sge->addr_lo = 0;
+	}
+}
+
+/*
+ * Free a range of scatter gather elements from the ring.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_free_rx_sge_range(struct bxe_softc *sc, struct bxe_fastpath *fp, int last)
+{
+	int i;
+
+	for (i = 0; i < last; i++)
+		bxe_free_rx_sge(sc, fp, i);
+}
+
+/*
+ * Allocate an mbuf of the specified size for the caller.
+ *
+ * Returns:
+ *   NULL on failure or an mbuf pointer on success.
+ */
+static struct mbuf*
+bxe_alloc_mbuf(struct bxe_fastpath *fp, int size)
+{
+	struct bxe_softc *sc;
+	struct mbuf *m_new;
+
+	sc = fp->sc;
+	DBENTER(BXE_INSANE);
+
+#ifdef BXE_DEBUG
+	/* Simulate an mbuf allocation failure. */
+	if (DB_RANDOMTRUE(bxe_debug_mbuf_allocation_failure)) {
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Simulated mbuf allocation failure!\n", __FUNCTION__);
+		fp->mbuf_alloc_failed++;
+		sc->debug_mbuf_sim_alloc_failed++;
+		m_new = NULL;
+		goto bxe_alloc_mbuf_exit;
+	}
+#endif
+
+	/* Allocate a new mbuf with memory attached. */
+	if (size <= MCLBYTES)
+		m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
+	else
+		m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, size);
+
+	/* Check whether the allocation succeeded and handle a failure. */
+   	if (__predict_false(m_new == NULL)) {
+		DBPRINT(sc, BXE_WARN, "%s(): mbuf allocation failure!\n",
+		    __FUNCTION__);
+		DBRUN(fp->mbuf_alloc_failed++);
+	    goto bxe_alloc_mbuf_exit;
+   	}
+
+	/* Do a little extra error checking when debugging. */
+	DBRUN(M_ASSERTPKTHDR(m_new));
+
+	/* Initialize the mbuf buffer length. */
+	m_new->m_pkthdr.len = m_new->m_len = size;
+	DBRUN(sc->debug_memory_allocated += size);
+
+bxe_alloc_mbuf_exit:
+	return (m_new);
+}
+
+/*
+ * Map an mbuf into non-paged memory for the caller.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ *
+ * Side-effects:
+ *   The mbuf passed will be released if a mapping failure occurs.
+ *   The segment mapping will be udpated if the mapping is successful.
+ */
+static int
+bxe_map_mbuf(struct bxe_fastpath *fp, struct mbuf *m, bus_dma_tag_t tag,
+    bus_dmamap_t map, bus_dma_segment_t *seg)
+{
+	struct bxe_softc *sc;
+	bus_dma_segment_t segs[4];
+	int nsegs, rc;
+
+	sc = fp->sc;
+	rc = 0;
+
+	DBENTER(BXE_INSANE);
+
+#ifdef BXE_DEBUG
+	/* Simulate an mbuf mapping failure. */
+	if (DB_RANDOMTRUE(bxe_debug_dma_map_addr_failure)) {
+		DBPRINT(sc, BXE_WARN, "%s(): Simulated mbuf mapping failure!\n",
+		    __FUNCTION__);
+		sc->debug_mbuf_sim_map_failed++;
+		fp->mbuf_alloc_failed++;
+		DBRUN(sc->debug_memory_allocated -= m->m_len);
+		m_freem(m);
+		rc = EINVAL;
+		goto bxe_map_mbuf_exit;
+	}
+#endif
+
+	/* Map the buffer memory into non-paged memory. */
+	rc = bus_dmamap_load_mbuf_sg(tag, map, m, segs, &nsegs, BUS_DMA_NOWAIT);
+
+	/* Handle any mapping errors. */
+	if (__predict_false(rc)) {
+		DBPRINT(sc, BXE_WARN, "%s(): mbuf mapping failure (%d)!\n",
+		    __FUNCTION__, rc);
+		m_freem(m);
+		DBRUN(fp->mbuf_alloc_failed++);
+		goto bxe_map_mbuf_exit;
+	}
+
+	/* All mubfs must map to a single segment. */
+	KASSERT(nsegs == 1, ("%s(): Too many segments (%d) returned!",
+	    __FUNCTION__, nsegs));
+
+	/* Save the DMA mapping tag for this memory buffer. */
+	*seg = segs[0];
+
+bxe_map_mbuf_exit:
+	return (rc);
+}
+
+/*
+ * Allocate an mbuf for the TPA pool.
+ *
+ * Returns:
+ *   NULL on failure or an mbuf pointer on success.
+ */
+static struct mbuf *
+bxe_alloc_tpa_mbuf(struct bxe_fastpath *fp, int index, int size)
+{
+	bus_dma_segment_t seg;
+	struct mbuf *m;
+	int rc;
+
+	/* Allocate the new mbuf. */
+	if ((m = bxe_alloc_mbuf(fp, size)) == NULL)
+		goto bxe_alloc_tpa_mbuf_exit;
+
+	/* Map the mbuf into non-paged pool. */
+	rc = bxe_map_mbuf(fp, m, fp->rx_mbuf_tag, fp->tpa_mbuf_map[index],
+	    &seg);
+
+	if (rc) {
+		m = NULL;
+		goto bxe_alloc_tpa_mbuf_exit;
+	}
+
+	DBRUN(fp->tpa_mbuf_alloc++);
+
+	/* Save the mapping info for the mbuf. */
+	fp->tpa_mbuf_segs[index] = seg;
+
+bxe_alloc_tpa_mbuf_exit:
+	return (m);
+}
+
+/*
+ * Allocate a receive scatter gather entry
+ *
+ * Returns:
+ *   0 = Success, != Failure.
+ */
+static int
+bxe_alloc_rx_sge(struct bxe_softc *sc, struct bxe_fastpath *fp,
+    uint16_t ring_prod)
+{
+	struct eth_rx_sge *sge;
+	bus_dma_segment_t seg;
+	struct mbuf *m;
+	int rc;
+
+	sge = &fp->rx_sge_chain[RX_SGE_PAGE(ring_prod)][RX_SGE_IDX(ring_prod)];
+	rc = 0;
+
+	/* Allocate a new mbuf. */
+	if ((m = bxe_alloc_mbuf(fp, PAGE_SIZE)) == NULL) {
+		rc = ENOMEM;
+		goto bxe_alloc_rx_sge_exit;
+	}
+
+	/* Map the mbuf into non-paged pool. */
+	rc = bxe_map_mbuf(fp, m, fp->rx_sge_buf_tag,
+		fp->rx_sge_buf_map[ring_prod], &seg);
+
+	if (rc)
+		goto bxe_alloc_rx_sge_exit;
+
+	DBRUN(fp->sge_mbuf_alloc++);
+
+	/* Add the SGE buffer to the SGE ring. */
+	sge->addr_hi = htole32(U64_HI(seg.ds_addr));
+	sge->addr_lo = htole32(U64_LO(seg.ds_addr));
+	fp->rx_sge_buf_ptr[ring_prod] = m;
+
+bxe_alloc_rx_sge_exit:
+	return (rc);
+}
+
+/*
+ * Initialize the receive rings.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static void
+bxe_init_rx_chains(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	struct eth_rx_sge *sge;
+	struct eth_rx_bd *rx_bd;
+	struct eth_rx_cqe_next_page *nextpg;
+	uint16_t ring_prod, cqe_ring_prod;
+	int func, i, j, max_agg_queues;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	func = BP_FUNC(sc);
+	max_agg_queues = CHIP_IS_E1(sc) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
+	    ETH_MAX_AGGREGATION_QUEUES_E1H;
+
+	sc->rx_buf_size = sc->mbuf_alloc_size;
+
+	/* Allocate memory for the TPA pool. */
+	if (TPA_ENABLED(sc)) {
+		DBPRINT(sc, (BXE_INFO_LOAD | BXE_INFO_RESET),
+		    "%s(): mtu = %d, rx_buf_size = %d\n", __FUNCTION__,
+		    (int)sc->bxe_ifp->if_mtu, sc->rx_buf_size);
+
+		for (i = 0; i < sc->num_queues; i++) {
+			fp = &sc->fp[i];
+			DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+			    "%s(): Initializing fp[%d] TPA pool.\n",
+			    __FUNCTION__, i);
+
+			for (j = 0; j < max_agg_queues; j++) {
+				DBPRINT(sc,
+				    (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+				    "%s(): Initializing fp[%d] TPA pool[%d].\n",
+				    __FUNCTION__, i, j);
+
+				fp->disable_tpa = 0;
+				fp->tpa_mbuf_ptr[j] = bxe_alloc_tpa_mbuf(fp, j,
+				    sc->mbuf_alloc_size);
+
+				if (fp->tpa_mbuf_ptr[j] == NULL) {
+					BXE_PRINTF(
+		"%s(%d): Failed to allocate TPA pool mbuf for fp[%d]! "
+		"Disabling TPA on this queue!\n",
+					    __FILE__, __LINE__, i);
+					bxe_free_tpa_pool(fp, j);
+					fp->disable_tpa = 1;
+					break;
+				}
+				fp->tpa_state[j] = BXE_TPA_STATE_STOP;
+			}
+		}
+	}
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+		    "%s(): Initializing fp[%d] RX chain.\n", __FUNCTION__, i);
+
+		fp->rx_bd_cons = 0;
+
+		/* Pointer to status block's completion queue consumer index. */
+		fp->rx_cons_sb = &fp->status_block->
+		    u_status_block.index_values[HC_INDEX_U_ETH_RX_CQ_CONS];
+
+		/* Pointer to status block's receive consumer index. */
+		fp->rx_bd_cons_sb = &fp->status_block->
+		    u_status_block.index_values[HC_INDEX_U_ETH_RX_BD_CONS];
+
+		if (TPA_ENABLED(sc)) {
+			DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+			    "%s(): Linking fp[%d] SGE rings.\n", __FUNCTION__,
+			    i);
+
+			/* Link the SGE Ring Pages to form SGE chain */
+			for (j = 0; j < NUM_RX_SGE_PAGES; j++) {
+				DBPRINT(sc,
+				    (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+				    "%s(): Linking fp[%d] SGE ring[%d].\n",
+				    __FUNCTION__, i, j);
+
+				sge = &fp->rx_sge_chain[j][MAX_RX_SGE_CNT];
+				sge->addr_hi =
+				    htole32(U64_HI(fp->rx_sge_chain_paddr[(j + 1) %	NUM_RX_SGE_PAGES]));
+				sge->addr_lo =
+				    htole32(U64_LO(fp->rx_sge_chain_paddr[(j + 1) %	NUM_RX_SGE_PAGES]));
+			}
+
+			bxe_init_sge_ring_bit_mask(fp);
+		}
+
+		DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+		    "%s(): Linking fp[%d] RX chain pages.\n", __FUNCTION__, i);
+
+		/* Link the pages to form the RX BD Chain. */
+		for (j = 0; j < NUM_RX_PAGES; j++) {
+			rx_bd = &fp->rx_bd_chain[j][USABLE_RX_BD_PER_PAGE];
+
+			DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+			    "%s(): Linking fp[%d] RX BD chain page[%d].\n",
+			    __FUNCTION__, i, j);
+
+			rx_bd->addr_hi =
+			    htole32(U64_HI(fp->rx_bd_chain_paddr[(j + 1) % NUM_RX_PAGES]));
+			rx_bd->addr_lo =
+			    htole32(U64_LO(fp->rx_bd_chain_paddr[(j + 1) % NUM_RX_PAGES]));
+		}
+
+		DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+		    "%s(): Linking fp[%d] RX completion chain pages.\n",
+		    __FUNCTION__, i);
+
+		/* Link the pages to form the RX Completion Queue.*/
+		for (j = 0; j < NUM_RCQ_PAGES; j++) {
+			nextpg = (struct eth_rx_cqe_next_page *)
+			    &fp->rx_comp_chain[j][USABLE_RCQ_ENTRIES_PER_PAGE];
+
+			DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+	"%s(): Linking fp[%d] RX completion chain page[%d].\n",
+			     __FUNCTION__, i, j);
+
+			nextpg->addr_hi =
+			    htole32(U64_HI(fp->rx_comp_chain_paddr[(j + 1) % NUM_RCQ_PAGES]));
+			nextpg->addr_lo =
+			    htole32(U64_LO(fp->rx_comp_chain_paddr[(j + 1) % NUM_RCQ_PAGES]));
+		}
+
+		if (TPA_ENABLED(sc)) {
+			/* Allocate SGEs and initialize the ring elements. */
+			ring_prod = 0;
+
+			while (ring_prod < sc->rx_ring_size) {
+				if (bxe_alloc_rx_sge(sc, fp, ring_prod) != 0) {
+					BXE_PRINTF(
+	"%s(%d): Memory allocation failure! Disabling TPA for fp[%d].\n",
+					    __FILE__, __LINE__, i);
+
+					/* Cleanup already allocated elements */
+					bxe_free_rx_sge_range(sc, fp,
+					    ring_prod);
+					fp->disable_tpa = 1;
+					ring_prod = 0;
+					break;
+				}
+				ring_prod = NEXT_SGE_IDX(ring_prod);
+			}
+
+			fp->rx_sge_prod = ring_prod;
+		}
+
+		/*
+		 * Allocate buffers for all the RX BDs in RX BD Chain.
+		 * Add completion queue entries at the same time.
+		 */
+		fp->rx_comp_cons = ring_prod = cqe_ring_prod = 0;
+		DBRUN(fp->free_rx_bd = USABLE_RX_BD);
+
+		while (ring_prod < sc->rx_ring_size) {
+			if (bxe_get_buf(fp, NULL, ring_prod)) {
+				BXE_PRINTF(
+	"%s(%d): Memory allocation failure! Cannot fill fp[%d] RX chain.\n",
+				    __FILE__, __LINE__, i);
+				break;
+			}
+			ring_prod = NEXT_RX_BD(ring_prod);
+			cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
+		}
+
+		/* Update the driver's copy of the producer indices. */
+		fp->rx_bd_prod = ring_prod;
+
+		fp->rx_comp_prod = cqe_ring_prod;
+		/*
+		 * fp->rx_comp_prod =
+		 *     (uint16_t)min(NUM_RCQ_PAGES*TOTAL_RCQ_ENTRIES_PER_PAGE,
+		 *     cqe_ring_prod);
+		 */
+
+		DBRUN(fp->rx_pkts = fp->rx_calls = 0);
+
+		/* Prepare the CQ buffers for DMA access. */
+		for (j = 0; j < NUM_RX_PAGES; j++)
+			bus_dmamap_sync(fp->rx_bd_chain_tag,
+			    fp->rx_bd_chain_map[j], BUS_DMASYNC_PREREAD |
+			    BUS_DMASYNC_PREWRITE);
+
+		for (j = 0; j < NUM_RCQ_PAGES; j++)
+			bus_dmamap_sync(fp->rx_comp_chain_tag,
+			    fp->rx_comp_chain_map[j], BUS_DMASYNC_PREREAD |
+			    BUS_DMASYNC_PREWRITE);
+
+		/*
+		 * Tell the controller that we have rx_bd's and CQE's available.
+		 * Warning! this will generate an interrupt (to the TSTORM).
+		 * This must only be done when the controller is initialized.
+		 */
+		bxe_update_rx_prod(sc, fp, ring_prod, fp->rx_comp_prod,
+		    fp->rx_sge_prod);
+
+		if (i != 0)
+			continue;
+
+		REG_WR(sc, BAR_USTORM_INTMEM +
+		    USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
+		    U64_LO(fp->rx_comp_chain_paddr[0]));
+		REG_WR(sc, BAR_USTORM_INTMEM +
+		    USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
+		    U64_HI(fp->rx_comp_chain_paddr[0]));
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize the transmit chain.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_tx_chains(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	struct eth_tx_next_bd *tx_bd;
+	int i, j;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+		    "%s(): Linking fp[%d] TX chain pages.\n", __FUNCTION__, i);
+
+		for (j = 0; j < NUM_TX_PAGES; j++) {
+			tx_bd =
+			    &fp->tx_bd_chain[j][USABLE_TX_BD_PER_PAGE].next_bd;
+
+			DBPRINT(sc, (BXE_INSANE_LOAD | BXE_INSANE_RESET),
+			    "%s(): Linking fp[%d] TX BD chain page[%d].\n",
+			    __FUNCTION__, i, j);
+
+			tx_bd->addr_hi =
+			    htole32(U64_HI(fp->tx_bd_chain_paddr[(j + 1) %
+			    NUM_TX_PAGES]));
+			tx_bd->addr_lo =
+			    htole32(U64_LO(fp->tx_bd_chain_paddr[(j + 1) %
+			    NUM_TX_PAGES]));
+		}
+
+		fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE;
+		fp->tx_db.data.zero_fill1 = 0;
+		fp->tx_db.data.prod = 0;
+
+		fp->tx_pkt_prod = 0;
+		fp->tx_pkt_cons = 0;
+		fp->tx_bd_prod  = 0;
+		fp->tx_bd_cons  = 0;
+		fp->used_tx_bd  = 0;
+
+		/*
+		 * Copy of TX BD Chain completion queue Consumer Index
+		 * from the Status Block.
+		 */
+		fp->tx_cons_sb =
+		    &fp->status_block->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX];
+
+		DBRUN(fp->tx_pkts = 0);
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Free memory and clear the RX data structures.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_free_rx_chains(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	int i, j, max_agg_queues;
+
+	DBENTER(BXE_VERBOSE_RESET);
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		if (fp->rx_mbuf_tag) {
+			/* Free any mbufs still in the RX mbuf chain. */
+			for (j = 0; j < TOTAL_RX_BD; j++) {
+				if (fp->rx_mbuf_ptr[j] != NULL) {
+					if (fp->rx_mbuf_map[j] != NULL)
+						bus_dmamap_sync(fp->rx_mbuf_tag,
+						    fp->rx_mbuf_map[j],
+						    BUS_DMASYNC_POSTREAD);
+					DBRUN(fp->rx_mbuf_alloc--);
+					m_freem(fp->rx_mbuf_ptr[j]);
+					fp->rx_mbuf_ptr[j] = NULL;
+				}
+			}
+
+			/* Clear each RX chain page. */
+			for (j = 0; j < NUM_RX_PAGES; j++) {
+				if (fp->rx_bd_chain[j] != NULL)
+					bzero((char *)fp->rx_bd_chain[j],
+					    BXE_RX_CHAIN_PAGE_SZ);
+			}
+
+			/* Clear each RX completion queue page. */
+			for (j = 0; j < NUM_RCQ_PAGES; j++) {
+				if (fp->rx_comp_chain[j] != NULL)
+					bzero((char *)fp->rx_comp_chain[j],
+					    BXE_RX_CHAIN_PAGE_SZ);
+			}
+
+			if (TPA_ENABLED(sc)) {
+				max_agg_queues = CHIP_IS_E1H(sc) ?
+				    ETH_MAX_AGGREGATION_QUEUES_E1H :
+				    ETH_MAX_AGGREGATION_QUEUES_E1;
+
+				/* Free the TPA Pool mbufs. */
+				bxe_free_tpa_pool(fp, max_agg_queues);
+
+				/*
+				 * Free any mbufs still in the RX SGE
+				 * buf chain.
+				 */
+				bxe_free_rx_sge_range(fp->sc, fp, MAX_RX_SGE);
+
+				/* Clear each RX SGE page. */
+				for (j = 0; j < NUM_RX_SGE_PAGES; j++) {
+					if (fp->rx_sge_chain[j] != NULL)
+						bzero(
+						    (char *)fp->rx_sge_chain[j],
+						    BXE_RX_CHAIN_PAGE_SZ);
+				}
+			}
+		}
+
+		/* Check if we lost any mbufs in the process. */
+		DBRUNIF((fp->rx_mbuf_alloc), DBPRINT(sc, BXE_FATAL,
+		    "%s(): Memory leak! Lost %d mbufs from fp[%d] RX chain!\n",
+		    __FUNCTION__, fp->rx_mbuf_alloc, fp->index));
+	}
+
+	DBEXIT(BXE_VERBOSE_RESET);
+}
+
+/*
+ * Free memory and clear the TX data structures.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_free_tx_chains(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	int i, j;
+
+	DBENTER(BXE_VERBOSE_RESET);
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		if (fp->tx_mbuf_tag) {
+			/*
+			 * Unmap, unload, and free any mbufs in the
+			 * TX mbuf chain.
+			 */
+			for (j = 0; j < TOTAL_TX_BD; j++) {
+				if (fp->tx_mbuf_ptr[j] != NULL) {
+					if (fp->tx_mbuf_map[j] != NULL)
+						bus_dmamap_sync(fp->tx_mbuf_tag,
+						    fp->tx_mbuf_map[j],
+						    BUS_DMASYNC_POSTWRITE);
+					DBRUN(fp->tx_mbuf_alloc--);
+					m_freem(fp->tx_mbuf_ptr[j]);
+					fp->tx_mbuf_ptr[j] = NULL;
+				}
+			}
+
+			/* Clear each TX chain page. */
+			for (j = 0; j < NUM_TX_PAGES; j++) {
+				if (fp->tx_bd_chain[j] != NULL)
+					bzero((char *)fp->tx_bd_chain[j],
+					    BXE_TX_CHAIN_PAGE_SZ);
+			}
+
+			/* Check if we lost any mbufs in the process. */
+			DBRUNIF((fp->tx_mbuf_alloc), DBPRINT(sc, BXE_FATAL,
+		"%s(): Memory leak! Lost %d mbufs from fp[%d] TX chain!\n",
+			    __FUNCTION__, fp->tx_mbuf_alloc, fp->index));
+		}
+	}
+
+	DBEXIT(BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize the slowpath ring.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_sp_ring(struct bxe_softc *sc)
+{
+	int func;
+
+	func = BP_FUNC(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	bzero((char *)sc->slowpath, BXE_SLOWPATH_SZ);
+
+	/* When the producer equals the consumer the chain is empty. */
+	sc->spq_left = MAX_SPQ_PENDING;
+	sc->spq_prod_idx = 0;
+	sc->dsb_sp_prod = BXE_SP_DSB_INDEX;
+	sc->spq_prod_bd = sc->spq;
+	sc->spq_last_bd = sc->spq_prod_bd + MAX_SP_DESC_CNT;
+
+	/* Tell the controller the address of the slowpath ring. */
+	REG_WR(sc, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
+	    U64_LO(sc->spq_paddr));
+	REG_WR(sc, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
+	    U64_HI(sc->spq_paddr));
+	REG_WR(sc, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
+	    sc->spq_prod_idx);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize STORM processor context.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_context(struct bxe_softc *sc)
+{
+	struct eth_context *context;
+	struct bxe_fastpath *fp;
+	uint8_t sb_id;
+	uint8_t cl_id;
+	int i;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	for (i = 0; i < sc->num_queues; i++) {
+		context = BXE_SP(sc, context[i].eth);
+		fp = &sc->fp[i];
+		sb_id = fp->sb_id;
+		cl_id = fp->cl_id;
+
+		/* Update the USTORM context. */
+		context->ustorm_st_context.common.sb_index_numbers =
+		    BXE_RX_SB_INDEX_NUM;
+		context->ustorm_st_context.common.clientId = cl_id;
+		context->ustorm_st_context.common.status_block_id = sb_id;
+		/* Enable packet alignment/pad and statistics. */
+		context->ustorm_st_context.common.flags =
+		    USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
+		if (bxe_stats_enable)
+			context->ustorm_st_context.common.flags |=
+		    USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
+		context->ustorm_st_context.common.statistics_counter_id=cl_id;
+		/*
+		 * Set packet alignment boundary.
+		 * (Must be >= 4 (i.e. 16 bytes).)
+		 */
+		context->ustorm_st_context.common.mc_alignment_log_size = 8;
+		/* Set the size of the receive buffers. */
+		context->ustorm_st_context.common.bd_buff_size =
+		    sc->rx_buf_size;
+
+		/* Set the address of the receive chain base page. */
+		context->ustorm_st_context.common.bd_page_base_hi =
+		    U64_HI(fp->rx_bd_chain_paddr[0]);
+		context->ustorm_st_context.common.bd_page_base_lo =
+		    U64_LO(fp->rx_bd_chain_paddr[0]);
+		if (TPA_ENABLED(sc) && !(fp->disable_tpa)) {
+			/* Enable TPA and SGE chain support. */
+			context->ustorm_st_context.common.flags |=
+			    USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
+			/* Set the size of the SGE buffer. */
+			context->ustorm_st_context.common.sge_buff_size =
+			    (uint16_t) (PAGES_PER_SGE * BCM_PAGE_SIZE);
+			/* Set the address of the SGE chain base page. */
+			context->ustorm_st_context.common.sge_page_base_hi =
+			    U64_HI(fp->rx_sge_chain_paddr[0]);
+			context->ustorm_st_context.common.sge_page_base_lo =
+			    U64_LO(fp->rx_sge_chain_paddr[0]);
+
+			context->ustorm_st_context.common.max_sges_for_packet =
+			    SGE_PAGE_ALIGN(sc->bxe_ifp->if_mtu) >>
+			    SGE_PAGE_SHIFT;
+			context->ustorm_st_context.common.max_sges_for_packet =
+			    ((context->ustorm_st_context.common.
+			    max_sges_for_packet + PAGES_PER_SGE - 1) &
+			    (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
+		}
+
+		/* Update USTORM context. */
+		context->ustorm_ag_context.cdu_usage =
+		    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, i),
+		    CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
+
+		/* Update XSTORM context. */
+		context->xstorm_ag_context.cdu_reserved =
+		    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, i),
+		    CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
+
+		/* Set the address of the transmit chain base page. */
+		context->xstorm_st_context.tx_bd_page_base_hi =
+		    U64_HI(fp->tx_bd_chain_paddr[0]);
+		context->xstorm_st_context.tx_bd_page_base_lo =
+		    U64_LO(fp->tx_bd_chain_paddr[0]);
+
+		/* Enable XSTORM statistics. */
+		context->xstorm_st_context.statistics_data = (cl_id |
+		    XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
+
+		/* Update CSTORM status block configuration. */
+		context->cstorm_st_context.sb_index_number =
+		    C_SB_ETH_TX_CQ_INDEX;
+		context->cstorm_st_context.status_block_id = sb_id;
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize indirection table.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_init_ind_table(struct bxe_softc *sc)
+{
+	int func, i;
+
+	func = BP_FUNC(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	if (sc->multi_mode == ETH_RSS_MODE_DISABLED)
+		return;
+
+	/* Initialize the indirection table. */
+	for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
+		REG_WR8(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
+		    sc->fp->cl_id + (i % sc->num_queues));
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Set client configuration.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_set_client_config(struct bxe_softc *sc)
+{
+	struct tstorm_eth_client_config tstorm_client = {0};
+	int i, port;
+
+	port = BP_PORT(sc);
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	tstorm_client.mtu = sc->bxe_ifp->if_mtu; /* ETHERMTU */
+	tstorm_client.config_flags =
+	    (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
+	    TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
+
+	/* Unconditionally enable VLAN tag stripping. */
+	if (sc->rx_mode) {
+		tstorm_client.config_flags |=
+		    TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
+		DBPRINT(sc, BXE_VERBOSE, "%s(): VLAN tag stripping enabled.\n",
+		    __FUNCTION__);
+	}
+
+	/* Initialize the receive mode for each receive queue. */
+	for (i = 0; i < sc->num_queues; i++) {
+		tstorm_client.statistics_counter_id = sc->fp[i].cl_id;
+
+		REG_WR(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_CLIENT_CONFIG_OFFSET(port, sc->fp[i].cl_id),
+		    ((uint32_t *) &tstorm_client)[0]);
+		REG_WR(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_CLIENT_CONFIG_OFFSET(port, sc->fp[i].cl_id) + 4,
+		    ((uint32_t *) &tstorm_client)[1]);
+	}
+
+	DBEXIT(BXE_VERBOSE_MISC);
+}
+
+/*
+ * Set receive mode.
+ *
+ * Programs the MAC according to the type of unicast/broadcast/multicast
+ * packets it should receive.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_set_storm_rx_mode(struct bxe_softc *sc)
+{
+	struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
+	uint32_t llh_mask;
+	int mode, mask;
+	int func, i , port;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	mode = sc->rx_mode;
+	mask = 1 << BP_L_ID(sc);
+	func = BP_FUNC(sc);
+	port = BP_PORT(sc);
+
+	/* All but management unicast packets should pass to the host as well */
+	llh_mask = NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
+	    NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
+	    NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
+	    NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
+
+	/* Set the individual accept/drop flags based on the receive mode. */
+	switch (mode) {
+	case BXE_RX_MODE_NONE:
+		/* Drop everything. */
+		DBPRINT(sc, BXE_VERBOSE,
+		    "%s(): Setting RX_MODE_NONE for function %d.\n",
+		    __FUNCTION__, func);
+		tstorm_mac_filter.ucast_drop_all = mask;
+		tstorm_mac_filter.mcast_drop_all = mask;
+		tstorm_mac_filter.bcast_drop_all = mask;
+		break;
+	case BXE_RX_MODE_NORMAL:
+		/* Accept all broadcast frames. */
+		DBPRINT(sc, BXE_VERBOSE,
+		    "%s(): Setting RX_MODE_NORMAL for function %d.\n",
+		    __FUNCTION__, func);
+		tstorm_mac_filter.bcast_accept_all = mask;
+		break;
+	case BXE_RX_MODE_ALLMULTI:
+		/* Accept all broadcast and multicast frames. */
+		DBPRINT(sc, BXE_VERBOSE,
+		    "%s(): Setting RX_MODE_ALLMULTI for function %d.\n",
+		    __FUNCTION__, func);
+		tstorm_mac_filter.mcast_accept_all = mask;
+		tstorm_mac_filter.bcast_accept_all = mask;
+		break;
+	case BXE_RX_MODE_PROMISC:
+		/* Accept all frames (promiscuous mode). */
+		DBPRINT(sc, BXE_VERBOSE,
+		    "%s(): Setting RX_MODE_PROMISC for function %d.\n",
+		    __FUNCTION__, func);
+		tstorm_mac_filter.ucast_accept_all = mask;
+		tstorm_mac_filter.mcast_accept_all = mask;
+		tstorm_mac_filter.bcast_accept_all = mask;
+		llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
+		break;
+
+	default:
+		BXE_PRINTF(
+		    "%s(%d): Tried to set unknown receive mode (0x%08X)!\n",
+		    __FILE__, __LINE__, mode);
+	}
+
+	REG_WR(sc, port ? NIG_REG_LLH1_BRB1_DRV_MASK :
+	    NIG_REG_LLH0_BRB1_DRV_MASK, llh_mask);
+
+	/* Write the RX mode filter to the TSTORM. */
+	for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config) / 4; i++)
+		REG_WR(sc, BAR_TSTORM_INTMEM +
+		    TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + (i * 4),
+		    ((uint32_t *) &tstorm_mac_filter)[i]);
+
+	if (mode != BXE_RX_MODE_NONE)
+		bxe_set_client_config(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize common internal resources.  (Applies to both ports and
+ * functions.)
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_init_internal_common(struct bxe_softc *sc)
+{
+	int i;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	/*
+	 * Zero this manually as its initialization is currently not
+	 * handled through block initialization.
+	 */
+	for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
+		REG_WR(sc, BAR_USTORM_INTMEM + USTORM_AGG_DATA_OFFSET + i * 4,
+		    0);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize port specific internal resources.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_init_internal_port(struct bxe_softc *sc)
+{
+	int port = BP_PORT(sc);
+
+	port = BP_PORT(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+	    "%s(): Port %d internal initialization.\n", __FUNCTION__, port);
+
+	/*
+	 * Each SDM timer tick is 4us. Configure host coalescing
+	 * basic timer resolution (BTR) to 12us (3 * 4us).
+	 */
+	REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BXE_BTR);
+	REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BXE_BTR);
+	REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BXE_BTR);
+	REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BXE_BTR);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize function specific internal resources.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_init_internal_func(struct bxe_softc *sc)
+{
+	struct tstorm_eth_function_common_config tstorm_config = {0};
+	struct stats_indication_flags stats_flags = {0};
+	struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
+	struct bxe_fastpath *fp;
+	struct eth_rx_cqe_next_page *nextpg;
+	uint32_t offset, size;
+	uint16_t max_agg_size;
+	uint8_t cl_id;
+	int func, i, j, port;
+
+	port = BP_PORT(sc);
+	func = BP_FUNC(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+	    "%s(): Port %d, function %d internal initialization.\n",
+	    __FUNCTION__, port, func);
+
+	/*
+	 * Configure which fields the controller looks at when
+	 * distributing incoming frames for RSS/multi-queue operation.
+	 */
+	if (sc->num_queues > 1) {
+		tstorm_config.config_flags = MULTI_FLAGS(sc);
+		tstorm_config.rss_result_mask = MULTI_MASK;
+	}
+
+	/* Enable TPA if needed */
+	if (sc->bxe_flags & BXE_TPA_ENABLE_FLAG)
+		tstorm_config.config_flags |=
+		    TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
+
+	if (IS_E1HMF(sc))
+		tstorm_config.config_flags |=
+		    TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
+
+	tstorm_config.leading_client_id = BP_L_ID(sc);
+
+	REG_WR(sc, BAR_TSTORM_INTMEM +
+	    TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
+	    (*(uint32_t *)&tstorm_config));
+
+	/* Don't receive anything until the link is up. */
+	sc->rx_mode = BXE_RX_MODE_NONE;
+	sc->rx_mode_cl_mask = (1 << BP_L_ID(sc));
+	bxe_set_storm_rx_mode(sc);
+
+	for (i = 0; i < sc->num_queues; i++) {
+		cl_id = sc->fp[i].cl_id;
+		/* Reset XSTORM per client statistics. */
+		size = sizeof(struct xstorm_per_client_stats) / 4;
+		offset = BAR_XSTORM_INTMEM +
+		    XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
+		for (j = 0; j < size; j++)
+			REG_WR(sc, offset +(j * 4), 0);
+
+		/* Reset TSTORM per client statistics. */
+		size = sizeof(struct tstorm_per_client_stats) / 4;
+		offset = BAR_TSTORM_INTMEM +
+		    TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
+		for (j = 0; j < size; j++)
+			REG_WR(sc, offset + (j * 4), 0);
+
+		/* Reset USTORM per client statistics. */
+		size = sizeof(struct ustorm_per_client_stats) / 4;
+		offset = BAR_USTORM_INTMEM +
+		    USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
+		for (j = 0; j < size; j++)
+			REG_WR(sc, offset + (j * 4), 0);
+	}
+
+	/* Initialize statistics related context. */
+	stats_flags.collect_eth = 1;
+
+	REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
+	    ((uint32_t *)&stats_flags)[0]);
+	REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
+	    ((uint32_t *)&stats_flags)[1]);
+
+	REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
+	    ((uint32_t *)&stats_flags)[0]);
+	REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
+	    ((uint32_t *)&stats_flags)[1]);
+
+	REG_WR(sc, BAR_USTORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
+	    ((uint32_t *)&stats_flags)[0]);
+	REG_WR(sc, BAR_USTORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
+	    ((uint32_t *)&stats_flags)[1]);
+
+	REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
+	    ((uint32_t *)&stats_flags)[0]);
+	REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
+	    ((uint32_t *)&stats_flags)[1]);
+
+	REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
+	    U64_LO(BXE_SP_MAPPING(sc, fw_stats)));
+	REG_WR(sc, BAR_XSTORM_INTMEM +
+	    XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
+	    U64_HI(BXE_SP_MAPPING(sc, fw_stats)));
+
+	REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
+	    U64_LO(BXE_SP_MAPPING(sc, fw_stats)));
+	REG_WR(sc, BAR_TSTORM_INTMEM +
+	    TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
+	    U64_HI(BXE_SP_MAPPING(sc, fw_stats)));
+
+	REG_WR(sc, BAR_USTORM_INTMEM + USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
+	    U64_LO(BXE_SP_MAPPING(sc, fw_stats)));
+	REG_WR(sc, BAR_USTORM_INTMEM +
+	    USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
+	    U64_HI(BXE_SP_MAPPING(sc, fw_stats)));
+
+	/* Additional initialization for 57711/57711E. */
+	if (CHIP_IS_E1H(sc)) {
+		REG_WR8(sc, BAR_XSTORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
+		    IS_E1HMF(sc));
+		REG_WR8(sc, BAR_TSTORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
+		    IS_E1HMF(sc));
+		REG_WR8(sc, BAR_CSTORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
+		    IS_E1HMF(sc));
+		REG_WR8(sc, BAR_USTORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
+		    IS_E1HMF(sc));
+
+		/* Set the outer VLAN tag. */
+		REG_WR16(sc, BAR_XSTORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
+		    sc->e1hov);
+	}
+
+	/* Init completion queue mapping and TPA aggregation size. */
+	max_agg_size = min((uint32_t)(sc->rx_buf_size + 8 * BCM_PAGE_SIZE *
+	    PAGES_PER_SGE), (uint32_t)0xffff);
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		nextpg = (struct eth_rx_cqe_next_page *)
+		    &fp->rx_comp_chain[i][USABLE_RCQ_ENTRIES_PER_PAGE];
+		/* Program the completion queue address. */
+		REG_WR(sc, BAR_USTORM_INTMEM +
+		    USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
+		    U64_LO(fp->rx_comp_chain_paddr[0]));
+		REG_WR(sc, BAR_USTORM_INTMEM +
+		    USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
+		    U64_HI(fp->rx_comp_chain_paddr[0]));
+
+		/* Next page */
+		REG_WR(sc, BAR_USTORM_INTMEM + USTORM_CQE_PAGE_NEXT_OFFSET(port,
+		    fp->cl_id), nextpg->addr_lo);
+		REG_WR(sc, BAR_USTORM_INTMEM + USTORM_CQE_PAGE_NEXT_OFFSET(port,
+		    fp->cl_id) + 4, nextpg->addr_hi);
+
+		/* Set the maximum TPA aggregation size. */
+		REG_WR16(sc, BAR_USTORM_INTMEM +
+		    USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id), max_agg_size);
+	}
+
+	/* Configure lossless flow control. */
+	if (CHIP_IS_E1H(sc)) {
+		rx_pause.bd_thr_low = 250;
+		rx_pause.cqe_thr_low = 250;
+		rx_pause.cos = 1;
+		rx_pause.sge_thr_low = 0;
+		rx_pause.bd_thr_high = 350;
+		rx_pause.cqe_thr_high = 350;
+		rx_pause.sge_thr_high = 0;
+
+		for (i = 0; i < sc->num_queues; i++) {
+			fp = &sc->fp[i];
+			if (!fp->disable_tpa) {
+				rx_pause.sge_thr_low = 150;
+				rx_pause.sge_thr_high = 250;
+			}
+
+			offset = BAR_USTORM_INTMEM +
+			    USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, fp->cl_id);
+
+			for (j = 0; j <
+			    sizeof(struct ustorm_eth_rx_pause_data_e1h) / 4;
+			    j++)
+				REG_WR(sc, offset + (j * 4),
+				    ((uint32_t *)&rx_pause)[j]);
+		}
+	}
+
+	memset(&(sc->cmng), 0, sizeof(struct cmng_struct_per_port));
+	if (IS_E1HMF(sc)) {
+		/*
+		 * During init there is no active link.
+		 * Until link is up, assume link rate @ 10Gbps
+		 */
+		bxe_read_mf_cfg(sc);
+
+		if (!sc->vn_wsum)
+			DBPRINT(sc, BXE_VERBOSE_MISC,
+			    "%s(): All MIN values are zeroes, "
+			    "fairness will be disabled.\n", __FUNCTION__);
+	}
+
+	switch (sc->multi_mode) {
+	case ETH_RSS_MODE_DISABLED:
+	case ETH_RSS_MODE_REGULAR:
+		break;
+	default:
+		break;
+	}
+
+	/* Store it to internal memory */
+	if (sc->port.pmf) {
+		for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
+			REG_WR(sc, BAR_XSTORM_INTMEM +
+			    XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
+			    ((uint32_t *)(&sc->cmng))[i]);
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Initialize internal resources.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_init_internal(struct bxe_softc *sc, uint32_t load_code)
+{
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	switch (load_code) {
+	case FW_MSG_CODE_DRV_LOAD_COMMON:
+		bxe_init_internal_common(sc);
+		/* FALLTHROUGH */
+
+	case FW_MSG_CODE_DRV_LOAD_PORT:
+		bxe_init_internal_port(sc);
+		/* FALLTHROUGH */
+
+	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
+		bxe_init_internal_func(sc);
+		break;
+
+	default:
+		BXE_PRINTF(
+		    "%s(%d): Unknown load_code (0x%08X) from MCP!\n", __FILE__,
+		    __LINE__, load_code);
+		break;
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+
+/*
+ * Perform driver instance specific initialization.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure
+ */
+static void
+bxe_init_nic(struct bxe_softc *sc, uint32_t load_code)
+{
+	struct bxe_fastpath *fp;
+	int i;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	/* Intialize fastpath structures and the status block. */
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		fp->disable_tpa = 1;
+
+		bzero((char *)fp->status_block, BXE_STATUS_BLK_SZ);
+		fp->fp_u_idx = 0;
+		fp->fp_c_idx = 0;
+
+		/* Set a pointer back to the driver instance. */
+		fp->sc = sc;
+
+		/* Set the fastpath starting state as closed. */
+		fp->state = BXE_FP_STATE_CLOSED;
+
+		/* Self-reference to this fastpath's instance. */
+		fp->index = i;
+
+		/* Set the client ID beginning with the leading id. */
+		fp->cl_id = BP_L_ID(sc) + i;
+
+		/* Set the status block ID for this fastpath instance. */
+		fp->sb_id = fp->cl_id;
+
+		DBPRINT(sc, (BXE_INFO_LOAD | BXE_INFO_RESET),
+		    "%s(): fp[%d]: cl_id = %d, sb_id = %d,\n",
+		    __FUNCTION__, fp->index, fp->cl_id, fp->sb_id);
+
+		/* Initialize the fastpath status block. */
+		bxe_init_sb(sc, fp->status_block, fp->status_block_paddr,
+		    fp->sb_id);
+		bxe_update_fpsb_idx(fp);
+	}
+
+	rmb();
+
+	bzero((char *)sc->def_status_block, BXE_DEF_STATUS_BLK_SZ);
+
+	/* Initialize the Default Status Block. */
+	bxe_init_def_sb(sc, sc->def_status_block, sc->def_status_block_paddr,
+	    DEF_SB_ID);
+	bxe_update_dsb_idx(sc);
+
+	/* Initialize the coalescence parameters. */
+	bxe_update_coalesce(sc);
+
+	/* Intiialize the Receive BD Chain and Receive Completion Chain. */
+	bxe_init_rx_chains(sc);
+
+	/* Initialize the Transmit BD Chain. */
+	bxe_init_tx_chains(sc);
+
+	/* Initialize the Slow Path Chain. */
+	bxe_init_sp_ring(sc);
+
+	/* Initialize STORM processor context/configuration. */
+	bxe_init_context(sc);
+
+	/* Initialize the Context. */
+	bxe_init_internal(sc, load_code);
+
+	/* Enable indirection table for multi-queue operation. */
+	bxe_init_ind_table(sc);
+
+	mb();
+
+	/* Disable the interrupts from device until init is complete.*/
+	bxe_int_disable(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+*
+* Returns:
+*   0 = Success, !0 = Failure
+*/
+static int
+bxe_gunzip_init(struct bxe_softc *sc)
+{
+	int rc;
+
+	rc = 0;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	bxe_dmamem_alloc(sc, sc->gunzip_tag, sc->gunzip_map, sc->gunzip_buf,
+	    FW_BUF_SIZE, &sc->gunzip_mapping);
+
+	if (sc->gunzip_buf == NULL)
+		goto bxe_gunzip_init_nomem1;
+
+	sc->strm = malloc(sizeof(*sc->strm), M_DEVBUF, M_NOWAIT);
+	if (sc->strm  == NULL)
+		goto bxe_gunzip_init_nomem2;
+
+	goto bxe_gunzip_init_exit;
+
+bxe_gunzip_init_nomem2:
+	bxe_dmamem_free(sc, sc->gunzip_tag, sc->gunzip_buf, sc->gunzip_map);
+	sc->gunzip_buf = NULL;
+
+bxe_gunzip_init_nomem1:
+	BXE_PRINTF(
+	    "%s(%d): Cannot allocate firmware buffer for un-compression!\n",
+	    __FILE__, __LINE__);
+	rc = ENOMEM;
+
+bxe_gunzip_init_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	return (rc);
+}
+
+/*
+ * Send a loopback packet through the Network Interface Glue (NIG) block.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_lb_pckt(struct bxe_softc *sc)
+{
+#ifdef USE_DMAE
+	uint32_t wb_write[3];
+#endif
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	/* Ethernet source and destination addresses. */
+#ifdef USE_DMAE
+	wb_write[0] = 0x55555555;
+	wb_write[1] = 0x55555555;
+	wb_write[2] = 0x20;	/* SOP */
+	REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
+#else
+	REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB, 0x55555555);
+	REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
+	REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 8, 0x20);
+#endif
+
+	/* NON-IP protocol. */
+#ifdef USE_DMAE
+	wb_write[0] = 0x09000000;
+	wb_write[1] = 0x55555555;
+	wb_write[2] = 0x10;	/* EOP */
+	REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
+#else
+	REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB, 0x09000000);
+	REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
+	REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 8, 0x10);
+#endif
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Perform an internal memory test.
+ *
+ * Some internal memories are not accessible through the PCIe interface so
+ * we send some debug packets for the test.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_int_mem_test(struct bxe_softc *sc)
+{
+	uint32_t val;
+	int count, i, rc;
+
+	rc = 0;
+	val = 0;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	/* Perform a single debug packet test. */
+
+	/* Disable inputs of parser neighbor blocks. */
+	REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
+	REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
+	REG_WR(sc, CFC_REG_DEBUG0, 0x1);
+	REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
+
+	/*  Write 0 to parser credits for CFC search request. */
+	REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
+
+	/* Send an Ethernet packet. */
+	bxe_lb_pckt(sc);
+
+	/* Wait until NIG register shows 1 packet of size 0x10. */
+	count = 1000;
+	while (count) {
+		bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
+		val = *BXE_SP(sc, wb_data[0]);
+		if (val == 0x10)
+			break;
+
+		DELAY(10000);
+		count--;
+	}
+
+	if (val != 0x10) {
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): NIG loopback test 1 timeout (val = 0x%08X)!\n",
+		    __FUNCTION__, val);
+		rc = 1;
+		goto bxe_int_mem_test_exit;
+	}
+
+	/* Wait until PRS register shows 1 packet */
+	count = 1000;
+	while (count) {
+		val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
+
+		if (val == 1)
+			break;
+
+		DELAY(10000);
+		count--;
+	}
+
+	if (val != 0x1) {
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): PRS loopback test 1 timeout (val = 0x%08X)!\n",
+		    __FUNCTION__, val);
+		rc = 2;
+		goto bxe_int_mem_test_exit;
+	}
+
+	/* Reset and init BRB, PRS. */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x3);
+	DELAY(50000);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x3);
+	DELAY(50000);
+	bxe_init_block(sc, BRB1_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, PRS_BLOCK, COMMON_STAGE);
+
+	/* Perform the test again, this time with 10 packets. */
+
+	/* Disable inputs of parser neighbor blocks. */
+	REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
+	REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
+	REG_WR(sc, CFC_REG_DEBUG0, 0x1);
+	REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
+
+	/* Write 0 to parser credits for CFC search request. */
+	REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
+
+	/* Send 10 Ethernet packets. */
+	for (i = 0; i < 10; i++)
+		bxe_lb_pckt(sc);
+
+	/* Wait until NIG shows 10 + 1 packets of size 11 * 0x10 = 0xb0. */
+	count = 1000;
+	while (count) {
+		bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
+		val = *BXE_SP(sc, wb_data[0]);
+		if (val == 0xb0)
+			break;
+
+		DELAY(10000);
+		count--;
+	}
+
+	if (val != 0xb0) {
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): NIG loopback test 2 timeout (val = 0x%08X)!\n",
+		    __FUNCTION__, val);
+		rc = 3;
+		goto bxe_int_mem_test_exit;
+	}
+
+	/* Wait until PRS register shows 2 packets. */
+	val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
+	if (val != 2) {
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): PRS loopback test 2 timeout (val = 0x%x)!\n",
+		    __FUNCTION__, val);
+		rc = 4;
+		goto bxe_int_mem_test_exit;
+	}
+
+	/* Write 1 to parser credits for CFC search request. */
+	REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
+
+	/* Wait until PRS register shows 3 packets. */
+	DELAY(10000);
+
+	/* Wait until NIG register shows 1 packet of size 0x10. */
+	val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
+	if (val != 3) {
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): PRS loopback test 3 timeout (val = 0x%08X)!\n",
+		    __FUNCTION__, val);
+		rc = 5;
+		goto bxe_int_mem_test_exit;
+	}
+
+	/* Clear NIG end-of-packet FIFO. */
+	for (i = 0; i < 11; i++)
+		REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
+
+	val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
+	if (val != 1) {
+		DBPRINT(sc, BXE_INFO, "clear of NIG failed\n");
+		rc = 6;
+		goto bxe_int_mem_test_exit;
+	}
+
+	/* Reset and init BRB, PRS, NIG. */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
+	DELAY(50000);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
+	DELAY(50000);
+	bxe_init_block(sc, BRB1_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, PRS_BLOCK, COMMON_STAGE);
+
+	/* Set NIC mode. */
+	REG_WR(sc, PRS_REG_NIC_MODE, 1);
+
+	/* Enable inputs of parser neighbor blocks. */
+	REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
+	REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
+	REG_WR(sc, CFC_REG_DEBUG0, 0x0);
+	REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
+
+bxe_int_mem_test_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	return (rc);
+}
+
+/*
+ * Enable attentions from various blocks.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_enable_blocks_attention(struct bxe_softc *sc)
+{
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
+	REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
+	REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
+	REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
+	REG_WR(sc, QM_REG_QM_INT_MASK, 0);
+	REG_WR(sc, TM_REG_TM_INT_MASK, 0);
+	REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
+	REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
+	REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
+
+	REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
+	REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
+	REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
+
+	REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
+	REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
+	REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
+	REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
+
+	REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
+
+	REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
+	REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
+	REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
+
+	REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
+	REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
+	REG_WR(sc, PBF_REG_PBF_INT_MASK, 0X18);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * PXP Arbiter
+ */
+
+/*
+ * This code configures the PCI read/write arbiter
+ * which implements a weighted round robin
+ * between the virtual queues in the chip.
+ *
+ * The values were derived for each PCI max payload and max request size.
+ * since max payload and max request size are only known at run time,
+ * this is done as a separate init stage.
+ */
+
+#define	NUM_WR_Q			13
+#define	NUM_RD_Q			29
+#define	MAX_RD_ORD			3
+#define	MAX_WR_ORD			2
+
+/* Configuration for one arbiter queue. */
+struct arb_line {
+	int l;
+	int add;
+	int ubound;
+};
+
+/* Derived configuration for each read queue for each max request size. */
+static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
+/* 1 */	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+	{ {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
+	{ {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
+	{ {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
+	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+/* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 64, 6},  {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+/* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
+};
+
+/* Derived configuration for each write queue for each max request size. */
+static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
+/* 1 */	{ {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
+	{ {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
+	{ {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+	{ {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+	{ {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+	{ {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
+	{ {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+	{ {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+/* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
+	{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
+	{ {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
+	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
+};
+
+/* Register addresses for read queues. */
+static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
+/* 1 */	{PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
+	    PXP2_REG_RQ_BW_RD_UBOUND0},
+	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+	    PXP2_REG_PSWRQ_BW_UB1},
+	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+	    PXP2_REG_PSWRQ_BW_UB2},
+	{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+	    PXP2_REG_PSWRQ_BW_UB3},
+	{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
+	    PXP2_REG_RQ_BW_RD_UBOUND4},
+	{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
+	    PXP2_REG_RQ_BW_RD_UBOUND5},
+	{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+	    PXP2_REG_PSWRQ_BW_UB6},
+	{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+	    PXP2_REG_PSWRQ_BW_UB7},
+	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+	    PXP2_REG_PSWRQ_BW_UB8},
+/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+	    PXP2_REG_PSWRQ_BW_UB9},
+	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+	    PXP2_REG_PSWRQ_BW_UB10},
+	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+	    PXP2_REG_PSWRQ_BW_UB11},
+	{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
+	    PXP2_REG_RQ_BW_RD_UBOUND12},
+	{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
+	    PXP2_REG_RQ_BW_RD_UBOUND13},
+	{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
+	    PXP2_REG_RQ_BW_RD_UBOUND14},
+	{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
+	    PXP2_REG_RQ_BW_RD_UBOUND15},
+	{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
+	    PXP2_REG_RQ_BW_RD_UBOUND16},
+	{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
+	    PXP2_REG_RQ_BW_RD_UBOUND17},
+	{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
+	    PXP2_REG_RQ_BW_RD_UBOUND18},
+/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
+	    PXP2_REG_RQ_BW_RD_UBOUND19},
+	{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
+	    PXP2_REG_RQ_BW_RD_UBOUND20},
+	{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
+	    PXP2_REG_RQ_BW_RD_UBOUND22},
+	{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
+	    PXP2_REG_RQ_BW_RD_UBOUND23},
+	{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
+	    PXP2_REG_RQ_BW_RD_UBOUND24},
+	{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
+	    PXP2_REG_RQ_BW_RD_UBOUND25},
+	{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
+	    PXP2_REG_RQ_BW_RD_UBOUND26},
+	{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
+	    PXP2_REG_RQ_BW_RD_UBOUND27},
+	{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+	    PXP2_REG_PSWRQ_BW_UB28}
+};
+
+/* Register addresses for write queues. */
+static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
+/* 1 */	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+	    PXP2_REG_PSWRQ_BW_UB1},
+	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+	    PXP2_REG_PSWRQ_BW_UB2},
+	{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+	    PXP2_REG_PSWRQ_BW_UB3},
+	{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+	    PXP2_REG_PSWRQ_BW_UB6},
+	{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+	    PXP2_REG_PSWRQ_BW_UB7},
+	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+	    PXP2_REG_PSWRQ_BW_UB8},
+	{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+	    PXP2_REG_PSWRQ_BW_UB9},
+	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+	    PXP2_REG_PSWRQ_BW_UB10},
+	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+	    PXP2_REG_PSWRQ_BW_UB11},
+/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+	    PXP2_REG_PSWRQ_BW_UB28},
+	{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
+	    PXP2_REG_RQ_BW_WR_UBOUND29},
+	{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
+	    PXP2_REG_RQ_BW_WR_UBOUND30}
+};
+
+static void
+bxe_init_pxp_arb(struct bxe_softc *sc, int r_order, int w_order)
+{
+	uint32_t val, i;
+
+	if (r_order > MAX_RD_ORD) {
+		DBPRINT(sc, BXE_INFO,
+		    "read order of %d order adjusted to %d\n", r_order,
+		    MAX_RD_ORD);
+		r_order = MAX_RD_ORD;
+	}
+	if (w_order > MAX_WR_ORD) {
+		DBPRINT(sc, BXE_INFO,
+		    "write order of %d order adjusted to %d\n", w_order,
+		    MAX_WR_ORD);
+		w_order = MAX_WR_ORD;
+	}
+
+	DBPRINT(sc, BXE_INFO, "read order %d write order %d\n", r_order,
+	    w_order);
+
+	for (i = 0; i < NUM_RD_Q - 1; i++) {
+		REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
+		REG_WR(sc, read_arb_addr[i].add, read_arb_data[i][r_order].add);
+		REG_WR(sc, read_arb_addr[i].ubound,
+		    read_arb_data[i][r_order].ubound);
+	}
+
+	for (i = 0; i < NUM_WR_Q - 1; i++) {
+		if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
+		    (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
+
+			REG_WR(sc, write_arb_addr[i].l,
+			    write_arb_data[i][w_order].l);
+
+			REG_WR(sc, write_arb_addr[i].add,
+			    write_arb_data[i][w_order].add);
+
+			REG_WR(sc, write_arb_addr[i].ubound,
+			    write_arb_data[i][w_order].ubound);
+		} else {
+
+			val = REG_RD(sc, write_arb_addr[i].l);
+			REG_WR(sc, write_arb_addr[i].l, val |
+			    (write_arb_data[i][w_order].l << 10));
+
+			val = REG_RD(sc, write_arb_addr[i].add);
+			REG_WR(sc, write_arb_addr[i].add, val |
+			    (write_arb_data[i][w_order].add << 10));
+
+			val = REG_RD(sc, write_arb_addr[i].ubound);
+			REG_WR(sc, write_arb_addr[i].ubound, val |
+			    (write_arb_data[i][w_order].ubound << 7));
+		}
+	}
+
+	val =  write_arb_data[NUM_WR_Q - 1][w_order].add;
+	val += write_arb_data[NUM_WR_Q - 1][w_order].ubound << 10;
+	val += write_arb_data[NUM_WR_Q - 1][w_order].l << 17;
+	REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
+
+	val =  read_arb_data[NUM_RD_Q - 1][r_order].add;
+	val += read_arb_data[NUM_RD_Q - 1][r_order].ubound << 10;
+	val += read_arb_data[NUM_RD_Q - 1][r_order].l << 17;
+	REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
+
+	REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
+	REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
+	REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
+	REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
+
+	if (r_order == MAX_RD_ORD)
+		REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
+
+	REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
+
+	if (CHIP_IS_E1H(sc)) {
+		/*    MPS      w_order     optimal TH      presently TH
+		 *    128         0             0               2
+		 *    256         1             1               3
+		 *    >=512       2             2               3
+		 */
+		val = ((w_order == 0) ? 2 : 3);
+		REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
+		REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
+		REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+	}
+}
+
+static void
+bxe_init_pxp(struct bxe_softc *sc)
+{
+	uint16_t devctl;
+	int r_order, w_order;
+
+	devctl = pci_read_config(sc->bxe_dev, sc->pcie_cap + PCI_EXP_DEVCTL, 2);
+	DBPRINT(sc, BXE_INFO, "read 0x%x from devctl\n", devctl);
+	w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
+	if (sc->mrrs == -1)
+		r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
+	else {
+		DBPRINT(sc, BXE_INFO, "force read order to %d\n", sc->mrrs);
+		r_order = sc->mrrs;
+	}
+
+	bxe_init_pxp_arb(sc, r_order, w_order);
+}
+
+static void
+bxe_setup_fan_failure_detection(struct bxe_softc *sc)
+{
+	uint32_t phy_type, val;
+	int is_required, port;
+
+	is_required = 0;
+	if (BP_NOMCP(sc))
+		return;
+
+	val = SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
+	    SHARED_HW_CFG_FAN_FAILURE_MASK;
+
+	if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
+		is_required = 1;
+
+	/*
+	 * The fan failure mechanism is usually related to the PHY type since
+	 * the power consumption of the board is affected by the PHY. Currently,
+	 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
+	 */
+	else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
+		for (port = PORT_0; port < PORT_MAX; port++) {
+			phy_type = SHMEM_RD(sc,
+			    dev_info.port_hw_config[port].external_phy_config) &
+			    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+			is_required |=
+			((phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
+			 (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
+			 (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
+		}
+
+	if (is_required == 0)
+		return;
+
+	/* Fan failure is indicated by SPIO 5. */
+	bxe_set_spio(sc, MISC_REGISTERS_SPIO_5, MISC_REGISTERS_SPIO_INPUT_HI_Z);
+
+	/* Set to active low mode. */
+	val = REG_RD(sc, MISC_REG_SPIO_INT);
+	val |= ((1 << MISC_REGISTERS_SPIO_5) <<
+					MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
+	REG_WR(sc, MISC_REG_SPIO_INT, val);
+
+	/* Enable interrupt to signal the IGU. */
+	val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
+	val |= (1 << MISC_REGISTERS_SPIO_5);
+	REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
+}
+
+/*
+ * Common initialization.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_init_common(struct bxe_softc *sc)
+{
+	uint32_t val;
+	int i, rc;
+
+	rc = 0;
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	/* Reset all blocks within the chip except the BMAC. */
+	bxe_reset_common(sc);
+	DELAY(30000);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
+	DELAY(30000);
+
+	bxe_init_block(sc, MISC_BLOCK, COMMON_STAGE);
+	if (CHIP_IS_E1H(sc))
+		REG_WR(sc, MISC_REG_E1HMF_MODE, IS_E1HMF(sc));
+
+	REG_WR(sc, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
+	DELAY(30000);
+	REG_WR(sc, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
+
+	bxe_init_block(sc, PXP_BLOCK, COMMON_STAGE);
+	if (CHIP_IS_E1(sc)) {
+		/*
+		 * Enable HW interrupt from PXP on USDM overflow
+		 * bit 16 on INT_MASK_0.
+		 */
+		REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
+	}
+
+	bxe_init_block(sc, PXP2_BLOCK, COMMON_STAGE);
+	bxe_init_pxp(sc);
+
+#ifdef __BIG_ENDIAN
+	REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
+	/* Make sure this value is 0. */
+	REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
+
+	REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
+	REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
+	REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
+	REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
+#endif
+
+	REG_WR(sc, PXP2_REG_RQ_CDU_P_SIZE, 2);
+
+	/* Let the HW do it's magic ... */
+	DELAY(100000);
+	/* Finish the PXP initialization. */
+	val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
+	if (val != 1) {
+		BXE_PRINTF("%s(%d): PXP2 CFG failed!\n", __FILE__, __LINE__);
+		rc = EBUSY;
+		goto bxe_init_common_exit;
+	}
+
+	val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
+	if (val != 1) {
+		BXE_PRINTF("%s(%d): PXP2 RD_INIT failed!\n", __FILE__,
+		    __LINE__);
+		rc = EBUSY;
+		goto bxe_init_common_exit;
+	}
+
+	REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
+	REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
+
+	bxe_init_block(sc, DMAE_BLOCK, COMMON_STAGE);
+
+	sc->dmae_ready = 1;
+	bxe_init_fill(sc, TSEM_REG_PRAM, 0, 8);
+
+	bxe_init_block(sc, TCM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, UCM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, CCM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, XCM_BLOCK, COMMON_STAGE);
+
+	bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
+	bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
+	bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
+	bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
+
+	bxe_init_block(sc, QM_BLOCK, COMMON_STAGE);
+
+	/* Soft reset pulse. */
+	REG_WR(sc, QM_REG_SOFT_RESET, 1);
+	REG_WR(sc, QM_REG_SOFT_RESET, 0);
+
+	bxe_init_block(sc, DQ_BLOCK, COMMON_STAGE);
+	REG_WR(sc, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
+
+	REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
+
+	bxe_init_block(sc, BRB1_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, PRS_BLOCK, COMMON_STAGE);
+	REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
+
+	if (CHIP_IS_E1H(sc))
+		REG_WR(sc, PRS_REG_E1HOV_MODE, IS_E1HMF(sc));
+
+	bxe_init_block(sc, TSDM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, CSDM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, USDM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, XSDM_BLOCK, COMMON_STAGE);
+	/* Clear STORM processor memory. */
+	bxe_init_fill(sc, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
+	bxe_init_fill(sc, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
+	bxe_init_fill(sc, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
+	bxe_init_fill(sc, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
+
+	bxe_init_block(sc, TSEM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, USEM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, CSEM_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, XSEM_BLOCK, COMMON_STAGE);
+
+	/* Sync semi rtc. */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
+
+	bxe_init_block(sc, UPB_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, XPB_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, PBF_BLOCK, COMMON_STAGE);
+
+	REG_WR(sc, SRC_REG_SOFT_RST, 1);
+	/* Setup RSS/multi-queue hasking keys. */
+	for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
+		REG_WR(sc, i, 0xc0cac01a);
+
+	bxe_init_block(sc, SRCH_BLOCK, COMMON_STAGE);
+
+	REG_WR(sc, SRC_REG_SOFT_RST, 0);
+
+	/* Make sure the cdu_context structure has the right size. */
+	if (sizeof(union cdu_context) != 1024) {
+		BXE_PRINTF("%s(%d): Invalid size for context (%ld != 1024)!\n",
+		    __FILE__, __LINE__, (long)sizeof(union cdu_context));
+		rc = EBUSY;
+		goto bxe_init_common_exit;
+	}
+
+	bxe_init_block(sc, CDU_BLOCK, COMMON_STAGE);
+
+	/*
+	 * val = (num_context_in_page << 24) +
+	 * (context_waste_size << 12) +
+	 * context_line_size.
+	 */
+
+	val = (4 << 24) + (0 << 12) + 1024;
+	REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
+
+	bxe_init_block(sc, CFC_BLOCK, COMMON_STAGE);
+	REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
+	/* Enable context validation interrupt from CFC. */
+	REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
+
+	/* Set the thresholds to prevent CFC/CDU race. */
+	REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
+
+	bxe_init_block(sc, HC_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, MISC_AEU_BLOCK, COMMON_STAGE);
+
+	bxe_init_block(sc, PXPCS_BLOCK, COMMON_STAGE);
+	/* Clear PCIe block debug status bits. */
+	REG_WR(sc, 0x2814, 0xffffffff);
+	REG_WR(sc, 0x3820, 0xffffffff);
+
+	bxe_init_block(sc, EMAC0_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, EMAC1_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, DBU_BLOCK, COMMON_STAGE);
+	bxe_init_block(sc, DBG_BLOCK, COMMON_STAGE);
+
+	bxe_init_block(sc, NIG_BLOCK, COMMON_STAGE);
+	if (CHIP_IS_E1H(sc)) {
+		REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_E1HMF(sc));
+		REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_E1HOV(sc));
+	}
+
+	/* Finish CFC initialization. */
+	val = bxe_reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
+	if (val != 1) {
+		BXE_PRINTF("%s(%d): CFC LL_INIT failed!\n", __FILE__, __LINE__);
+		rc = EBUSY;
+		goto bxe_init_common_exit;
+	}
+
+	val = bxe_reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
+	if (val != 1) {
+		BXE_PRINTF("%s(%d): CFC AC_INIT failed!\n", __FILE__, __LINE__);
+		rc = EBUSY;
+		goto bxe_init_common_exit;
+	}
+
+	val = bxe_reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
+	if (val != 1) {
+		BXE_PRINTF("%s(%d): CFC CAM_INIT failed!\n", __FILE__,
+		   __LINE__);
+		rc = EBUSY;
+		goto bxe_init_common_exit;
+	}
+
+	REG_WR(sc, CFC_REG_DEBUG0, 0);
+
+	/* Read NIG statistic and check for first load since powerup. */
+ 	bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
+ 	val = *BXE_SP(sc, wb_data[0]);
+
+ 	/* Do internal memory self test only after a full power cycle. */
+ 	if ((CHIP_IS_E1(sc)) && (val == 0) && bxe_int_mem_test(sc)) {
+		BXE_PRINTF("%s(%d): Internal memory self-test failed!\n",
+		    __FILE__, __LINE__);
+		rc = EBUSY;
+		goto bxe_init_common_exit;
+	}
+
+	/* Handle any board specific initialization. */
+	switch (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config)) {
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+		break;
+
+	default:
+		break;
+	}
+
+	bxe_setup_fan_failure_detection(sc);
+
+	/* Clear PXP2 attentions. */
+	REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
+
+	bxe_enable_blocks_attention(sc);
+
+	if (!BP_NOMCP(sc)) {
+		bxe_acquire_phy_lock(sc);
+		bxe_common_init_phy(sc, sc->common.shmem_base);
+		bxe_release_phy_lock(sc);
+	} else
+		BXE_PRINTF(
+		    "%s(%d): Bootcode is missing - cannot initialize PHY!\n",
+		    __FILE__, __LINE__);
+
+bxe_init_common_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	return (rc);
+}
+
+/*
+ * Port initialization.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_init_port(struct bxe_softc *sc)
+{
+	uint32_t val, low, high;
+	uint32_t swap_val, swap_override, aeu_gpio_mask, offset;
+	uint32_t reg_addr;
+	int i, init_stage, port;
+
+	port = BP_PORT(sc);
+	init_stage = port ? PORT1_STAGE : PORT0_STAGE;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+	    "%s(): Initializing port %d.\n", __FUNCTION__, port);
+
+	REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
+
+	bxe_init_block(sc, PXP_BLOCK, init_stage);
+	bxe_init_block(sc, PXP2_BLOCK, init_stage);
+
+	bxe_init_block(sc, TCM_BLOCK, init_stage);
+	bxe_init_block(sc, UCM_BLOCK, init_stage);
+	bxe_init_block(sc, CCM_BLOCK, init_stage);
+	bxe_init_block(sc, XCM_BLOCK, init_stage);
+
+	bxe_init_block(sc, DQ_BLOCK, init_stage);
+
+	bxe_init_block(sc, BRB1_BLOCK, init_stage);
+
+	/* Determine the pause threshold for the BRB */
+	if (IS_E1HMF(sc))
+		low = (sc->bxe_flags & BXE_ONE_PORT_FLAG) ? 160 : 246;
+	else if (sc->bxe_ifp->if_mtu > 4096) {
+		if (sc->bxe_flags & BXE_ONE_PORT_FLAG)
+			low = 160;
+		else {
+			val = sc->bxe_ifp->if_mtu;
+			/* (24*1024 + val*4)/256 */
+			low = 96 + (val/64) + ((val % 64) ? 1 : 0);
+		}
+	} else
+		low = (sc->bxe_flags & BXE_ONE_PORT_FLAG) ? 80 : 160;
+	high = low + 56;	/* 14 * 1024 / 256 */
+
+	REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
+	REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
+
+	if (sc->bxe_flags & BXE_SAFC_TX_FLAG) {
+		REG_WR(sc, BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 + port * 4, 0xa0);
+		REG_WR(sc, BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 + port * 4,
+		    0xd8);
+		REG_WR(sc, BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 + port *4, 0xa0);
+		REG_WR(sc, BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 + port * 4, 0xd8);
+	}
+
+	/* Port PRS comes here. */
+	bxe_init_block(sc, PRS_BLOCK, init_stage);
+
+	bxe_init_block(sc, TSDM_BLOCK, init_stage);
+	bxe_init_block(sc, CSDM_BLOCK, init_stage);
+	bxe_init_block(sc, USDM_BLOCK, init_stage);
+	bxe_init_block(sc, XSDM_BLOCK, init_stage);
+
+	bxe_init_block(sc, TSEM_BLOCK, init_stage);
+	bxe_init_block(sc, USEM_BLOCK, init_stage);
+	bxe_init_block(sc, CSEM_BLOCK, init_stage);
+	bxe_init_block(sc, XSEM_BLOCK, init_stage);
+
+	bxe_init_block(sc, UPB_BLOCK, init_stage);
+	bxe_init_block(sc, XPB_BLOCK, init_stage);
+
+	bxe_init_block(sc, PBF_BLOCK, init_stage);
+
+	/* Configure PBF to work without pause for MTU = 9000. */
+	REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
+
+	/* Update threshold. */
+	REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040/16));
+	/* Update initial credit. */
+	REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, (9040/16) + 553 - 22);
+
+	/* Probe changes. */
+	REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
+	DELAY(5000);
+	REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
+
+	bxe_init_block(sc, CDU_BLOCK, init_stage);
+	bxe_init_block(sc, CFC_BLOCK, init_stage);
+
+	if (CHIP_IS_E1(sc)) {
+		REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
+		REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
+	}
+	bxe_init_block(sc, HC_BLOCK, init_stage);
+
+	bxe_init_block(sc, MISC_AEU_BLOCK, init_stage);
+	/*
+	 * init aeu_mask_attn_func_0/1:
+	 *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
+	 *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
+	 *             bits 4-7 are used for "per vn group attention"
+	 */
+	REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4,
+	    (IS_E1HMF(sc) ? 0xF7 : 0x7));
+
+	bxe_init_block(sc, PXPCS_BLOCK, init_stage);
+	bxe_init_block(sc, EMAC0_BLOCK, init_stage);
+	bxe_init_block(sc, EMAC1_BLOCK, init_stage);
+	bxe_init_block(sc, DBU_BLOCK, init_stage);
+	bxe_init_block(sc, DBG_BLOCK, init_stage);
+
+	bxe_init_block(sc, NIG_BLOCK, init_stage);
+
+	REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
+
+	if (CHIP_IS_E1H(sc)) {
+		/* Enable outer VLAN support if required. */
+		REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
+		    (IS_E1HOV(sc) ? 0x1 : 0x2));
+
+		if (sc->bxe_flags & BXE_SAFC_TX_FLAG){
+			high = 0;
+			for (i = 0; i < BXE_MAX_PRIORITY; i++) {
+				if (sc->pri_map[i] == 1)
+					high |= (1 << i);
+			}
+			REG_WR(sc, NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 +
+			    port * 4, high);
+			low = 0;
+			for (i = 0; i < BXE_MAX_PRIORITY; i++) {
+				if (sc->pri_map[i] == 0)
+					low |= (1 << i);
+			}
+			REG_WR(sc, NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 +
+			    port * 4, low);
+
+			REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 0);
+			REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 1);
+			REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 1);
+		} else {
+			REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
+			REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
+			REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
+		}
+	}
+
+	bxe_init_block(sc, MCP_BLOCK, init_stage);
+	bxe_init_block(sc, DMAE_BLOCK, init_stage);
+
+	switch (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config)) {
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
+		bxe_set_gpio(sc, MISC_REGISTERS_GPIO_3,
+		    MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
+
+		/*
+		 * The GPIO should be swapped if the swap register is
+		 * set and active.
+		 */
+		swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
+		swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
+
+		/* Select function upon port-swap configuration. */
+		if (port == 0) {
+			offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
+			aeu_gpio_mask = (swap_val && swap_override) ?
+			    AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
+			    AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
+		} else {
+			offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
+			aeu_gpio_mask = (swap_val && swap_override) ?
+			    AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
+			    AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
+		}
+		val = REG_RD(sc, offset);
+		/* Add GPIO3 to group. */
+		val |= aeu_gpio_mask;
+		REG_WR(sc, offset, val);
+		break;
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
+	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
+		/* Add SPIO 5 to group 0. */
+		reg_addr = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+		    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
+		val = REG_RD(sc, reg_addr);
+		val |= AEU_INPUTS_ATTN_BITS_SPIO5;
+		REG_WR(sc, reg_addr, val);
+		break;
+	default:
+		break;
+	}
+
+	bxe__link_reset(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	return (0);
+}
+
+#define	ILT_PER_FUNC		(768/2)
+#define	FUNC_ILT_BASE(func)	(func * ILT_PER_FUNC)
+/*
+ * The phys address is shifted right 12 bits and has an added 1=valid
+ * bit added to the 53rd bit (bit 52) then since this is a wide
+ * register(TM) we split it into two 32 bit writes.
+ */
+#define	ONCHIP_ADDR1(x)		((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
+#define	ONCHIP_ADDR2(x)		((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
+#define	PXP_ONE_ILT(x)		(((x) << 10) | x)
+#define	PXP_ILT_RANGE(f, l)	(((l) << 10) | f)
+#define	CNIC_ILT_LINES		0
+
+/*
+ * ILT write.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_ilt_wr(struct bxe_softc *sc, uint32_t index, bus_addr_t addr)
+{
+	int reg;
+
+	DBENTER(BXE_INSANE_LOAD | BXE_INSANE_RESET);
+
+	if (CHIP_IS_E1H(sc))
+		reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
+	else
+		reg = PXP2_REG_RQ_ONCHIP_AT + index * 8;
+
+	bxe_wb_wr(sc, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
+
+	DBEXIT(BXE_INSANE_LOAD | BXE_INSANE_RESET);
+}
+
+/*
+ * Initialize a function.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_init_func(struct bxe_softc *sc)
+{
+	uint32_t addr, val;
+	int func, i, port;
+
+	port = BP_PORT(sc);
+	func = BP_FUNC(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+	    "%s(): Initializing port %d, function %d.\n", __FUNCTION__, port,
+	    func);
+
+	/* Set MSI reconfigure capability. */
+	addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
+	val = REG_RD(sc, addr);
+	val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
+	REG_WR(sc, addr, val);
+
+	i = FUNC_ILT_BASE(func);
+
+	bxe_ilt_wr(sc, i, BXE_SP_MAPPING(sc, context));
+
+	if (CHIP_IS_E1H(sc)) {
+		REG_WR(sc, PXP2_REG_RQ_CDU_FIRST_ILT, i);
+		REG_WR(sc, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
+	} else /* E1 */
+		REG_WR(sc, PXP2_REG_PSWRQ_CDU0_L2P + func * 4,
+		    PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
+
+	if (CHIP_IS_E1H(sc)) {
+		bxe_init_block(sc, MISC_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, TCM_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, UCM_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, CCM_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, XCM_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, TSEM_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, USEM_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, CSEM_BLOCK, FUNC0_STAGE + func);
+		bxe_init_block(sc, XSEM_BLOCK, FUNC0_STAGE + func);
+
+		REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
+		REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, sc->e1hov);
+	}
+
+	/* Host Coalescing initialization per function. */
+	if (CHIP_IS_E1H(sc)) {
+		REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
+		REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
+		REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
+	}
+
+	bxe_init_block(sc, HC_BLOCK, FUNC0_STAGE + func);
+
+	/* Reset PCIe block debug values. */
+	REG_WR(sc, 0x2114, 0xffffffff);
+	REG_WR(sc, 0x2120, 0xffffffff);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	return (0);
+}
+
+/*
+ *
+ * Returns:
+ *   0 = Failure, !0 = Failure.
+ */
+static int
+bxe_init_hw(struct bxe_softc *sc, uint32_t load_code)
+{
+	int func, i, rc;
+
+	rc = 0;
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	sc->dmae_ready = 0;
+	bxe_gunzip_init(sc);
+	switch (load_code) {
+	case FW_MSG_CODE_DRV_LOAD_COMMON:
+		rc = bxe_init_common(sc);
+		if (rc)
+			goto bxe_init_hw_exit;
+		/* FALLTHROUGH */
+	case FW_MSG_CODE_DRV_LOAD_PORT:
+		sc->dmae_ready = 1;
+		rc = bxe_init_port(sc);
+		if (rc)
+			goto bxe_init_hw_exit;
+		/* FALLTHROUGH */
+	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
+		sc->dmae_ready = 1;
+		rc = bxe_init_func(sc);
+		if (rc)
+			goto bxe_init_hw_exit;
+		break;
+	default:
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Unknown load_code (0x%08X) from MCP!\n",
+		    __FUNCTION__, load_code);
+		break;
+	}
+
+	/* Fetch additional config data if the bootcode is running. */
+	if (!BP_NOMCP(sc)) {
+		func = BP_FUNC(sc);
+		/* Fetch the pulse sequence number. */
+		sc->fw_drv_pulse_wr_seq = (SHMEM_RD(sc,
+		    func_mb[func].drv_pulse_mb) & DRV_PULSE_SEQ_MASK);
+	}
+
+	/* This needs to be done before gunzip end. */
+	bxe_zero_def_sb(sc);
+	for (i = 0; i < sc->num_queues; i++)
+		bxe_zero_sb(sc, BP_L_ID(sc) + i);
+
+bxe_init_hw_exit:
+	bxe_gunzip_end(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	return (rc);
+}
+
+/*
+ * Send a firmware command and wait for the response.
+ *
+ * Post a command to shared memory for the bootcode running on the MCP and
+ * stall until the bootcode responds or a timeout occurs.
+ *
+ * Returns:
+ *   0 = Failure, otherwise firmware response code (FW_MSG_CODE_*).
+ */
+static int
+bxe_fw_command(struct bxe_softc *sc, uint32_t command)
+{
+	uint32_t cnt, rc, seq;
+	int func;
+
+	func = BP_FUNC(sc);
+	seq = ++sc->fw_seq;
+	rc = 0;
+	cnt = 1;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	DBRUNMSG(BXE_VERBOSE, bxe_decode_mb_msgs(sc, (command | seq), 0));
+
+	BXE_FWMB_LOCK(sc);
+
+	/* Write the command to the shared memory mailbox. */
+	SHMEM_WR(sc, func_mb[func].drv_mb_header, (command | seq));
+
+	/* Wait up to 2 seconds for a response. */
+	do {
+		/* Wait 10ms for a response. */
+		DELAY(10000);
+
+		/* Pickup the response. */
+		rc = SHMEM_RD(sc, func_mb[func].fw_mb_header);
+	} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 400));
+
+	DBRUNMSG(BXE_VERBOSE, bxe_decode_mb_msgs(sc, 0, rc));
+
+	/* Make sure we read the right response. */
+	if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK ))
+		rc &= FW_MSG_CODE_MASK;
+	else {
+		BXE_PRINTF("%s(%d): Bootcode failed to respond!\n", __FILE__,
+		    __LINE__);
+		DBRUN(bxe_dump_fw(sc));
+		rc = 0;
+	}
+
+	BXE_FWMB_UNLOCK(sc);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	return (rc);
+}
+
+/*
+ * Free any DMA memory owned by the driver.
+ *
+ * Scans through each data structre that requires DMA memory and frees
+ * the memory if allocated.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_dma_free(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	int i, j;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	if (sc->parent_tag != NULL) {
+
+		for (i = 0; i < sc->num_queues; i++) {
+			fp = &sc->fp[i];
+			/* Trust no one! */
+			if (fp) {
+				/* Free, unmap, and destroy the status block. */
+				if (fp->status_block_tag != NULL) {
+					if (fp->status_block_map != NULL) {
+						if (fp->status_block != NULL)
+							bus_dmamem_free(
+							  fp->status_block_tag,
+							  fp->status_block,
+							  fp->status_block_map);
+
+						bus_dmamap_unload(
+						    fp->status_block_tag,
+						    fp->status_block_map);
+						bus_dmamap_destroy(
+						    fp->status_block_tag,
+						    fp->status_block_map);
+					}
+
+					bus_dma_tag_destroy(
+					    fp->status_block_tag);
+				}
+
+				/*
+				 * Free, unmap and destroy all TX BD
+				 * chain pages.
+				 */
+				if (fp->tx_bd_chain_tag != NULL) {
+					for (j = 0; j < NUM_TX_PAGES; j++ ) {
+						if (fp->tx_bd_chain_map[j] != NULL) {
+							if (fp->tx_bd_chain[j] != NULL)
+								bus_dmamem_free(fp->tx_bd_chain_tag,
+									fp->tx_bd_chain[j],
+									fp->tx_bd_chain_map[j]);
+
+							bus_dmamap_unload(fp->tx_bd_chain_tag,
+								fp->tx_bd_chain_map[j]);
+							bus_dmamap_destroy(fp->tx_bd_chain_tag,
+								fp->tx_bd_chain_map[j]);
+						}
+					}
+
+					bus_dma_tag_destroy(fp->tx_bd_chain_tag);
+				}
+
+				/* Free, unmap and destroy all RX BD chain pages. */
+				if (fp->rx_bd_chain_tag != NULL) {
+
+					for (j = 0; j < NUM_RX_PAGES; j++ ) {
+						if (fp->rx_bd_chain_map[j] != NULL) {
+							if (fp->rx_bd_chain[j] != NULL)
+								bus_dmamem_free(fp->rx_bd_chain_tag,
+									fp->rx_bd_chain[j],
+									fp->rx_bd_chain_map[j]);
+
+							bus_dmamap_unload(fp->rx_bd_chain_tag,
+								fp->rx_bd_chain_map[j]);
+							bus_dmamap_destroy(fp->rx_bd_chain_tag,
+								fp->rx_bd_chain_map[j]);
+						}
+					}
+
+					bus_dma_tag_destroy(fp->rx_bd_chain_tag);
+				}
+
+				/*
+				 * Free, unmap and destroy all RX CQ
+				 * chain pages.
+				 */
+				if (fp->rx_comp_chain_tag != NULL) {
+					for (j = 0; j < NUM_RCQ_PAGES; j++ ) {
+						if (fp->rx_comp_chain_map[j] != NULL) {
+							if (fp->rx_comp_chain[j] != NULL)
+								bus_dmamem_free(fp->rx_comp_chain_tag,
+									fp->rx_comp_chain[j],
+									fp->rx_comp_chain_map[j]);
+
+							bus_dmamap_unload(fp->rx_comp_chain_tag,
+								fp->rx_comp_chain_map[j]);
+							bus_dmamap_destroy(fp->rx_comp_chain_tag,
+								fp->rx_comp_chain_map[j]);
+						}
+					}
+
+					bus_dma_tag_destroy(fp->rx_comp_chain_tag);
+				}
+
+				/* Unload and destroy the TX mbuf maps. */
+				if (fp->tx_mbuf_tag != NULL) {
+					for (j = 0; j < TOTAL_TX_BD; j++) {
+						if (fp->tx_mbuf_map[j] != NULL) {
+							bus_dmamap_unload(fp->tx_mbuf_tag,
+								fp->tx_mbuf_map[j]);
+							bus_dmamap_destroy(fp->tx_mbuf_tag,
+								fp->tx_mbuf_map[j]);
+						}
+					}
+
+					bus_dma_tag_destroy(fp->tx_mbuf_tag);
+				}
+
+
+				if (TPA_ENABLED(sc)) {
+					int tpa_pool_max = CHIP_IS_E1H(sc) ?
+						ETH_MAX_AGGREGATION_QUEUES_E1H :
+						ETH_MAX_AGGREGATION_QUEUES_E1;
+
+					/* Unload and destroy the TPA pool mbuf maps. */
+					if (fp->rx_mbuf_tag != NULL) {
+
+						for (j = 0; j < tpa_pool_max; j++) {
+
+							if (fp->tpa_mbuf_map[j] != NULL) {
+								bus_dmamap_unload(fp->rx_mbuf_tag,
+									fp->tpa_mbuf_map[j]);
+								bus_dmamap_destroy(fp->rx_mbuf_tag,
+									fp->tpa_mbuf_map[j]);
+							}
+						}
+					}
+
+					/* Free, unmap and destroy all RX SGE chain pages. */
+					if (fp->rx_sge_chain_tag != NULL) {
+						for (j = 0; j < NUM_RX_SGE_PAGES; j++ ) {
+							if (fp->rx_sge_chain_map[j] != NULL) {
+								if (fp->rx_sge_chain[j] != NULL)
+									bus_dmamem_free(fp->rx_sge_chain_tag,
+										fp->rx_sge_chain[j],
+										fp->rx_sge_chain_map[j]);
+
+								bus_dmamap_unload(fp->rx_sge_chain_tag,
+									fp->rx_sge_chain_map[j]);
+								bus_dmamap_destroy(fp->rx_sge_chain_tag,
+									fp->rx_sge_chain_map[j]);
+							}
+						}
+
+						bus_dma_tag_destroy(fp->rx_sge_chain_tag);
+					}
+
+					/* Unload and destroy the SGE Buf maps. */
+					if (fp->rx_sge_buf_tag != NULL) {
+
+						for (j = 0; j < TOTAL_RX_SGE; j++) {
+							if (fp->rx_sge_buf_map[j] != NULL) {
+								bus_dmamap_unload(fp->rx_sge_buf_tag,
+									fp->rx_sge_buf_map[j]);
+								bus_dmamap_destroy(fp->rx_sge_buf_tag,
+									fp->rx_sge_buf_map[j]);
+							}
+						}
+
+						bus_dma_tag_destroy(fp->rx_sge_buf_tag);
+					}
+				}
+
+				/* Unload and destroy the RX mbuf maps. */
+				if (fp->rx_mbuf_tag != NULL) {
+					for (j = 0; j < TOTAL_RX_BD; j++) {
+						if (fp->rx_mbuf_map[j] != NULL) {
+							bus_dmamap_unload(fp->rx_mbuf_tag,
+								fp->rx_mbuf_map[j]);
+							bus_dmamap_destroy(fp->rx_mbuf_tag,
+								fp->rx_mbuf_map[j]);
+						}
+					}
+
+					bus_dma_tag_destroy(fp->rx_mbuf_tag);
+				}
+
+			}
+		}
+
+		/* Destroy the def_status block. */
+		if (sc->def_status_block_tag != NULL) {
+			if (sc->def_status_block_map != NULL) {
+				if (sc->def_status_block != NULL)
+					bus_dmamem_free(
+					    sc->def_status_block_tag,
+					    sc->def_status_block,
+					    sc->def_status_block_map);
+
+				bus_dmamap_unload(sc->def_status_block_tag,
+				    sc->def_status_block_map);
+				bus_dmamap_destroy(sc->def_status_block_tag,
+				    sc->def_status_block_map);
+			}
+
+			bus_dma_tag_destroy(sc->def_status_block_tag);
+		}
+
+		/* Destroy the statistics block. */
+		if (sc->stats_tag != NULL) {
+			if (sc->stats_map != NULL) {
+				if (sc->stats_block != NULL)
+					bus_dmamem_free(sc->stats_tag,
+					    sc->stats_block, sc->stats_map);
+				bus_dmamap_unload(sc->stats_tag, sc->stats_map);
+				bus_dmamap_destroy(sc->stats_tag,
+				    sc->stats_map);
+			}
+
+			bus_dma_tag_destroy(sc->stats_tag);
+		}
+
+		/* Destroy the Slow Path block. */
+		if (sc->slowpath_tag != NULL) {
+			if (sc->slowpath_map != NULL) {
+				if (sc->slowpath != NULL)
+					bus_dmamem_free(sc->slowpath_tag,
+					    sc->slowpath, sc->slowpath_map);
+
+				bus_dmamap_unload(sc->slowpath_tag,
+				    sc->slowpath_map);
+				bus_dmamap_destroy(sc->slowpath_tag,
+				    sc->slowpath_map);
+			}
+
+			bus_dma_tag_destroy(sc->slowpath_tag);
+		}
+
+		/* Destroy the Slow Path Ring. */
+		if (sc->spq_tag != NULL) {
+			if (sc->spq_map != NULL) {
+				if (sc->spq != NULL)
+					bus_dmamem_free(sc->spq_tag, sc->spq,
+					    sc->spq_map);
+
+				bus_dmamap_unload(sc->spq_tag, sc->spq_map);
+				bus_dmamap_destroy(sc->spq_tag, sc->spq_map);
+			}
+
+			bus_dma_tag_destroy(sc->spq_tag);
+		}
+
+
+		free(sc->strm, M_DEVBUF);
+		sc->strm = NULL;
+
+		if (sc->gunzip_tag != NULL) {
+			if (sc->gunzip_map != NULL) {
+				if (sc->gunzip_buf != NULL)
+					bus_dmamem_free(sc->gunzip_tag,
+					    sc->gunzip_buf, sc->gunzip_map);
+
+				bus_dmamap_unload(sc->gunzip_tag,
+				    sc->gunzip_map);
+				bus_dmamap_destroy(sc->gunzip_tag,
+				    sc->gunzip_map);
+			}
+
+			bus_dma_tag_destroy(sc->gunzip_tag);
+		}
+
+		bus_dma_tag_destroy(sc->parent_tag);
+	}
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Free paged pool memory maps and tags.
+ *
+ * Returns:
+ *   Nothing.
+ */
+
+static void
+bxe_dmamem_free(struct bxe_softc *sc, bus_dma_tag_t tag, caddr_t buf,
+    bus_dmamap_t map)
+{
+
+	DBENTER(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+
+	if (tag) {
+		if (sc->gunzip_buf != NULL)
+			bus_dmamem_free(tag, buf, map);
+
+		if (map != NULL) {
+			bus_dmamap_unload(tag, map);
+			bus_dmamap_destroy(tag, map);
+		}
+
+		if (tag != NULL)
+			bus_dma_tag_destroy(tag);
+	}
+
+
+	DBEXIT(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+}
+
+/*
+ * Get DMA memory from the OS.
+ *
+ * Validates that the OS has provided DMA buffers in response to a
+ * bus_dmamap_load call and saves the physical address of those buffers.
+ * When the callback is used the OS will return 0 for the mapping function
+ * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
+ * failures back to the caller.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+	bus_addr_t *busaddr;
+
+	busaddr = arg;
+	/* Check for an error and signal the caller that an error occurred. */
+	if (error) {
+		printf(
+		    "bxe %s(%d): DMA mapping error (error = %d, nseg = %d)!\n",
+		    __FILE__, __LINE__, error, nseg);
+		*busaddr = 0;
+		return;
+	}
+
+	*busaddr = segs->ds_addr;
+}
+
+/*
+ * Allocate any non-paged DMA memory needed by the driver.
+ *
+ * Allocates DMA memory needed for the various global structures which are
+ * read or written by the hardware.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_dma_alloc(device_t dev)
+{
+	struct bxe_softc *sc;
+	struct bxe_fastpath *fp;
+	int error, rc;
+	bus_addr_t busaddr;
+	bus_size_t max_size, max_seg_size;
+	int i, j, max_segments;
+
+	sc = device_get_softc(dev);
+	rc = 0;
+
+	DBENTER(BXE_VERBOSE_RESET);
+
+	/*
+	 * Allocate the parent bus DMA tag appropriate for PCI.
+	 */
+	if (bus_dma_tag_create(NULL,	/* parent tag */
+	    1,				/* alignment for segs */
+	    BXE_DMA_BOUNDARY,		/* cannot cross */
+	    BUS_SPACE_MAXADDR,		/* restricted low */
+	    BUS_SPACE_MAXADDR,		/* restricted hi */
+	    NULL,			/* filter f() */
+	    NULL,			/* filter f() arg */
+	    MAXBSIZE,			/* max map for this tag */
+	    BUS_SPACE_UNRESTRICTED,	/* #of discontinuities */
+	    BUS_SPACE_MAXSIZE_32BIT,	/* max seg size */
+	    0,				/* flags */
+	    NULL,			/* lock f() */
+	    NULL,			/* lock f() arg */
+	    &sc->parent_tag)		/* dma tag */
+	    ) {
+		BXE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	/* Allocate DMA memory for each fastpath structure. */
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+		    "%s(): fp[%d] virtual address = %p, size = %lu\n",
+		    __FUNCTION__,  i, fp,
+		    (long unsigned int)sizeof(struct bxe_fastpath));
+
+		/*
+		 * Create a DMA tag for the status block, allocate and clear the
+		 * memory, map the memory into DMA space, and fetch the physical
+		 * address of the block.
+		 */
+
+		if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
+		    BXE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
+		    NULL, NULL, BXE_STATUS_BLK_SZ, 1, BXE_STATUS_BLK_SZ,
+		    0, NULL, NULL, &fp->status_block_tag)) {
+			BXE_PRINTF("%s(%d): Could not allocate fp[%d] "
+			    "status block DMA tag!\n", __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		if (bus_dmamem_alloc(fp->status_block_tag,
+		    (void **)&fp->status_block, BUS_DMA_NOWAIT,
+		    &fp->status_block_map)) {
+			BXE_PRINTF(
+			    "%s(%d): Could not allocate fp[%d] status block "
+			    "DMA memory!\n", __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		bzero((char *)fp->status_block, BXE_STATUS_BLK_SZ);
+
+		error = bus_dmamap_load(fp->status_block_tag,
+		    fp->status_block_map, fp->status_block, BXE_STATUS_BLK_SZ,
+		    bxe_dma_map_addr, &busaddr, BUS_DMA_NOWAIT);
+
+		if (error) {
+			BXE_PRINTF("%s(%d): Could not map fp[%d] status block "
+			    "DMA memory!\n", __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		/* Physical address of Status Block */
+		fp->status_block_paddr = busaddr;
+		DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+		    "%s(): fp[%d] status block physical address = 0x%jX\n",
+		    __FUNCTION__, i, (uintmax_t) fp->status_block_paddr);
+
+		/*
+		 * Create a DMA tag for the TX buffer descriptor chain,
+		 * allocate and clear the  memory, and fetch the
+		 * physical address of the block.
+		 */
+		if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
+		    BXE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
+		    NULL, NULL, BXE_TX_CHAIN_PAGE_SZ, 1, BXE_TX_CHAIN_PAGE_SZ,
+		    0, NULL, NULL, &fp->tx_bd_chain_tag)) {
+			BXE_PRINTF(
+			    "%s(%d): Could not allocate fp[%d] TX descriptor "
+			    "chain DMA tag!\n", __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		for (j = 0; j < NUM_TX_PAGES; j++) {
+			if (bus_dmamem_alloc(fp->tx_bd_chain_tag,
+			    (void **)&fp->tx_bd_chain[j], BUS_DMA_NOWAIT,
+			    &fp->tx_bd_chain_map[j])) {
+				BXE_PRINTF(
+				    "%s(%d): Could not allocate fp[%d] TX "
+				    "descriptor chain DMA memory!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			bzero((char *)fp->tx_bd_chain[j], BXE_TX_CHAIN_PAGE_SZ);
+
+			error = bus_dmamap_load(fp->tx_bd_chain_tag,
+			    fp->tx_bd_chain_map[j], fp->tx_bd_chain[j],
+			    BXE_TX_CHAIN_PAGE_SZ, bxe_dma_map_addr,
+			    &busaddr, BUS_DMA_NOWAIT);
+
+			if (error) {
+				BXE_PRINTF("%s(%d): Could not map fp[%d] "
+				    "TX descriptor chain DMA memory!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			/* Physical Address of each page in the Tx BD Chain. */
+			fp->tx_bd_chain_paddr[j] = busaddr;
+			DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+			    "%s(): fp[%d]->tx_bd_chain_paddr[%d] = 0x%jX\n",
+			    __FUNCTION__, i, j, (uintmax_t)busaddr);
+		}
+
+		/*
+		 * Check the required size before mapping to conserve resources.
+		 */
+		if (bxe_tso_enable) {
+			max_size = BXE_TSO_MAX_SIZE;
+			max_segments = 32; /* BXE_MAX_SEGMENTS; */
+			max_seg_size = BXE_TSO_MAX_SEG_SIZE;
+		} else {
+			max_size  = MCLBYTES * BXE_MAX_SEGMENTS;
+			max_segments = BXE_MAX_SEGMENTS;
+			max_seg_size = MCLBYTES;
+		}
+
+		/* Create a DMA tag for TX mbufs. */
+		if (bus_dma_tag_create(sc->parent_tag, 1, BXE_DMA_BOUNDARY,
+		    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+		    max_size, max_segments, max_seg_size,
+		    0, NULL, NULL, &fp->tx_mbuf_tag)) {
+			BXE_PRINTF(
+		"%s(%d): Could not allocate fp[%d] TX mbuf DMA tag!\n",
+			    __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		/* Create DMA maps for each the TX mbuf cluster(ext buf). */
+		for (j = 0; j < TOTAL_TX_BD; j++) {
+			if (bus_dmamap_create(fp->tx_mbuf_tag, BUS_DMA_NOWAIT,
+			    &(fp->tx_mbuf_map[j]))) {
+				BXE_PRINTF(
+		"%s(%d): Unable to create fp[%d] TX mbuf DMA map!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+		}
+
+		/*
+		 * Create a DMA tag for the RX buffer
+		 * descriptor chain, allocate and clear
+		 * the  memory, and fetch the physical
+		 * address of the blocks.
+		 */
+		if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
+		    BXE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
+		    NULL, NULL, BXE_RX_CHAIN_PAGE_SZ, 1, BXE_RX_CHAIN_PAGE_SZ,
+		    0, NULL, NULL, &fp->rx_bd_chain_tag)) {
+			BXE_PRINTF(
+		"%s(%d): Could not allocate fp[%d] RX BD chain DMA tag!\n",
+			    __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		for (j = 0; j < NUM_RX_PAGES; j++) {
+			if (bus_dmamem_alloc(fp->rx_bd_chain_tag,
+			    (void **)&fp->rx_bd_chain[j], BUS_DMA_NOWAIT,
+			    &fp->rx_bd_chain_map[j])) {
+				BXE_PRINTF(
+	"%s(%d): Could not allocate fp[%d] RX BD chain[%d] DMA memory!\n",
+				    __FILE__, __LINE__, i, j);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			bzero((char *)fp->rx_bd_chain[j], BXE_RX_CHAIN_PAGE_SZ);
+
+			error = bus_dmamap_load(fp->rx_bd_chain_tag,
+			    fp->rx_bd_chain_map[j], fp->rx_bd_chain[j],
+			    BXE_RX_CHAIN_PAGE_SZ, bxe_dma_map_addr, &busaddr,
+			    BUS_DMA_NOWAIT);
+
+			if (error) {
+				BXE_PRINTF(
+		"%s(%d): Could not map fp[%d] RX BD chain[%d] DMA memory!\n",
+				    __FILE__, __LINE__, i, j);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			/* Physical address of each page in the RX BD chain */
+			fp->rx_bd_chain_paddr[j] = busaddr;
+
+			DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+			    "%s(): fp[%d]->rx_bd_chain_paddr[%d] = 0x%jX\n",
+			    __FUNCTION__, i, j, (uintmax_t)busaddr);
+		}
+
+		/*
+		 * Create a DMA tag for RX mbufs.
+		 */
+		if (bus_dma_tag_create(sc->parent_tag, 1, BXE_DMA_BOUNDARY,
+		    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+		    MJUM9BYTES, 1, MJUM9BYTES, 0, NULL,  NULL,
+		    &fp->rx_mbuf_tag)) {
+			BXE_PRINTF(
+		"%s(%d): Could not allocate fp[%d] RX mbuf DMA tag!\n",
+			    __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		/* Create DMA maps for the RX mbuf clusters. */
+		for (j = 0; j < TOTAL_RX_BD; j++) {
+			if (bus_dmamap_create(fp->rx_mbuf_tag, BUS_DMA_NOWAIT,
+			    &(fp->rx_mbuf_map[j]))) {
+				BXE_PRINTF(
+		"%s(%d): Unable to create fp[%d] RX mbuf DMA map!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+		}
+
+		/*
+		 * Create a DMA tag for the RX Completion
+		 * Queue, allocate and clear the  memory,
+		 * map the memory into DMA space, and fetch
+		 * the physical address of the block.
+		 */
+		if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
+		    BXE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
+		    NULL, NULL, BXE_RX_CHAIN_PAGE_SZ, 1, BXE_RX_CHAIN_PAGE_SZ,
+		    0, NULL, NULL, &fp->rx_comp_chain_tag)) {
+			BXE_PRINTF(
+	"%s(%d): Could not allocate fp[%d] RX Completion Queue DMA tag!\n",
+			    __FILE__, __LINE__, i);
+			rc = ENOMEM;
+			goto bxe_dma_alloc_exit;
+		}
+
+		for (j = 0; j < NUM_RCQ_PAGES; j++) {
+			if (bus_dmamem_alloc(fp->rx_comp_chain_tag,
+			    (void **)&fp->rx_comp_chain[j], BUS_DMA_NOWAIT,
+			    &fp->rx_comp_chain_map[j])) {
+				BXE_PRINTF(
+	"%s(%d): Could not allocate fp[%d] RX Completion Queue DMA memory!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			bzero((char *)fp->rx_comp_chain[j],
+			    BXE_RX_CHAIN_PAGE_SZ);
+
+			error = bus_dmamap_load(fp->rx_comp_chain_tag,
+			    fp->rx_comp_chain_map[j], fp->rx_comp_chain[j],
+			    BXE_RX_CHAIN_PAGE_SZ, bxe_dma_map_addr, &busaddr,
+			    BUS_DMA_NOWAIT);
+
+			if (error) {
+				BXE_PRINTF(
+	"%s(%d): Could not map fp[%d] RX Completion Queue DMA memory!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			/*
+			 * Physical address of each page in the RX
+			 * Completion Chain.
+			 */
+			fp->rx_comp_chain_paddr[j] = busaddr;
+
+			DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+			    "%s(): fp[%d]->rx_comp_chain_paddr[%d] = 0x%jX\n",
+			    __FUNCTION__, i, j, (uintmax_t)busaddr);
+		}
+
+		if (TPA_ENABLED(sc)) {
+			int tpa_pool_max = CHIP_IS_E1H(sc) ?
+				ETH_MAX_AGGREGATION_QUEUES_E1H :
+				ETH_MAX_AGGREGATION_QUEUES_E1;
+
+			/*
+			 * Create a DMA tag for the RX SGE Ring,
+			 * allocate and clear the memory, map the
+			 * memory into DMA space, and fetch the
+			 * physical address of the block.
+			 */
+			if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
+			    BXE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
+			    BUS_SPACE_MAXADDR, NULL, NULL, BXE_RX_CHAIN_PAGE_SZ,
+			    1, BXE_RX_CHAIN_PAGE_SZ, 0,  NULL, NULL,
+			    &fp->rx_sge_chain_tag)) {
+				BXE_PRINTF(
+	"%s(%d): Could not allocate fp[%d] RX SGE descriptor chain DMA tag!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			for (j = 0; j < NUM_RX_SGE_PAGES; j++) {
+				if (bus_dmamem_alloc(fp->rx_sge_chain_tag,
+				    (void **)&fp->rx_sge_chain[j],
+				    BUS_DMA_NOWAIT, &fp->rx_sge_chain_map[j])) {
+					BXE_PRINTF(
+	"%s(%d): Could not allocate fp[%d] RX SGE chain[%d] DMA memory!\n",
+					    __FILE__, __LINE__, i, j);
+					rc = ENOMEM;
+					goto bxe_dma_alloc_exit;
+				}
+
+				bzero((char *)fp->rx_sge_chain[j],
+				    BXE_RX_CHAIN_PAGE_SZ);
+
+				error = bus_dmamap_load(fp->rx_sge_chain_tag,
+				    fp->rx_sge_chain_map[j],
+				    fp->rx_sge_chain[j], BXE_RX_CHAIN_PAGE_SZ,
+				    bxe_dma_map_addr, &busaddr, BUS_DMA_NOWAIT);
+
+				if (error) {
+					BXE_PRINTF(
+	"%s(%d): Could not map fp[%d] RX SGE chain[%d] DMA memory!\n",
+					    __FILE__, __LINE__, i, j);
+					rc = ENOMEM;
+					goto bxe_dma_alloc_exit;
+				}
+
+				/*
+				 * Physical address of each page in the RX
+				 * SGE chain.
+				 */
+				DBPRINT(sc,
+				    (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+			"%s(): fp[%d]->rx_sge_chain_paddr[%d] = 0x%jX\n",
+				    __FUNCTION__, i, j, (uintmax_t)busaddr);
+				fp->rx_sge_chain_paddr[j] = busaddr;
+			}
+
+			/*
+			 * Create a DMA tag for RX SGE bufs.
+			 */
+			if (bus_dma_tag_create(sc->parent_tag, 1,
+			    BXE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
+			    BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1,
+			    PAGE_SIZE, 0, NULL, NULL, &fp->rx_sge_buf_tag)) {
+				BXE_PRINTF(
+		"%s(%d): Could not allocate fp[%d] RX SGE mbuf DMA tag!\n",
+				    __FILE__, __LINE__, i);
+				rc = ENOMEM;
+				goto bxe_dma_alloc_exit;
+			}
+
+			/* Create DMA maps for the SGE mbuf clusters. */
+			for (j = 0; j < TOTAL_RX_SGE; j++) {
+				if (bus_dmamap_create(fp->rx_sge_buf_tag,
+				    BUS_DMA_NOWAIT, &(fp->rx_sge_buf_map[j]))) {
+					BXE_PRINTF(
+		"%s(%d): Unable to create fp[%d] RX SGE mbuf DMA map!\n",
+					    __FILE__, __LINE__, i);
+					rc = ENOMEM;
+					goto bxe_dma_alloc_exit;
+				}
+			}
+
+			/* Create DMA maps for the TPA pool mbufs. */
+			for (j = 0; j < tpa_pool_max; j++) {
+				if (bus_dmamap_create(fp->rx_mbuf_tag,
+				    BUS_DMA_NOWAIT, &(fp->tpa_mbuf_map[j]))) {
+					BXE_PRINTF(
+			"%s(%d): Unable to create fp[%d] TPA DMA map!\n",
+					    __FILE__, __LINE__, i);
+					rc = ENOMEM;
+					goto bxe_dma_alloc_exit;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Create a DMA tag for the def_status block, allocate and clear the
+	 * memory, map the memory into DMA space, and fetch the physical
+	 * address of the block.
+	 */
+	if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BXE_DMA_BOUNDARY,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+	    BXE_DEF_STATUS_BLK_SZ, 1, BXE_DEF_STATUS_BLK_SZ, 0, NULL, NULL,
+	    &sc->def_status_block_tag)) {
+		BXE_PRINTF(
+		    "%s(%d): Could not allocate def_status block DMA tag!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	if (bus_dmamem_alloc(sc->def_status_block_tag,
+	    (void **)&sc->def_status_block, BUS_DMA_NOWAIT,
+	    &sc->def_status_block_map)) {
+		BXE_PRINTF(
+		    "%s(%d): Could not allocate def_status block DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	bzero((char *)sc->def_status_block, BXE_DEF_STATUS_BLK_SZ);
+
+	error = bus_dmamap_load(sc->def_status_block_tag,
+	    sc->def_status_block_map, sc->def_status_block,
+	    BXE_DEF_STATUS_BLK_SZ, bxe_dma_map_addr, &busaddr, BUS_DMA_NOWAIT);
+
+	if (error) {
+		BXE_PRINTF(
+		    "%s(%d): Could not map def_status block DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	/* Physical Address of Default Status Block. */
+	sc->def_status_block_paddr = busaddr;
+	DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+	    "%s(): Default status block physical address = 0x%08X\n",
+	    __FUNCTION__, (uint32_t)sc->def_status_block_paddr);
+
+	/*
+	 * Create a DMA tag for the statistics block, allocate and clear the
+	 * memory, map the memory into DMA space, and fetch the physical
+	 * address of the block.
+	 */
+	if (bus_dma_tag_create(sc->parent_tag, BXE_DMA_ALIGN, BXE_DMA_BOUNDARY,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BXE_STATS_BLK_SZ,
+	    1, BXE_STATS_BLK_SZ, 0, NULL, NULL, &sc->stats_tag)) {
+		BXE_PRINTF(
+		    "%s(%d): Could not allocate statistics block DMA tag!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
+	    BUS_DMA_NOWAIT, &sc->stats_map)) {
+		BXE_PRINTF(
+		    "%s(%d): Could not allocate statistics block DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	bzero((char *)sc->stats_block, BXE_STATS_BLK_SZ);
+
+	error = bus_dmamap_load(sc->stats_tag, sc->stats_map, sc->stats_block,
+	    BXE_STATS_BLK_SZ, bxe_dma_map_addr, &busaddr, BUS_DMA_NOWAIT);
+
+	if (error) {
+		BXE_PRINTF(
+		    "%s(%d): Could not map statistics block DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	/* Physical Address of Statistics Block. */
+	sc->stats_block_paddr = busaddr;
+	DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+	    "%s(): Statistics block physical address = 0x%08X\n",
+	    __FUNCTION__, (uint32_t)sc->stats_block_paddr);
+
+	/*
+	 * Create a DMA tag for slowpath memory, allocate and clear the
+	 * memory, map the memory into DMA space, and fetch the physical
+	 * address of the block.
+	 */
+	if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BXE_DMA_BOUNDARY,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BXE_SLOWPATH_SZ,
+	    1, BXE_SLOWPATH_SZ, 0, NULL, NULL, &sc->slowpath_tag)) {
+		BXE_PRINTF(
+		    "%s(%d): Could not allocate slowpath DMA tag!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	if (bus_dmamem_alloc(sc->slowpath_tag, (void **)&sc->slowpath,
+	    BUS_DMA_NOWAIT, &sc->slowpath_map)) {
+		BXE_PRINTF(
+		    "%s(%d): Could not allocate slowpath DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	bzero((char *)sc->slowpath, BXE_SLOWPATH_SZ);
+
+	error = bus_dmamap_load(sc->slowpath_tag, sc->slowpath_map,
+	    sc->slowpath, BXE_SLOWPATH_SZ, bxe_dma_map_addr, &busaddr,
+	    BUS_DMA_NOWAIT);
+
+	if (error) {
+		BXE_PRINTF("%s(%d): Could not map slowpath DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	/* Physical Address For Slow Path Context. */
+	sc->slowpath_paddr = busaddr;
+	DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
+	    "%s(): Slowpath context physical address = 0x%08X\n",
+		__FUNCTION__, (uint32_t)sc->slowpath_paddr);
+
+	/*
+	 * Create a DMA tag for the Slow Path Queue, allocate and clear the
+	 * memory, map the memory into DMA space, and fetch the physical
+	 * address of the block.
+	 */
+	if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BXE_DMA_BOUNDARY,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BXE_SPQ_SZ, 1,
+	    BXE_SPQ_SZ, 0, NULL, NULL, &sc->spq_tag)) {
+		BXE_PRINTF("%s(%d): Could not allocate SPQ DMA tag!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	if (bus_dmamem_alloc(sc->spq_tag, (void **)&sc->spq, BUS_DMA_NOWAIT,
+	    &sc->spq_map)) {
+		BXE_PRINTF("%s(%d): Could not allocate SPQ DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	bzero((char *)sc->spq, BXE_SPQ_SZ);
+
+	error = bus_dmamap_load(sc->spq_tag, sc->spq_map, sc->spq, BXE_SPQ_SZ,
+	    bxe_dma_map_addr, &busaddr, BUS_DMA_NOWAIT);
+
+	if (error) {
+		BXE_PRINTF("%s(%d): Could not map SPQ DMA memory!\n",
+			__FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+	/* Physical address of slow path queue. */
+	sc->spq_paddr = busaddr;
+	DBPRINT(sc, (BXE_EXTREME_LOAD | BXE_EXTREME_RESET),
+	    "%s(): Slowpath queue physical address = 0x%08X\n",
+	    __FUNCTION__, (uint32_t)sc->spq_paddr);
+
+	if (bxe_gunzip_init(sc)) {
+		rc = ENOMEM;
+		goto bxe_dma_alloc_exit;
+	}
+
+bxe_dma_alloc_exit:
+	DBEXIT(BXE_VERBOSE_RESET);
+	return (rc);
+}
+
+/*
+ * Allocate DMA memory used for the firmware gunzip memory.
+ *
+ * Returns:
+ *   0 for success, !0 = Failure.
+ */
+
+static int
+bxe_dmamem_alloc(struct bxe_softc *sc, bus_dma_tag_t tag, bus_dmamap_t map,
+    void *buf, uint32_t buflen, bus_addr_t *busaddr)
+{
+	int rc;
+
+	rc = 0;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	/*
+	 * Create a DMA tag for the block, allocate and clear the
+	 * memory, map the memory into DMA space, and fetch the physical
+	 * address of the block.
+	 */
+	if (bus_dma_tag_create(sc->parent_tag, BXE_DMA_ALIGN, BXE_DMA_BOUNDARY,
+	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, buflen, 1, buflen,
+	    0, NULL, NULL, &sc->gunzip_tag)) {
+		BXE_PRINTF("%s(%d): Could not allocate DMA tag!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dmamem_alloc_exit;
+	}
+
+	if (bus_dmamem_alloc(sc->gunzip_tag, (void **)&sc->gunzip_buf,
+	    BUS_DMA_NOWAIT, &sc->gunzip_map)) {
+		BXE_PRINTF("%s(%d): Could not allocate DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+		goto bxe_dmamem_alloc_exit;
+	}
+
+	bzero((char *)sc->gunzip_buf, buflen);
+
+	if (bus_dmamap_load(sc->gunzip_tag, sc->gunzip_map, sc->gunzip_buf,
+	    buflen, bxe_dma_map_addr, busaddr, BUS_DMA_NOWAIT)) {
+		BXE_PRINTF("%s(%d): Could not map DMA memory!\n",
+		    __FILE__, __LINE__);
+		rc = ENOMEM;
+	}
+
+bxe_dmamem_alloc_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+	return (rc);
+}
+
+/*
+ * Program the MAC address for 57710 controllers.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_set_mac_addr_e1(struct bxe_softc *sc, int set)
+{
+	struct mac_configuration_cmd *config;
+	int port;
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	config = BXE_SP(sc, mac_config);
+	port = BP_PORT(sc);
+	/*
+	 * CAM allocation:
+	 * Port 0 Unicast Addresses: 32 Perfect Match Filters (31-0)
+	 * Port 1 Unicast Addresses: 32 Perfect Match Filters (63-32)
+	 * Port 0 Multicast Addresses: 128 Hashes (127-64)
+	 * Port 1 Multicast Addresses: 128 Hashes (191-128)
+	 */
+
+	config->hdr.length = 2;
+	config->hdr.offset = port ? 32 : 0;
+	config->hdr.client_id = BP_CL_ID(sc);
+	config->hdr.reserved1 = 0;
+
+	/* Program the primary MAC address. */
+	config->config_table[0].cam_entry.msb_mac_addr =
+	    ntohs(*(uint16_t *)&sc->link_params.mac_addr[0]);
+	config->config_table[0].cam_entry.middle_mac_addr =
+	    ntohs(*(uint16_t *)&sc->link_params.mac_addr[2]);
+	config->config_table[0].cam_entry.lsb_mac_addr =
+	    ntohs(*(uint16_t *)&sc->link_params.mac_addr[4]);
+	config->config_table[0].cam_entry.flags = htole16(port);
+
+	if (set)
+		config->config_table[0].target_table_entry.flags = 0;
+	else
+		CAM_INVALIDATE(config->config_table[0]);
+
+	/* t48 	config->config_table[0].target_table_entry.client_id = 0; */
+	config->config_table[0].target_table_entry.vlan_id = 0;
+
+	DBPRINT(sc, BXE_VERBOSE, "%s(): %s MAC (%04x:%04x:%04x)\n",
+	   __FUNCTION__, (set ? "Setting" : "Clearing"),
+	   config->config_table[0].cam_entry.msb_mac_addr,
+	   config->config_table[0].cam_entry.middle_mac_addr,
+	   config->config_table[0].cam_entry.lsb_mac_addr);
+
+	/* Program the broadcast MAC address. */
+	config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
+	config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
+	config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
+	config->config_table[1].cam_entry.flags = htole16(port);
+
+	if (set)
+		config->config_table[1].target_table_entry.flags =
+		    TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
+	else
+		CAM_INVALIDATE(config->config_table[1]);
+
+	/*t48	config->config_table[1].target_table_entry.client_id = 0; */
+	config->config_table[1].target_table_entry.vlan_id = 0;
+
+
+	/* Post the command to slow path queue. */
+	bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+	    U64_HI(BXE_SP_MAPPING(sc, mac_config)),
+	    U64_LO(BXE_SP_MAPPING(sc, mac_config)), 0);
+
+	DBEXIT(BXE_VERBOSE_MISC);
+}
+
+/*
+ * Program the MAC address for 57711/57711E controllers.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_set_mac_addr_e1h(struct bxe_softc *sc, int set)
+{
+	struct mac_configuration_cmd_e1h *config;
+	int func, port;
+
+	DBENTER(BXE_VERBOSE_MISC);
+
+	config = (struct mac_configuration_cmd_e1h *)BXE_SP(sc, mac_config);
+	port = BP_PORT(sc);
+	func = BP_FUNC(sc);
+
+	if (set && (sc->state != BXE_STATE_OPEN)) {
+		DBPRINT(sc, BXE_VERBOSE,
+		    "%s(): Can't set E1H MAC in state 0x%08X!\n", __FUNCTION__,
+		    sc->state);
+		goto bxe_set_mac_addr_e1h_exit;
+	}
+
+	/*
+	 * CAM allocation:
+	 * Function 0-7 Unicast Addresses: 8 Perfect Match Filters
+	 * Multicast Addresses: 20 + FUNC * 20, 20 each (???)
+	 */
+	config->hdr.length = 1;
+	config->hdr.offset = func;
+	config->hdr.client_id = 0xff;
+	config->hdr.reserved1 = 0;
+
+	/* Program the primary MAC address. */
+	config->config_table[0].msb_mac_addr =
+	    ntohs(*(uint16_t *)&sc->link_params.mac_addr[0]);
+	config->config_table[0].middle_mac_addr =
+	    ntohs(*(uint16_t *)&sc->link_params.mac_addr[2]);
+	config->config_table[0].lsb_mac_addr =
+	    ntohs(*(uint16_t *)&sc->link_params.mac_addr[4]);
+	config->config_table[0].clients_bit_vector =
+	    htole32(1 << sc->fp->cl_id);
+
+	config->config_table[0].vlan_id = 0;
+	config->config_table[0].e1hov_id = htole16(sc->e1hov);
+
+	if (set)
+		config->config_table[0].flags = port;
+	else
+		config->config_table[0].flags =
+			MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
+
+	DBPRINT(sc, BXE_VERBOSE_MISC,
+	    "%s(): %s MAC (%04x:%04x:%04x), E1HOV = %d, CLID = %d\n",
+	    __FUNCTION__, (set ? "Setting" : "Clearing"),
+	    config->config_table[0].msb_mac_addr,
+	    config->config_table[0].middle_mac_addr,
+	    config->config_table[0].lsb_mac_addr, sc->e1hov, BP_L_ID(sc));
+
+	bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+	    U64_HI(BXE_SP_MAPPING(sc, mac_config)),
+	    U64_LO(BXE_SP_MAPPING(sc, mac_config)), 0);
+
+bxe_set_mac_addr_e1h_exit:
+	DBEXIT(BXE_VERBOSE_MISC);
+}
+
+/*
+ * Programs the various packet receive modes (broadcast and multicast).
+ *
+ * Returns:
+ *   Nothing.
+ */
+
+static void
+bxe_set_rx_mode(struct bxe_softc *sc)
+{
+	struct ifnet *ifp;
+	struct ifmultiaddr *ifma;
+	struct mac_configuration_cmd *config;
+	uint32_t mc_filter[MC_HASH_SIZE];
+	uint32_t crc, bit, regidx, rx_mode;
+	int i, old, offset, port;
+
+	BXE_CORE_LOCK_ASSERT(sc);
+
+	rx_mode = BXE_RX_MODE_NORMAL;
+	port = BP_PORT(sc);
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+
+	if (sc->state != BXE_STATE_OPEN) {
+		DBPRINT(sc, BXE_WARN, "%s(): State (0x%08X) is not open!\n",
+		    __FUNCTION__, sc->state);
+		goto bxe_set_rx_mode_exit;
+	}
+
+	ifp = sc->bxe_ifp;
+
+	/*
+	 * Check for promiscuous, all multicast, or selected
+	 * multicast address filtering.
+	 */
+	if (ifp->if_flags & IFF_PROMISC) {
+		DBPRINT(sc, BXE_INFO, "%s(): Enabling promiscuous mode.\n",
+		    __FUNCTION__);
+
+		/* Enable promiscuous mode. */
+		rx_mode = BXE_RX_MODE_PROMISC;
+	} else if ((ifp->if_flags & IFF_ALLMULTI) ||
+	    (ifp->if_amcount > BXE_MAX_MULTICAST)) {
+		DBPRINT(sc, BXE_INFO, "%s(): Enabling all multicast mode.\n",
+		    __FUNCTION__);
+
+		/* Enable all multicast addresses. */
+		rx_mode = BXE_RX_MODE_ALLMULTI;
+	} else {
+		/* Enable selective multicast mode. */
+		DBPRINT(sc, BXE_INFO,
+		    "%s(): Enabling selective multicast mode.\n", __FUNCTION__);
+
+		if (CHIP_IS_E1(sc)) {
+			i = 0;
+			config = BXE_SP(sc, mcast_config);
+
+			IF_ADDR_LOCK(ifp);
+
+			TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+				if (ifma->ifma_addr->sa_family != AF_LINK)
+					continue;
+
+				config->config_table[i].cam_entry.msb_mac_addr =
+					bswap16(*(uint32_t *)(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)));
+				config->config_table[i].cam_entry.middle_mac_addr =
+					bswap16(*(uint16_t *)(LLADDR((struct sockaddr_dl *)ifma->ifma_addr) + 2));
+				config->config_table[i].cam_entry.lsb_mac_addr =
+					bswap16(*(uint16_t *)(LLADDR((struct sockaddr_dl *)ifma->ifma_addr) + 4));
+
+				config->config_table[i].cam_entry.flags = htole16(port);
+				config->config_table[i].target_table_entry.flags = 0;
+				config->config_table[i].target_table_entry.
+					clients_bit_vector = htole32(1 << BP_L_ID(sc));
+				config->config_table[i].target_table_entry.vlan_id = 0;
+
+				i++;
+
+				DBPRINT(sc, BXE_INFO,
+			"%s(): Setting MCAST[%d] (%04X:%04X:%04X)\n",
+				    __FUNCTION__, i,
+				    config->config_table[i].cam_entry.msb_mac_addr,
+				    config->config_table[i].cam_entry.middle_mac_addr,
+				    config->config_table[i].cam_entry.lsb_mac_addr);
+			}
+
+			IF_ADDR_UNLOCK(ifp);
+
+			old = config->hdr.length;
+
+			/* Invalidate any extra MC entries in the CAM. */
+			if (old > i) {
+				for (; i < old; i++) {
+					if (CAM_IS_INVALID(
+					    config->config_table[i]))
+						break;
+					/* Invalidate */
+					CAM_INVALIDATE(config->config_table[i]);
+				}
+			}
+
+			offset = BXE_MAX_MULTICAST * (1 + port);
+			config->hdr.length = i;
+			config->hdr.offset = offset;
+			config->hdr.client_id = sc->fp->cl_id;
+			config->hdr.reserved1 = 0;
+			wmb();
+			bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+			    U64_HI(BXE_SP_MAPPING(sc, mcast_config)),
+			    U64_LO(BXE_SP_MAPPING(sc, mcast_config)), 0);
+
+		} else { /* E1H */
+			/* Accept one or more multicasts */
+			memset(mc_filter, 0, 4 * MC_HASH_SIZE);
+
+			IF_ADDR_LOCK(ifp);
+
+			TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+				if (ifma->ifma_addr->sa_family != AF_LINK)
+					continue;
+				crc = ether_crc32_le(ifma->ifma_addr->sa_data,
+				    ETHER_ADDR_LEN);
+				bit = (crc >> 24) & 0xff;
+				regidx = bit >> 5;
+				bit &= 0x1f;
+				mc_filter[regidx] |= (1 << bit);
+			}
+			IF_ADDR_UNLOCK(ifp);
+
+			for (i = 0; i < MC_HASH_SIZE; i++)
+				REG_WR(sc, MC_HASH_OFFSET(sc, i), mc_filter[i]);
+		}
+	}
+
+	DBPRINT(sc, BXE_VERBOSE, "%s(): Enabling new receive mode: 0x%08X\n",
+	    __FUNCTION__, rx_mode);
+
+	sc->rx_mode = rx_mode;
+	bxe_set_storm_rx_mode(sc);
+
+bxe_set_rx_mode_exit:
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
+}
+
+/*
+ * Function specific controller reset.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_reset_func(struct bxe_softc *sc)
+{
+	int base, func, i, port;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+
+	port = BP_PORT(sc);
+	func = BP_FUNC(sc);
+
+	/* Configure IGU. */
+	REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
+	REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
+
+	REG_WR(sc, HC_REG_CONFIG_0 + (port * 4), 0x1000);
+
+	/* Clear ILT. */
+	base = FUNC_ILT_BASE(func);
+	for (i = base; i < base + ILT_PER_FUNC; i++)
+		bxe_ilt_wr(sc, i, 0);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+}
+
+/*
+ * Port specific controller reset.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_reset_port(struct bxe_softc *sc)
+{
+	uint32_t val;
+	int port;
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+
+	port = BP_PORT(sc);
+	REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
+
+	/* Do not receive packets to BRB. */
+	REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
+
+	/* Do not direct receive packets that are not for MCP to the BRB. */
+	REG_WR(sc, port ? NIG_REG_LLH1_BRB1_NOT_MCP :
+	    NIG_REG_LLH0_BRB1_NOT_MCP, 0x0);
+
+	/* Configure AEU. */
+	REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
+
+	DELAY(100000);
+
+	/* Check for BRB port occupancy. */
+	val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
+	if (val)
+		DBPRINT(sc, BXE_VERBOSE,
+		    "%s(): BRB1 is not empty (%d blocks are occupied)!\n",
+		    __FUNCTION__, val);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+}
+
+/*
+ * Common controller reset.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_reset_common(struct bxe_softc *sc)
+{
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0xd3ffff7f);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+}
+
+/*
+ * Reset the controller.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_reset_chip(struct bxe_softc *sc, uint32_t reset_code)
+{
+
+	DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+	DBRUNLV(BXE_INFO, bxe_decode_mb_msgs(sc, 0, reset_code));
+
+	switch (reset_code) {
+	case FW_MSG_CODE_DRV_UNLOAD_COMMON:
+		bxe_reset_port(sc);
+		bxe_reset_func(sc);
+		bxe_reset_common(sc);
+		break;
+	case FW_MSG_CODE_DRV_UNLOAD_PORT:
+		bxe_reset_port(sc);
+		bxe_reset_func(sc);
+		break;
+	case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
+		bxe_reset_func(sc);
+		break;
+	default:
+		BXE_PRINTF("%s(%d): Unknown reset code (0x%08X) from MCP!\n",
+		    __FILE__, __LINE__, reset_code);
+		break;
+	}
+
+	DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
+}
+
+/*
+ * Called by the OS to set media options (link, speed, etc.).
+ *
+ * Returns:
+ *   0 = Success, positive value for failure.
+ */
+static int
+bxe_ifmedia_upd(struct ifnet *ifp)
+{
+	struct bxe_softc *sc;
+	struct ifmedia *ifm;
+	int rc;
+
+	sc = ifp->if_softc;
+	DBENTER(BXE_VERBOSE_PHY);
+
+	ifm = &sc->bxe_ifmedia;
+	rc = 0;
+	/* This is an Ethernet controller. */
+	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
+		rc = EINVAL;
+		goto bxe_ifmedia_upd_exit;
+	}
+
+	BXE_CORE_LOCK(sc);
+
+	switch (IFM_SUBTYPE(ifm->ifm_media)) {
+	case IFM_AUTO:
+		 DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "%s(): Media set to IFM_AUTO, restarting autonegotiation.\n",
+		    __FUNCTION__);
+		 break;
+	case IFM_10G_CX4:
+		DBPRINT(sc, BXE_VERBOSE_PHY,
+	    "%s(): Media set to IFM_10G_CX4, forced mode.\n", __FUNCTION__);
+		break;
+	default:
+		DBPRINT(sc, BXE_WARN, "%s(): Invalid media type!\n",
+		    __FUNCTION__);
+		rc = EINVAL;
+	}
+
+	BXE_CORE_UNLOCK(sc);
+
+bxe_ifmedia_upd_exit:
+	DBENTER(BXE_VERBOSE_PHY);
+	return (rc);
+}
+
+/*
+ * Called by the OS to report current media status
+ * (link, speed, etc.).
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct bxe_softc *sc;
+
+	sc = ifp->if_softc;
+	DBENTER(BXE_EXTREME_LOAD | BXE_EXTREME_RESET);
+
+	/* Report link down if the driver isn't running. */
+	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
+		ifmr->ifm_active |= IFM_NONE;
+		goto bxe_ifmedia_status_exit;
+	}
+
+	/* Setup the default interface info. */
+	ifmr->ifm_status = IFM_AVALID;
+	ifmr->ifm_active = IFM_ETHER;
+
+	if (sc->link_vars.link_up)
+		ifmr->ifm_status |= IFM_ACTIVE;
+	else {
+		ifmr->ifm_active |= IFM_NONE;
+		goto bxe_ifmedia_status_exit;
+	}
+
+	ifmr->ifm_active |= IFM_10G_CX4;
+
+	if (sc->link_vars.duplex == MEDIUM_FULL_DUPLEX)
+		ifmr->ifm_active |= IFM_FDX;
+	else
+		ifmr->ifm_active |= IFM_HDX;
+
+bxe_ifmedia_status_exit:
+	DBEXIT(BXE_EXTREME_LOAD | BXE_EXTREME_RESET);
+}
+
+
+/*
+ * Update last maximum scatter gather entry.
+ *
+ * Returns:
+ *   None.
+ */
+static __inline void
+bxe_update_last_max_sge(struct bxe_fastpath *fp, uint16_t idx)
+{
+	uint16_t last_max;
+
+	last_max = fp->last_max_sge;
+	if (SUB_S16(idx, last_max) > 0)
+		fp->last_max_sge = idx;
+}
+
+/*
+ * Clear scatter gather mask next elements.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
+{
+	int i, idx, j;
+
+	for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
+		idx = RX_SGE_CNT * i - 1;
+		for (j = 0; j < 2; j++) {
+			SGE_MASK_CLEAR_BIT(fp, idx);
+			idx--;
+		}
+	}
+}
+
+/*
+ * Update SGE producer.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_update_sge_prod(struct bxe_fastpath *fp,
+    struct eth_fast_path_rx_cqe *fp_cqe)
+{
+	struct bxe_softc *sc;
+	uint16_t delta, last_max, last_elem, first_elem, sge_len;
+	int i;
+
+	sc = fp->sc;
+	DBENTER(BXE_EXTREME_RECV);
+
+	delta = 0;
+	sge_len = SGE_PAGE_ALIGN(le16toh(fp_cqe->pkt_len) -
+	    le16toh(fp_cqe->len_on_bd)) >> SGE_PAGE_SHIFT;
+	if (!sge_len)
+		return;
+
+	/* First mark all used pages. */
+	for (i = 0; i < sge_len; i++)
+		SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16toh(fp_cqe->sgl[i])));
+
+	/* Assume that the last SGE index is the biggest. */
+	bxe_update_last_max_sge(fp, le16toh(fp_cqe->sgl[sge_len - 1]));
+
+	last_max = RX_SGE(fp->last_max_sge);
+	last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
+	first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
+
+	/* If ring is not full. */
+	if (last_elem + 1 != first_elem)
+		last_elem++;
+
+	/* Now update the producer index. */
+	for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
+		if (fp->sge_mask[i])
+			break;
+
+		fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
+		delta += RX_SGE_MASK_ELEM_SZ;
+	}
+
+	if (delta > 0) {
+		fp->rx_sge_prod += delta;
+		/* clear page-end entries */
+		bxe_clear_sge_mask_next_elems(fp);
+	}
+
+	DBEXIT(BXE_EXTREME_RECV);
+}
+
+/*
+ * Initialize scatter gather ring bitmask.
+ *
+ * Elements may be taken from the scatter gather ring out of order since
+ * TCP frames may be out of order or intermingled among multiple TCP
+ * flows on the wire.  The SGE bitmask tracks which elements are used
+ * or available.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
+{
+
+	/* Set the mask to all 1s, it's faster to compare to 0 than to 0xf. */
+	memset(fp->sge_mask, 0xff,
+	    (TOTAL_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT) * sizeof(uint64_t));
+
+	/*
+	 * Clear the two last indices in the page to 1.  These are the
+	 * indices that correspond to the "next" element which will
+	 * never be indicated and should be removed from calculations.
+	 */
+	bxe_clear_sge_mask_next_elems(fp);
+}
+
+/*
+ * The current mbuf is part of an aggregation.  Swap the mbuf into the TPA
+ * aggregation queue, swap an empty mbuf back onto the receive chain, and
+ * mark the current aggregation queue as in-progress.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_tpa_start(struct bxe_fastpath *fp, uint16_t queue, uint16_t cons,
+    uint16_t prod)
+{
+	struct bxe_softc *sc = fp->sc;
+	struct mbuf *m_temp;
+	struct eth_rx_bd *rx_bd;
+	bus_dmamap_t map_temp;
+
+	sc = fp->sc;
+	DBENTER(BXE_EXTREME_RECV);
+
+	/* Move the empty mbuf and mapping from the TPA pool. */
+	m_temp = fp->tpa_mbuf_ptr[queue];
+	map_temp = fp->tpa_mbuf_map[queue];
+
+	/* Move received mbuf and mapping to TPA pool. */
+	fp->tpa_mbuf_ptr[queue] = fp->rx_mbuf_ptr[cons];
+	fp->tpa_mbuf_map[queue] = fp->rx_mbuf_map[cons];
+
+	DBRUNIF((fp->tpa_state[queue] != BXE_TPA_STATE_STOP),
+	    DBPRINT(sc, BXE_FATAL, "%s(): Starting bin[%d] even though queue "
+	    "is not in the TPA_STOP state!\n", __FUNCTION__, queue));
+
+	/* Place the TPA bin into the START state. */
+	fp->tpa_state[queue] = BXE_TPA_STATE_START;
+	DBRUN(fp->tpa_queue_used |= (1 << queue));
+
+	/* Get the rx_bd for the next open entry on the receive chain. */
+	rx_bd = &fp->rx_bd_chain[RX_PAGE(prod)][RX_IDX(prod)];
+
+	/* Update the rx_bd with the empty mbuf from the TPA pool. */
+	rx_bd->addr_hi = htole32(U64_HI(fp->tpa_mbuf_segs[queue].ds_addr));
+	rx_bd->addr_lo = htole32(U64_LO(fp->tpa_mbuf_segs[queue].ds_addr));
+	fp->rx_mbuf_ptr[prod] = m_temp;
+	fp->rx_mbuf_map[prod] = map_temp;
+
+	DBEXIT(BXE_EXTREME_RECV);
+}
+
+/*
+ * When a TPA aggregation is completed, loop through the individual mbufs
+ * of the aggregation, combining them into a single mbuf which will be sent
+ * up the stack.  Refill all mbufs freed as we go along.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_fill_frag_mbuf(struct bxe_softc *sc, struct bxe_fastpath *fp,
+    struct mbuf *m, struct eth_fast_path_rx_cqe *fp_cqe, uint16_t cqe_idx)
+{
+	uint32_t frag_len, frag_size, pages, i;
+	uint16_t sge_idx, len_on_bd;
+	int rc, j;
+
+	DBENTER(BXE_EXTREME_RECV);
+
+	rc = 0;
+	len_on_bd = le16toh(fp_cqe->len_on_bd);
+	frag_size = le16toh(fp_cqe->pkt_len) - len_on_bd;
+	pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
+
+	/* Make sure the aggregated frame is not too big to handle. */
+	if (pages > 8 * PAGES_PER_SGE) {
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): SGL length (%d) is too long! CQE index is %d\n",
+		    __FUNCTION__, pages, cqe_idx);
+		DBPRINT(sc, BXE_FATAL,
+		    "%s(): fp_cqe->pkt_len = %d fp_cqe->len_on_bd = %d\n",
+		    __FUNCTION__, le16toh(fp_cqe->pkt_len), len_on_bd);
+		bxe_panic_dump(sc);
+		rc = EINVAL;
+		goto bxe_fill_frag_mbuf_exit;
+	}
+
+	/*
+	 * Run through the scatter gather list, pulling the individual
+	 * mbufs into a single mbuf for the host stack.
+	 */
+	for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
+		sge_idx = RX_SGE(le16toh(fp_cqe->sgl[j]));
+
+		/*
+		 * Firmware gives the indices of the SGE as if the ring is an
+		 * array (meaning that the "next" element will consume 2
+		 * indices).
+		 */
+		frag_len = min(frag_size, (uint32_t)(BCM_PAGE_SIZE *
+		    PAGES_PER_SGE));
+
+		/* Update the mbuf with the fragment length. */
+		fp->rx_sge_buf_ptr[sge_idx]->m_len = frag_len;
+
+		/* Unmap the mbuf from DMA space. */
+		bus_dmamap_sync(fp->rx_sge_buf_tag, fp->rx_sge_buf_map[sge_idx],
+		    BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(fp->rx_sge_buf_tag,
+		    fp->rx_sge_buf_map[sge_idx]);
+
+		/* Concatenate the current fragment to the aggregated mbuf. */
+		m_cat(m, fp->rx_sge_buf_ptr[sge_idx]);
+
+		/* The SGE mbuf was freed in the call to m_cat(). */
+		DBRUN(fp->sge_mbuf_alloc--);
+		fp->rx_sge_buf_ptr[sge_idx] = NULL;
+
+		/*
+		 * Try an allocate a new mbuf for the SGE that was just
+		 * released. If an allocation error occurs stop where we
+		 * are and drop the whole frame.
+		 */
+		rc = bxe_alloc_rx_sge(sc, fp, sge_idx);
+		if (rc)
+			goto bxe_fill_frag_mbuf_exit;
+
+		m->m_pkthdr.len += frag_len;
+
+		frag_size -= frag_len;
+	}
+
+bxe_fill_frag_mbuf_exit:
+	DBEXIT(BXE_EXTREME_RECV);
+	return (rc);
+}
+
+/*
+ * The aggregation on the current TPA queue has completed.  Pull the
+ * individual mbuf fragments together into a single mbuf, perform all
+ * necessary checksum calculations, and send the resuting mbuf to the stack.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_tpa_stop(struct bxe_softc *sc, struct bxe_fastpath *fp, uint16_t queue,
+    int pad, int len, union eth_rx_cqe *cqe, uint16_t cqe_idx)
+{
+	struct mbuf *m_old, *m_new;
+	struct ip *ip;
+	struct ifnet *ifp;
+	struct ether_vlan_header *eh;
+	bus_dma_segment_t seg;
+	int rc, e_hlen;
+
+	DBENTER(BXE_EXTREME_RECV);
+	DBPRINT(sc, BXE_VERBOSE_RECV,
+	    "%s(): fp[%d], tpa queue = %d, len = %d, pad = %d\n", __FUNCTION__,
+	    fp->index, queue, len, pad);
+
+	rc = 0;
+	ifp = sc->bxe_ifp;
+	/* Unmap m_old from DMA space. */
+	m_old = fp->tpa_mbuf_ptr[queue];
+	bus_dmamap_sync(fp->rx_mbuf_tag, fp->tpa_mbuf_map[queue],
+	    BUS_DMASYNC_POSTREAD);
+	bus_dmamap_unload(fp->rx_mbuf_tag, fp->tpa_mbuf_map[queue]);
+
+	/* Skip over the pad when passing the data up the stack. */
+	m_adj(m_old, pad);
+
+	/* Adjust the packet length to match the received data. */
+	m_old->m_pkthdr.len = m_old->m_len = len;
+
+	/* Validate the checksum if offload enabled. */
+	m_old->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID |
+	    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
+	m_old->m_pkthdr.csum_data = 0xffff;
+
+	/* Map the header and find the Ethernet type & header length. */
+	eh = mtod(m_old, struct ether_vlan_header *);
+	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN))
+		e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
+	else
+		e_hlen = ETHER_HDR_LEN;
+
+	/* Get the IP header pointer. */
+	ip = (struct ip *)(m_old->m_data + e_hlen);
+
+	ip->ip_sum = 0;
+	ip->ip_sum = in_cksum_hdr(ip);
+
+	/* Try and aggregate all of the receive mbufs into a single mbuf. */
+	if (!bxe_fill_frag_mbuf(sc, fp, m_old, &cqe->fast_path_cqe, cqe_idx)) {
+		/*
+		 * We have an aggregated frame.  If the frame has a vlan tag
+		 * attach that information to the mbuf.
+		 */
+		if ((le16toh(cqe->fast_path_cqe.pars_flags.flags) &
+		    PARSING_FLAGS_VLAN)) {
+			m_old->m_pkthdr.ether_vtag =
+			    cqe->fast_path_cqe.vlan_tag;
+			m_old->m_flags |= M_VLANTAG;
+		}
+
+		/* Send the packet to the appropriate interface. */
+		m_old->m_pkthdr.rcvif = ifp;
+
+		/* Pass the packet up to the stack. */
+		fp->ipackets++;
+		DBRUN(fp->tpa_pkts++);
+		(*ifp->if_input)(ifp, m_old);
+	} else 	{
+		DBPRINT(sc, BXE_WARN,
+		    "%s(): Failed to allocate new SGE page, dropping frame!\n",
+		    __FUNCTION__);
+		fp->soft_rx_errors++;
+		m_freem(m_old);
+	}
+
+	/* We passed m_old up the stack or dropped the frame. */
+	DBRUN(fp->tpa_mbuf_alloc--);
+
+	/* Allocate a replacement mbuf. */
+	if (__predict_false((m_new = bxe_alloc_mbuf(fp,
+	    sc->mbuf_alloc_size)) == NULL))
+		goto bxe_tpa_stop_exit;
+
+	/* Map the new mbuf and place it in the pool. */
+	rc = bxe_map_mbuf(fp, m_new, fp->rx_mbuf_tag,
+		fp->tpa_mbuf_map[queue], &seg);
+	if (rc)
+		goto bxe_tpa_stop_exit;
+
+	DBRUN(fp->tpa_mbuf_alloc++);
+
+	fp->tpa_mbuf_ptr[queue] = m_new;
+	fp->tpa_mbuf_segs[queue] = seg;
+
+bxe_tpa_stop_exit:
+	fp->tpa_state[queue] = BXE_TPA_STATE_STOP;
+	DBRUN(fp->tpa_queue_used &= ~(1 << queue));
+
+	DBEXIT(BXE_EXTREME_RECV);
+}
+
+/*
+ * Notify the controller that the RX producer indices have been updated for
+ * a fastpath connection by writing them to the controller.
+ *
+ * Returns:
+ *   None
+ */
+static __inline void
+bxe_update_rx_prod(struct bxe_softc *sc, struct bxe_fastpath *fp,
+    uint16_t bd_prod, uint16_t rx_comp_prod, uint16_t rx_sge_prod)
+{
+	volatile struct ustorm_eth_rx_producers rx_prods = {0};
+	int i;
+
+	/* Update producers. */
+	rx_prods.bd_prod =  bd_prod;/* htole16(bd_prod);*/
+	rx_prods.cqe_prod = rx_comp_prod;/*htole16(rx_comp_prod);*/
+	rx_prods.sge_prod = rx_sge_prod;/*htole16(rx_sge_prod);*/
+
+	wmb();
+
+	for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++){
+		REG_WR(sc, BAR_USTORM_INTMEM +
+		    USTORM_RX_PRODS_OFFSET(BP_PORT(sc), fp->cl_id) + i * 4,
+		    ((volatile uint32_t *)&rx_prods)[i]);
+	}
+
+	DBPRINT(sc, BXE_EXTREME_RECV, "%s(): Wrote fp[%d] bd_prod = 0x%04X, "
+	    "cqe_prod = 0x%04X, sge_prod = 0x%04X\n", __FUNCTION__, fp->index,
+	    bd_prod, rx_comp_prod, rx_sge_prod);
+}
+
+/*
+ * Handles received frame interrupt events.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_rxeof(struct bxe_fastpath *fp)
+{
+	struct bxe_softc *sc;
+	struct ifnet *ifp;
+	uint16_t bd_cons, bd_prod, bd_prod_fw;
+	uint16_t hw_comp_cons_idx, sw_comp_cons_idx, sw_comp_prod;
+	uint16_t comp_ring_cons;
+
+#ifdef BXE_DEBUG
+	unsigned long rx_pkts = 0;
+#endif
+	sc = fp->sc;
+	ifp = sc->bxe_ifp;
+
+	DBENTER(BXE_EXTREME_RECV);
+	/* Get the sb's view of the RX completion consumer index. */
+	hw_comp_cons_idx = le16toh(*fp->rx_cons_sb);
+	if ((hw_comp_cons_idx & USABLE_RCQ_ENTRIES_PER_PAGE) ==
+	    USABLE_RCQ_ENTRIES_PER_PAGE)
+		hw_comp_cons_idx++;
+	/* Get working copies of the driver's view of the RX indices. */
+	bd_cons = fp->rx_bd_cons;
+	bd_prod = bd_prod_fw = fp->rx_bd_prod;
+	sw_comp_cons_idx = fp->rx_comp_cons;
+	sw_comp_prod = fp->rx_comp_prod;
+
+	DBPRINT(sc, (BXE_EXTREME_RECV),
+	    "%s(): fp[%d], bd_cons = 0x%04X, bd_prod = 0x%04X, "
+	    "sw_comp_cons = 0x%04X, sw_comp_prod = 0x%04X\n", __FUNCTION__,
+	    fp->index, bd_cons, bd_prod, sw_comp_cons_idx, sw_comp_prod);
+
+	/*
+	 * Memory barrier to prevent speculative reads of the RX buffer
+	 * from getting ahead of the index in the status block.
+	 */
+	rmb();
+
+	/*
+	 * Scan through the receive chain as long
+	 * as there is work to do.
+	 */
+	while (sw_comp_cons_idx != hw_comp_cons_idx) {
+		struct mbuf *m;
+		union eth_rx_cqe *cqe;
+		uint8_t cqe_fp_flags;
+		uint16_t len, pad;
+
+		/* Convert the indices to an actual rx_bd index. */
+		comp_ring_cons = RCQ_ENTRY(sw_comp_cons_idx);
+		bd_prod = RX_BD(bd_prod);
+		bd_cons = RX_BD(bd_cons);
+		wmb();
+		/* Fetch the cookie. */
+		cqe = (union eth_rx_cqe*)
+		    &fp->rx_comp_chain[RCQ_PAGE(comp_ring_cons)][RCQ_IDX(comp_ring_cons)];
+		cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
+
+#ifdef BXE_DEBUG
+		/* Simulate an error on the received frame. */
+		if (DB_RANDOMTRUE(bxe_debug_received_frame_error)) {
+			DBPRINT(sc, BXE_WARN,
+			    "%s(): Simulated CQE error flags!\n", __FUNCTION__);
+			cqe_fp_flags |= ETH_RX_ERROR_FLAGS;
+			sc->debug_received_frame_error++;
+		}
+#endif
+
+		DBRUNIF((cqe_fp_flags == 0), BXE_PRINTF(
+		    "%s(): CQE received with null type/error flags!\n",
+		    __FUNCTION__));
+
+		/* Check the CQE type for slowpath or fastpath completion. */
+		if (__predict_false(CQE_TYPE(cqe_fp_flags) == 1)) {
+			/* This is a slowpath completion. */
+			bxe_sp_event(fp, cqe);
+			goto bxe_rxeof_next_cqe;
+
+		} else {
+			/* This is a fastpath completion. */
+
+			/* Get the length and pad information from the CQE. */
+			len = le16toh(cqe->fast_path_cqe.pkt_len);
+			pad = cqe->fast_path_cqe.placement_offset;
+
+			/* Check if the completion is for TPA. */
+			if ((!fp->disable_tpa) && (TPA_TYPE(cqe_fp_flags) !=
+			    (TPA_TYPE_START | TPA_TYPE_END))) {
+				uint16_t queue = cqe->fast_path_cqe.queue_index;
+
+				/*
+				 * No need to worry about error flags in
+				 * the frame as the firmware has already
+				 * managed that for us when aggregating
+				 * the frames.
+				 */
+
+				/*
+				 * Check if a TPA aggregation has been started.
+				 */
+				if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
+					bxe_tpa_start(fp, queue, bd_cons,
+					    bd_prod);
+					goto bxe_rxeof_next_rx;
+				}
+
+				/* Check if a TPA aggregation has completed. */
+				if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
+					if (!BXE_RX_SUM_FIX(cqe))
+						DBPRINT(sc, BXE_FATAL,
+						"%s(): STOP on non-TCP data.\n",
+						    __FUNCTION__);
+
+					/*
+					 * This is the size of the linear
+					 * data on this mbuf.
+					 */
+					len = le16toh(cqe->fast_path_cqe.len_on_bd);
+
+					/*
+					 * Stop the aggregation and pass
+					 * the frame up.
+					 */
+					bxe_tpa_stop(sc, fp, queue, pad, len,
+					    cqe, comp_ring_cons);
+					bxe_update_sge_prod(fp,
+					    &cqe->fast_path_cqe);
+					goto bxe_rxeof_next_cqe;
+				}
+			}
+
+			/* Remove the mbuf from the RX chain. */
+			m = fp->rx_mbuf_ptr[bd_cons];
+			fp->rx_mbuf_ptr[bd_cons] = NULL;
+
+			DBRUN(fp->free_rx_bd++);
+			DBRUNIF((fp->free_rx_bd > USABLE_RX_BD),
+				DBPRINT(sc, BXE_FATAL,
+			"%s(): fp[%d] - Too many free rx_bd's (0x%04X)!\n",
+				    __FUNCTION__, fp->index, fp->free_rx_bd));
+
+			/* Unmap the mbuf from DMA space. */
+			bus_dmamap_sync(fp->rx_mbuf_tag,
+			    fp->rx_mbuf_map[bd_cons], BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(fp->rx_mbuf_tag,
+			    fp->rx_mbuf_map[bd_cons]);
+
+			/* Check if the received frame has any errors. */
+			if (__predict_false(cqe_fp_flags &
+			    ETH_RX_ERROR_FLAGS)) {
+				DBPRINT(sc, BXE_WARN ,
+				    "%s(): Found error flags (0x%08X) "
+				    "set in received frame on fp[%d]!\n",
+				    __FUNCTION__, cqe_fp_flags, fp->index);
+
+				fp->soft_rx_errors++;
+
+				/* Reuse the mbuf for a new frame. */
+				if (bxe_get_buf(fp, m, bd_prod)) {
+					DBPRINT(sc, BXE_FATAL,
+					    "%s(): Can't reuse RX mbuf!\n",
+					    __FUNCTION__);
+					DBRUN(bxe_breakpoint(sc));
+					panic("bxe%d: Can't reuse RX mbuf!\n",
+					    sc->bxe_unit);
+				}
+
+				/* Go handle any additional received frames. */
+				goto bxe_rxeof_next_rx;
+			}
+
+			/*
+			 * The high level logic used here is to
+			 * immediatley replace each	receive buffer
+			 * as it is used so that the receive chain
+			 * is full at all times.  First we try to
+			 * allocate a new receive buffer, but if
+			 * that fails then we will reuse the
+			 * existing mbuf and log an error for the
+			 * lost packet.
+			 */
+
+			/* Allocate a new mbuf for the receive chain. */
+			if (__predict_false(bxe_get_buf(fp, NULL, bd_prod))) {
+				/*
+				 * Drop the current frame if we can't get
+				 * a new mbuf.
+				 */
+				fp->soft_rx_errors++;
+
+				/*
+				 * Place the current mbuf back in the
+				 * receive chain.
+				 */
+				if (__predict_false(bxe_get_buf(fp, m,
+				    bd_prod))) {
+					/* This is really bad! */
+					DBPRINT(sc, BXE_FATAL,
+					    "%s(): Can't reuse RX mbuf!\n",
+					    __FUNCTION__);
+
+					DBRUN(bxe_breakpoint(sc));
+
+					panic(
+				"bxe%d: Double mbuf allocation failure!\n",
+					    sc->bxe_unit);
+				}
+
+				/* Go handle any additional received frames. */
+				goto bxe_rxeof_next_rx;
+			}
+
+			/*
+			 * Skip over the pad when passing the data up the stack.
+			 */
+			m_adj(m, pad);
+
+			/*
+			 * Adjust the packet length to match the received data.
+			 */
+			m->m_pkthdr.len = m->m_len = len;
+
+			/* Send the packet to the appropriate interface. */
+			m->m_pkthdr.rcvif = ifp;
+
+			/* Assume no hardware checksum. */
+			m->m_pkthdr.csum_flags = 0;
+
+			/* Validate the checksum if offload enabled. */
+			if (ifp->if_capenable & IFCAP_RXCSUM) {
+				/* Check whether IP checksummed or not. */
+				if (sc->rx_csum &&
+				    !(cqe->fast_path_cqe.status_flags &
+				    ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
+					m->m_pkthdr.csum_flags |=
+					    CSUM_IP_CHECKED;
+					if (__predict_false(cqe_fp_flags &
+					    ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
+						DBPRINT(sc, BXE_WARN_SEND,
+					"%s(): Invalid IP checksum!\n",
+						    __FUNCTION__);
+					} else
+						m->m_pkthdr.csum_flags |=
+						    CSUM_IP_VALID;
+				}
+
+				/* Check for a valid TCP/UDP frame. */
+				if (sc->rx_csum &&
+				    !(cqe->fast_path_cqe.status_flags &
+				    ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
+					/* Check for a good TCP/UDP checksum. */
+					if (__predict_false(cqe_fp_flags &
+					    ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
+						DBPRINT(sc, BXE_VERBOSE_RECV,
+					"%s(): Invalid TCP/UDP checksum!\n",
+						    __FUNCTION__);
+					} else {
+						m->m_pkthdr.csum_data = 0xFFFF;
+						m->m_pkthdr.csum_flags |=
+						    (CSUM_DATA_VALID |
+						    CSUM_PSEUDO_HDR);
+					}
+				}
+			}
+
+			/*
+			 * If we received a packet with a vlan tag,
+			 * attach that information to the packet.
+			 */
+			if (cqe->fast_path_cqe.pars_flags.flags &
+			    PARSING_FLAGS_VLAN) {
+				m->m_pkthdr.ether_vtag =
+				    cqe->fast_path_cqe.vlan_tag;
+				m->m_flags |= M_VLANTAG;
+			}
+
+			/* Last chance to check for problems. */
+			DBRUN(bxe_validate_rx_packet(fp, comp_ring_cons, cqe,
+			    m));
+
+			/* Pass the mbuf off to the upper layers. */
+			ifp->if_ipackets++;
+
+			/* Pass the frame to the stack. */
+			(*ifp->if_input)(ifp, m);
+
+			DBRUN(fp->rx_mbuf_alloc--);
+		}
+
+bxe_rxeof_next_rx:
+		bd_prod = NEXT_RX_BD(bd_prod);
+		bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
+		bd_cons = NEXT_RX_BD(bd_cons);
+		DBRUN(rx_pkts++);
+
+bxe_rxeof_next_cqe:
+		sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
+		sw_comp_cons_idx = NEXT_RCQ_IDX(sw_comp_cons_idx);
+
+		/*
+		 * Memory barrier to prevent speculative reads of the RX buffer
+		 * from getting ahead of the index in the status block.
+		 */
+		rmb();
+	}
+
+	/* Update the driver copy of the fastpath indices. */
+	fp->rx_bd_cons = bd_cons;
+	fp->rx_bd_prod = bd_prod_fw;
+	fp->rx_comp_cons = sw_comp_cons_idx;
+	fp->rx_comp_prod = sw_comp_prod;
+
+	DBPRINT(sc, (BXE_EXTREME_RECV),
+	    "%s(): fp[%d], bd_cons = 0x%04X, bd_prod = 0x%04X, "
+	    "sw_comp_cons = 0x%04X, sw_comp_prod = 0x%04X\n", __FUNCTION__,
+	    fp->index, bd_cons, bd_prod, sw_comp_cons_idx, sw_comp_prod);
+
+	/* Update producers */
+	bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_comp_prod, fp->rx_sge_prod);
+	bus_space_barrier(sc->bxe_btag, sc->bxe_bhandle, 0, 0,
+	    BUS_SPACE_BARRIER_READ);
+
+	DBRUN(fp->rx_pkts += rx_pkts);
+	DBRUN(fp->rx_calls++);
+	DBEXIT(BXE_EXTREME_RECV);
+}
+
+/*
+ * Handles transmit completion interrupt events.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_txeof(struct bxe_fastpath *fp)
+{
+	struct bxe_softc *sc;
+	struct ifnet *ifp;
+	struct eth_tx_start_bd *txbd;
+	uint16_t hw_pkt_cons, sw_pkt_cons, sw_tx_bd_cons, sw_tx_chain_cons;
+	uint16_t pkt_cons, nbds;
+	int i;
+
+	sc = fp->sc;
+	ifp = sc->bxe_ifp;
+
+	DBENTER(BXE_EXTREME_SEND);
+
+	/* Get the hardware's view of the TX packet consumer index. */
+	hw_pkt_cons = le16toh(*fp->tx_cons_sb);
+	sw_pkt_cons = fp->tx_pkt_cons;
+	sw_tx_bd_cons = fp->tx_bd_cons;
+
+	/* Cycle through any completed TX chain page entries. */
+	while (sw_pkt_cons != hw_pkt_cons) {
+		txbd = NULL;
+		sw_tx_chain_cons = TX_BD(sw_tx_bd_cons);
+		pkt_cons = TX_BD(sw_pkt_cons);
+#ifdef BXE_DEBUG
+		if (sw_tx_chain_cons > MAX_TX_BD) {
+			BXE_PRINTF(
+		"%s(): TX chain consumer out of range! 0x%04X > 0x%04X\n",
+			    __FUNCTION__, sw_tx_chain_cons, (int)MAX_TX_BD);
+			bxe_breakpoint(sc);
+		}
+#endif
+
+		txbd = &fp->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)].start_bd;
+
+#ifdef BXE_DEBUG
+		if (txbd == NULL) {
+			BXE_PRINTF("%s(): Unexpected NULL tx_bd[0x%04X]!\n",
+			    __FUNCTION__, sw_tx_chain_cons);
+			bxe_breakpoint(sc);
+		}
+#endif
+		/*
+		 * Find the number of BD's that were used in the completed pkt.
+		 */
+		nbds = txbd->nbd;
+
+		/*
+		 * Free the ext mbuf cluster from the mbuf of the completed
+		 * frame.
+		 */
+		if (__predict_true(fp->tx_mbuf_ptr[pkt_cons] != NULL)) {
+			/* Unmap it from the mbuf. */
+			bus_dmamap_unload(fp->tx_mbuf_tag,
+			    fp->tx_mbuf_map[pkt_cons]);
+
+			/* Return the mbuf to the stack. */
+			DBRUN(fp->tx_mbuf_alloc--);
+			m_freem(fp->tx_mbuf_ptr[pkt_cons]);
+			fp->tx_mbuf_ptr[pkt_cons] = NULL;
+			fp->opackets++;
+		} else {
+			BXE_PRINTF("%s(%d): Lost an mbuf from the TX chain!\n",
+			    __FILE__, __LINE__);
+		}
+
+		/* Skip over the remaining used buffer descriptors. */
+		fp->used_tx_bd -= nbds;
+
+		for (i = 0; i < nbds; i++)
+			sw_tx_bd_cons = NEXT_TX_BD(sw_tx_bd_cons);
+
+		/* Increment the software copy of packet consumer index */
+		sw_pkt_cons++;
+
+		/*
+		 * Refresh the hw packet consumer index to see if there's
+		 * new work.
+		 */
+		hw_pkt_cons = le16toh(*fp->tx_cons_sb);
+		rmb();
+	}
+
+	/* Enable new transmits if we've made enough room. */
+	if (fp->used_tx_bd < BXE_TX_CLEANUP_THRESHOLD) {
+		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+		if (fp->used_tx_bd == 0) {
+			/*
+			 * Clear the watchdog timer if we've emptied
+			 * the TX chain.
+			 */
+			sc->watchdog_timer = 0;
+		} else {
+			/*
+			 * Reset the watchdog timer if we still have
+			 * transmits pending.
+			 */
+			sc->watchdog_timer = BXE_TX_TIMEOUT;
+		}
+	}
+
+	/* Save our indices. */
+	fp->tx_pkt_cons = sw_pkt_cons;
+	fp->tx_bd_cons = sw_tx_bd_cons;
+	DBEXIT(BXE_EXTREME_SEND);
+}
+
+/*
+ * Encapsulate an mbuf cluster into the rx_bd.
+ *
+ * This routine will map an mbuf cluster into 1 rx_bd
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_get_buf(struct bxe_fastpath *fp, struct mbuf *m, uint16_t prod)
+{
+	struct bxe_softc *sc;
+	bus_dma_segment_t seg;
+	struct mbuf *m_new;
+	struct eth_rx_bd *rxbd;
+	int rc;
+
+	sc = fp->sc;
+	m_new = NULL;
+	rc = 0;
+
+	DBENTER(BXE_INSANE_LOAD | BXE_INSANE_RESET | BXE_INSANE_RECV);
+
+	/* Make sure the inputs are valid. */
+	DBRUNIF((prod > MAX_RX_BD),
+	    BXE_PRINTF("%s(): RX producer out of range: 0x%04X > 0x%04X\n",
+	    __FUNCTION__, prod, (uint16_t) MAX_RX_BD));
+
+	/* Check whether this is a new mbuf allocation. */
+	if (m == NULL) {
+		if ((m_new = bxe_alloc_mbuf(fp, sc->mbuf_alloc_size)) == NULL) {
+			rc = ENOBUFS;
+			goto bxe_get_buf_exit;
+		}
+
+		DBRUN(fp->rx_mbuf_alloc++);
+	} else {
+		/* Reuse the existing mbuf. */
+		m_new = m;
+		m_new->m_pkthdr.len = m_new->m_len = sc->mbuf_alloc_size;
+	}
+
+	/* Do some additional sanity checks on the mbuf. */
+	DBRUN(m_sanity(m_new, FALSE));
+
+	rc = bxe_map_mbuf(fp, m_new, fp->rx_mbuf_tag,
+	    fp->rx_mbuf_map[prod], &seg);
+
+	if (__predict_false(rc)) {
+		DBRUN(fp->rx_mbuf_alloc--);
+		rc = ENOBUFS;
+		goto bxe_get_buf_exit;
+	}
+
+	/* Setup the rx_bd for the first segment. */
+	rxbd = &fp->rx_bd_chain[RX_PAGE(prod)][RX_IDX(prod)];
+	rxbd->addr_lo  = htole32(U64_LO(seg.ds_addr));
+	rxbd->addr_hi  = htole32(U64_HI(seg.ds_addr));
+
+	/* Save the mbuf and update our counter. */
+	fp->rx_mbuf_ptr[prod] = m_new;
+
+	DBRUN(fp->free_rx_bd--);
+	DBRUNIF((fp->free_rx_bd > USABLE_RX_BD),
+	    DBPRINT(sc, BXE_FATAL, "%s(): fp[%d] - Too many free rx_bd's "
+	    "(0x%04X)!\n", __FUNCTION__, fp->index, fp->free_rx_bd));
+
+bxe_get_buf_exit:
+	DBEXIT(BXE_INSANE_LOAD | BXE_INSANE_RESET | BXE_INSANE_RECV);
+	return (rc);
+}
+
+/*
+ * Transmit timeout handler.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_watchdog(struct bxe_softc *sc)
+{
+
+	DBENTER(BXE_INSANE_SEND);
+
+	BXE_CORE_LOCK_ASSERT(sc);
+
+	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
+		goto bxe_watchdog_exit;
+
+	BXE_PRINTF("%s(%d): Watchdog timeout occurred, resetting! \n",
+		__FILE__, __LINE__);
+
+	/* DBRUNLV(BXE_FATAL, bxe_breakpoint(sc)); */
+
+	/* Mark the interface as down. */
+	sc->bxe_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+
+	bxe_stop_locked(sc, UNLOAD_NORMAL);
+	DELAY(10000);
+	bxe_init_locked(sc, LOAD_OPEN);
+
+bxe_watchdog_exit:
+	DBEXIT(BXE_INSANE_SEND);
+}
+
+/*
+ * Change the MTU size for the port.  The MTU should be validated before
+ * calling this routine.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+static int
+bxe_change_mtu(struct bxe_softc *sc, int if_drv_running)
+{
+	struct ifnet *ifp;
+	int rc;
+
+	BXE_CORE_LOCK_ASSERT(sc);
+
+	rc = 0;
+	ifp = sc->bxe_ifp;
+	sc->bxe_ifp->if_mtu = ifp->if_mtu;
+	if (if_drv_running) {
+		DBPRINT(sc, BXE_INFO_IOCTL, "%s(): Changing the MTU to %d.\n",
+		    __FUNCTION__, sc->port.ether_mtu);
+
+		bxe_stop_locked(sc, UNLOAD_NORMAL);
+		bxe_init_locked(sc, LOAD_NORMAL);
+	}
+
+	return (rc);
+}
+
+/*
+ * The periodic timer tick routine.
+ *
+ * This code only runs when the interface is up.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_tick(void *xsc)
+{
+	struct bxe_softc *sc;
+//zz 	uint32_t drv_pulse, mcp_pulse;
+	int func;
+
+	sc = xsc;
+	DBENTER(BXE_INSANE_MISC);
+	BXE_CORE_LOCK(sc);
+func = BP_FUNC(sc);
+	/* Schedule the next tick. */
+	callout_reset(&sc->bxe_tick_callout, hz, bxe_tick, sc);
+	/*
+	 * Check if a transmit timeout has
+	 * occurred and reset the device if
+	 * necessary to get back in service.
+	 */
+	bxe_watchdog(sc);
+
+#if 0
+
+	if (!BP_NOMCP(sc)) {
+		func = BP_FUNC(sc);
+
+		++sc->fw_drv_pulse_wr_seq;
+		sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
+
+		/* Let the MCP know we're alive. */
+		drv_pulse = sc->fw_drv_pulse_wr_seq;
+		SHMEM_WR(sc, func_mb[func].drv_pulse_mb, drv_pulse);
+
+		/* Check if the MCP is still alive. */
+		mcp_pulse = (SHMEM_RD(sc, func_mb[func].mcp_pulse_mb) &
+		    MCP_PULSE_SEQ_MASK);
+
+		/*
+		 * The delta between driver pulse and MCP response should be 1
+		 * (before MCP response) or 0 (after MCP response).
+		 */
+		if ((drv_pulse != mcp_pulse) && (drv_pulse != ((mcp_pulse + 1) &
+		    MCP_PULSE_SEQ_MASK))) {
+			/* Someone's in cardiac arrest. */
+			DBPRINT(sc, BXE_WARN,
+			    "%s(): drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
+			    __FUNCTION__, drv_pulse, mcp_pulse);
+		}
+	}
+#endif
+	if ((sc->state == BXE_STATE_OPEN) || (sc->state == BXE_STATE_DISABLED))
+		bxe_stats_handle(sc, STATS_EVENT_UPDATE);
+
+	BXE_CORE_UNLOCK(sc);
+}
+
+#ifdef BXE_DEBUG
+/*
+ * Allows the driver state to be dumped through the sysctl interface.
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	struct bxe_fastpath *fp;
+	int error, i, result;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if (result == 1) {
+		bxe_dump_driver_state(sc);
+		for (i = 0; i < sc->num_queues; i++) {
+			fp = &sc->fp[i];
+			bxe_dump_fp_state(fp);
+		}
+	}
+
+	return (error);
+}
+
+/*
+ * Allows the hardware state to be dumped through the sysctl interface.
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	int error, result;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if (result == 1)
+		bxe_dump_hw_state(sc);
+
+	return (error);
+}
+
+/*
+ * Allows the MCP firmware to be dumped through the sysctl interface.
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_sysctl_dump_fw(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	int error, result;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if (result == 1)
+		bxe_dump_fw(sc);
+
+	return (error);
+}
+
+/*
+ * Provides a sysctl interface to allow dumping the RX completion chain.
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_sysctl_dump_cqe_chain(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	struct bxe_fastpath *fp;
+	int error, result;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if ((result >= 0) && (result <= sc->num_queues)) {
+		fp = &sc->fp[result];
+		bxe_dump_cqe_chain(fp, 0, USABLE_RX_BD);
+	}
+
+	return (error);
+}
+
+
+/*
+ * Provides a sysctl interface to allow dumping the RX chain.
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	struct bxe_fastpath *fp;
+	int error, result;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if ((result >= 0) && (result <= sc->num_queues)) {
+		fp = &sc->fp[result];
+		bxe_dump_rx_chain(fp, 0, USABLE_RX_BD);
+	}
+
+	return (error);
+}
+
+/*
+* Provides a sysctl interface to allow dumping the TX chain.
+*
+* Returns:
+*   0 for success, positive value for failure.
+*/
+static int
+bxe_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	struct bxe_fastpath *fp;
+	int error, result;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if ((result >= 0) && (result <= sc->num_queues)) {
+		fp = &sc->fp[result];
+		bxe_dump_tx_chain(fp, 0, USABLE_TX_BD);
+	}
+
+	return (error);
+}
+
+/*
+ * Provides a sysctl interface to allow reading arbitrary registers in the
+ * device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	uint32_t result, val;
+	int error;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || (req->newptr == NULL))
+		return (error);
+
+	val = REG_RD(sc, result);
+	BXE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
+
+	return (error);
+}
+
+/*
+* Provides a sysctl interface to allow generating a grcdump.
+*
+* Returns:
+*   0 for success, positive value for failure.
+*/
+static int
+bxe_sysctl_dump_grc(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	int error, result;
+
+	sc = (struct bxe_softc *)arg1;
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if (result == 1) {
+		/* Generate a grcdump and log the contents.*/
+		bxe_dump_grc(sc, 1);
+	} else {
+		/* Generate a grcdump and don't log the contents. */
+		bxe_dump_grc(sc, 0);
+	}
+
+	return (error);
+}
+
+/*
+ * Provides a sysctl interface to forcing the driver to dump state and
+ * enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!
+ *
+ * Returns:
+ *   0 for success, positive value for failure.
+ */
+static int
+bxe_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
+{
+	struct bxe_softc *sc;
+	int error, result;
+
+	result = -1;
+	error = sysctl_handle_int(oidp, &result, 0, req);
+	if (error || !req->newptr)
+		return (error);
+
+	if (result == 1) {
+		sc = (struct bxe_softc *)arg1;
+		bxe_breakpoint(sc);
+	}
+
+	return (error);
+}
+#endif
+
+/*
+ * Adds any sysctl parameters for tuning or debugging purposes.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_add_sysctls(struct bxe_softc *sc)
+{
+	struct sysctl_ctx_list *ctx;
+	struct sysctl_oid_list *children;
+	struct bxe_eth_stats *estats;
+
+	estats = &sc->eth_stats;
+	ctx = device_get_sysctl_ctx(sc->bxe_dev);
+	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bxe_dev));
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_bytes_received_hi",
+	    CTLFLAG_RD, &estats->total_bytes_received_hi,
+	    0, "Total bytes received (hi)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_bytes_received_lo",
+	    CTLFLAG_RD, &estats->total_bytes_received_lo,
+	    0, "Total bytes received (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	   "estats_valid_bytes_received_hi",
+	   CTLFLAG_RD, &estats->valid_bytes_received_hi,
+	   0, "Valid bytes received (hi)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_valid_bytes_received_lo",
+	    CTLFLAG_RD, &estats->valid_bytes_received_lo,
+	    0, "Valid bytes received (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_unicast_packets_received_hi",
+	    CTLFLAG_RD, &estats->total_unicast_packets_received_hi,
+	    0, "Total unicast packets received (hi)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_unicast_packets_received_lo",
+	    CTLFLAG_RD, &estats->total_unicast_packets_received_lo,
+	    0, "Total unicast packets received (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+		"estats_total_bytes_transmitted_hi",
+		CTLFLAG_RD, &estats->total_bytes_transmitted_hi,
+		0, "Total bytes transmitted (hi)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+		"estats_total_bytes_transmitted_lo",
+		CTLFLAG_RD, &estats->total_bytes_transmitted_lo,
+		0, "Total bytes transmitted (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_unicast_packets_transmitted_hi",
+	    CTLFLAG_RD, &estats->total_unicast_packets_transmitted_hi,
+	    0, "Total unicast packets transmitted (hi)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_unicast_packets_transmitted_lo",
+	    CTLFLAG_RD, &estats->total_unicast_packets_transmitted_lo,
+	    0, "Total unicast packets transmitted (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_broadcast_packets_received_lo",
+	    CTLFLAG_RD, &estats->total_broadcast_packets_received_lo,
+	    0, "Total broadcast packets received (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_broadcast_packets_transmitted_lo",
+	    CTLFLAG_RD, &estats->total_broadcast_packets_transmitted_lo,
+	    0, "Total broadcast packets transmitted (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_multicast_packets_received_lo",
+	    CTLFLAG_RD, &estats->total_multicast_packets_received_lo,
+	    0, "Total multicast packets received (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "estats_total_multicast_packets_transmitted_lo",
+	    CTLFLAG_RD, &estats->total_multicast_packets_transmitted_lo,
+	    0, "Total multicast packets transmitted (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "tx_stat_etherstatspkts64octets_hi",
+	    CTLFLAG_RD, &estats->tx_stat_etherstatspkts64octets_hi,
+	    0, "Total 64 byte packets transmitted (hi)");
+
+	/* ToDo: Fix for 64 bit access. */
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "tx_stat_etherstatspkts64octets_lo",
+	    CTLFLAG_RD, &estats->tx_stat_etherstatspkts64octets_lo,
+	    0, "Total 64 byte packets transmitted (lo)");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
+	    "driver_xoff",
+	    CTLFLAG_RD, &estats->driver_xoff,
+	    0, "Driver transmit queue full count");
+
+	/* ToDo: Add more statistics here. */
+
+#ifdef BXE_DEBUG
+	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "bxe_debug",
+	    CTLFLAG_RW, &bxe_debug, 0,
+	    "Debug message level flag");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tso_offload_frames",
+	    CTLFLAG_RD, &sc->debug_tso_offload_frames,
+	    0, "TSO offload frames processed count");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "ip_csum_offload_frames",
+	    CTLFLAG_RD, &sc->debug_ip_csum_offload_frames,
+	    0, "IP checksum offload frames processed count");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tcp_csum_offload_frames",
+	    CTLFLAG_RD, &sc->debug_tcp_csum_offload_frames,
+	    0, "TCP checksum offload frames processed count");
+
+	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "udp_csum_offload_frames",
+	    CTLFLAG_RD, &sc->debug_udp_csum_offload_frames,
+	    0, "UDP checksum offload frames processed count");
+
+	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mbuf_alloc_failed",
+	    CTLFLAG_RD, &sc->mbuf_alloc_failed, 0,
+	    "mbuf cluster allocation failures");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "driver_state",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_driver_state,
+	    "I", "Drive state information");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_state",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_hw_state,
+	    "I", "Hardware state information");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_fw",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_dump_fw,
+	    "I", "Dump MCP firmware");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_rx_chain",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_dump_rx_chain,
+	    "I", "Dump rx_bd chain");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_cqe_chain",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_dump_cqe_chain,
+	    "I", "Dump cqe chain");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_tx_chain",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_dump_tx_chain,
+	    "I", "Dump tx_bd chain");
+
+	/*
+	 * Generates a GRCdump (run sysctl dev.bxe.0.grcdump=0
+	 * before access buffer below).
+	 */
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "grcdump",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_dump_grc,
+	    "I", "Initiate a grcdump operation");
+
+	/*
+	 * Hidden sysctl.
+	 *  Use "sysctl -b dev.bxe.0.grcdump_buffer > buf.bin".
+	 */
+	SYSCTL_ADD_OPAQUE(ctx, children, OID_AUTO, "grcdump_buffer",
+	    CTLFLAG_RD | CTLFLAG_SKIP, sc->grcdump_buffer, BXE_GRCDUMP_BUF_SIZE,
+	    "IU", "Grcdump buffer");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "breakpoint",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_breakpoint,
+	    "I", "Driver breakpoint");
+
+	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
+	    CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_reg_read,
+	    "I", "Register read");
+#endif /* BXE_DEBUG */
+}
+
+/*
+ * BXE Debug Routines
+ */
+#ifdef BXE_DEBUG
+/*
+ * Writes out the header for the debug dump buffer.
+ *
+ * Returns:
+ * 	 None.
+ *
+ * Modifies:
+ *   index
+ */
+static void
+bxe_dump_debug_header(struct bxe_softc *sc, uint32_t *index)
+{
+	struct hd_param hd_param_cu = {0};
+	uint32_t *buf;
+
+	buf = sc->grcdump_buffer;
+	if (CHIP_IS_E1H(sc))
+		hd_param_cu = hd_param_e1h;
+	else
+		hd_param_cu = hd_param_e1;
+
+	buf[(*index)++] = hd_param_cu.time_stamp;
+	buf[(*index)++] = hd_param_cu.diag_ver;
+	buf[(*index)++] = hd_param_cu.grc_dump_ver;
+
+	buf[(*index)++] = REG_RD_IND(sc, XSTORM_WAITP_ADDRESS);
+	buf[(*index)++] = REG_RD_IND(sc, TSTORM_WAITP_ADDRESS);
+	buf[(*index)++] = REG_RD_IND(sc, USTORM_WAITP_ADDRESS);
+	buf[(*index)++] = REG_RD_IND(sc, CSTORM_WAITP_ADDRESS);
+
+	/* The size of the header is stored at the first DWORD. */
+	buf[0] = (*index) - 1;
+}
+
+
+/*
+ * Writes to the controller to prepare it for a dump.
+ *
+ * Returns:
+ * 	 None.
+ *
+ * Modifies:
+ *   None.
+ */
+static void
+bxe_dump_debug_writes(struct bxe_softc *sc)
+{
+	uint32_t write_val;
+
+	write_val = 1;
+	/* Halt the STORMs to get a consistent device state. */
+	REG_WR_IND(sc, XSTORM_WAITP_ADDRESS, write_val);
+	REG_WR_IND(sc, TSTORM_WAITP_ADDRESS, write_val);
+	REG_WR_IND(sc, USTORM_WAITP_ADDRESS, write_val);
+	REG_WR_IND(sc, CSTORM_WAITP_ADDRESS, write_val);
+
+	if (CHIP_IS_E1H(sc))
+		REG_WR_IND(sc, TSTORM_CAM_MODE, write_val);
+}
+
+
+/*
+ * Cycles through the required register reads and dumps them
+ * to the debug buffer.
+ *
+ * Returns:
+ * 	 None.
+ *
+ * Modifies:
+ *   index
+ */
+static void
+bxe_dump_debug_reg_read(struct bxe_softc *sc, uint32_t *index)
+{
+	preg_addr preg_addrs;
+	uint32_t regs_count, *buf;
+	uint32_t i, reg_addrs_index;
+
+	buf = sc->grcdump_buffer;
+	preg_addrs = NULL;
+
+	/* Read different registers for different controllers. */
+	if (CHIP_IS_E1H(sc)) {
+		regs_count = regs_count_e1h;
+		preg_addrs = &reg_addrs_e1h[0];
+	} else {
+		regs_count = regs_count_e1;
+		preg_addrs = &reg_addrs_e1[0];
+	}
+
+	/* ToDo: Add a buffer size check. */
+	for (reg_addrs_index = 0; reg_addrs_index < regs_count;
+	    reg_addrs_index++) {
+		for (i = 0; i < preg_addrs[reg_addrs_index].size; i++) {
+			buf[(*index)++] = REG_RD_IND(sc,
+			    preg_addrs[reg_addrs_index].addr + (i * 4));
+		}
+	}
+}
+
+/*
+ * Cycles through the required wide register reads and dumps them
+ * to the debug buffer.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_dump_debug_reg_wread(struct bxe_softc *sc, uint32_t *index)
+{
+	pwreg_addr pwreg_addrs;
+	uint32_t reg_addrs_index, reg_add_read,	reg_add_count;
+	uint32_t *buf, cam_index, wregs_count;
+
+	buf = sc->grcdump_buffer;
+	pwreg_addrs = NULL;
+
+	/* Read different registers for different controllers. */
+    if (CHIP_IS_E1H(sc)) {
+        wregs_count = wregs_count_e1h;
+        pwreg_addrs = &wreg_addrs_e1h[0];
+    } else {
+        wregs_count = wregs_count_e1;
+        pwreg_addrs = &wreg_addrs_e1[0];
+    }
+
+	for (reg_addrs_index = 0; reg_addrs_index < wregs_count;
+	    reg_addrs_index++) {
+		reg_add_read = pwreg_addrs[reg_addrs_index].addr;
+		for (reg_add_count = 0; reg_add_count <
+		    pwreg_addrs[reg_addrs_index].size; reg_add_count++) {
+			buf[(*index)++] = REG_RD_IND(sc, reg_add_read);
+			reg_add_read += sizeof(uint32_t);
+
+			for (cam_index = 0; cam_index <
+			    pwreg_addrs[reg_addrs_index].const_regs_count;
+			    cam_index++)
+				buf[(*index)++] = REG_RD_IND(sc,
+				    pwreg_addrs[reg_addrs_index].const_regs[cam_index]);
+		}
+	}
+}
+
+/*
+ * Performs a debug dump for offline diagnostics.
+ *
+ * Note that when this routine is called the STORM
+ * processors will be stopped in order to create a
+ * cohesive dump.  The controller will need to be
+ * reset before the device can begin passing traffic
+ * again.
+ *
+ * Returns:
+ *   None.
+ */
+static void
+bxe_dump_grc(struct bxe_softc *sc, int log)
+{
+	uint32_t *buf, i, index;
+
+	index = 1;
+	buf = sc->grcdump_buffer;
+	if (buf != NULL) {
+
+		/* Write the header and regsiters contents to the dump buffer. */
+		bxe_dump_debug_header(sc, &index);
+		bxe_dump_debug_writes(sc);
+		bxe_dump_debug_reg_read(sc,&index);
+		bxe_dump_debug_reg_wread(sc, &index);
+
+		/* Print the results to the system log is necessary. */
+		if (log) {
+			BXE_PRINTF(
+			    "-----------------------------"
+			    "    grcdump   "
+			    "-----------------------------\n");
+			BXE_PRINTF("Buffer length = 0x%08X bytes\n", index * 4);
+
+			for (i = 0; i < index; i += 8) {
+				BXE_PRINTF(
+				    "0x%08X - 0x%08X 0x%08X 0x%08X 0x%08X "
+				    "0x%08X 0x%08X 0x%08X 0x%08X\n", i * 4,
+				    buf[i + 0], buf[i + 1], buf[i + 2],
+				    buf[i + 3], buf[i + 4], buf[i + 5],
+				    buf[i + 6], buf[i + 7]);
+			}
+
+			BXE_PRINTF(
+			    "-----------------------------"
+			    "--------------"
+			    "-----------------------------\n");
+		}
+	} else {
+		BXE_PRINTF("No grcdump buffer allocated!\n");
+	}
+}
+
+/*
+ * Check that an Etherent frame is valid and prints out debug info if it's
+ * not.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_validate_rx_packet(struct bxe_fastpath *fp, uint16_t comp_cons,
+    union eth_rx_cqe *cqe, struct mbuf *m)
+{
+	struct bxe_softc *sc;
+
+	sc = fp->sc;
+	/* Check that the mbuf is sane. */
+	m_sanity(m, FALSE);
+
+	/* Make sure the packet has a valid length. */
+	if ((m->m_len < ETHER_HDR_LEN) |
+		(m->m_len > ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)) {
+		m_print(m, 128);
+		bxe_dump_enet(sc, m);
+		bxe_dump_cqe_locked(fp, comp_cons, cqe);
+	}
+}
+
+/*
+ * Prints out Ethernet frame information from an mbuf.
+ *
+ * Partially decode an Ethernet frame to look at some important headers.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_enet(struct bxe_softc *sc, struct mbuf *m)
+{
+	struct ether_vlan_header *eh;
+	uint16_t etype;
+	int e_hlen;
+	struct ip *ip;
+	struct tcphdr *th;
+	struct udphdr *uh;
+	struct arphdr *ah;
+
+	BXE_PRINTF(
+	    "-----------------------------"
+	    " Frame Decode "
+	    "-----------------------------\n");
+
+	eh = mtod(m, struct ether_vlan_header *);
+
+	/* Handle VLAN encapsulation if present. */
+	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
+		etype = ntohs(eh->evl_proto);
+		e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
+	} else {
+		etype = ntohs(eh->evl_encap_proto);
+		e_hlen = ETHER_HDR_LEN;
+	}
+
+	BXE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, e_hlen = %d\n",
+	    eh->evl_dhost, ":", eh->evl_shost, ":", etype, e_hlen);
+
+	switch (etype) {
+	case ETHERTYPE_IP:
+		ip = (struct ip *)(m->m_data + e_hlen);
+		BXE_PRINTF(
+		    "--ip: dest = 0x%08X , src = 0x%08X, "
+		    "ip_hlen = %d bytes, len = %d bytes, protocol = 0x%02X, "
+		    "ip_id = 0x%04X, csum = 0x%04X\n",
+		    ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
+		    (ip->ip_hl << 2), ntohs(ip->ip_len), ip->ip_p,
+		    ntohs(ip->ip_id), ntohs(ip->ip_sum));
+
+		switch (ip->ip_p) {
+		case IPPROTO_TCP:
+			th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
+			BXE_PRINTF(
+			    "-tcp: dest = %d, src = %d, tcp_hlen = %d "
+			    "bytes, flags = 0x%b, csum = 0x%04X\n",
+			    ntohs(th->th_dport), ntohs(th->th_sport),
+			    (th->th_off << 2), th->th_flags,
+			    "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST\02SYN\01FIN",
+			    ntohs(th->th_sum));
+			break;
+		case IPPROTO_UDP:
+			uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
+			BXE_PRINTF(
+			    "-udp: dest = %d, src = %d, udp_hlen = %d "
+			    "bytes, len = %d bytes, csum = 0x%04X\n",
+			    ntohs(uh->uh_dport), ntohs(uh->uh_sport),
+			    (int)sizeof(struct udphdr), ntohs(uh->uh_ulen),
+			    ntohs(uh->uh_sum));
+			break;
+		case IPPROTO_ICMP:
+			BXE_PRINTF("icmp:\n");
+			break;
+		default:
+			BXE_PRINTF("----: Other IP protocol.\n");
+		}
+		break;
+	case ETHERTYPE_IPV6:
+		/* ToDo: Add IPv6 support. */
+		BXE_PRINTF("IPv6 not supported!.\n");
+		break;
+	case ETHERTYPE_ARP:
+		BXE_PRINTF("-arp: ");
+		ah = (struct arphdr *) (m->m_data + e_hlen);
+		switch (ntohs(ah->ar_op)) {
+		case ARPOP_REVREQUEST:
+			printf("reverse ARP request\n");
+			break;
+		case ARPOP_REVREPLY:
+			printf("reverse ARP reply\n");
+			break;
+		case ARPOP_REQUEST:
+			printf("ARP request\n");
+			break;
+		case ARPOP_REPLY:
+			printf("ARP reply\n");
+			break;
+		default:
+			printf("other ARP operation\n");
+		}
+		break;
+	default:
+		BXE_PRINTF("----: Other protocol.\n");
+	}
+
+	BXE_PRINTF(
+	   "-----------------------------"
+	   "--------------"
+	   "-----------------------------\n");
+}
+
+static void
+bxe_dump_mbuf_data(struct mbuf *m, int len)
+{
+	uint8_t *ptr;
+	int i;
+
+	ptr = mtod(m, uint8_t *);
+	printf("\nmbuf->m_data:");
+	printf("\n0x");
+	for (i = 0; i < len; i++){
+		if (i != 0 && i % 40 == 0)
+			printf("\n0x");
+		else if (i != 0 && i % 6 == 0)
+			printf(" 0x");
+		printf("%02x", *ptr++);
+	}
+	printf("\n\n");
+}
+
+/*
+ * Prints out information about an mbuf.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_mbuf(struct bxe_softc *sc, struct mbuf *m)
+{
+	struct mbuf *mp, *mx;
+	int i, n;
+
+	if (m == NULL) {
+		BXE_PRINTF("mbuf: null pointer\n");
+		return;
+	}
+
+	mp = m;
+	for (i = 0, mx = m; mx; i++)
+		mx = mx->m_next;
+	for (n=0, mx = m; mx; n++)
+		mx = mx->m_nextpkt;
+	printf("There are %d mbufs on the mbuf chain & %d packets "
+	    "on the mbuf queue.\n", i, n);
+
+	for (n = 0, mx = m; mx;  n++, i = 0){
+		printf("packet#%d on packet queue\n", n);
+		while (mp) {
+			BXE_PRINTF(
+		"mbuf#%d: %p, m_len = %d, m_flags = 0x%b, m_data = %p\n",
+			    i, mp, mp->m_len, mp->m_flags,
+			    "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY",
+			    mp->m_data);
+
+			if (mp->m_flags & M_PKTHDR) {
+				BXE_PRINTF(
+		"- m_pkthdr: len = %d, flags = 0x%b, csum_flags = %b\n",
+				    mp->m_pkthdr.len, mp->m_flags,
+				    "\20\12M_BCAST\13M_MCAST\14M_FRAG\15M_FIRSTFRAG"
+				    "\16M_LASTFRAG\21M_VLANTAG\22M_PROMISC\23M_NOFREE",
+				    mp->m_pkthdr.csum_flags,
+				    "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
+				    "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
+				    "\12CSUM_IP_VALID\13CSUM_DATA_VALID\14CSUM_PSEUDO_HDR");
+			}
+
+			if (mp->m_flags & M_EXT) {
+				BXE_PRINTF(
+				    "- m_ext: %p, ext_size = %d, type = ",
+				    mp->m_ext.ext_buf, mp->m_ext.ext_size);
+				switch (mp->m_ext.ext_type) {
+				case EXT_CLUSTER:
+					printf("EXT_CLUSTER\n");
+					break;
+				case EXT_SFBUF:
+					printf("EXT_SFBUF\n");
+					break;
+				case EXT_JUMBO9:
+					printf("EXT_JUMBO9\n");
+					break;
+				case EXT_JUMBO16:
+					printf("EXT_JUMBO16\n");
+					break;
+				case EXT_PACKET:
+					printf("EXT_PACKET\n");
+					break;
+				case EXT_MBUF:
+					printf("EXT_MBUF\n");
+					break;
+				case EXT_NET_DRV:
+					printf("EXT_NET_DRV\n");
+					break;
+				case EXT_MOD_TYPE:
+					printf("EXT_MDD_TYPE\n");
+					break;
+				case EXT_DISPOSABLE:
+					printf("EXT_DISPOSABLE\n");
+					break;
+				case EXT_EXTREF:
+					printf("EXT_EXTREF\n");
+					break;
+				default:
+					printf("UNKNOWN\n");
+				}
+			}
+			bxe_dump_mbuf_data(mp, 64);
+			mp = mp->m_next;
+			i++;
+		}
+		mx = mx->m_nextpkt;
+	}
+}
+
+/*
+ * Prints out information about an rx_bd.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_rxbd_locked(struct bxe_fastpath *fp, int idx,
+    struct eth_rx_bd *rxbd)
+{
+	struct bxe_softc *sc;
+
+	sc = fp->sc;
+	/* Check if index out of range. */
+	if (idx > MAX_RX_BD)
+		BXE_PRINTF("fp[%d].rx_bd[0x%04X]: Invalid rx_bd index!\n",
+		    fp->index, idx);
+
+	BXE_PRINTF("fp[%d].rx_bd[0x%04X]: 0x%08X:%08X\n", fp->index, idx,
+	    rxbd->addr_hi, rxbd->addr_lo);
+}
+
+/*
+ * Prints out a completion queue entry.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_cqe_locked(struct bxe_fastpath *fp, int idx,
+    union eth_rx_cqe *cqe)
+{
+	struct bxe_softc *sc;
+
+	sc = fp->sc;
+	if (idx > MAX_RX_BD) {
+		/* Index out of range. */
+		BXE_PRINTF("fp[%d].rx_cqe[0x%04X]: Invalid rx_cqe index!\n",
+		    fp->index, idx);
+	} else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
+		/* CQE next page pointer. */
+		BXE_PRINTF("fp[%d].rx_cqe[0x%04X]: Next page pointer.\n",
+		    fp->index, idx);
+	} else {
+		/* Normal CQE. */
+		BXE_PRINTF("fp[%d].rx_cqe[0x%04X]: error_flags = 0x%b, "
+		    "pkt_len = 0x%04X, status_flags = 0x%02X, vlan = 0x%04X "
+		    "rss_hash = 0x%08X\n", fp->index, idx,
+		    cqe->fast_path_cqe.type_error_flags,
+		    BXE_ETH_FAST_PATH_RX_CQE_ERROR_FLAGS_PRINTFB,
+		    le16toh(cqe->fast_path_cqe.pkt_len),
+		    cqe->fast_path_cqe.status_flags,
+		    le16toh(cqe->fast_path_cqe.vlan_tag),
+		    le32toh(cqe->fast_path_cqe.rss_hash_result));
+	}
+}
+
+/*
+ * Prints out information about a parsing BD.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_pbd_locked(struct bxe_softc *sc, int idx,
+    struct eth_tx_parse_bd *pbd)
+{
+
+	BXE_PRINTF(
+	    "---------pbd[0x%04X]: gdata = 0x%b, tcp_flags = 0x%b, "
+	    "ip_hlen = %d, cs_offset = %d, total_hlen = %d, lso_mss = 0x%04X, "
+	    "tcp_pseudo_csum = 0x%04X, ip_id = 0x%04X\n", idx,
+	    pbd->global_data, BXE_ETH_TX_PARSE_BD_GLOBAL_DATA_PRINTFB,
+	    pbd->tcp_flags, BXE_ETH_TX_PARSE_BD_TCP_FLAGS_PRINTFB,
+	    pbd->ip_hlen, /* t48 pbd->cs_offset*/ 0/*zz*/, pbd->total_hlen,
+	    pbd->lso_mss, pbd->tcp_pseudo_csum, pbd->ip_id);
+}
+
+/*
+ * Prints out information about a tx_bd.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_txbd_locked(struct bxe_fastpath *fp, int idx,
+    struct eth_tx_bd *txbd)
+{
+	struct bxe_softc *sc;
+
+	sc = fp->sc;
+	if (idx > MAX_TX_BD){
+		/* Index out of range. */
+		BXE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
+	} else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
+		/* TX Chain page pointer. */
+		BXE_PRINTF("fp[02%d]:tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
+		    "chain page pointer\n", fp->index, idx, txbd->addr_hi,
+		    txbd->addr_lo);
+	} else {
+		/* Normal tx_bd entry. */
+		BXE_PRINTF("fp[%02d]:tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
+		    "nbytes = %d, nbd = %d, flags = 0x%b, gendata = 0x%02X\n",
+		    fp->index, idx, txbd->addr_hi, txbd->addr_lo,
+		    txbd->nbytes, /* t48 txbd->nbd*/ 0,
+		    /* t48 txbd->bd_flags.as_bitfield*/0,
+		    BXE_ETH_TX_BD_FLAGS_PRINTFB, /*t48 txbd->general_data*/ 0);
+	}
+}
+
+/*
+ * Prints out the transmit chain.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_tx_chain(struct bxe_fastpath * fp, int tx_bd_prod, int count)
+{
+	struct bxe_softc *sc;
+	struct eth_tx_bd *txbd;
+	uint32_t val_hi, val_lo;
+	int i, parsing_bd;
+
+	sc = fp->sc;
+	parsing_bd = 0;
+	/* First some info about the tx_bd chain structure. */
+	BXE_PRINTF(
+	    "----------------------------"
+	    "  tx_bd chain "
+	    "----------------------------\n");
+
+	val_hi = U64_HI(fp->tx_bd_chain_paddr);
+	val_lo = U64_LO(fp->tx_bd_chain_paddr);
+	BXE_PRINTF(
+	    "0x%08X:%08X - (fp->tx_bd_chain_paddr) TX Chain physical address\n",
+	    val_hi, val_lo);
+	BXE_PRINTF(
+	    "page size      = 0x%08X, tx chain pages        = 0x%08X\n",
+	    (uint32_t)BCM_PAGE_SIZE, (uint32_t)NUM_TX_PAGES);
+	BXE_PRINTF(
+	    "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
+	    (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE);
+	BXE_PRINTF(
+	    "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
+
+	BXE_PRINTF(
+	    "-----------------------------"
+	    "  tx_bd data  "
+	    "-----------------------------\n");
+
+	/* Now print out the tx_bd's themselves. */
+	for (i = 0; i < count; i++) {
+		txbd = &fp->tx_bd_chain[TX_PAGE(tx_bd_prod)][TX_IDX(tx_bd_prod)].reg_bd;
+		if (parsing_bd) {
+			bxe_dump_pbd_locked(sc, tx_bd_prod,
+			    (struct eth_tx_parse_bd *)txbd);
+			parsing_bd = 0;
+		} else {
+			bxe_dump_txbd_locked(fp, tx_bd_prod, txbd);
+			if (/*t48 txbd->bd_flags.as_bitfield &*/
+			    (ETH_TX_BD_FLAGS_IP_CSUM
+			    /* t48 | ETH_TX_BD_FLAGS_TCP_CSUM*/))
+				parsing_bd = 1;
+		}
+
+		tx_bd_prod = TX_BD(NEXT_TX_BD(tx_bd_prod));
+	}
+
+	BXE_PRINTF(
+	    "-----------------------------"
+	    "--------------"
+	    "-----------------------------\n");
+}
+
+/*
+ * Prints out the receive completion queue chain.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_cqe_chain(struct bxe_fastpath *fp, int rx_cqe_prod, int count)
+{
+	struct bxe_softc *sc = fp->sc;
+	union eth_rx_cqe *cqe;
+	int i;
+
+	sc = fp->sc;
+	/* First some info about the tx_bd chain structure. */
+	BXE_PRINTF(
+	   "----------------------------"
+	   "   CQE  Chain   "
+	   "----------------------------\n");
+
+	BXE_PRINTF("----- CQE Chain -----\n");
+
+	BXE_PRINTF("page size = 0x%08X, cq chain pages = 0x%08X\n",
+	    (uint32_t)BCM_PAGE_SIZE, (uint32_t) NUM_RCQ_PAGES);
+
+	BXE_PRINTF("cqe_bd per page = 0x%08X, usable cqe_bd per "
+	    "page = 0x%08X\n",
+	    (uint32_t) TOTAL_RCQ_ENTRIES_PER_PAGE,
+	    (uint32_t) USABLE_RCQ_ENTRIES_PER_PAGE);
+
+	BXE_PRINTF("total cqe_bd = 0x%08X\n",(uint32_t) TOTAL_RCQ_ENTRIES);
+
+	/* Now the RXCQE entries themselves. */
+	BXE_PRINTF(
+	    "----------------------------"
+	    "    CQE Data    "
+	    "----------------------------\n");
+
+	/* Now print out the rx_bd's themselves. */
+	for (i = 0; i < 10; i++) {
+		cqe = (union eth_rx_cqe *)&fp->rx_comp_chain[0][i];
+		bxe_dump_cqe_locked(fp, rx_cqe_prod, cqe);
+		cqe = (union eth_rx_cqe *)&fp->rx_comp_chain
+		    [RCQ_PAGE(rx_cqe_prod)][RCQ_IDX(rx_cqe_prod)];
+		bxe_dump_cqe_locked(fp, rx_cqe_prod, cqe);
+		rx_cqe_prod = RCQ_ENTRY(NEXT_RCQ_IDX(rx_cqe_prod));
+	}
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "--------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Prints out the receive chain.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_rx_chain(struct bxe_fastpath *fp, int rx_prod, int count)
+{
+	struct bxe_softc *sc;
+	struct eth_rx_bd *rxbd;
+	int i;
+
+	sc = fp->sc;
+	/* First some info about the tx_bd chain structure. */
+	BXE_PRINTF(
+	    "----------------------------"
+	    "  rx_bd  chain  "
+	    "----------------------------\n");
+
+	BXE_PRINTF(
+	    "----- RX_BD Chain -----\n");
+
+	BXE_PRINTF(
+	    "page size = 0x%08X, rx chain pages = 0x%08X\n",
+	    (uint32_t)BCM_PAGE_SIZE, (uint32_t)NUM_RX_PAGES);
+
+	BXE_PRINTF(
+	    "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
+	    (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE);
+
+	BXE_PRINTF(
+	    "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
+
+	/* Now the rx_bd entries themselves. */
+	BXE_PRINTF(
+	    "----------------------------"
+	    "   rx_bd data   "
+	    "----------------------------\n");
+
+	/* Now print out the rx_bd's themselves. */
+	for (i = 0; i < count; i++) {
+		rxbd = (struct eth_rx_bd *)
+		    (&fp->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]);
+		bxe_dump_rxbd_locked(fp, rx_prod, rxbd);
+		rx_prod = RX_BD(NEXT_RX_BD(rx_prod));
+	}
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "--------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Prints out a register dump.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_hw_state(struct bxe_softc *sc)
+{
+	int i;
+
+	BXE_PRINTF(
+		"----------------------------"
+		" Hardware State "
+		"----------------------------\n");
+
+	for (i = 0x2000; i < 0x10000; i += 0x10)
+		BXE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
+		    REG_RD(sc, 0 + i), REG_RD(sc, 0 + i + 0x4),
+		    REG_RD(sc, 0 + i + 0x8), REG_RD(sc, 0 + i + 0xC));
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Prints out the RX mbuf chain.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_rx_mbuf_chain(struct bxe_softc *sc, int chain_prod, int count)
+{
+	struct mbuf *m;
+	int i;
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "  rx mbuf data  "
+	    "----------------------------\n");
+
+	for (i = 0; i < count; i++) {
+	 	m = sc->fp->rx_mbuf_ptr[chain_prod];
+		BXE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
+		bxe_dump_mbuf(sc, m);
+		chain_prod = RX_BD(NEXT_RX_BD(chain_prod));
+	}
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Prints out the mbufs in the TX mbuf chain.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_tx_mbuf_chain(struct bxe_softc *sc, int chain_prod, int count)
+{
+	struct mbuf *m;
+	int i;
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "  tx mbuf data  "
+	    "----------------------------\n");
+
+	for (i = 0; i < count; i++) {
+	 	m = sc->fp->tx_mbuf_ptr[chain_prod];
+		BXE_PRINTF("txmbuf[%d]\n", chain_prod);
+		bxe_dump_mbuf(sc, m);
+		chain_prod = TX_BD(NEXT_TX_BD(chain_prod));
+	}
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Prints out the status block from host memory.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_status_block(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	struct host_def_status_block *dsb;
+	struct host_status_block *fpsb;
+	int i;
+
+	dsb = sc->def_status_block;
+	BXE_PRINTF(
+	    "----------------------------"
+	    "  Status Block  "
+	    "----------------------------\n");
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		fpsb = fp->status_block;
+		BXE_PRINTF(
+		    "----------------------------"
+		    "     fp[%02d]     "
+		    "----------------------------\n", fp->index);
+
+		/* Print the USTORM fields (HC_USTORM_SB_NUM_INDICES). */
+		BXE_PRINTF(
+		    "0x%08X - USTORM Flags (F/W RESERVED)\n",
+		    fpsb->u_status_block.__flags);
+		BXE_PRINTF(
+		    "      0x%02X - USTORM PCIe Function\n",
+		    fpsb->u_status_block.func);
+		BXE_PRINTF(
+		    "      0x%02X - USTORM Status Block ID\n",
+		    fpsb->u_status_block.status_block_id);
+		BXE_PRINTF(
+		    "    0x%04X - USTORM Status Block Index (Tag)\n",
+		    fpsb->u_status_block.status_block_index);
+		BXE_PRINTF(
+		    "    0x%04X - USTORM [TOE_RX_CQ_CONS]\n",
+		    fpsb->u_status_block.index_values[HC_INDEX_U_TOE_RX_CQ_CONS]);
+		BXE_PRINTF(
+		    "    0x%04X - USTORM [ETH_RX_CQ_CONS]\n",
+		    fpsb->u_status_block.index_values[HC_INDEX_U_ETH_RX_CQ_CONS]);
+		BXE_PRINTF(
+		    "    0x%04X - USTORM [ETH_RX_BD_CONS]\n",
+		    fpsb->u_status_block.index_values[HC_INDEX_U_ETH_RX_BD_CONS]);
+		BXE_PRINTF(
+		    "    0x%04X - USTORM [RESERVED]\n",
+		    fpsb->u_status_block.index_values[3]);
+
+		/* Print the CSTORM fields (HC_CSTORM_SB_NUM_INDICES). */
+		BXE_PRINTF(
+		    "0x%08X - CSTORM Flags (F/W RESERVED)\n",
+		    fpsb->c_status_block.__flags);
+		BXE_PRINTF(
+		    "      0x%02X - CSTORM PCIe Function\n",
+		    fpsb->c_status_block.func);
+		BXE_PRINTF(
+		    "      0x%02X - CSTORM Status Block ID\n",
+		    fpsb->c_status_block.status_block_id);
+		BXE_PRINTF(
+		    "    0x%04X - CSTORM Status Block Index (Tag)\n",
+		    fpsb->c_status_block.status_block_index);
+		BXE_PRINTF(
+		    "    0x%04X - CSTORM [TOE_TX_CQ_CONS]\n",
+		    fpsb->c_status_block.index_values[HC_INDEX_C_TOE_TX_CQ_CONS]);
+		BXE_PRINTF(
+		    "    0x%04X - CSTORM [ETH_TX_CQ_CONS]\n",
+		    fpsb->c_status_block.index_values[HC_INDEX_C_ETH_TX_CQ_CONS]);
+		BXE_PRINTF(
+		    "    0x%04X - CSTORM [ISCSI_EQ_CONS]\n",
+		    fpsb->c_status_block.index_values[HC_INDEX_C_ISCSI_EQ_CONS]);
+		BXE_PRINTF(
+		    "    0x%04X - CSTORM [RESERVED]\n",
+		    fpsb->c_status_block.index_values[3]);
+	}
+
+	BXE_PRINTF(
+	    "--------------------------"
+	    "  Def Status Block  "
+	    "--------------------------\n");
+
+	/* Print attention information. */
+	BXE_PRINTF(
+	    "      0x%02X - Status Block ID\n",
+	    dsb->atten_status_block.status_block_id);
+	BXE_PRINTF(
+	    "0x%08X - Attn Bits\n",
+	    dsb->atten_status_block.attn_bits);
+	BXE_PRINTF(
+	    "0x%08X - Attn Bits Ack\n",
+	    dsb->atten_status_block.attn_bits_ack);
+	BXE_PRINTF(
+	    "    0x%04X - Attn Block Index\n",
+	    le16toh(dsb->atten_status_block.attn_bits_index));
+
+	/* Print the USTORM fields (HC_USTORM_DEF_SB_NUM_INDICES). */
+	BXE_PRINTF(
+	    "      0x%02X - USTORM Status Block ID\n",
+	    dsb->u_def_status_block.status_block_id);
+	BXE_PRINTF(
+	    "    0x%04X - USTORM Status Block Index\n",
+	    le16toh(dsb->u_def_status_block.status_block_index));
+	BXE_PRINTF(
+	    "    0x%04X - USTORM [ETH_RDMA_RX_CQ_CONS]\n",
+	    le16toh(dsb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS]));
+	BXE_PRINTF(
+	    "    0x%04X - USTORM [ETH_ISCSI_RX_CQ_CONS]\n",
+	    le16toh(dsb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS]));
+	BXE_PRINTF(
+	    "    0x%04X - USTORM [ETH_RDMA_RX_BD_CONS]\n",
+	    le16toh(dsb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS]));
+	BXE_PRINTF(
+	    "    0x%04X - USTORM [ETH_ISCSI_RX_BD_CONS]\n",
+	    le16toh(dsb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS]));
+
+	/* Print the CSTORM fields (HC_CSTORM_DEF_SB_NUM_INDICES). */
+	BXE_PRINTF(
+	    "      0x%02X - CSTORM Status Block ID\n",
+	    dsb->c_def_status_block.status_block_id);
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM Status Block Index\n",
+	    le16toh(dsb->c_def_status_block.status_block_index));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [RDMA_EQ_CONS]\n",
+	    le16toh(dsb->c_def_status_block.index_values[HC_INDEX_DEF_C_RDMA_EQ_CONS]));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [RDMA_NAL_PROD]\n",
+	    le16toh(dsb->c_def_status_block.index_values[HC_INDEX_DEF_C_RDMA_NAL_PROD]));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [ETH_FW_TX_CQ_CONS]\n",
+	    le16toh(dsb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS]));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [ETH_SLOW_PATH]\n",
+	    le16toh(dsb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_SLOW_PATH]));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [ETH_RDMA_CQ_CONS]\n",
+	    le16toh(dsb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS]));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [ETH_ISCSI_CQ_CONS]\n",
+	    le16toh(dsb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS]));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [UNUSED]\n",
+	    le16toh(dsb->c_def_status_block.index_values[6]));
+	BXE_PRINTF(
+	    "    0x%04X - CSTORM [UNUSED]\n",
+	    le16toh(dsb->c_def_status_block.index_values[7]));
+
+	/* Print the TSTORM fields (HC_TSTORM_DEF_SB_NUM_INDICES). */
+	BXE_PRINTF(
+	    "      0x%02X - TSTORM Status Block ID\n",
+	    dsb->t_def_status_block.status_block_id);
+	BXE_PRINTF(
+	    "    0x%04X - TSTORM Status Block Index\n",
+	    le16toh(dsb->t_def_status_block.status_block_index));
+	for (i = 0; i < HC_TSTORM_DEF_SB_NUM_INDICES; i++)
+		BXE_PRINTF("    0x%04X - TSTORM [UNUSED]\n",
+		    le16toh(dsb->t_def_status_block.index_values[i]));
+
+	/* Print the XSTORM fields (HC_XSTORM_DEF_SB_NUM_INDICES). */
+	BXE_PRINTF(
+	    "      0x%02X - XSTORM Status Block ID\n",
+	    dsb->x_def_status_block.status_block_id);
+	BXE_PRINTF(
+	    "    0x%04X - XSTORM Status Block Index\n",
+	    le16toh(dsb->x_def_status_block.status_block_index));
+	for (i = 0; i < HC_XSTORM_DEF_SB_NUM_INDICES; i++)
+		BXE_PRINTF("    0x%04X - XSTORM [UNUSED]\n",
+		    le16toh(dsb->x_def_status_block.index_values[i]));
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+
+/*
+ * Prints out the statistics block from host memory.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_stats_block(struct bxe_softc *sc)
+{
+
+}
+
+/*
+ * Prints out a summary of the fastpath state.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_fp_state(struct bxe_fastpath *fp)
+{
+	struct bxe_softc *sc;
+	uint32_t val_hi, val_lo;
+	int i;
+
+	sc = fp->sc;
+	BXE_PRINTF(
+	    "----------------------------"
+		" Fastpath State "
+		"----------------------------\n");
+
+	val_hi = U64_HI(fp);
+	val_lo = U64_LO(fp);
+	BXE_PRINTF(
+	    "0x%08X:%08X - (fp[%02d]) fastpath virtual address\n",
+	    val_hi, val_lo, fp->index);
+	BXE_PRINTF(
+	    "                %3d - (fp[%02d]->sb_id)\n",
+	    fp->sb_id, fp->index);
+	BXE_PRINTF(
+	    "                %3d - (fp[%02d]->cl_id)\n",
+	    fp->cl_id, fp->index);
+	BXE_PRINTF(
+	    "         0x%08X - (fp[%02d]->state)\n",
+	    (uint32_t)fp->state, fp->index);
+
+	if (CHIP_IS_E1(sc)) {
+		for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1; i++)
+			BXE_PRINTF(
+			    "         0x%08X - (fp[%02d]->tpa_state[%02d])\n",
+			    (uint32_t)fp->tpa_state[i], fp->index, i);
+	} else {
+		for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1; i++)
+			BXE_PRINTF(
+			    "         0x%08X - (fp[%02d]->tpa_state[%02d])\n",
+			    (uint32_t)fp->tpa_state[i], fp->index, i);
+	}
+
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->free_rx_bd)\n",
+	    fp->free_rx_bd, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->rx_bd_prod)\n",
+	    fp->rx_bd_prod, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->rx_bd_cons)\n",
+	    fp->rx_bd_cons, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->rx_comp_prod)\n",
+	    fp->rx_comp_prod, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->rx_comp_cons)\n",
+	    fp->rx_comp_cons, fp->index);
+	BXE_PRINTF(
+	    "   %16lu - (fp[%02d]->rx_pkts)\n",
+	    fp->rx_pkts, fp->index);
+	BXE_PRINTF(
+	    "   %16lu - (fp[%02d]->tpa_pkts)\n",
+	    fp->tpa_pkts, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->used_tx_bd)\n",
+	    fp->used_tx_bd, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->tx_pkt_prod)\n",
+	    fp->tx_pkt_prod, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->tx_pkt_cons)\n",
+	    fp->tx_pkt_cons, fp->index);
+	BXE_PRINTF(
+	    "             0x%04X - (fp[%02d]->tx_bd_prod)\n",
+	    fp->tx_bd_prod, fp->index);
+	BXE_PRINTF(
+	    "   %16lu - (fp[%02d]->tx_pkts)\n",
+	    fp->tx_pkts, fp->index);
+	BXE_PRINTF(
+	    "         0x%08X - (fp[%02d]->tx_mbuf_alloc)\n",
+	    fp->tx_mbuf_alloc, fp->index);
+	BXE_PRINTF(
+	    "         0x%08X - (fp[%02d]->rx_mbuf_alloc)\n",
+	    fp->rx_mbuf_alloc, fp->index);
+	BXE_PRINTF(
+	    "         0x%08X - (fp[%02d]->tpa_mbuf_alloc)\n",
+	    fp->tpa_mbuf_alloc, fp->index);
+	BXE_PRINTF(
+	    "         0x%08X - (fp[%02d]->sge_mbuf_alloc)\n",
+	    fp->sge_mbuf_alloc, fp->index);
+	BXE_PRINTF(
+	    "   %16lu - (fp[%02d]->ipackets)\n",
+	    fp->ipackets, fp->index);
+	BXE_PRINTF(
+	    "   %16lu - (fp[%02d]->opackets)\n",
+	    fp->opackets, fp->index);
+	BXE_PRINTF(
+	    "   %16lu - (fp[%02d]->soft_rx_errors)\n",
+	    fp->soft_rx_errors, fp->index);
+	BXE_PRINTF(
+	    "   %16lu - (fp[%02d]->soft_tx_errors)\n",
+	    fp->soft_tx_errors, fp->index);
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_port_state_locked(struct bxe_softc *sc)
+{
+
+	BXE_PRINTF(
+	    "------------------------------"
+	    " Port State "
+	    "------------------------------\n");
+
+	BXE_PRINTF(
+	    "        %2d - (port) pmf\n", sc->port.pmf);
+	BXE_PRINTF(
+	    "0x%08X - (port) link_config\n", sc->port.link_config);
+	BXE_PRINTF(
+	    "0x%08X - (port) supported\n", sc->port.supported);
+	BXE_PRINTF(
+	    "0x%08X - (port) advertising\n", sc->port.advertising);
+	BXE_PRINTF(
+	    "0x%08X - (port) port_stx\n", sc->port.port_stx);
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_link_vars_state_locked(struct bxe_softc *sc)
+{
+	BXE_PRINTF(
+	    "---------------------------"
+	    " Link Vars State "
+	    "----------------------------\n");
+
+	switch (sc->link_vars.mac_type) {
+	case MAC_TYPE_NONE:
+		BXE_PRINTF("      NONE");
+		break;
+	case MAC_TYPE_EMAC:
+		BXE_PRINTF("      EMAC");
+		break;
+	case MAC_TYPE_BMAC:
+		BXE_PRINTF("      BMAC");
+		break;
+	default:
+		BXE_PRINTF("      UNKN");
+	}
+	printf(" - (link_vars->mac_type)\n");
+
+	BXE_PRINTF(
+	    "        %2d - (link_vars->phy_link_up)\n",
+	    sc->link_vars.phy_link_up);
+	BXE_PRINTF(
+	    "        %2d - (link_vars->link_up)\n",
+	    sc->link_vars.link_up);
+	BXE_PRINTF(
+	    "        %2d - (link_vars->duplex)\n",
+	    sc->link_vars.duplex);
+	BXE_PRINTF(
+	    "    0x%04X - (link_vars->flow_ctrl)\n",
+	    sc->link_vars.flow_ctrl);
+	BXE_PRINTF(
+	    "    0x%04X - (link_vars->line_speed)\n",
+	    sc->link_vars.line_speed);
+	BXE_PRINTF(
+	    "0x%08X - (link_vars->ieee_fc)\n",
+	    sc->link_vars.ieee_fc);
+	BXE_PRINTF(
+	    "0x%08X - (link_vars->autoneg)\n",
+	    sc->link_vars.autoneg);
+	BXE_PRINTF(
+	    "0x%08X - (link_vars->phy_flags)\n",
+	    sc->link_vars.phy_flags);
+	BXE_PRINTF(
+	    "0x%08X - (link_vars->link_status)\n",
+	    sc->link_vars.link_status);
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+
+/*
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_link_params_state_locked(struct bxe_softc *sc)
+{
+	BXE_PRINTF(
+	    "--------------------------"
+	    " Link Params State "
+	    "---------------------------\n");
+
+	BXE_PRINTF(
+	    "        %2d - (link_params->port)\n",
+	    sc->link_params.port);
+	BXE_PRINTF(
+	    "        %2d - (link_params->loopback_mode)\n",
+	    sc->link_params.loopback_mode);
+	BXE_PRINTF(
+	    "       %3d - (link_params->phy_addr)\n",
+	    sc->link_params.phy_addr);
+	BXE_PRINTF(
+	    "    0x%04X - (link_params->req_duplex)\n",
+	    sc->link_params.req_duplex);
+	BXE_PRINTF(
+	    "    0x%04X - (link_params->req_flow_ctrl)\n",
+	    sc->link_params.req_flow_ctrl);
+	BXE_PRINTF(
+	    "    0x%04X - (link_params->req_line_speed)\n",
+	    sc->link_params.req_line_speed);
+	BXE_PRINTF(
+	    "     %5d - (link_params->ether_mtu)\n",
+	    sc->port.ether_mtu);
+	BXE_PRINTF(
+	    "0x%08X - (link_params->shmem_base) shared memory base address\n",
+	    sc->link_params.shmem_base);
+	BXE_PRINTF(
+	    "0x%08X - (link_params->speed_cap_mask)\n",
+	    sc->link_params.speed_cap_mask);
+	BXE_PRINTF(
+	    "0x%08X - (link_params->ext_phy_config)\n",
+	    sc->link_params.ext_phy_config);
+	BXE_PRINTF(
+	    "0x%08X - (link_params->switch_cfg)\n",
+	    sc->link_params.switch_cfg);
+
+	BXE_PRINTF(
+	    "----------------------------"
+		"----------------"
+		"----------------------------\n");
+}
+
+/*
+ * Prints out a summary of the driver state.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static __attribute__ ((noinline))
+void bxe_dump_driver_state(struct bxe_softc *sc)
+{
+	uint32_t val_hi, val_lo;
+
+	BXE_PRINTF(
+	    "-----------------------------"
+	    " Driver State "
+	    "-----------------------------\n");
+
+	val_hi = U64_HI(sc);
+	val_lo = U64_LO(sc);
+	BXE_PRINTF(
+	    "0x%08X:%08X - (sc) driver softc structure virtual address\n",
+	    val_hi, val_lo);
+
+	val_hi = U64_HI(sc->bxe_vhandle);
+	val_lo = U64_LO(sc->bxe_vhandle);
+	BXE_PRINTF(
+	    "0x%08X:%08X - (sc->bxe_vhandle) PCI BAR0 virtual address\n",
+	    val_hi, val_lo);
+
+	val_hi = U64_HI(sc->bxe_db_vhandle);
+	val_lo = U64_LO(sc->bxe_db_vhandle);
+	BXE_PRINTF(
+	    "0x%08X:%08X - (sc->bxe_db_vhandle) PCI BAR2 virtual address\n",
+	    val_hi, val_lo);
+
+	val_hi = U64_HI(sc->fp);
+	val_lo = U64_LO(sc->fp);
+	BXE_PRINTF(
+	    "0x%08X:%08X - (sc->fp) Fastpath address\n",
+	    val_hi, val_lo);
+	BXE_PRINTF(
+	    "         0x%08X - (sc->num_queues) Number of fastpath queues\n",
+	    sc->num_queues);
+	BXE_PRINTF(
+	    "         0x%08X - (sc->rx_lane_swap) Receive XAUI lane swap\n",
+	    sc->rx_lane_swap);
+	BXE_PRINTF(
+	    "         0x%08X - (sc->tx_lane_swap) Transmit XAUI lane swap\n",
+	    sc->tx_lane_swap);
+	BXE_PRINTF(
+	    "   %16lu - (sc->debug_mbuf_sim_alloc_failed)\n",
+	    sc->debug_mbuf_sim_alloc_failed);
+	BXE_PRINTF(
+	    "   %16lu - (sc->debug_mbuf_sim_map_failed)\n",
+	    sc->debug_mbuf_sim_map_failed);
+	BXE_PRINTF(
+	    "   %16lu - (sc->debug_memory_allocated)\n",
+	    sc->debug_memory_allocated);
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+
+	bxe_dump_port_state_locked(sc);
+	bxe_dump_link_params_state_locked(sc);
+	bxe_dump_link_vars_state_locked(sc);
+}
+
+/*
+ * Dump bootcode debug buffer to the console.
+ *
+ * Returns:
+ *   None
+ */
+static __attribute__ ((noinline))
+void bxe_dump_fw(struct bxe_softc *sc)
+{
+	uint32_t data[9], mark, offset;
+	int word;
+
+	mark = REG_RD(sc, MCP_REG_MCPR_SCRATCH + 0xf104);
+	mark = ((mark + 0x3) & ~0x3);
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    " Bootcode State "
+	    "----------------------------\n");
+	BXE_PRINTF("Begin MCP bootcode dump (mark = 0x%08X)\n", mark);
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+
+	for (offset = mark - 0x08000000; offset <= 0xF900;
+	    offset += (0x8 * 4)) {
+		for (word = 0; word < 8; word++)
+			data[word] = htonl(REG_RD(sc, MCP_REG_MCPR_SCRATCH +
+			    offset + 4 * word));
+		data[8] = 0x0;
+		printf("%s", (char *) data);
+	}
+
+	for (offset = 0xF108; offset <= mark - 0x08000000;
+		offset += (0x8 * 4)) {
+		for (word = 0; word < 8; word++)
+			data[word] = htonl(REG_RD(sc, MCP_REG_MCPR_SCRATCH +
+			    offset + 4 * word));
+		data[8] = 0x0;
+		printf("%s", (char *) data);
+	}
+
+	BXE_PRINTF(
+	    "----------------------------"
+	    "----------------"
+	    "----------------------------\n");
+}
+
+/*
+ * Decode firmware messages.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_decode_mb_msgs(struct bxe_softc *sc, uint32_t drv_mb_header,
+    uint32_t fw_mb_header)
+{
+
+	if (drv_mb_header) {
+		BXE_PRINTF("Driver message is ");
+		switch (drv_mb_header & DRV_MSG_CODE_MASK) {
+		case DRV_MSG_CODE_LOAD_REQ:
+			printf(
+			    "LOAD_REQ (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_LOAD_REQ);
+			break;
+		case DRV_MSG_CODE_LOAD_DONE:
+			printf(
+			    "LOAD_DONE (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_LOAD_DONE);
+			break;
+		case DRV_MSG_CODE_UNLOAD_REQ_WOL_EN:
+			printf(
+			    "UNLOAD_REQ_WOL_EN (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_UNLOAD_REQ_WOL_EN);
+			break;
+		case DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS:
+			printf(
+			    "UNLOAD_REQ_WOL_DIS (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS);
+			break;
+		case DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP:
+			printf(
+			    "UNLOADREQ_WOL_MCP (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
+			break;
+		case DRV_MSG_CODE_UNLOAD_DONE:
+			printf(
+			    "UNLOAD_DONE (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_UNLOAD_DONE);
+			break;
+		case DRV_MSG_CODE_DIAG_ENTER_REQ:
+			printf(
+			    "DIAG_ENTER_REQ (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_DIAG_ENTER_REQ);
+			break;
+		case DRV_MSG_CODE_DIAG_EXIT_REQ:
+			printf(
+			    "DIAG_EXIT_REQ (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_DIAG_EXIT_REQ);
+			break;
+		case DRV_MSG_CODE_VALIDATE_KEY:
+			printf(
+			    "CODE_VALIDITY_KEY (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_VALIDATE_KEY);
+			break;
+		case DRV_MSG_CODE_GET_CURR_KEY:
+			printf(
+			    "GET_CURR_KEY (0x%08X)",
+			    (uint32_t) DRV_MSG_CODE_GET_CURR_KEY);
+			break;
+		case DRV_MSG_CODE_GET_UPGRADE_KEY:
+			printf(
+			    "GET_UPGRADE_KEY (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_GET_UPGRADE_KEY);
+			break;
+		case DRV_MSG_CODE_GET_MANUF_KEY:
+			printf(
+			    "GET_MANUF_KEY (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_GET_MANUF_KEY);
+			break;
+		case DRV_MSG_CODE_LOAD_L2B_PRAM:
+			printf(
+			    "LOAD_L2B_PRAM (0x%08X)",
+			    (uint32_t)DRV_MSG_CODE_LOAD_L2B_PRAM);
+				break;
+		case BIOS_MSG_CODE_LIC_CHALLENGE:
+			printf(
+			    "LIC_CHALLENGE (0x%08X)",
+			    (uint32_t)BIOS_MSG_CODE_LIC_CHALLENGE);
+			break;
+		case BIOS_MSG_CODE_LIC_RESPONSE:
+			printf(
+			    "LIC_RESPONSE (0x%08X)",
+			    (uint32_t)BIOS_MSG_CODE_LIC_RESPONSE);
+			break;
+		case BIOS_MSG_CODE_VIRT_MAC_PRIM:
+			printf(
+			    "VIRT_MAC_PRIM (0x%08X)",
+			    (uint32_t)BIOS_MSG_CODE_VIRT_MAC_PRIM);
+			break;
+		case BIOS_MSG_CODE_VIRT_MAC_ISCSI:
+			printf(
+			    "VIRT_MAC_ISCSI (0x%08X)",
+			    (uint32_t)BIOS_MSG_CODE_VIRT_MAC_ISCSI);
+			break;
+		default:
+			printf(
+			    "Unknown command (0x%08X)!",
+			    (drv_mb_header & DRV_MSG_CODE_MASK));
+		}
+
+		printf(" (seq = 0x%04X)\n", (drv_mb_header &
+		    DRV_MSG_SEQ_NUMBER_MASK));
+	}
+
+	if (fw_mb_header) {
+		BXE_PRINTF("Firmware response is ");
+		switch (fw_mb_header & FW_MSG_CODE_MASK) {
+		case FW_MSG_CODE_DRV_LOAD_COMMON:
+			printf(
+			    "DRV_LOAD_COMMON (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_LOAD_COMMON);
+			break;
+		case FW_MSG_CODE_DRV_LOAD_PORT:
+			printf(
+			    "DRV_LOAD_PORT (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_LOAD_PORT);
+			break;
+		case FW_MSG_CODE_DRV_LOAD_FUNCTION:
+			printf(
+			    "DRV_LOAD_FUNCTION (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_LOAD_FUNCTION);
+			break;
+		case FW_MSG_CODE_DRV_LOAD_REFUSED:
+			printf(
+			    "DRV_LOAD_REFUSED (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_LOAD_REFUSED);
+			break;
+		case FW_MSG_CODE_DRV_LOAD_DONE:
+			printf(
+			    "DRV_LOAD_DONE (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_LOAD_DONE);
+			break;
+		case FW_MSG_CODE_DRV_UNLOAD_COMMON:
+			printf(
+			    "DRV_UNLOAD_COMMON (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_UNLOAD_COMMON);
+			break;
+		case FW_MSG_CODE_DRV_UNLOAD_PORT:
+			printf(
+			    "DRV_UNLOAD_PORT (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_UNLOAD_PORT);
+			break;
+		case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
+			printf(
+			    "DRV_UNLOAD_FUNCTION (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
+			break;
+		case FW_MSG_CODE_DRV_UNLOAD_DONE:
+			printf(
+			    "DRV_UNLOAD_DONE (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DRV_UNLOAD_DONE);
+			break;
+		case FW_MSG_CODE_DIAG_ENTER_DONE:
+			printf(
+			    "DIAG_ENTER_DONE (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DIAG_ENTER_DONE);
+			break;
+		case FW_MSG_CODE_DIAG_REFUSE:
+			printf(
+			    "DIAG_REFUSE (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DIAG_REFUSE);
+			break;
+		case FW_MSG_CODE_DIAG_EXIT_DONE:
+			printf(
+			    "DIAG_EXIT_DONE (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_DIAG_EXIT_DONE);
+			break;
+		case FW_MSG_CODE_VALIDATE_KEY_SUCCESS:
+			printf(
+			    "VALIDATE_KEY_SUCCESS (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_VALIDATE_KEY_SUCCESS);
+			break;
+		case FW_MSG_CODE_VALIDATE_KEY_FAILURE:
+			printf(
+			    "VALIDATE_KEY_FAILURE (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_VALIDATE_KEY_FAILURE);
+			break;
+		case FW_MSG_CODE_GET_KEY_DONE:
+			printf(
+			    "GET_KEY_DONE (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_GET_KEY_DONE);
+			break;
+		case FW_MSG_CODE_NO_KEY:
+			printf(
+			    "NO_KEY (0x%08X)",
+			    (uint32_t)FW_MSG_CODE_NO_KEY);
+			break;
+		default:
+			printf(
+			    "unknown value (0x%08X)!",
+			    (fw_mb_header & FW_MSG_CODE_MASK));
+		}
+
+		printf(" (seq = 0x%04X)\n", (fw_mb_header &
+		    FW_MSG_SEQ_NUMBER_MASK));
+	}
+}
+
+/*
+ * Prints a text string for the ramrod command.
+ *
+ * Returns:
+ *   None
+ */
+static void
+bxe_decode_ramrod_cmd(struct bxe_softc *sc, int command)
+{
+	BXE_PRINTF("Ramrod command = ");
+
+	switch (command) {
+	case RAMROD_CMD_ID_ETH_PORT_SETUP:
+		printf("ETH_PORT_SETUP\n");
+		break;
+	case RAMROD_CMD_ID_ETH_CLIENT_SETUP:
+		printf("ETH_CLIENT_SETUP\n");
+		break;
+	case RAMROD_CMD_ID_ETH_STAT_QUERY:
+		printf("ETH_STAT_QUERY\n");
+		break;
+	case RAMROD_CMD_ID_ETH_UPDATE:
+		printf("ETH_UPDATE\n");
+		break;
+	case RAMROD_CMD_ID_ETH_HALT:
+		printf("ETH_HALT\n");
+		break;
+	case RAMROD_CMD_ID_ETH_SET_MAC:
+		printf("ETH_SET_MAC\n");
+		break;
+	case RAMROD_CMD_ID_ETH_CFC_DEL:
+		printf("ETH_CFC_DEL\n");
+		break;
+	case RAMROD_CMD_ID_ETH_PORT_DEL:
+		printf("ETH_PORT_DEL\n");
+		break;
+	case RAMROD_CMD_ID_ETH_FORWARD_SETUP:
+		printf("ETH_FORWARD_SETUP\n");
+		break;
+	default:
+		printf("Unknown ramrod command!\n");
+	}
+}
+
+
+/*
+ * Prints out driver information and forces a kernel breakpoint.
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_breakpoint(struct bxe_softc *sc)
+{
+	struct bxe_fastpath *fp;
+	int i;
+
+	fp = &sc->fp[0];
+	/* Unreachable code to silence the compiler about unused functions. */
+	if (0) {
+		bxe_reg_read16(sc, PCICFG_OFFSET);
+		bxe_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
+		bxe_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
+		bxe_dump_tx_chain(fp, 0, USABLE_TX_BD);
+		bxe_dump_cqe_chain(fp, 0, USABLE_RCQ_ENTRIES);
+		bxe_dump_rx_chain(fp, 0, USABLE_RX_BD);
+		bxe_dump_status_block(sc);
+		bxe_dump_stats_block(sc);
+		bxe_dump_fp_state(fp);
+		bxe_dump_driver_state(sc);
+		bxe_dump_hw_state(sc);
+		bxe_dump_fw(sc);
+	}
+
+	/*
+	 * Do some device sanity checking.  Run it twice in case
+	 * the hardware is still running so we can identify any
+	 * transient conditions.
+	 */
+	bxe_idle_chk(sc); bxe_idle_chk(sc);
+
+	bxe_dump_driver_state(sc);
+
+	for (i = 0; i < sc->num_queues; i++)
+		bxe_dump_fp_state(&sc->fp[i]);
+
+	bxe_dump_status_block(sc);
+
+	/* Call the OS debugger. */
+	breakpoint();
+}
+#endif
+
+/*
+ *
+ * Returns:
+ *   Nothing.
+ */
+static void
+bxe_gunzip_end(struct bxe_softc *sc)
+{
+	free(sc->strm, M_DEVBUF);
+	sc->strm = NULL;
+
+	if (sc->gunzip_buf) {
+		bxe_dmamem_free(sc, sc->gunzip_tag, sc->gunzip_buf,
+		    sc->gunzip_map);
+		sc->gunzip_buf = NULL;
+	}
+}
diff --git a/sys/dev/bxe/if_bxe.h b/sys/dev/bxe/if_bxe.h
new file mode 100755
index 0000000..2b9fefb
--- /dev/null
+++ b/sys/dev/bxe/if_bxe.h
@@ -0,0 +1,1853 @@
+/*-
+ * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
+ *
+ *    Gary Zambrano <zambrano@broadcom.com>
+ *    David Christensen <davidch@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*$FreeBSD$*/
+
+#ifndef _IF_BXE_H
+#define	_IF_BXE_H
+
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/sysctl.h>
+#include <sys/queue.h>
+#include <sys/taskqueue.h>
+#include <sys/pcpu.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+#include <net/zlib.h>
+#include <net/bpf.h>
+
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <netinet/ip6.h>
+#include <netinet/tcp.h>
+#include <netinet/udp.h>
+
+#include <machine/resource.h>
+#include <machine/in_cksum.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include "miidevs.h"
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include "miibus_if.h"
+
+
+/*
+ * Device identification definitions.
+ */
+#define	BRCM_VENDORID				0x14E4
+#define	BRCM_DEVICEID_BCM57710		0x164E
+#define	BRCM_DEVICEID_BCM57711		0x164F
+#define	BRCM_DEVICEID_BCM57711E		0x1650
+
+#define PCI_ANY_ID				(u_int16_t) (~0U)
+
+
+struct bxe_type {
+	u_int16_t		bxe_vid;
+	u_int16_t		bxe_did;
+	u_int16_t		bxe_svid;
+	u_int16_t		bxe_sdid;
+	char			*bxe_name;
+};
+
+#define	STORM_ASSERT_ARRAY_SIZE	50
+
+#define	ATTN_NIG_FOR_FUNC	(1L << 8)
+#define	ATTN_SW_TIMER_4_FUNC	(1L << 9)
+#define	GPIO_2_FUNC		(1L << 10)
+#define	GPIO_3_FUNC		(1L << 11)
+#define	GPIO_4_FUNC		(1L << 12)
+
+#define	ATTN_GENERAL_ATTN_1	(1L << 13)
+#define	ATTN_GENERAL_ATTN_2	(1L << 14)
+#define	ATTN_GENERAL_ATTN_3	(1L << 15)
+#define	ATTN_GENERAL_ATTN_4	(1L << 13)
+#define	ATTN_GENERAL_ATTN_5	(1L << 14)
+#define	ATTN_GENERAL_ATTN_6	(1L << 15)
+
+#define	ATTN_HARD_WIRED_MASK	0xff00
+
+
+/*
+ * Convenience definitions.
+ */
+#define	BXE_CORE_LOCK_INIT(sc, name)					\
+	mtx_init(&(sc->bxe_core_mtx), name,				\
+	"BXE Core Lock", MTX_DEF)
+#define	BXE_SP_LOCK_INIT(sc, name)					\
+	mtx_init(&(sc->bxe_sp_mtx), name,				\
+	"BXE Slowpath Lock", MTX_DEF)
+#define	BXE_DMAE_LOCK_INIT(sc, name)					\
+	mtx_init(&(sc->bxe_dmae_mtx), name,				\
+	"BXE DMAE Lock", MTX_DEF)
+#define	BXE_PHY_LOCK_INIT(sc, name)					\
+	mtx_init(&(sc->port.bxe_phy_mtx), name,				\
+	"BXE PHY Lock", MTX_DEF)
+#define	BXE_FWMB_LOCK_INIT(sc, name)					\
+	mtx_init(&(sc->bxe_fwmb_mtx), name,				\
+	"BXE FWMB Lock", MTX_DEF)
+
+#define	BXE_PRINT_LOCK_INIT(sc, name)					\
+	mtx_init(&(sc->bxe_print_mtx), name,				\
+	"BXE PRINT Lock", MTX_DEF)
+
+#define	BXE_CORE_LOCK(sc)						\
+	mtx_lock(&(sc->bxe_core_mtx))
+#define	BXE_SP_LOCK(sc)							\
+	mtx_lock(&(sc->bxe_sp_mtx))
+#define	BXE_DMAE_LOCK(sc)						\
+	mtx_lock(&(sc->bxe_dmae_mtx))
+#define	BXE_PHY_LOCK(sc)						\
+	mtx_lock(&(sc->port.bxe_phy_mtx))
+#define	BXE_FWMB_LOCK(sc)						\
+	mtx_lock(&(sc->bxe_fwmb_mtx))
+
+#define	BXE_PRINT_LOCK(sc)						\
+	mtx_lock(&(sc->bxe_print_mtx))
+
+#define	BXE_CORE_LOCK_ASSERT(sc)					\
+	mtx_assert(&(sc->bxe_core_mtx), MA_OWNED)
+#define	BXE_SP_LOCK_ASSERT(sc)						\
+	mtx_assert(&(sc->bxe_sp_mtx), MA_OWNED)
+#define	BXE_DMAE_LOCK_ASSERT(sc)					\
+	mtx_assert(&(sc->bxe_dmae_mtx), MA_OWNED)
+#define	BXE_PHY_LOCK_ASSERT(sc)						\
+	mtx_assert(&(sc->port.bxe_phy_mtx), MA_OWNED)
+
+#define	BXE_CORE_UNLOCK(sc)						\
+	mtx_unlock(&(sc->bxe_core_mtx))
+#define	BXE_SP_UNLOCK(sc)						\
+	mtx_unlock(&(sc->bxe_sp_mtx))
+#define	BXE_DMAE_UNLOCK(sc)						\
+	mtx_unlock(&(sc->bxe_dmae_mtx))
+#define	BXE_PHY_UNLOCK(sc)						\
+	mtx_unlock(&(sc->port.bxe_phy_mtx))
+#define	BXE_FWMB_UNLOCK(sc)						\
+	mtx_unlock(&(sc->bxe_fwmb_mtx))
+
+#define	BXE_PRINT_UNLOCK(sc)						\
+	mtx_unlock(&(sc->bxe_print_mtx))
+
+#define	BXE_CORE_LOCK_DESTROY(sc)					\
+	if (mtx_initialized(&(sc->bxe_core_mtx))) {			\
+		mtx_destroy(&(sc->bxe_core_mtx));			\
+	}
+#define	BXE_SP_LOCK_DESTROY(sc)						\
+	if (mtx_initialized(&(sc->bxe_sp_mtx))) {			\
+		mtx_destroy(&(sc->bxe_sp_mtx));				\
+	}
+#define	BXE_DMAE_LOCK_DESTROY(sc)					\
+	if (mtx_initialized(&(sc->bxe_dmae_mtx))) {			\
+		mtx_destroy(&(sc->bxe_dmae_mtx));			\
+	}
+#define	BXE_PHY_LOCK_DESTROY(sc)					\
+	if (mtx_initialized(&(sc->port.bxe_phy_mtx))) {			\
+		mtx_destroy(&(sc->port.bxe_phy_mtx));			\
+	}
+
+#define	BXE_FWMB_LOCK_DESTROY(sc)					\
+	if (mtx_initialized(&(sc->bxe_fwmb_mtx))) {			\
+		mtx_destroy(&(sc->bxe_fwmb_mtx));			\
+	}
+
+#define	BXE_PRINT_LOCK_DESTROY(sc)					\
+	if (mtx_initialized(&(sc->bxe_print_mtx))) {			\
+		mtx_destroy(&(sc->bxe_print_mtx));			\
+	}
+
+/* Must be used on a CID before placing it on a HW chain. */
+#define	HW_CID(sc, x)							\
+	((BP_PORT(sc) << 23) | (BP_E1HVN(sc) << 17) | x)
+
+/* Used on a CID received from the HW. */
+#define	SW_CID(x)							\
+	(le32toh(x) & (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
+
+#define	CQE_CMD(x)							\
+	(le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
+
+#define	DPM_TRIGGER_TYPE	0x40
+#define	DOORBELL(sc, cid, val)	do{					\
+	bus_space_write_4(sc->bxe_db_btag, sc->bxe_db_bhandle,		\
+	((BCM_PAGE_SIZE * (cid)) + DPM_TRIGGER_TYPE), (uint32_t)val);	\
+} while(0)
+
+#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
+/* Define the macro based on whether CPU is 32 or 64 bit. */
+#define	U64_LO(y)		((uint64_t) (y) & 0xFFFFFFFF)
+#define	U64_HI(y)		((uint64_t) (y) >> 32)
+#else
+#define	U64_LO(y)		((uint32_t)y)
+#define	U64_HI(y)		(0)
+#endif
+
+#define	HILO_U64(hi, lo)	(((uint64_t)hi << 32) + lo)
+
+#define	BXE_HAS_WORK(fp)						\
+	(bxe_has_rx_work(fp) || bxe_has_tx_work(fp))
+
+/* Define the page size of the host CPU. */
+#define	BCM_PAGE_SHIFT		12
+#define	BCM_PAGE_SIZE		(1 << BCM_PAGE_SHIFT)
+#define	BCM_PAGE_MASK		(~(BCM_PAGE_SIZE - 1))
+#define	BCM_PAGE_ALIGN(addr)	((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
+
+#if BCM_PAGE_SIZE != 4096
+#error Page sizes other than 4KB not currently supported!
+#endif
+
+/* MC hsi */
+#define	PAGES_PER_SGE_SHIFT	0
+#define	PAGES_PER_SGE		(1 << PAGES_PER_SGE_SHIFT)
+#define	SGE_PAGE_SIZE		PAGE_SIZE
+#define	SGE_PAGE_SHIFT		PAGE_SHIFT
+#define	SGE_PAGE_ALIGN(addr)	PAGE_ALIGN(addr)
+
+/* SGE ring related macros */
+#define	NUM_RX_SGE_PAGES	2
+#define	RX_SGE_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
+#define	MAX_RX_SGE_CNT		(RX_SGE_CNT - 2)
+
+/* RX_SGE_CNT is required to be a power of 2 */
+#define	RX_SGE_MASK		(RX_SGE_CNT - 1)
+#define	TOTAL_RX_SGE		(RX_SGE_CNT * NUM_RX_SGE_PAGES)
+#define	MAX_RX_SGE		(TOTAL_RX_SGE - 1)
+#define	NEXT_SGE_IDX(x)							\
+	((((x) & RX_SGE_MASK) == (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
+#define	RX_SGE(x)		((x) & MAX_RX_SGE)
+#define	RX_SGE_PAGE(x)		(((x) & ~RX_SGE_MASK) >> 9)
+#define	RX_SGE_IDX(x)		((x) & RX_SGE_MASK)
+
+/* SGE producer mask related macros. */
+/* Number of bits in one sge_mask array element. */
+#define	RX_SGE_MASK_ELEM_SZ	64
+#define	RX_SGE_MASK_ELEM_SHIFT	6
+#define	RX_SGE_MASK_ELEM_MASK	((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
+
+/*
+ * Creates a bitmask of all ones in less significant bits.
+ * idx - index of the most significant bit in the created mask.
+ */
+#define	RX_SGE_ONES_MASK(idx)						\
+	(((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
+#define	RX_SGE_MASK_ELEM_ONE_MASK	((uint64_t)(~0))
+
+/* Number of uint64_t elements in SGE mask array. */
+#define	RX_SGE_MASK_LEN							\
+	((NUM_RX_SGE_PAGES * RX_SGE_CNT) / RX_SGE_MASK_ELEM_SZ)
+#define	RX_SGE_MASK_LEN_MASK	(RX_SGE_MASK_LEN - 1)
+#define	NEXT_SGE_MASK_ELEM(el)	(((el) + 1) & RX_SGE_MASK_LEN_MASK)
+
+/* Transmit Buffer Descriptor (tx_bd) definitions. */
+
+/* ToDo: Tune this value based on multi-queue/RSS enable/disable. */
+#define	NUM_TX_PAGES		2
+
+#define	TOTAL_TX_BD_PER_PAGE	(BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
+#define	USABLE_TX_BD_PER_PAGE	(TOTAL_TX_BD_PER_PAGE - 1)
+#define	TOTAL_TX_BD		(TOTAL_TX_BD_PER_PAGE * NUM_TX_PAGES)
+#define	USABLE_TX_BD		(USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES)
+#define	MAX_TX_AVAIL		(USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES - 2)
+#define	MAX_TX_BD		(TOTAL_TX_BD - 1)
+#define	NEXT_TX_BD(x)							\
+	((((x) & USABLE_TX_BD_PER_PAGE) ==				\
+	(USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
+#define	TX_BD(x)		((x) & MAX_TX_BD)
+#define	TX_PAGE(x)		(((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
+#define	TX_IDX(x)		((x) & USABLE_TX_BD_PER_PAGE)
+
+/* Receive Buffer Descriptor (rx_bd) definitions. */
+#define	NUM_RX_PAGES		2
+/* 512 (0x200) of 8 byte bds in 4096 byte page. */
+#define	TOTAL_RX_BD_PER_PAGE	(BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
+/* 510 (0x1fe) = 512 - 2 */
+#define	USABLE_RX_BD_PER_PAGE	(TOTAL_RX_BD_PER_PAGE - 2)
+/* 1024 (0x400) */
+#define	TOTAL_RX_BD		(TOTAL_RX_BD_PER_PAGE * NUM_RX_PAGES)
+/* 1020 (0x3fc) = 1024 - 4 */
+#define	USABLE_RX_BD		(USABLE_RX_BD_PER_PAGE * NUM_RX_PAGES)
+/* 1023 (0x3ff) = 1024 -1 */
+#define	MAX_RX_BD		(TOTAL_RX_BD - 1)
+/* 511 (0x1ff) = 512 - 1 */
+#define	RX_DESC_MASK		(TOTAL_RX_BD_PER_PAGE - 1)
+
+#define	NEXT_RX_BD(x)							\
+	((((x) & RX_DESC_MASK) ==					\
+	(USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
+/* x & 0x3ff */
+#define	RX_BD(x)		((x) & MAX_RX_BD)
+#define	RX_PAGE(x)		(((x) & ~RX_DESC_MASK) >> 9)
+#define	RX_IDX(x)		((x) & RX_DESC_MASK)
+
+/* Receive Completion Queue definitions. */
+
+/* CQEs are 4 times larger (32 bytes) than rx_bd's (8 bytes). 8pages. */
+#define	NUM_RCQ_PAGES		(NUM_RX_PAGES * 4)
+/* 128 (0x80) */
+#define	TOTAL_RCQ_ENTRIES_PER_PAGE					\
+	(BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
+/* 127 (0x7f)for the next page RCQ bd */
+#define	USABLE_RCQ_ENTRIES_PER_PAGE	(TOTAL_RCQ_ENTRIES_PER_PAGE - 1)
+/* 1024 (0x400) */
+#define	TOTAL_RCQ_ENTRIES	(TOTAL_RCQ_ENTRIES_PER_PAGE * NUM_RCQ_PAGES)
+/* 1016 (0x3f8) */
+#define	USABLE_RCQ_ENTRIES	(USABLE_RCQ_ENTRIES_PER_PAGE * NUM_RCQ_PAGES)
+/* 1023 (0x3ff) */
+#define	MAX_RCQ_ENTRIES		(TOTAL_RCQ_ENTRIES - 1)
+
+#define	NEXT_RCQ_IDX(x)							\
+	((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) ==			\
+	(USABLE_RCQ_ENTRIES_PER_PAGE-1)) ? (x) + 2 : (x) + 1)
+#define	RCQ_ENTRY(x)		((x) & MAX_RCQ_ENTRIES)
+#define	RCQ_PAGE(x)		(((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
+#define	RCQ_IDX(x)		((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
+
+/* Slowpath Queue definitions. */
+#define	SP_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_spe))
+#define	MAX_SP_DESC_CNT		(SP_DESC_CNT - 1)
+#define	NEXT_SPE(x)		(((x) + 1 == (MAX_SP_DESC_CNT)) ? 0 : (x) + 1)
+
+/* This is needed for determening of last_max */
+#define	SUB_S16(a, b)		(int16_t)((int16_t)(a) - (int16_t)(b))
+
+#define	__SGE_MASK_SET_BIT(el, bit)	do {				\
+	el = ((el) | ((uint64_t)0x1 << (bit)));				\
+} while (0)
+
+#define	__SGE_MASK_CLEAR_BIT(el, bit)	do {				\
+	el = ((el) & (~((uint64_t)0x1 << (bit))));			\
+} while (0)
+
+#define	SGE_MASK_SET_BIT(fp, idx)					\
+	__SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
+	    ((idx) & RX_SGE_MASK_ELEM_MASK))
+
+#define	SGE_MASK_CLEAR_BIT(fp, idx)					\
+	__SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
+	    ((idx) & RX_SGE_MASK_ELEM_MASK))
+
+#define	BXE_TX_TIMEOUT			5
+#define	BXE_TX_CLEANUP_THRESHOLD	((USABLE_TX_BD * 7 ) / 8)
+
+#define	BXE_DMA_ALIGN			8
+#define	BXE_DMA_BOUNDARY		0
+
+/* ToDo: Need to verify the following 3 values. */
+
+/* Reduce from 13 to leave room for the parsing buffer. */
+#define	BXE_MAX_SEGMENTS		12
+#define	BXE_TSO_MAX_SIZE		65536
+#define	BXE_TSO_MAX_SEG_SIZE		4096
+
+/*
+ * Hardware Support For IP and TCP checksum.
+ * (Per packet hardware assist capabilites, derived.
+ * from CSUM_* in sys/mbuf.h).
+*/
+#define	BXE_IF_HWASSIST		(CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO)
+
+/*
+ * Per interface capabilities.
+ *
+ * ToDo: Consider adding IFCAP_WOL_MAGIC, IFCAP_TOE4,
+ * IFCAP_TSO6, IFCAP_WOL_UCAST.
+ */
+#if __FreeBSD_version < 700000
+#define	BXE_IF_CAPABILITIES						\
+	(IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM |		\
+	IFCAP_JUMBO_MTU | IFCAP_LRO)
+#else
+	/* TSO was introduced in FreeBSD 7 */
+#define	BXE_IF_CAPABILITIES						\
+	(IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM |		\
+	IFCAP_JUMBO_MTU | IFCAP_LRO | IFCAP_TSO4 | IFCAP_VLAN_HWCSUM)
+#endif
+
+/* Some typical Ethernet frame sizes */
+#define	BXE_MIN_MTU			60
+#define	BXE_MIN_ETHER_MTU		64
+
+#define	BXE_STD_MTU			1500
+#define	BXE_STD_ETHER_MTU		1518
+#define	BXE_STD_ETHER_MTU_VLAN		1522
+
+#define	BXE_JUMBO_MTU			9000
+#define	BXE_JUMBO_ETHER_MTU		9018
+#define	BXE_JUMBO_ETHER_MTU_VLAN	9022
+
+#define	BXE_BTR				3
+#define	MAX_SPQ_PENDING			8
+
+/* Derived E1HVN constants for rate shaping. */
+#define	DEF_MIN_RATE			100
+
+/* Resolution of the rate shaping timer - 100 usec */
+#define	RS_PERIODIC_TIMEOUT_USEC	100
+
+/*
+ * Resolution of fairness algorithm, in usecs.
+ * Coefficient for calculating the actual t_fair.
+ */
+#define	T_FAIR_COEF		10000000
+
+/*
+ * Number of bytes in single QM arbitration cycle.
+ * Coefficient for calculating the fairness timer.
+ */
+#define	QM_ARB_BYTES		40000
+#define	FAIR_MEM		2
+
+#define	MIN_BXE_BC_VER		0x00040200
+
+
+#define	BXE_NO_RX_FLAGS							\
+	(TSTORM_ETH_DROP_FLAGS_DROP_ALL_PACKETS)
+
+#define	BXE_NORMAL_RX_FLAGS						\
+	(TSTORM_ETH_DROP_FLAGS_DROP_TCP_CS_ERROR_FLG |			\
+	TSTORM_ETH_DROP_FLAGS_DROP_IP_CS_ERROR_FLG |			\
+	TSTORM_ETH_DROP_FLAGS_DONT_DROP_MAC_ERR_FLG |			\
+	TSTORM_ETH_DROP_FLAGS_DROP_TOO_BIG_PACKETS |			\
+	TSTORM_ETH_DROP_FLAGS_DROP_UNMATCH_UNICAST |			\
+	TSTORM_ETH_DROP_FLAGS_DROP_UNMATCH_MULTICAST |			\
+	TSTORM_ETH_DROP_FLAGS_DONT_DROP_TTL0_FLG)
+
+#define	BXE_ALLMULTI_RX_FLAGS						\
+	(TSTORM_ETH_DROP_FLAGS_DROP_TCP_CS_ERROR_FLG |			\
+	TSTORM_ETH_DROP_FLAGS_DROP_IP_CS_ERROR_FLG |			\
+	 TSTORM_ETH_DROP_FLAGS_DONT_DROP_MAC_ERR_FLG |			\
+	 TSTORM_ETH_DROP_FLAGS_DROP_TOO_BIG_PACKETS |			\
+	 TSTORM_ETH_DROP_FLAGS_DROP_UNMATCH_UNICAST |			\
+	 TSTORM_ETH_DROP_FLAGS_DONT_DROP_TTL0_FLG)
+
+#define	BXE_PROMISC_RX_FLAGS						\
+	(TSTORM_ETH_DROP_FLAGS_DONT_DROP_TTL0_FLG)
+
+
+
+/*
+ * External definitions.
+ */
+/* FreeBSD multip proc number of active cpus on the system. */
+extern int mp_ncpus;
+
+#define	MAX_DYNAMIC_ATTN_GRPS		8
+
+#define	MAC_STX_NA			0xffffffff
+
+/* Attention group wiring. */
+struct attn_route {
+    uint32_t sig[4];
+};
+
+struct regp {
+	uint32_t lo;
+	uint32_t hi;
+};
+
+struct nig_stats {
+	uint32_t brb_discard;
+	uint32_t brb_packet;
+	uint32_t brb_truncate;
+	uint32_t flow_ctrl_discard;
+	uint32_t flow_ctrl_octets;
+	uint32_t flow_ctrl_packet;
+	uint32_t mng_discard;
+	uint32_t mng_octet_inp;
+	uint32_t mng_octet_out;
+	uint32_t mng_packet_inp;
+	uint32_t mng_packet_out;
+	uint32_t pbf_octets;
+	uint32_t pbf_packet;
+	uint32_t safc_inp;
+	uint32_t egress_mac_pkt0_lo;
+	uint32_t egress_mac_pkt0_hi;
+	uint32_t egress_mac_pkt1_lo;
+	uint32_t egress_mac_pkt1_hi;
+};
+
+enum bxe_stats_event {
+	STATS_EVENT_PMF = 0,
+	STATS_EVENT_LINK_UP,
+	STATS_EVENT_UPDATE,
+	STATS_EVENT_STOP,
+	STATS_EVENT_MAX
+};
+
+enum bxe_stats_state {
+	STATS_STATE_DISABLED = 0,
+	STATS_STATE_ENABLED,
+	STATS_STATE_MAX
+};
+
+struct bxe_eth_stats {
+	uint32_t total_bytes_received_hi;
+	uint32_t total_bytes_received_lo;
+	uint32_t total_bytes_transmitted_hi;
+	uint32_t total_bytes_transmitted_lo;
+	uint32_t total_unicast_packets_received_hi;
+	uint32_t total_unicast_packets_received_lo;
+	uint32_t total_multicast_packets_received_hi;
+	uint32_t total_multicast_packets_received_lo;
+	uint32_t total_broadcast_packets_received_hi;
+	uint32_t total_broadcast_packets_received_lo;
+	uint32_t total_unicast_packets_transmitted_hi;
+	uint32_t total_unicast_packets_transmitted_lo;
+	uint32_t total_multicast_packets_transmitted_hi;
+	uint32_t total_multicast_packets_transmitted_lo;
+	uint32_t total_broadcast_packets_transmitted_hi;
+	uint32_t total_broadcast_packets_transmitted_lo;
+	uint32_t valid_bytes_received_hi;
+	uint32_t valid_bytes_received_lo;
+	uint32_t error_bytes_received_hi;
+	uint32_t error_bytes_received_lo;
+	uint32_t rx_stat_ifhcinbadoctets_hi;
+	uint32_t rx_stat_ifhcinbadoctets_lo;
+	uint32_t tx_stat_ifhcoutbadoctets_hi;
+	uint32_t tx_stat_ifhcoutbadoctets_lo;
+	uint32_t rx_stat_dot3statsfcserrors_hi;
+	uint32_t rx_stat_dot3statsfcserrors_lo;
+	uint32_t rx_stat_dot3statsalignmenterrors_hi;
+	uint32_t rx_stat_dot3statsalignmenterrors_lo;
+	uint32_t rx_stat_dot3statscarriersenseerrors_hi;
+	uint32_t rx_stat_dot3statscarriersenseerrors_lo;
+	uint32_t rx_stat_falsecarriererrors_hi;
+	uint32_t rx_stat_falsecarriererrors_lo;
+	uint32_t rx_stat_etherstatsundersizepkts_hi;
+	uint32_t rx_stat_etherstatsundersizepkts_lo;
+	uint32_t rx_stat_dot3statsframestoolong_hi;
+	uint32_t rx_stat_dot3statsframestoolong_lo;
+	uint32_t rx_stat_etherstatsfragments_hi;
+	uint32_t rx_stat_etherstatsfragments_lo;
+	uint32_t rx_stat_etherstatsjabbers_hi;
+	uint32_t rx_stat_etherstatsjabbers_lo;
+	uint32_t rx_stat_maccontrolframesreceived_hi;
+	uint32_t rx_stat_maccontrolframesreceived_lo;
+	uint32_t rx_stat_bmac_xpf_hi;
+	uint32_t rx_stat_bmac_xpf_lo;
+	uint32_t rx_stat_bmac_xcf_hi;
+	uint32_t rx_stat_bmac_xcf_lo;
+	uint32_t rx_stat_xoffstateentered_hi;
+	uint32_t rx_stat_xoffstateentered_lo;
+	uint32_t rx_stat_xonpauseframesreceived_hi;
+	uint32_t rx_stat_xonpauseframesreceived_lo;
+	uint32_t rx_stat_xoffpauseframesreceived_hi;
+	uint32_t rx_stat_xoffpauseframesreceived_lo;
+	uint32_t tx_stat_outxonsent_hi;
+	uint32_t tx_stat_outxonsent_lo;
+	uint32_t tx_stat_outxoffsent_hi;
+	uint32_t tx_stat_outxoffsent_lo;
+	uint32_t tx_stat_flowcontroldone_hi;
+	uint32_t tx_stat_flowcontroldone_lo;
+	uint32_t tx_stat_etherstatscollisions_hi;
+	uint32_t tx_stat_etherstatscollisions_lo;
+	uint32_t tx_stat_dot3statssinglecollisionframes_hi;
+	uint32_t tx_stat_dot3statssinglecollisionframes_lo;
+	uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
+	uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
+	uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
+	uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
+	uint32_t tx_stat_dot3statsexcessivecollisions_hi;
+	uint32_t tx_stat_dot3statsexcessivecollisions_lo;
+	uint32_t tx_stat_dot3statslatecollisions_hi;
+	uint32_t tx_stat_dot3statslatecollisions_lo;
+	uint32_t tx_stat_etherstatspkts64octets_hi;
+	uint32_t tx_stat_etherstatspkts64octets_lo;
+	uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
+	uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
+	uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
+	uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
+	uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
+	uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
+	uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
+	uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
+	uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
+	uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
+	uint32_t tx_stat_etherstatspktsover1522octets_hi;
+	uint32_t tx_stat_etherstatspktsover1522octets_lo;
+	uint32_t tx_stat_bmac_2047_hi;
+	uint32_t tx_stat_bmac_2047_lo;
+	uint32_t tx_stat_bmac_4095_hi;
+	uint32_t tx_stat_bmac_4095_lo;
+	uint32_t tx_stat_bmac_9216_hi;
+	uint32_t tx_stat_bmac_9216_lo;
+	uint32_t tx_stat_bmac_16383_hi;
+	uint32_t tx_stat_bmac_16383_lo;
+	uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
+	uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
+	uint32_t tx_stat_bmac_ufl_hi;
+	uint32_t tx_stat_bmac_ufl_lo;
+	uint32_t brb_drop_hi;
+	uint32_t brb_drop_lo;
+	uint32_t brb_truncate_hi;
+	uint32_t brb_truncate_lo;
+	uint32_t pause_frames_received_hi;
+	uint32_t pause_frames_received_lo;
+	uint32_t pause_frames_sent_hi;
+	uint32_t pause_frames_sent_lo;
+	uint32_t jabber_packets_received;
+
+	uint32_t etherstatspkts1024octetsto1522octets_hi;
+	uint32_t etherstatspkts1024octetsto1522octets_lo;
+	uint32_t etherstatspktsover1522octets_hi;
+	uint32_t etherstatspktsover1522octets_lo;
+
+	uint32_t no_buff_discard_hi;
+	uint32_t no_buff_discard_lo;
+
+	uint32_t mac_filter_discard;
+	uint32_t xxoverflow_discard;
+	uint32_t brb_truncate_discard;
+	uint32_t mac_discard;
+
+	uint32_t driver_xoff;
+	uint32_t rx_err_discard_pkt;
+	uint32_t rx_skb_alloc_failed;
+	uint32_t hw_csum_err;
+
+	uint32_t nig_timer_max;
+};
+
+#define	STATS_OFFSET32(stat_name)					\
+	(offsetof(struct bxe_eth_stats, stat_name) / 4)
+
+#define	MAX_CONTEXT			16
+
+union cdu_context {
+	struct eth_context eth;
+	char pad[1024];
+};
+
+/* Load/unload mode. */
+#define	LOAD_NORMAL			0
+#define	LOAD_OPEN			1
+#define	LOAD_DIAG			2
+#define	UNLOAD_NORMAL			0
+#define	UNLOAD_CLOSE			1
+
+#define	BXE_MAX_POLL_COUNT		1024
+
+struct sw_rx_bd {
+   struct mbuf *pmbuf;
+};
+
+/*
+ * Common data structure.
+ * This information is shared across all ports and functions.
+ */
+struct bxe_common {
+	uint32_t	chip_id;
+/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
+#define	CHIP_ID(sc)		(sc->common.chip_id & 0xfffffff0)
+#define	CHIP_NUM(sc)		(sc->common.chip_id >> 16)
+#define	CHIP_NUM_57710		0x164e
+#define	CHIP_NUM_57711		0x164f
+#define	CHIP_NUM_57711E		0x1650
+#define	CHIP_IS_E1(sc)		(CHIP_NUM(sc) == CHIP_NUM_57710)
+#define	CHIP_IS_57711(sc)	(CHIP_NUM(sc) == CHIP_NUM_57711)
+#define	CHIP_IS_57711E(sc)	(CHIP_NUM(sc) == CHIP_NUM_57711E)
+#define	CHIP_IS_E1H(sc)		(CHIP_IS_57711(sc) || CHIP_IS_57711E(sc))
+#define	CHIP_IS_MF_CAP(sc)	(CHIP_IS_57711E(sc))
+#define	IS_E1H_OFFSET		CHIP_IS_E1H(sc)
+
+#define	CHIP_REV(sc)		((sc->common.chip_id) & 0x0000f000)
+#define	CHIP_REV_Ax		0x00000000
+#define	CHIP_REV_Bx		0x00001000
+#define	CHIP_REV_Cx		0x00002000
+
+#define	CHIP_METAL(sc)		((sc->common.chip_id) & 0x00000ff0)
+#define	CHIP_BOND_ID(sc)	((sc->common.chip_id) & 0x0000000f)
+
+	int		flash_size;
+#define	NVRAM_1MB_SIZE		0x20000
+#define	NVRAM_TIMEOUT_COUNT	30000
+#define	NVRAM_PAGE_SIZE		256
+
+	/* Bootcode shared memory address in BAR memory. */
+	uint32_t	shmem_base;
+	uint32_t	shmem2_base;
+
+	/* Device configuration read from bootcode shared memory. */
+	uint32_t	hw_config;
+	uint32_t	bc_ver;
+
+};	/* End struct bxe_common */
+
+/*
+ * Port specifc data structure.
+ */
+struct bxe_port {
+	/*
+	 * Port Management Function (for 57711E only).
+	 * When this field is set the driver instance is
+	 * responsible for managing port specifc
+	 * configurations such as handling link attentions.
+	 */
+	uint32_t	pmf;
+
+	/* Ethernet maximum transmission unit. */
+	uint16_t	ether_mtu;
+
+	uint32_t	link_config;
+
+	/* Defines the features	supported by the PHY. */
+	uint32_t	supported;
+#define	SUPPORTED_10baseT_Half		(1 << 1)
+#define	SUPPORTED_10baseT_Full		(1 << 2)
+#define	SUPPORTED_100baseT_Half		(1 << 3)
+#define	SUPPORTED_100baseT_Full		(1 << 4)
+#define	SUPPORTED_1000baseT_Half	(1 << 5)
+#define	SUPPORTED_1000baseT_Full	(1 << 6)
+#define	SUPPORTED_TP			(1 << 7)
+#define	SUPPORTED_FIBRE			(1 << 8)
+#define	SUPPORTED_Autoneg		(1 << 9)
+#define	SUPPORTED_Asym_Pause		(1 << 10)
+#define	SUPPORTED_Pause			(1 << 11)
+#define	SUPPORTED_2500baseX_Full	(1 << 15)
+#define	SUPPORTED_10000baseT_Full	(1 << 16)
+
+	/* Defines the features	advertised by the PHY. */
+	uint32_t	advertising;
+#define	ADVERTISED_10baseT_Half		(1 << 1)
+#define	ADVERTISED_10baseT_Full		(1 << 2)
+#define	ADVERTISED_100baseT_Half	(1 << 3)
+#define	ADVERTISED_100baseT_Full	(1 << 4)
+#define	ADVERTISED_1000baseT_Half	(1 << 5)
+#define	ADVERTISED_1000baseT_Full	(1 << 6)
+#define	ADVERTISED_TP			(1 << 7)
+#define	ADVERTISED_FIBRE		(1 << 8)
+#define	ADVERTISED_Autoneg		(1 << 9)
+#define	ADVERTISED_Asym_Pause		(1 << 10)
+#define	ADVERTISED_Pause		(1 << 11)
+#define	ADVERTISED_2500baseX_Full	(1 << 15)
+#define	ADVERTISED_10000baseT_Full	(1 << 16)
+
+	uint32_t	phy_addr;
+
+	/* Used to synchronize phy accesses. */
+	struct mtx	bxe_phy_mtx;
+
+	/*
+	 * MCP scratchpad address for port specific statistics.
+	 * The device is responsible for writing statistcss
+	 * back to the MCP for use with management firmware such
+	 * as UMP/NC-SI.
+	 */
+	uint32_t	port_stx;
+
+	struct nig_stats	old_nig_stats;
+};	/* End struct bxe_port */
+
+/* DMAE command defines */
+#define	DMAE_CMD_SRC_PCI		0
+#define	DMAE_CMD_SRC_GRC		DMAE_COMMAND_SRC
+
+#define	DMAE_CMD_DST_PCI		(1 << DMAE_COMMAND_DST_SHIFT)
+#define	DMAE_CMD_DST_GRC		(2 << DMAE_COMMAND_DST_SHIFT)
+
+#define	DMAE_CMD_C_DST_PCI		0
+#define	DMAE_CMD_C_DST_GRC		(1 << DMAE_COMMAND_C_DST_SHIFT)
+
+#define	DMAE_CMD_C_ENABLE		DMAE_COMMAND_C_TYPE_ENABLE
+
+#define	DMAE_CMD_ENDIANITY_NO_SWAP	(0 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define	DMAE_CMD_ENDIANITY_B_SWAP	(1 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define	DMAE_CMD_ENDIANITY_DW_SWAP	(2 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define	DMAE_CMD_ENDIANITY_B_DW_SWAP	(3 << DMAE_COMMAND_ENDIANITY_SHIFT)
+
+#define	DMAE_CMD_PORT_0			0
+#define	DMAE_CMD_PORT_1			DMAE_COMMAND_PORT
+
+#define	DMAE_CMD_SRC_RESET		DMAE_COMMAND_SRC_RESET
+#define	DMAE_CMD_DST_RESET		DMAE_COMMAND_DST_RESET
+#define	DMAE_CMD_E1HVN_SHIFT		DMAE_COMMAND_E1HVN_SHIFT
+
+#define	DMAE_LEN32_RD_MAX		0x80
+#define	DMAE_LEN32_WR_MAX(sc)		(CHIP_IS_E1(sc) ? 0x400 : 0x2000)
+
+#define	DMAE_COMP_VAL			0xe0d0d0ae
+
+#define	MAX_DMAE_C			8
+#define	MAX_DMAE_C_PER_PORT		8
+
+#define	INIT_DMAE_C(sc)							\
+	(BP_PORT(sc) * MAX_DMAE_C_PER_PORT + BP_E1HVN(sc))
+#define	PMF_DMAE_C(sc)							\
+	(BP_PORT(sc) * MAX_DMAE_C_PER_PORT + E1HVN_MAX)
+
+/*
+ * This is the slowpath data structure.  It is mapped into non-paged memory
+ * so that the hardware can access it's contents directly and must be page
+ * aligned.
+ */
+struct bxe_slowpath {
+	/*
+	 * The cdu_context array MUST be the first element in this
+	 * structure.  It is used during the leading edge ramrod
+	 * operation.
+	 */
+	union cdu_context	context[MAX_CONTEXT];
+
+	struct eth_stats_query	fw_stats;
+
+	/* Used as a DMA source for MAC configuration. */
+	struct mac_configuration_cmd	mac_config;
+	struct mac_configuration_cmd	mcast_config;
+
+	/* Used by the DMAE command executer. */
+	struct dmae_command	dmae[MAX_DMAE_C];
+
+	/* Statistics completion. */
+	uint32_t		stats_comp;
+
+	/* Firmware defined statistics blocks. */
+	union mac_stats		mac_stats;
+	struct nig_stats	nig_stats;
+	struct host_port_stats	port_stats;
+	struct host_func_stats	func_stats;
+	struct host_func_stats	func_stats_base;
+
+	/* DMAE completion value. */
+	uint32_t		wb_comp;
+#define	BXE_WB_COMP_VAL		0xe0d0d0ae
+
+	/* DMAE data source/sink. */
+	uint32_t		wb_data[4];
+};	/* End struct bxe_slowpath */
+
+#define	BXE_SP(sc, var)		(&sc->slowpath->var)
+#define	BXE_SP_CHECK(sc, var)	((sc->slowpath) ? (&sc->slowpath->var) : NULL)
+#define	BXE_SP_MAPPING(sc, var)						\
+	(sc->slowpath_paddr + offsetof(struct bxe_slowpath, var))
+
+union db_prod {
+	struct doorbell_set_prod data;
+	uint32_t		 raw;
+};
+
+struct bxe_q_stats {
+	uint32_t total_bytes_received_hi;
+	uint32_t total_bytes_received_lo;
+	uint32_t total_bytes_transmitted_hi;
+	uint32_t total_bytes_transmitted_lo;
+	uint32_t total_unicast_packets_received_hi;
+	uint32_t total_unicast_packets_received_lo;
+	uint32_t total_multicast_packets_received_hi;
+	uint32_t total_multicast_packets_received_lo;
+	uint32_t total_broadcast_packets_received_hi;
+	uint32_t total_broadcast_packets_received_lo;
+	uint32_t total_unicast_packets_transmitted_hi;
+	uint32_t total_unicast_packets_transmitted_lo;
+	uint32_t total_multicast_packets_transmitted_hi;
+	uint32_t total_multicast_packets_transmitted_lo;
+	uint32_t total_broadcast_packets_transmitted_hi;
+	uint32_t total_broadcast_packets_transmitted_lo;
+	uint32_t valid_bytes_received_hi;
+	uint32_t valid_bytes_received_lo;
+	uint32_t error_bytes_received_hi;
+	uint32_t error_bytes_received_lo;
+	uint32_t etherstatsoverrsizepkts_hi;
+	uint32_t etherstatsoverrsizepkts_lo;
+	uint32_t no_buff_discard_hi;
+	uint32_t no_buff_discard_lo;
+	uint32_t driver_xoff;
+	uint32_t rx_err_discard_pkt;
+	uint32_t rx_skb_alloc_failed;
+	uint32_t hw_csum_err;
+};
+
+/*
+ * This is the fastpath data structure.  There can be up to MAX_CONTEXT
+ * instances of the fastpath structure when using RSS/multi-queue.
+ */
+struct bxe_fastpath {
+	/* Pointer back to parent structure. */
+	struct bxe_softc	*sc;
+
+	/* Hardware maintained status block. */
+	bus_dma_tag_t		status_block_tag;
+	bus_dmamap_t		status_block_map;
+	struct host_status_block	*status_block;
+	bus_addr_t		status_block_paddr;
+#ifdef notyet
+	/*
+	 * In this implementation the doorbell data block
+	 * (eth_tx_db_data) is mapped into memory immediately
+	 * following the status block and is part of the same
+	 * memory allocation.
+	 */
+	struct eth_tx_db_data	*hw_tx_prods;
+	bus_addr_t		tx_prods_paddr;
+#endif
+
+	/* Hardware maintained TX buffer descriptor chains. */
+	bus_dma_tag_t		tx_bd_chain_tag;
+	bus_dmamap_t		tx_bd_chain_map[NUM_TX_PAGES];
+
+	union eth_tx_bd_types	*tx_bd_chain[NUM_TX_PAGES];
+	bus_addr_t		tx_bd_chain_paddr[NUM_TX_PAGES];
+
+	/* Bus resource tag for TX mbufs. */
+	bus_dma_tag_t		tx_mbuf_tag;
+	bus_dmamap_t		tx_mbuf_map[TOTAL_TX_BD];
+	struct mbuf		*tx_mbuf_ptr[TOTAL_TX_BD];
+
+	/* Hardware maintained RX buffer descriptor chains. */
+	bus_dma_tag_t		rx_bd_chain_tag;
+	bus_dmamap_t		rx_bd_chain_map[NUM_RX_PAGES];
+	struct eth_rx_bd	*rx_bd_chain[NUM_RX_PAGES];
+	bus_addr_t		rx_bd_chain_paddr[NUM_RX_PAGES];
+
+	/* Bus resource tag for RX mbufs. */
+	bus_dma_tag_t		rx_mbuf_tag;
+	bus_dmamap_t		rx_mbuf_map[TOTAL_RX_BD];
+	struct mbuf		*rx_mbuf_ptr[TOTAL_RX_BD];
+
+	/* Hardware maintained Completion Queue (CQ) chains. */
+	bus_dma_tag_t		rx_comp_chain_tag;
+	bus_dmamap_t		rx_comp_chain_map[NUM_RCQ_PAGES];
+	union eth_rx_cqe	*rx_comp_chain[NUM_RCQ_PAGES];
+	bus_addr_t		rx_comp_chain_paddr[NUM_RCQ_PAGES];
+
+	/* Taskqueue reqources. */
+	struct task		task;
+	struct taskqueue	*tq;
+
+	/* Fastpath state. */
+	/* ToDo: Why use 'int' here, why not 'uint32_t'? */
+	int			state;
+#define	BXE_FP_STATE_CLOSED	0x00000
+#define	BXE_FP_STATE_IRQ	0x80000
+#define	BXE_FP_STATE_OPENING	0x90000
+#define	BXE_FP_STATE_OPEN	0xa0000
+#define	BXE_FP_STATE_HALTING	0xb0000
+#define	BXE_FP_STATE_HALTED	0xc0000
+
+	/* Self-reference back to this fastpath's queue number. */
+	uint8_t			index;
+#define	FP_IDX(fp)		(fp->index)
+
+	/* Ethernet client ID (each fastpath set of RX/TX/CQE is a client). */
+	uint8_t			cl_id;
+#define	BP_CL_ID(sc)		(sc->fp[0].cl_id)
+
+	/* Status block number in hardware. */
+	uint8_t			sb_id;
+#define	FP_SB_ID(fp)		(fp->sb_id)
+
+	/* Class of service. */
+	uint8_t			cos;
+
+	union db_prod		tx_db;
+
+	/* Transmit packet producer index (used in eth_tx_bd). */
+	uint16_t		tx_pkt_prod;
+
+	/* Transmit packet consumer index. */
+	uint16_t		tx_pkt_cons;
+
+	/* Transmit buffer descriptor producer index. */
+	uint16_t		tx_bd_prod;
+
+	/* Transmit buffer descriptor consumer index. */
+	uint16_t		tx_bd_cons;
+
+	/* Driver's copy of the fastpath CSTORM/USTORM indices. */
+	uint16_t		fp_c_idx;
+	uint16_t		fp_u_idx;
+
+	/* Driver's copy of the receive buffer descriptor prod/cons indices. */
+	uint16_t		rx_bd_prod;
+	uint16_t		rx_bd_cons;
+
+	/* Driver's copy of the receive completion queue prod/cons indices. */
+	uint16_t		rx_comp_prod;
+	uint16_t		rx_comp_cons;
+
+	/* Pointer to the receive consumer index in the status block. */
+	uint16_t		*rx_cons_sb;
+
+	/*
+	 * Pointer to the receive buffer descriptor consumer in the
+	 * status block.
+	 */
+	uint16_t		*rx_bd_cons_sb;
+
+	/* Pointer to the transmit consumer in the status block. */
+	uint16_t		*tx_cons_sb;
+
+	/* Free/used buffer descriptor counters. */
+	uint16_t		used_tx_bd;
+
+	/* Begin: TPA Related data structure. */
+
+	/* Hardware maintained RX Scatter Gather Entry chains. */
+	bus_dma_tag_t		rx_sge_chain_tag;
+	bus_dmamap_t		rx_sge_chain_map[NUM_RX_SGE_PAGES];
+	struct eth_rx_sge	*rx_sge_chain[NUM_RX_SGE_PAGES];
+	bus_addr_t		rx_sge_chain_paddr[NUM_RX_SGE_PAGES];
+
+	/* Bus tag for RX SGE bufs. */
+	bus_dma_tag_t		rx_sge_buf_tag;
+	bus_dmamap_t		rx_sge_buf_map[TOTAL_RX_SGE];
+	struct mbuf		*rx_sge_buf_ptr[TOTAL_RX_SGE];
+
+	uint64_t		sge_mask[RX_SGE_MASK_LEN];
+	uint16_t		rx_sge_prod;
+
+	/* The last maximal completed SGE. */
+	uint16_t		last_max_sge;
+
+	uint16_t		rx_sge_free_idx;
+
+	/* Use the larger supported size for TPA queue length. */
+	bus_dmamap_t		tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H];
+	struct mbuf		*tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H];
+	bus_dma_segment_t	tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H];
+
+	uint8_t			tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
+#define	BXE_TPA_STATE_START	1
+#define	BXE_TPA_STATE_STOP	2
+
+	uint8_t			segs;
+	uint8_t			disable_tpa;
+	/* End: TPA related data structure. */
+
+	struct tstorm_per_client_stats	old_tclient;
+	struct ustorm_per_client_stats	old_uclient;
+	struct xstorm_per_client_stats	old_xclient;
+	struct bxe_q_stats	eth_q_stats;
+
+#ifdef BXE_DEBUG
+	uint16_t		free_rx_bd;
+
+	/* Recieve/transmit packet counters. */
+	unsigned long		rx_pkts;
+	unsigned long		tx_pkts;
+	unsigned long		tpa_pkts;
+
+	/* Receive interrupt counter. */
+	unsigned long		rx_calls;
+
+	/* Memory buffer allocation failure counter. */
+	unsigned long		mbuf_alloc_failed;
+
+	/* Track the number of enqueued mbufs. */
+	int			tx_mbuf_alloc;
+	int			rx_mbuf_alloc;
+	int			sge_mbuf_alloc;
+	int			tpa_mbuf_alloc;
+
+	uint64_t		tpa_queue_used;
+#endif
+	/* FreeBSD interface statistics. */
+	unsigned long		soft_rx_errors;
+	unsigned long		soft_tx_errors;
+	unsigned long		ipackets;
+	unsigned long		opackets;
+
+}; /* bxe_fastpath */
+
+/*
+ * BXE Device State Data Structure
+ */
+#define	BXE_STATUS_BLK_SZ						\
+	sizeof(struct host_status_block) /* +sizeof(struct eth_tx_db_data) */
+#define	BXE_DEF_STATUS_BLK_SZ	sizeof(struct host_def_status_block)
+#define	BXE_STATS_BLK_SZ	sizeof(struct bxe_eth_stats)
+#define	BXE_SLOWPATH_SZ		sizeof(struct bxe_slowpath)
+#define	BXE_SPQ_SZ		BCM_PAGE_SIZE
+#define	BXE_TX_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
+#define	BXE_RX_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
+
+/* ToDo: Audit this structure for unused varaibles. */
+struct bxe_softc {
+	/*
+	 * MUST start with ifnet pointer (see definition of miibus_statchg()).
+	 */
+	struct ifnet		*bxe_ifp;
+
+	/* Parent device handle. */
+	device_t		bxe_dev;
+
+	/* Driver instance number. */
+	u_int8_t		bxe_unit;
+
+	/* FreeBSD network interface media structure. */
+	struct ifmedia		bxe_ifmedia;
+
+	/* Bus tag for the bxe controller. */
+	bus_dma_tag_t		parent_tag;
+	/* OS resources for BAR0 memory. */
+	struct resource		*bxe_res;
+	bus_space_tag_t		bxe_btag;
+	bus_space_handle_t	bxe_bhandle;
+	vm_offset_t		bxe_vhandle;
+
+	/* OS resources for BAR2 memory. */
+
+	/* OS resources for BAR1 doorbell memory. */
+#define	BXE_DB_SIZE		(16 * 2048)
+	struct resource		*bxe_db_res;
+	bus_space_tag_t		bxe_db_btag;
+	bus_space_handle_t	bxe_db_bhandle;
+	vm_offset_t		bxe_db_vhandle;
+
+	/* Driver mutex. */
+	struct mtx		bxe_core_mtx;
+	struct mtx		bxe_sp_mtx;
+	struct mtx		bxe_dmae_mtx;
+	struct mtx		bxe_fwmb_mtx;
+	struct mtx		bxe_print_mtx;
+
+	/* Per-queue state. */
+	/* ToDo: Convert to an array of pointers to conserve memory. */
+	struct bxe_fastpath	fp[MAX_CONTEXT];
+
+	int			tx_ring_size;
+
+	/* Legacy interrupt handler resources. */
+	struct resource		*bxe_irq_res;
+	int			bxe_irq_rid;
+	void			*bxe_irq_tag;
+
+	/* MSI-X interrupt handler resources (up to 17 vectors). */
+	struct resource		*bxe_msix_res[MAX_CONTEXT + 1];
+	int			bxe_msix_rid[MAX_CONTEXT + 1];
+	void			*bxe_msix_tag[MAX_CONTEXT + 1];
+	int			msix_count;
+
+	/* MSI interrupt handler resources (up to XX vectors). */
+#define	BXE_MSI_VECTOR_COUNT	8
+	struct resource		*bxe_msi_res[BXE_MSI_VECTOR_COUNT];
+	int			bxe_msi_rid[BXE_MSI_VECTOR_COUNT];
+	void			*bxe_msi_tag[BXE_MSI_VECTOR_COUNT];
+	int			msi_count;
+
+	/* Taskqueue resources. */
+	struct task		task;
+	struct taskqueue	*tq;
+	/* RX Driver parameters*/
+	uint32_t		rx_csum;
+	int			rx_buf_size;
+
+	/* ToDo: Replace with OS specific defintions. */
+#define	ETH_HLEN			14
+#define	ETH_OVREHEAD			(ETH_HLEN + 8)	/* 8 for CRC + VLAN */
+#define	ETH_MIN_PACKET_SIZE		60
+#define	ETH_MAX_PACKET_SIZE		1500
+#define	ETH_MAX_JUMBO_PACKET_SIZE	9600
+
+	/* Hardware Maintained Host Default Status Block. */
+	bus_dma_tag_t		def_status_block_tag;
+	bus_dmamap_t		def_status_block_map;
+	struct host_def_status_block	*def_status_block;
+	bus_addr_t		def_status_block_paddr;
+
+#define	DEF_SB_ID		16
+	uint16_t		def_c_idx;
+	uint16_t		def_u_idx;
+	uint16_t		def_t_idx;
+	uint16_t		def_x_idx;
+	uint16_t		def_att_idx;
+
+	uint32_t		attn_state;
+	struct attn_route	attn_group[MAX_DYNAMIC_ATTN_GRPS];
+
+	/* H/W maintained statistics block. */
+	bus_dma_tag_t		stats_tag;
+	bus_dmamap_t		stats_map;
+	struct statistics_block	*stats_block;
+	bus_addr_t		stats_block_paddr;
+
+	/* H/W maintained slow path. */
+	bus_dma_tag_t		slowpath_tag;
+	bus_dmamap_t		slowpath_map;
+	struct bxe_slowpath	*slowpath;
+	bus_addr_t		slowpath_paddr;
+
+ 	/* Slow path ring. */
+	bus_dma_tag_t		spq_tag;
+	bus_dmamap_t		spq_map;
+	struct eth_spe		*spq;
+	bus_addr_t		spq_paddr;
+	uint16_t		spq_prod_idx;
+	struct eth_spe		*spq_prod_bd;
+	struct eth_spe		*spq_last_bd;
+	uint16_t		*dsb_sp_prod;
+	uint16_t		*spq_hw_con;
+	uint16_t		spq_left;
+
+	/* State information for pending ramrod commands. */
+	uint8_t			stats_pending;
+	uint8_t			set_mac_pending;
+
+	int			panic;
+
+	/* Device flags. */
+	uint32_t		bxe_flags;
+#define	BXE_ONE_PORT_FLAG	0x00000004
+#define	BXE_NO_WOL_FLAG		0x00000008
+#define	BXE_USING_DAC_FLAG	0x00000010
+#define	BXE_USING_MSIX_FLAG	0x00000020
+#define	BXE_USING_MSI_FLAG	0x00000040
+#define	BXE_TPA_ENABLE_FLAG	0x00000080
+#define	BXE_NO_MCP_FLAG		0x00000100
+#define	BP_NOMCP(sc)		(sc->bxe_flags & BXE_NO_MCP_FLAG)
+#define	BXE_SAFC_TX_FLAG	0x00000200
+
+#define	TPA_ENABLED(sc)		(sc->bxe_flags & BXE_TPA_ENABLE_FLAG)
+
+	/* PCI Express function number for the device. */
+	int			bxe_func;
+
+/*
+ * Ethernet port to PCIe function mapping for
+ * 57710 and 57711:
+ * +---------------+---------------+-------------+
+ * | Ethernet Port | PCIe Function | Virtual NIC |
+ * |       0       |       0       |      0      |
+ * |       1       |       1       |      0      |
+ * +---------------+---------------+-------------+
+ *
+ * Ethernet port to PCIe function mapping for
+ * 57711E:
+ * +---------------+---------------+-------------+
+ * | Ethernet Port | PCIe Function | Virtual NIC |
+ * |       0       |       0       |      1      |
+ * |       1       |       1       |      2      |
+ * |       0       |       2       |      3      |
+ * |       1       |       3       |      4      |
+ * |       0       |       4       |      5      |
+ * |       1       |       5       |      6      |
+ * |       0       |       6       |      7      |
+ * |       1       |       7       |      8      |
+ * +---------------+---------------+-------------+
+ */
+
+#define	BP_PORT(sc)		(sc->bxe_func % PORT_MAX)
+#define	BP_FUNC(sc)		(sc->bxe_func)
+#define	BP_E1HVN(sc)		(sc->bxe_func >> 1)
+#define	BP_L_ID(sc)		(BP_E1HVN(sc) << 2)
+
+	/* PCI Express link information. */
+	uint16_t		pcie_link_width;
+	uint16_t		pcie_link_speed;
+	uint32_t		bxe_cap_flags;
+#define	BXE_MSI_CAPABLE_FLAG	0x00000001
+#define	BXE_MSIX_CAPABLE_FLAG	0x00000002
+#define	BXE_PCIE_CAPABLE_FLAG	0x00000004
+	uint16_t		pcie_cap;
+	uint16_t		pm_cap;
+
+	/* PCIe maximum read request size. */
+	int			mrrs;
+
+	/* ToDo: Is this really needed? */
+	uint16_t		sp_running;
+
+	/* Driver/firmware synchronization. */
+	uint16_t		fw_seq;
+	uint16_t		fw_drv_pulse_wr_seq;
+	uint32_t		fw_mb;
+
+	/*
+	 * MCP scratchpad address for function specific statistics.
+	 * The device is responsible for writing statistics back to
+	 * the MCP for use with management firmware such as UMP/NC-SI.
+	 */
+	uint32_t		func_stx;
+
+	struct link_params	link_params;
+	struct link_vars	link_vars;
+
+	struct bxe_common	common;
+	struct bxe_port		port;
+
+	struct cmng_struct_per_port	cmng;
+	uint32_t		vn_wsum;
+	uint32_t		cos_wsum;
+
+	uint8_t			ser_lane;
+	uint8_t			rx_lane_swap;
+	uint8_t			tx_lane_swap;
+
+	uint8_t			wol;
+
+	int			rx_ring_size;
+
+	/* RX/TX Interrupt Coalescing Parameters */
+	uint16_t		rx_ticks;
+	uint16_t		tx_ticks;
+
+	/* Device State: Used for Driver-FW communication. */
+	int			state;
+#define	BXE_STATE_CLOSED		0x0
+#define	BXE_STATE_OPENING_WAIT4_LOAD	0x1000
+#define	BXE_STATE_OPENING_WAIT4_PORT	0x2000
+#define	BXE_STATE_OPEN			0x3000
+#define	BXE_STATE_CLOSING_WAIT4_HALT	0x4000
+#define	BXE_STATE_CLOSING_WAIT4_DELETE	0x5000
+#define	BXE_STATE_CLOSING_WAIT4_UNLOAD	0x6000
+#define	BXE_STATE_DISABLED		0xD000
+#define	BXE_STATE_DIAG			0xE000
+#define	BXE_STATE_ERROR			0xF000
+
+	int			int_mode;
+	int			multi_mode;
+
+#define	BXE_MAX_COS		3
+#define	BXE_MAX_PRIORITY	8
+#define	BXE_MAX_ENTRIES_PER_PRI	16
+
+	/* Number of queues per class of service. */
+	uint8_t			qs_per_cos[BXE_MAX_COS];
+
+	/* Priority to class of service mapping. */
+	uint8_t			pri_map[BXE_MAX_PRIORITY];
+
+	/* min rate per cos */
+	uint16_t		cos_min_rate[BXE_MAX_COS];
+
+	/* Class of service to queue mapping. */
+	uint8_t			cos_map[BXE_MAX_COS];
+
+	/* The number of fastpath queues (for RSS/multi-queue). */
+	int			num_queues;
+
+#define	BXE_NUM_QUEUES(cos)						\
+	((bxe_qs_per_cos & (0xff << (cos * 8))) >> (cos * 8))
+#define	BXE_MAX_QUEUES(sc)						\
+	(IS_E1HMF(sc) ? (MAX_CONTEXT / E1HVN_MAX) : MAX_CONTEXT)
+
+	/* Used for multiple function devices. */
+	uint32_t		mf_config[E1HVN_MAX];
+
+	/* Outer VLAN tag. */
+	uint16_t		e1hov;
+#define	IS_E1HOV(sc)		(sc->e1hov != 0)
+
+	uint8_t			e1hmf;
+#define	IS_E1HMF(sc)		(sc->e1hmf != 0)
+
+	/* Receive mode settings (i.e promiscuous, multicast, etc.). */
+	uint32_t		rx_mode;
+
+#define	BXE_RX_MODE_NONE	0
+#define	BXE_RX_MODE_NORMAL	1
+#define	BXE_RX_MODE_ALLMULTI	2
+#define	BXE_RX_MODE_PROMISC	3
+#define	BXE_MAX_MULTICAST	64
+#define	BXE_MAX_EMUL_MULTI	16
+
+	uint32_t		rx_mode_cl_mask;
+
+	/* Device name */
+	char			*name;
+
+	/* Used to synchronize statistics collection. */
+	int			stats_state;
+#define	STATS_STATE_DISABLE	0
+#define	STATS_STATE_ENABLE	1
+#define	STATS_STATE_STOP	2
+
+	int			dmae_ready;
+
+	/* Used by the DMAE command loader. */
+	struct dmae_command	stats_dmae;
+	struct dmae_command	init_dmae;
+	int			executer_idx;
+
+	/* Statistics. */
+	uint16_t		stats_counter;
+
+	struct bxe_eth_stats	eth_stats;
+
+	z_streamp		strm;
+	bus_dma_tag_t		gunzip_tag;
+	bus_dmamap_t		gunzip_map;
+	void			*gunzip_buf;
+	bus_addr_t		gunzip_mapping;
+	int			gunzip_outlen;
+#define	FW_BUF_SIZE		0x40000
+
+	struct raw_op		*init_ops;
+	/* Init blocks offsets inside init_ops */
+	const uint16_t		*init_ops_offsets;
+	/* Data blob - has 32 bit granularity */
+	const uint32_t		*init_data;
+	/* PRAM blobs - raw data */
+	const uint8_t		*tsem_int_table_data;
+	const uint8_t		*tsem_pram_data;
+	const uint8_t		*usem_int_table_data;
+	const uint8_t		*usem_pram_data;
+	const uint8_t		*xsem_int_table_data;
+	const uint8_t		*xsem_pram_data;
+	const uint8_t		*csem_int_table_data;
+	const uint8_t		*csem_pram_data;
+#define	INIT_OPS(sc)			(sc->init_ops)
+#define	INIT_OPS_OFFSETS(sc)		(sc->init_ops_offsets)
+#define	INIT_DATA(sc)			(sc->init_data)
+#define	INIT_TSEM_INT_TABLE_DATA(sc)	(sc->tsem_int_table_data)
+#define	INIT_TSEM_PRAM_DATA(sc)		(sc->tsem_pram_data)
+#define	INIT_USEM_INT_TABLE_DATA(sc)	(sc->usem_int_table_data)
+#define	INIT_USEM_PRAM_DATA(sc)		(sc->usem_pram_data)
+#define	INIT_XSEM_INT_TABLE_DATA(sc)	(sc->xsem_int_table_data)
+#define	INIT_XSEM_PRAM_DATA(sc)		(sc->xsem_pram_data)
+#define	INIT_CSEM_INT_TABLE_DATA(sc)	(sc->csem_int_table_data)
+#define	INIT_CSEM_PRAM_DATA(sc)		(sc->csem_pram_data)
+
+	/* OS handle for periodic tick routine. */
+	struct callout		bxe_tick_callout;
+
+	uint8_t			pad;
+
+	/* Frame size and mbuf allocation size for RX frames. */
+	uint32_t		max_frame_size;
+	int			mbuf_alloc_size;
+	uint32_t		mbuf_alloc_failed;
+
+	uint16_t		tx_driver;
+
+	/* Ticks until chip reset. */
+	int			watchdog_timer;
+
+	/* Verify bxe_function_init is run before handling interrupts. */
+	uint8_t			intr_sem;
+
+#ifdef BXE_DEBUG
+	unsigned long		debug_mbuf_sim_alloc_failed;
+	unsigned long		debug_mbuf_sim_map_failed;
+	unsigned long		debug_received_frame_error;
+	unsigned long		debug_memory_allocated;
+	unsigned long		debug_udp_csum_offload_frames;
+	unsigned long		debug_tcp_csum_offload_frames;
+	unsigned long		debug_ip_csum_offload_frames;
+	unsigned long		debug_ip6_csum_offload_frames;
+	unsigned long		debug_tso_offload_frames;
+
+	/* A buffer for hardware/firmware state information (grcdump). */
+	uint32_t		*grcdump_buffer;
+#endif
+
+#ifdef EVST_STOP_ON_ERROR
+	uint32_t		next_free;
+	uint32_t		last_alloc;
+#endif
+}; /* end of struct bxe_softc */
+
+#define	MDIO_AN_CL73_OR_37_COMPLETE					\
+	(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |		\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
+
+#define	GP_STATUS_PAUSE_RSOLUTION_TXSIDE				\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
+#define	GP_STATUS_PAUSE_RSOLUTION_RXSIDE				\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
+#define	GP_STATUS_SPEED_MASK						\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
+#define	GP_STATUS_10M	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
+#define	GP_STATUS_100M	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
+#define	GP_STATUS_1G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
+#define	GP_STATUS_2_5G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
+#define	GP_STATUS_5G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
+#define	GP_STATUS_6G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
+#define	GP_STATUS_10G_HIG						\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
+#define	GP_STATUS_10G_CX4						\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
+#define	GP_STATUS_12G_HIG						\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
+#define	GP_STATUS_12_5G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
+#define	GP_STATUS_13G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
+#define	GP_STATUS_15G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
+#define	GP_STATUS_16G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
+#define	GP_STATUS_1G_KX	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
+#define	GP_STATUS_10G_KX4						\
+	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
+
+#define	LINK_10THD		LINK_STATUS_SPEED_AND_DUPLEX_10THD
+#define	LINK_10TFD		LINK_STATUS_SPEED_AND_DUPLEX_10TFD
+#define	LINK_100TXHD		LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
+#define	LINK_100T4		LINK_STATUS_SPEED_AND_DUPLEX_100T4
+#define	LINK_100TXFD		LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
+#define	LINK_1000THD		LINK_STATUS_SPEED_AND_DUPLEX_1000THD
+#define	LINK_1000TFD		LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
+#define	LINK_1000XFD		LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
+#define	LINK_2500THD		LINK_STATUS_SPEED_AND_DUPLEX_2500THD
+#define	LINK_2500TFD		LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
+#define	LINK_2500XFD		LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
+#define	LINK_10GTFD		LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
+#define	LINK_10GXFD		LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
+#define	LINK_12GTFD		LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
+#define	LINK_12GXFD		LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
+#define	LINK_12_5GTFD		LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
+#define	LINK_12_5GXFD		LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
+#define	LINK_13GTFD		LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
+#define	LINK_13GXFD		LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
+#define	LINK_15GTFD		LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
+#define	LINK_15GXFD		LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
+#define	LINK_16GTFD		LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
+#define	LINK_16GXFD		LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
+
+#define	MEDIUM_FULL_DUPLEX	0
+#define	MEDIUM_HALF_DUPLEX	1
+
+#define	DUPLEX_FULL		0
+#define	DUPLEX_HALF		1
+
+#define	SPEED_10		10
+#define	SPEED_100		100
+#define	SPEED_1000		1000
+#define	SPEED_2500		2500
+#define	SPEED_10000		10000
+
+#ifdef notyet
+#define	NIG_STATUS_XGXS0_LINK10G					\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
+#define	NIG_STATUS_XGXS0_LINK_STATUS					\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
+#define	NIG_STATUS_XGXS0_LINK_STATUS_SIZE				\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
+#define	NIG_STATUS_SERDES0_LINK_STATUS					\
+	NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
+#define	NIG_MASK_MI_INT							\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
+#define	NIG_MASK_XGXS0_LINK10G						\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
+#define	NIG_MASK_XGXS0_LINK_STATUS					\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
+#define	NIG_MASK_SERDES0_LINK_STATUS					\
+	NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
+
+#define	XGXS_RESET_BITS							\
+	(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |		\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |		\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
+
+#define	SERDES_RESET_BITS						\
+	(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |		\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |	\
+	MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
+
+#define	SFP_EEPROM_CON_TYPE_ADDR		0x2
+#define	SFP_EEPROM_CON_TYPE_VAL_LC		0x7
+#define	SFP_EEPROM_CON_TYPE_VAL_COPPER		0x21
+
+#define	SFP_EEPROM_FC_TX_TECH_ADDR		0x8
+#define	SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE	0x8
+#define	SFP_EEPROM_VENDOR_NAME_SIZE		16
+#define	SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK	0x1
+#define	SFP_EEPROM_OPTIONS_SIZE			2
+#endif
+
+#define	BXE_PMF_LINK_ASSERT						\
+	GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(sc))
+
+#define	BXE_MC_ASSERT_BITS						\
+	(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) |	\
+	GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) |	\
+	GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) |	\
+	GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
+
+#define	BXE_MCP_ASSERT							\
+	GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
+
+#define	BXE_GRC_TIMEOUT							\
+	GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
+
+#define	BXE_GRC_RSV							\
+	(GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) |			\
+	 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) |			\
+	 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) |			\
+	 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) |			\
+	 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) |			\
+	 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
+
+#define	HW_INTERRUT_ASSERT_SET_0					\
+	(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |				\
+	AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
+
+#define	HW_PRTY_ASSERT_SET_0						\
+	(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
+
+#define	HW_INTERRUT_ASSERT_SET_1					\
+	(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |				\
+	AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |				\
+	AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |				\
+	AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |				\
+	AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
+
+#define	HW_PRTY_ASSERT_SET_1						\
+	(AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |				\
+	AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |			\
+    	AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |		\
+	AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |				\
+	AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
+
+#define	HW_INTERRUT_ASSERT_SET_2					\
+	(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |				\
+	AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |			\
+	AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |		\
+	AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
+
+#define	HW_PRTY_ASSERT_SET_2						\
+	(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |			\
+	AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |				\
+	AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |		\
+	AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |				\
+	AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |				\
+	AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |				\
+	AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
+
+/* Stuff added to make the code fit 80Col. */
+#define	CQE_TYPE(cqe_fp_flags)	((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
+
+#define	TPA_TYPE_START		ETH_FAST_PATH_RX_CQE_START_FLG
+#define	TPA_TYPE_END		ETH_FAST_PATH_RX_CQE_END_FLG
+#define	TPA_TYPE(cqe_fp_flags)						\
+	((cqe_fp_flags) & (TPA_TYPE_START | TPA_TYPE_END))
+
+#define	ETH_RX_ERROR_FLAGS	ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
+
+#define	BXE_IP_CSUM_ERR(cqe)						\
+	(!((cqe)->fast_path_cqe.status_flags &				\
+	ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) &&		\
+	((cqe)->fast_path_cqe.type_error_flags &			\
+	ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
+
+#define	BXE_L4_CSUM_ERR(cqe)						\
+	(!((cqe)->fast_path_cqe.status_flags &				\
+	ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) &&		\
+	((cqe)->fast_path_cqe.type_error_flags &			\
+	ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
+
+#define	BXE_RX_CSUM_OK(cqe)						\
+	(!(BXE_L4_CSUM_ERR(cqe) || BXE_IP_CSUM_ERR(cqe)))
+
+#define	BXE_RX_SUM_FIX(cqe) 						\
+	((le16toh(cqe->fast_path_cqe.pars_flags.flags) &		\
+	PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==			\
+	(1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
+
+#define	MULTI_FLAGS(sc)							\
+	(TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY |	\
+	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY |	\
+	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY |		\
+	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY |	\
+	(sc->multi_mode <<						\
+	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
+
+#define	MULTI_MASK		0x7f
+
+#define	FP_USB_FUNC_OFF		(2 + 2 * HC_USTORM_SB_NUM_INDICES)
+#define	FP_CSB_FUNC_OFF		(2 + 2 * HC_CSTORM_SB_NUM_INDICES)
+
+#define	U_SB_ETH_RX_CQ_INDEX	HC_INDEX_U_ETH_RX_CQ_CONS
+#define	U_SB_ETH_RX_BD_INDEX	HC_INDEX_U_ETH_RX_BD_CONS
+#define	C_SB_ETH_TX_CQ_INDEX	HC_INDEX_C_ETH_TX_CQ_CONS
+
+#define	DEF_USB_FUNC_OFF	(2 + 2 * HC_USTORM_DEF_SB_NUM_INDICES)
+#define	DEF_CSB_FUNC_OFF	(2 + 2 * HC_CSTORM_DEF_SB_NUM_INDICES)
+#define	DEF_XSB_FUNC_OFF	(2 + 2 * HC_XSTORM_DEF_SB_NUM_INDICES)
+#define	DEF_TSB_FUNC_OFF	(2 + 2 * HC_TSTORM_DEF_SB_NUM_INDICES)
+
+#define	C_DEF_SB_SP_INDEX	HC_INDEX_DEF_C_ETH_SLOW_PATH
+
+#define	BXE_RX_SB_INDEX							\
+	&fp->status_block->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
+
+#define	BXE_RX_SB_BD_INDEX						\
+	(&fp->status_block->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
+
+#define	BXE_TX_SB_INDEX							\
+	(&fp->status_block->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
+
+#define	BXE_SP_DSB_INDEX						\
+	&sc->def_status_block->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
+
+#define	BXE_RX_SB_INDEX_NUM						\
+	(((U_SB_ETH_RX_CQ_INDEX <<					\
+	USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) &	\
+	USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) |		\
+	((U_SB_ETH_RX_BD_INDEX <<					\
+	USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) &	\
+	USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
+
+#define	CAM_IS_INVALID(x)						\
+	(x.target_table_entry.flags ==					\
+	TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
+
+#define	CAM_INVALIDATE(x)						\
+	(x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
+
+/* Number of uint32_t elements in multicast hash array. */
+#define	MC_HASH_SIZE			8
+#define	MC_HASH_OFFSET(sc, i)						\
+	(BAR_TSTORM_INTMEM +						\
+	TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(sc)) + \
+	i * 4)
+
+#define	UINT_MAX			(~0U)
+
+/*
+ * PCIE Capability Register Definitions. Need to replace with the system
+ * header file later.
+ */
+#define	PCI_EXP_DEVCTL			8
+#define	PCI_EXP_DEVCTL_CERE		0x0001
+#define	PCI_EXP_DEVCTL_NFERE		0x0002
+#define	PCI_EXP_DEVCTL_FERE		0x0004
+#define	PCI_EXP_DEVCTL_URRE		0x0008
+#define	PCI_EXP_DEVCTL_RELAX_EN		0x0010
+#define	PCI_EXP_DEVCTL_PAYLOAD		0x00e0
+#define	PCI_EXP_DEVCTL_EXT_TAG		0x0100
+#define	PCI_EXP_DEVCTL_PHANTOM		0x0200
+#define	PCI_EXP_DEVCTL_AUX_PME		0x0400
+#define	PCI_EXP_DEVCTL_NOSNOOP_EN	0x0800
+#define	PCI_EXP_DEVCTL_READRQ		0x7000
+
+/*
+ * Return Value for bxe_attach/bxe_detach when device is not found.
+ */
+/* ToDo: Are these necessary? */
+#ifndef	ENODEV
+#define	ENODEV	3
+#endif
+
+/* Return Vlaue for sp_post */
+#ifndef	ESPQOVERFLOW
+#define	ESPQOVERFLOW	4
+#endif
+
+/* Return Value for bxe_write_phy, bxe_read_phy. */
+#ifndef	EBUSY
+#define	EBUSY	5
+#endif
+
+#ifndef	PCI_EXP_DEVCTL
+#define	PCI_EXP_DEVCTL			8	/* Device Control */
+#endif
+
+#ifndef	PCI_EXP_DEVCTL_PAYLOAD
+#define	PCI_EXP_DEVCTL_PAYLOAD		0x00e0	/* Max_Payload_Size */
+#endif
+
+#ifndef	PCI_EXP_DEVCTL_READRQ
+#define	PCI_EXP_DEVCTL_READRQ		0x7000	/* Max_Read_Request_Size */
+#endif
+
+#if defined(__i386__) || defined(__amd64__)
+/* ToDo: Validate this! */
+/* 128 byte L1 cache size. */
+#define	BXE_RX_ALIGN_SHIFT	7
+#else
+/* ToDo: Validate this! */
+/* 256 byte L1 cache size. */
+#define	BXE_RX_ALIGN_SHIFT	8
+#endif
+
+#define	BXE_RX_ALIGN		(1 << BXE_RX_ALIGN_SHIFT)
+
+#if __FreeBSD_version < 800054
+#if defined(__i386__) || defined(__amd64__)
+#define	mb()		__asm volatile("mfence" ::: "memory")
+#define	wmb()		__asm volatile("sfence" ::: "memory")
+#define	rmb()		__asm volatile("lfence" ::: "memory")
+static __inline void
+prefetch(void *x)
+{
+	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
+}
+#else
+#define	mb()
+#define	rmb()
+#define	wmb()
+#define	prefetch()
+#endif
+#endif
+
+#define	BXE_RX_ALIGN		(1 << BXE_RX_ALIGN_SHIFT)
+
+#define	PAGE_ALIGN(addr)	(((addr) + PAGE_SIZE - 1) & (~PAGE_MASK))
+
+/* External PHY definitions. */
+#define	LED_MODE_OFF	0
+#define	LED_MODE_OPER	2
+
+#endif /*_IF_BXE_H */
+
diff --git a/sys/i386/conf/GENERIC b/sys/i386/conf/GENERIC
index 2d91cca..b709f36 100644
--- a/sys/i386/conf/GENERIC
+++ b/sys/i386/conf/GENERIC
@@ -203,6 +203,7 @@ device		ppi		# Parallel port interface device
 #device		puc
 
 # PCI Ethernet NICs.
+device		bxe		# Broadcom BCM57710/BCM57711/BCM57711E 10Gb Ethernet
 device		de		# DEC/Intel DC21x4x (``Tulip'')
 device		em		# Intel PRO/1000 Gigabit Ethernet Family
 device		igb		# Intel PRO/1000 PCIE Server Gigabit Family
diff --git a/sys/modules/bxe/Makefile b/sys/modules/bxe/Makefile
new file mode 100755
index 0000000..c299480
--- /dev/null
+++ b/sys/modules/bxe/Makefile
@@ -0,0 +1,13 @@
+# $FreeBSD$
+BXE	= ${.CURDIR}/../../dev/bxe
+.PATH:	${BXE}
+
+KMOD=	if_bxe
+SRCS	= opt_bxe.h device_if.h bus_if.h pci_if.h miibus_if.h miidevs.h 
+SRCS	+= if_bxe.c bxe_link.c
+
+CFLAGS += -I${BXE} -DBXE_TASK
+#CFLAGS += -DBXE_DEBUG
+#CFLAGS += -DBXE_NVRAM_WRITE_SUPPORT
+
+.include <bsd.kmod.mk>
diff --git a/usr.sbin/sysinstall/devices.c b/usr.sbin/sysinstall/devices.c
index 53ebb89..18a33b5 100644
--- a/usr.sbin/sysinstall/devices.c
+++ b/usr.sbin/sysinstall/devices.c
@@ -106,6 +106,7 @@ static struct _devname {
     NETWORK("bge",	"Broadcom BCM570x PCI Gigabit Ethernet card"),
     NETWORK("bm",	"Apple BMAC Built-in Ethernet"),
     NETWORK("bwn",	"Broadcom BCM43xx IEEE 802.11 wireless adapter"),
+    NETWORK("bxe",	"Broadcom NetXtreme II 10Gb Ethernet card"),
     NETWORK("cas",	"Sun Cassini/Cassini+ or NS DP83065 Saturn Ethernet"),
     NETWORK("cue",	"CATC USB Ethernet adapter"),
     NETWORK("cxgb",	"Chelsio T3 10Gb Ethernet card"),