Cave in and disable the ADC DC gain/offset calibrations if they're

not needed.

These calibrations are only applicable if the chip operating mode
engages both interleaved RX ADCs (ie, it's compensating for the
differences in DC gain and DC offset -between- the two ADCs.)
Otherwise the chip reads values of 0x0 for the secondary ADC
(as I guess it's not enabled here) and thus writes potentially
bogus info into the chip.

I've tested this on the AR9160 and AR9280; both behave themselves
in 11g mode with these calibrations disabled.

1 files changed, 6 insertions, 3 deletions

diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
index f37f62f..7e031bb 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
@@ -72,9 +72,12 @@ ar5416IsCalSupp(struct ath_hal *ah, const struct ieee80211_channel *chan,
 		return !IEEE80211_IS_CHAN_B(chan);
 	case ADC_GAIN_CAL:
 	case ADC_DC_CAL:
-		/* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
-		return !IEEE80211_IS_CHAN_B(chan) &&
-		    !(IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan));
+		/* Run ADC Gain Cal for either 5ghz any or 2ghz HT40 */
+		if (IEEE80211_IS_CHAN_2GHZ(chan))
+			return AH_FALSE;
+		if (IEEE80211_IS_CHAN_HT20(chan))
+			return AH_FALSE;
+		return AH_TRUE;
 	}
 	return AH_FALSE;
 }