MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,

    r262482, r262483, r262531,

  Move the declaration for mpentry() into a header file instead of pasting
  it into a bunch of different .c files.

  If the L2 cache type is PIPT, pass a physical address for a flush.

  Actually set the proper bit to indicate TTB shared memory.

  Add a new cache maintenance function, idcache_inv_all, to the table, and
  implementations for each of the chips we support.

  Invalidate caches immediately upon entry to init_secondary().  Also set
  the Bufferable bit in the PDE entries of the secondary processor startup
  pagetables.

  Add the bits needed to run SMP on imx6.

  Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.

  Minor tweaks to the imx GPT timer

  Vybrid enhancements...
  - Pin configuration is a complete iomux register now and includes
    drive strength, pull mode, mux mode, speed, etc.
  - Add i2c devices to the tree
  - Add IPG clock
  - Add support for Quartz Module.
  - Pin configuration is a complete iomux register now and includes
    drive strength, pull mode, mux mode, speed, etc.
  - Add i2c devices to the tree
  - Add IPG clock

23 files changed, 549 insertions, 100 deletions

diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 923745f..b8ad4e5 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -146,6 +146,7 @@ struct cpu_functions arm7tdmi_cpufuncs = {
 	(void *)arm7tdmi_cache_flushID,	/* dcache_inv_range	*/
 	(void *)cpufunc_nullop,		/* dcache_wb_range	*/
 
+	cpufunc_nullop,			/* idcache_inv_all	*/
 	arm7tdmi_cache_flushID,		/* idcache_wbinv_all	*/
 	(void *)arm7tdmi_cache_flushID,	/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -208,6 +209,7 @@ struct cpu_functions arm8_cpufuncs = {
 /*XXX*/	(void *)arm8_cache_purgeID,	/* dcache_inv_range	*/
 	(void *)arm8_cache_cleanID,	/* dcache_wb_range	*/
 
+	cpufunc_nullop,			/* idcache_inv_all	*/
 	arm8_cache_purgeID,		/* idcache_wbinv_all	*/
 	(void *)arm8_cache_purgeID,	/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -269,6 +271,7 @@ struct cpu_functions arm9_cpufuncs = {
 	arm9_dcache_inv_range,		/* dcache_inv_range	*/
 	arm9_dcache_wb_range,		/* dcache_wb_range	*/
 
+	armv4_idcache_inv_all,		/* idcache_inv_all	*/
 	arm9_idcache_wbinv_all,		/* idcache_wbinv_all	*/
 	arm9_idcache_wbinv_range,	/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -331,6 +334,7 @@ struct cpu_functions armv5_ec_cpufuncs = {
 	armv5_ec_dcache_inv_range,	/* dcache_inv_range	*/
 	armv5_ec_dcache_wb_range,	/* dcache_wb_range	*/
 
+	armv4_idcache_inv_all,		/* idcache_inv_all	*/
 	armv5_ec_idcache_wbinv_all,	/* idcache_wbinv_all	*/
 	armv5_ec_idcache_wbinv_range,	/* idcache_wbinv_range	*/
 
@@ -392,6 +396,7 @@ struct cpu_functions sheeva_cpufuncs = {
 	sheeva_dcache_inv_range,	/* dcache_inv_range	*/
 	sheeva_dcache_wb_range,		/* dcache_wb_range	*/
 
+	armv4_idcache_inv_all,		/* idcache_inv_all	*/
 	armv5_ec_idcache_wbinv_all,	/* idcache_wbinv_all	*/
 	sheeva_idcache_wbinv_range,	/* idcache_wbinv_all	*/
 
@@ -454,6 +459,7 @@ struct cpu_functions arm10_cpufuncs = {
 	arm10_dcache_inv_range,		/* dcache_inv_range	*/
 	arm10_dcache_wb_range,		/* dcache_wb_range	*/
 
+	armv4_idcache_inv_all,		/* idcache_inv_all	*/
 	arm10_idcache_wbinv_all,	/* idcache_wbinv_all	*/
 	arm10_idcache_wbinv_range,	/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -515,6 +521,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
 	armv7_dcache_inv_range,		/* dcache_inv_range	*/
 	armv7_dcache_wb_range,		/* dcache_wb_range	*/
 
+	armv7_idcache_inv_all,		/* idcache_inv_all	*/
 	armv7_idcache_wbinv_all,	/* idcache_wbinv_all	*/
 	armv7_idcache_wbinv_range,	/* idcache_wbinv_all	*/
 
@@ -577,6 +584,7 @@ struct cpu_functions sa110_cpufuncs = {
 /*XXX*/	sa1_cache_purgeD_rng,		/* dcache_inv_range	*/
 	sa1_cache_cleanD_rng,		/* dcache_wb_range	*/
 
+	sa1_cache_flushID,		/* idcache_inv_all	*/
 	sa1_cache_purgeID,		/* idcache_wbinv_all	*/
 	sa1_cache_purgeID_rng,		/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -638,6 +646,7 @@ struct cpu_functions sa11x0_cpufuncs = {
 /*XXX*/	sa1_cache_purgeD_rng,		/* dcache_inv_range	*/
 	sa1_cache_cleanD_rng,		/* dcache_wb_range	*/
 
+	sa1_cache_flushID,		/* idcache_inv_all	*/
 	sa1_cache_purgeID,		/* idcache_wbinv_all	*/
 	sa1_cache_purgeID_rng,		/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -699,6 +708,7 @@ struct cpu_functions ixp12x0_cpufuncs = {
 /*XXX*/	sa1_cache_purgeD_rng,		/* dcache_inv_range	*/
 	sa1_cache_cleanD_rng,		/* dcache_wb_range	*/
 
+	sa1_cache_flushID,		/* idcache_inv_all	*/
 	sa1_cache_purgeID,		/* idcache_wbinv_all	*/
 	sa1_cache_purgeID_rng,		/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -763,6 +773,7 @@ struct cpu_functions xscale_cpufuncs = {
 	xscale_cache_flushD_rng,	/* dcache_inv_range	*/
 	xscale_cache_cleanD_rng,	/* dcache_wb_range	*/
 
+	xscale_cache_flushID,		/* idcache_inv_all	*/
 	xscale_cache_purgeID,		/* idcache_wbinv_all	*/
 	xscale_cache_purgeID_rng,	/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all 	*/
@@ -826,6 +837,7 @@ struct cpu_functions xscalec3_cpufuncs = {
 	xscale_cache_flushD_rng,	/* dcache_inv_range	*/
 	xscalec3_cache_cleanD_rng,	/* dcache_wb_range	*/
 
+	xscale_cache_flushID,		/* idcache_inv_all	*/
 	xscalec3_cache_purgeID,		/* idcache_wbinv_all	*/
 	xscalec3_cache_purgeID_rng,	/* idcache_wbinv_range	*/
 	xscalec3_l2cache_purge,		/* l2cache_wbinv_all	*/
@@ -888,6 +900,7 @@ struct cpu_functions fa526_cpufuncs = {
 	fa526_dcache_inv_range,		/* dcache_inv_range	*/
 	fa526_dcache_wb_range,		/* dcache_wb_range	*/
 
+	armv4_idcache_inv_all,		/* idcache_inv_all	*/
 	fa526_idcache_wbinv_all,	/* idcache_wbinv_all	*/
 	fa526_idcache_wbinv_range,	/* idcache_wbinv_range	*/
 	cpufunc_nullop,			/* l2cache_wbinv_all	*/
@@ -949,6 +962,7 @@ struct cpu_functions arm1136_cpufuncs = {
 	armv6_dcache_inv_range,         /* dcache_inv_range     */
 	armv6_dcache_wb_range,          /* dcache_wb_range      */
 	
+	armv6_idcache_inv_all,		/* idcache_inv_all	*/
 	arm11x6_idcache_wbinv_all,      /* idcache_wbinv_all    */
 	arm11x6_idcache_wbinv_range,    /* idcache_wbinv_range  */
 	
@@ -1010,6 +1024,7 @@ struct cpu_functions arm1176_cpufuncs = {
 	armv6_dcache_inv_range,         /* dcache_inv_range     */
 	armv6_dcache_wb_range,          /* dcache_wb_range      */
 	
+	armv6_idcache_inv_all,		/* idcache_inv_all	*/
 	arm11x6_idcache_wbinv_all,      /* idcache_wbinv_all    */
 	arm11x6_idcache_wbinv_range,    /* idcache_wbinv_range  */
 	
@@ -1072,6 +1087,7 @@ struct cpu_functions cortexa_cpufuncs = {
 	armv7_dcache_inv_range,         /* dcache_inv_range     */
 	armv7_dcache_wb_range,          /* dcache_wb_range      */
 	
+	armv7_idcache_inv_all,		/* idcache_inv_all	*/
 	armv7_idcache_wbinv_all,        /* idcache_wbinv_all    */
 	armv7_idcache_wbinv_range,      /* idcache_wbinv_range  */
 	
diff --git a/sys/arm/arm/cpufunc_asm_armv4.S b/sys/arm/arm/cpufunc_asm_armv4.S
index 1123e4a..a61a3dc 100644
--- a/sys/arm/arm/cpufunc_asm_armv4.S
+++ b/sys/arm/arm/cpufunc_asm_armv4.S
@@ -71,3 +71,9 @@ ENTRY(armv4_drain_writebuf)
 	RET
 END(armv4_drain_writebuf)
 
+ENTRY(armv4_idcache_inv_all)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* invalidate all I+D cache */
+	RET
+END(armv4_drain_writebuf)
+
diff --git a/sys/arm/arm/cpufunc_asm_armv6.S b/sys/arm/arm/cpufunc_asm_armv6.S
index b8a2d9c..5ba0076 100644
--- a/sys/arm/arm/cpufunc_asm_armv6.S
+++ b/sys/arm/arm/cpufunc_asm_armv6.S
@@ -148,3 +148,9 @@ ENTRY(armv6_dcache_wbinv_all)
 END(armv6_idcache_wbinv_all)
 END(armv6_dcache_wbinv_all)
 
+ENTRY(armv6_idcache_inv_all)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* invalidate all I+D cache */
+	RET
+END(armv6_idcache_inv_all)
+
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S
index bc28f82..74933eb 100644
--- a/sys/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arm/arm/cpufunc_asm_armv7.S
@@ -1,4 +1,5 @@
 /*-
+ * Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
  * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
  * All rights reserved.
  *
@@ -305,3 +306,40 @@ ENTRY(armv7_auxctrl)
 	RET
 END(armv7_auxctrl)
 
+ENTRY(armv7_idcache_inv_all)
+	mov     r0, #0
+	mcr     p15, 2, r0, c0, c0, 0   @ set cache level to L1
+	mrc     p15, 1, r0, c0, c0, 0   @ read CCSIDR
+
+	ubfx    r2, r0, #13, #15        @ get num sets - 1 from CCSIDR
+	ubfx    r3, r0, #3, #10         @ get numways - 1 from CCSIDR
+	clz     r1, r3                  @ number of bits to MSB of way
+	lsl     r3, r3, r1              @ shift into position
+	mov     ip, #1                  @
+	lsl     ip, ip, r1              @ ip now contains the way decr
+
+	ubfx    r0, r0, #0, #3          @ get linesize from CCSIDR
+	add     r0, r0, #4              @ apply bias
+	lsl     r2, r2, r0              @ shift sets by log2(linesize)
+	add     r3, r3, r2              @ merge numsets - 1 with numways - 1
+	sub     ip, ip, r2              @ subtract numsets - 1 from way decr
+	mov     r1, #1
+	lsl     r1, r1, r0              @ r1 now contains the set decr
+	mov     r2, ip                  @ r2 now contains set way decr
+
+	/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
+1:      mcr     p15, 0, r3, c7, c6, 2   @ invalidate line
+	movs    r0, r3                  @ get current way/set
+	beq     2f                      @ at 0 means we are done.
+	movs    r0, r0, lsl #10         @ clear way bits leaving only set bits
+	subne   r3, r3, r1              @ non-zero?, decrement set #
+	subeq   r3, r3, r2              @ zero?, decrement way # and restore set count
+	b       1b
+
+2:	dsb                             @ wait for stores to finish
+	mov     r0, #0                  @ and ...
+	mcr     p15, 0, r0, c7, c5, 0   @ invalidate instruction+branch cache
+	isb                             @ instruction sync barrier
+	bx      lr                      @ return
+END(armv7_l1cache_inv_all)
+
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index 2813dec..364d19e 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -425,7 +425,7 @@ Ltag:
 	orr	r0, r0, #PHYSADDR
 	ldr	r0, [r0]
 #if defined(SMP)
-	orr 	r0, r0, #0		/* Set TTB shared memory flag */
+	orr 	r0, r0, #2		/* Set TTB shared memory flag */
 #endif
 	mcr	p15, 0, r0, c2, c0, 0	/* Set TTB */
 	mcr	p15, 0, r0, c8, c7, 0	/* Flush TLB */
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c
index 8544dc1..1386210 100644
--- a/sys/arm/arm/machdep.c
+++ b/sys/arm/arm/machdep.c
@@ -410,7 +410,11 @@ cpu_flush_dcache(void *ptr, size_t len)
 {
 
 	cpu_dcache_wb_range((uintptr_t)ptr, len);
+#ifdef ARM_L2_PIPT
+	cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
+#else
 	cpu_l2cache_wb_range((uintptr_t)ptr, len);
+#endif
 }
 
 /* Get current clock frequency for the given cpu id. */
diff --git a/sys/arm/arm/mp_machdep.c b/sys/arm/arm/mp_machdep.c
index 64b7388..584eda5 100644
--- a/sys/arm/arm/mp_machdep.c
+++ b/sys/arm/arm/mp_machdep.c
@@ -128,10 +128,10 @@ cpu_mp_start(void)
 	bzero((void *)temp_pagetable_va,  L1_TABLE_SIZE);
 	for (addr = arm_physmem_kernaddr; addr <= addr_end; addr += L1_S_SIZE) { 
 		((int *)(temp_pagetable_va))[addr >> L1_S_SHIFT] =
-		    L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr;
+		    L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr;
 		((int *)(temp_pagetable_va))[(addr -
 			arm_physmem_kernaddr + KERNVIRTADDR) >> L1_S_SHIFT] = 
-		    L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr;
+		    L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr;
 	}
 
 #if defined(CPU_MV_PJ4B)
@@ -173,6 +173,8 @@ init_secondary(int cpu)
 	uint32_t loop_counter;
 	int start = 0, end = 0;
 
+	cpu_idcache_inv_all();
+
 	cpu_setup(NULL);
 	setttb(pmap_pa);
 	cpu_tlb_flushID();
diff --git a/sys/arm/conf/QUARTZ b/sys/arm/conf/QUARTZ
new file mode 100644
index 0000000..4a31667
--- /dev/null
+++ b/sys/arm/conf/QUARTZ
@@ -0,0 +1,26 @@
+# Kernel configuration for Device Solutions Quartz Module.
+#
+# For more information on this file, please read the config(5) manual page,
+# and/or the handbook section on Kernel Configuration Files:
+#
+#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+include		"VYBRID.common"
+ident		QUARTZ
+
+#FDT
+options		FDT
+options		FDT_DTB_STATIC
+makeoptions	FDT_DTS_FILE=vybrid-quartz.dts
diff --git a/sys/arm/freescale/imx/files.imx6 b/sys/arm/freescale/imx/files.imx6
index 943c679..41060da 100644
--- a/sys/arm/freescale/imx/files.imx6
+++ b/sys/arm/freescale/imx/files.imx6
@@ -22,6 +22,7 @@ arm/freescale/imx/common.c		standard
 arm/freescale/imx/imx6_anatop.c		standard
 arm/freescale/imx/imx6_ccm.c		standard
 arm/freescale/imx/imx6_machdep.c	standard
+arm/freescale/imx/imx6_mp.c		optional smp
 arm/freescale/imx/imx6_pl310.c		standard
 arm/freescale/imx/imx_machdep.c		standard
 arm/freescale/imx/imx_gpt.c		standard
diff --git a/sys/arm/freescale/imx/imx6_mp.c b/sys/arm/freescale/imx/imx6_mp.c
new file mode 100644
index 0000000..5b5136b
--- /dev/null
+++ b/sys/arm/freescale/imx/imx6_mp.c
@@ -0,0 +1,170 @@
+/*-
+ * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de>
+ * Copyright (c) 2014 Ian Lepore <ian@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/smp.h>
+
+#include <machine/smp.h>
+#include <machine/fdt.h>
+#include <machine/intr.h>
+
+#define	SCU_PHYSBASE			0x00a00000
+#define	SCU_SIZE			0x00001000
+
+#define	SCU_CONTROL_REG			0x00
+#define	  SCU_CONTROL_ENABLE		  (1 << 0)
+#define	SCU_CONFIG_REG			0x04
+#define	  SCU_CONFIG_REG_NCPU_MASK	  0x03
+#define	SCU_CPUPOWER_REG		0x08
+#define	SCU_INV_TAGS_REG		0x0c
+#define	SCU_DIAG_CONTROL		0x30
+#define	  SCU_DIAG_DISABLE_MIGBIT	  (1 << 0)
+#define	SCU_FILTER_START_REG		0x40
+#define	SCU_FILTER_END_REG		0x44
+#define	SCU_SECURE_ACCESS_REG		0x50
+#define	SCU_NONSECURE_ACCESS_REG	0x54
+
+#define	SRC_PHYSBASE			0x020d8000
+#define SRC_SIZE			0x4000
+#define	SRC_CONTROL_REG			0x00
+#define	SRC_CONTROL_C1ENA_SHIFT		  22	/* Bit for Core 1 enable */
+#define	SRC_CONTROL_C1RST_SHIFT		  14	/* Bit for Core 1 reset */
+#define	SRC_GPR0_C1FUNC			0x20	/* Register for Core 1 entry func */
+#define	SRC_GPR1_C1ARG			0x24	/* Register for Core 1 entry arg */
+
+void
+platform_mp_init_secondary(void)
+{
+
+	gic_init_secondary();
+}
+
+void
+platform_mp_setmaxid(void)
+{
+	bus_space_handle_t scu;
+	uint32_t val;
+
+	/* If we've already set the global vars don't bother to do it again. */
+	if (mp_ncpus != 0)
+		return;
+
+	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
+		panic("Couldn't map the SCU\n");
+	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG);
+	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
+
+	mp_maxid = (val & SCU_CONFIG_REG_NCPU_MASK);
+	mp_ncpus = mp_maxid + 1;
+}
+
+int
+platform_mp_probe(void)
+{
+
+	/* I think platform_mp_setmaxid must get called first, but be safe. */
+	if (mp_ncpus == 0)
+		platform_mp_setmaxid();
+
+	return (mp_ncpus > 1);
+}
+
+void    
+platform_mp_start_ap(void)
+{
+	bus_space_handle_t scu;
+	bus_space_handle_t src;
+
+	uint32_t val;
+	int i;
+
+	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
+		panic("Couldn't map the SCU\n");
+	if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
+		panic("Couldn't map the system reset controller (SRC)\n");
+
+	/*
+	 * Invalidate SCU cache tags.  The 0x0000ffff constant invalidates all
+	 * ways on all cores 0-3.  Per the ARM docs, it's harmless to write to
+	 * the bits for cores that are not present.
+	 */
+	bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
+
+	/*
+	 * Erratum ARM/MP: 764369 (problems with cache maintenance).
+	 * Setting the "disable-migratory bit" in the undocumented SCU
+	 * Diagnostic Control Register helps work around the problem.
+	 */
+	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
+	bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, 
+	    val | SCU_DIAG_DISABLE_MIGBIT);
+
+	/*
+	 * Enable the SCU, then clean the cache on this core.  After these two
+	 * operations the cache tag ram in the SCU is coherent with the contents
+	 * of the cache on this core.  The other cores aren't running yet so
+	 * their caches can't contain valid data yet, but we've initialized
+	 * their SCU tag ram above, so they will be coherent from startup.
+	 */
+	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
+	bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, 
+	    val | SCU_CONTROL_ENABLE);
+	cpu_idcache_wbinv_all();
+
+	/*
+	 * For each AP core, set the entry point address and argument registers,
+	 * and set the core-enable and core-reset bits in the control register.
+	 */
+	val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
+	for (i=1; i < mp_ncpus; i++) {
+		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
+		    pmap_kextract((vm_offset_t)mpentry));
+		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG  + 8*i, 0);
+
+		val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
+		    ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
+
+	}
+	bus_space_write_4(fdtbus_bs_tag, src, 0, val);
+
+	armv7_sev();
+
+	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
+	bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
+}
+
+void
+platform_ipi_send(cpuset_t cpus, u_int ipi)
+{
+
+	pic_ipi_send(cpus, ipi);
+}
diff --git a/sys/arm/freescale/imx/imx_gpt.c b/sys/arm/freescale/imx/imx_gpt.c
index 0e32bc9..f792a97 100644
--- a/sys/arm/freescale/imx/imx_gpt.c
+++ b/sys/arm/freescale/imx/imx_gpt.c
@@ -75,7 +75,7 @@ static int imx_gpt_probe(device_t);
 static int imx_gpt_attach(device_t);
 
 static struct timecounter imx_gpt_timecounter = {
-	.tc_name           = "i.MX GPT Timecounter",
+	.tc_name           = "iMXGPT",
 	.tc_get_timecount  = imx_gpt_get_timecount,
 	.tc_counter_mask   = ~0u,
 	.tc_frequency      = 0,
@@ -244,9 +244,9 @@ imx_gpt_attach(device_t dev)
 	}
 
 	/* Register as an eventtimer. */
-	sc->et.et_name = "i.MXxxx GPT Eventtimer";
+	sc->et.et_name = "iMXGPT";
 	sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
-	sc->et.et_quality = 1000;
+	sc->et.et_quality = 800;
 	sc->et.et_frequency = sc->clkfreq;
 	sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency;
 	sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
@@ -286,9 +286,9 @@ imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 		/* Do not disturb, otherwise event will be lost */
 		spinlock_enter();
 		/* Set expected value */
-		WRITE4(sc, IMX_GPT_OCR1, READ4(sc, IMX_GPT_CNT) + ticks);
+		WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks);
 		/* Enable compare register 1 Interrupt */
-		SET4(sc, IMX_GPT_IR, GPT_IR_OF1);
+		SET4(sc, IMX_GPT_IR, GPT_IR_OF3);
 		/* Now everybody can relax */
 		spinlock_exit();
 		return (0);
@@ -349,7 +349,7 @@ imx_gpt_intr(void *arg)
 	WRITE4(sc, IMX_GPT_SR, status);
 
 	/* Handle one-shot timer events. */
-	if (status & GPT_IR_OF1) {
+	if (status & GPT_IR_OF3) {
 		if (sc->et.et_active) {
 			sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 		}
diff --git a/sys/arm/freescale/imx/std.imx6 b/sys/arm/freescale/imx/std.imx6
index c328b22..51f82a8 100644
--- a/sys/arm/freescale/imx/std.imx6
+++ b/sys/arm/freescale/imx/std.imx6
@@ -10,5 +10,8 @@ options		KERNPHYSADDR		= 0x12000000
 makeoptions	KERNPHYSADDR		= 0x12000000
 options		PHYSADDR		= 0x10000000
 
+options		IPI_IRQ_START=0
+options		IPI_IRQ_END=15
+
 files "../freescale/imx/files.imx6"
 
diff --git a/sys/arm/freescale/vybrid/vf_ccm.c b/sys/arm/freescale/vybrid/vf_ccm.c
index 9d9b517..39c3079 100644
--- a/sys/arm/freescale/vybrid/vf_ccm.c
+++ b/sys/arm/freescale/vybrid/vf_ccm.c
@@ -164,6 +164,18 @@ struct clk {
 	uint32_t	sel_val;
 };
 
+static struct clk ipg_clk = {
+	.reg = CCM_CACRR,
+	.enable_reg = 0,
+	.div_mask = IPG_CLK_DIV_MASK,
+	.div_shift = IPG_CLK_DIV_SHIFT,
+	.div_val = 1, /* Divide by 2 */
+	.sel_reg = 0,
+	.sel_mask = 0,
+	.sel_shift = 0,
+	.sel_val = 0,
+};
+
 /*
   PLL4 clock divider (before switching the clocks should be gated)
   000 Divide by 1 (only if PLL frequency less than or equal to 650 MHz)
@@ -310,6 +322,7 @@ struct clock_entry {
 };
 
 static struct clock_entry clock_map[] = {
+	{"ipg",		&ipg_clk},
 	{"pll4",	&pll4_clk},
 	{"sai3",	&sai3_clk},
 	{"cko1",	&cko1_clk},
diff --git a/sys/arm/freescale/vybrid/vf_iomuxc.c b/sys/arm/freescale/vybrid/vf_iomuxc.c
index 8bfaa8d..8d8f7fd 100644
--- a/sys/arm/freescale/vybrid/vf_iomuxc.c
+++ b/sys/arm/freescale/vybrid/vf_iomuxc.c
@@ -56,21 +56,42 @@ __FBSDID("$FreeBSD$");
 #include <arm/freescale/vybrid/vf_iomuxc.h>
 #include <arm/freescale/vybrid/vf_common.h>
 
-#define	IBE		(1 << 0) /* Input Buffer Enable Field */
-#define	OBE		(1 << 1) /* Output Buffer Enable Field. */
-#define	PUE		(1 << 2) /* Pull / Keep Select Field. */
-#define	PKE		(1 << 3) /* Pull / Keep Enable Field. */
-#define	PUS_MASK	(3 << 4) /* Pull Up / Down Config Field. */
-#define	DSE_MASK	(7 << 6) /* Drive Strength Field. */
-#define	HYS		(1 << 9) /* Hysteresis Enable Field */
-
 #define	MUX_MODE_MASK		7
 #define	MUX_MODE_SHIFT		20
 #define	MUX_MODE_GPIO		0
 #define	MUX_MODE_VBUS_EN_OTG	2
 
-#define	PUS_22_KOHM_PULL_UP	(3 << 4)
-#define	DSE_25_OHM		(6 << 6)
+#define	IBE		(1 << 0)	/* Input Buffer Enable Field */
+#define	OBE		(1 << 1)	/* Output Buffer Enable Field. */
+#define	PUE		(1 << 2)	/* Pull / Keep Select Field. */
+#define	PKE		(1 << 3)	/* Pull / Keep Enable Field. */
+#define	HYS		(1 << 9)	/* Hysteresis Enable Field */
+#define	ODE		(1 << 10)	/* Open Drain Enable Field. */
+#define	SRE		(1 << 11)	/* Slew Rate Field. */
+
+#define	SPEED_SHIFT		12
+#define	SPEED_MASK		0x3
+#define	SPEED_LOW		0	/* 50 MHz */
+#define	SPEED_MEDIUM		0x1	/* 100 MHz */
+#define	SPEED_HIGH		0x3	/* 200 MHz */
+
+#define	PUS_SHIFT		4	/* Pull Up / Down Config Field Shift */
+#define	PUS_MASK		0x3
+#define	PUS_100_KOHM_PULL_DOWN	0
+#define	PUS_47_KOHM_PULL_UP	0x1
+#define	PUS_100_KOHM_PULL_UP	0x2
+#define	PUS_22_KOHM_PULL_UP	0x3
+
+#define	DSE_SHIFT		6	/* Drive Strength Field Shift */
+#define	DSE_MASK		0x7
+#define	DSE_DISABLED		0	/* Output driver disabled */
+#define	DSE_150_OHM		0x1
+#define	DSE_75_OHM		0x2
+#define	DSE_50_OHM		0x3
+#define	DSE_37_OHM		0x4
+#define	DSE_30_OHM		0x5
+#define	DSE_25_OHM		0x6
+#define	DSE_20_OHM		0x7
 
 #define	MAX_MUX_LEN		1024
 
@@ -101,19 +122,6 @@ iomuxc_probe(device_t dev)
 }
 
 static int
-configure_pad(struct iomuxc_softc *sc, int pad, int mux_mode)
-{
-	int reg;
-
-	reg = READ4(sc, pad);
-	reg &= ~(MUX_MODE_MASK << MUX_MODE_SHIFT);
-	reg |= (mux_mode << MUX_MODE_SHIFT);
-	WRITE4(sc, pad, reg);
-
-	return (0);
-}
-
-static int
 pinmux_set(struct iomuxc_softc *sc)
 {
 	phandle_t child, parent, root;
@@ -121,7 +129,7 @@ pinmux_set(struct iomuxc_softc *sc)
 	int len;
 	int values;
 	int pin;
-	int mux_mode;
+	int pin_cfg;
 	int i;
 
 	root = OF_finddevice("/");
@@ -146,12 +154,12 @@ pinmux_set(struct iomuxc_softc *sc)
 			values = len / (sizeof(uint32_t));
 			for (i = 0; i < values; i += 2) {
 				pin = fdt32_to_cpu(iomux_config[i]);
-				mux_mode = fdt32_to_cpu(iomux_config[i+1]);
+				pin_cfg = fdt32_to_cpu(iomux_config[i+1]);
 #if 0
-				device_printf(sc->dev, "Set pin %d to ALT%d\n",
-				    pin, mux_mode);
+				device_printf(sc->dev, "Set pin %d to 0x%08x\n",
+				    pin, pin_cfg);
 #endif
-				configure_pad(sc, IOMUXC(pin), mux_mode);
+				WRITE4(sc, IOMUXC(pin), pin_cfg);
 			}
 		}
 
@@ -169,7 +177,6 @@ static int
 iomuxc_attach(device_t dev)
 {
 	struct iomuxc_softc *sc;
-	int reg;
 
 	sc = device_get_softc(dev);
 	sc->dev = dev;
@@ -183,11 +190,6 @@ iomuxc_attach(device_t dev)
 	sc->bst = rman_get_bustag(sc->tmr_res[0]);
 	sc->bsh = rman_get_bushandle(sc->tmr_res[0]);
 
-	/* USB */
-	configure_pad(sc, IOMUXC_PTA17, MUX_MODE_VBUS_EN_OTG);
-	reg = (PKE | PUE | PUS_22_KOHM_PULL_UP | DSE_25_OHM | OBE);
-	WRITE4(sc, IOMUXC_PTA7, reg);
-
 	pinmux_set(sc);
 
 	return (0);
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 0b53906..f38f9c1 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -104,6 +104,12 @@ struct cpu_functions {
 	 *
 	 * There are some rules that must be followed:
 	 *
+	 *	ID-cache Invalidate All:
+	 *		Unlike other functions, this one must never write back.
+	 *		It is used to intialize the MMU when it is in an unknown
+	 *		state (such as when it may have lines tagged as valid
+	 *		that belong to a previous set of mappings).
+	 *                                          
 	 *	I-cache Synch (all or range):
 	 *		The goal is to synchronize the instruction stream,
 	 *		so you may beed to write-back dirty D-cache blocks
@@ -138,6 +144,7 @@ struct cpu_functions {
 	void	(*cf_dcache_inv_range)	(vm_offset_t, vm_size_t);
 	void	(*cf_dcache_wb_range)	(vm_offset_t, vm_size_t);
 
+	void	(*cf_idcache_inv_all)	(void);
 	void	(*cf_idcache_wbinv_all)	(void);
 	void	(*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
 	void	(*cf_l2cache_wbinv_all) (void);
@@ -238,6 +245,7 @@ void tlb_broadcast(int);
 #define	cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
 #define	cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
 
+#define	cpu_idcache_inv_all()	cpufuncs.cf_idcache_inv_all()
 #define	cpu_idcache_wbinv_all()	cpufuncs.cf_idcache_wbinv_all()
 #define	cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
 #define cpu_l2cache_wbinv_all()	cpufuncs.cf_l2cache_wbinv_all()
@@ -495,6 +503,7 @@ void	armv6_dcache_wbinv_range	(vm_offset_t, vm_size_t);
 void	armv6_dcache_inv_range		(vm_offset_t, vm_size_t);
 void	armv6_dcache_wb_range		(vm_offset_t, vm_size_t);
 
+void	armv6_idcache_inv_all		(void);
 void	armv6_idcache_wbinv_all		(void);
 void	armv6_idcache_wbinv_range	(vm_offset_t, vm_size_t);
 
@@ -503,6 +512,7 @@ void	armv7_tlb_flushID		(void);
 void	armv7_tlb_flushID_SE		(u_int);
 void	armv7_icache_sync_range		(vm_offset_t, vm_size_t);
 void	armv7_idcache_wbinv_range	(vm_offset_t, vm_size_t);
+void	armv7_idcache_inv_all		(void);
 void	armv7_dcache_wbinv_all		(void);
 void	armv7_idcache_wbinv_all		(void);
 void	armv7_dcache_wbinv_range	(vm_offset_t, vm_size_t);
@@ -587,6 +597,7 @@ void	armv4_tlb_flushD	(void);
 void	armv4_tlb_flushD_SE	(u_int va);
 
 void	armv4_drain_writebuf	(void);
+void	armv4_idcache_inv_all	(void);
 #endif
 
 #if defined(CPU_IXP12X0)
diff --git a/sys/arm/include/smp.h b/sys/arm/include/smp.h
index 883c5b9..179882d 100644
--- a/sys/arm/include/smp.h
+++ b/sys/arm/include/smp.h
@@ -15,6 +15,7 @@
 #define IPI_TLB		7
 
 void	init_secondary(int cpu);
+void	mpentry(void);
 
 void	ipi_all_but_self(u_int ipi);
 void	ipi_cpu(int cpu, u_int ipi);
diff --git a/sys/arm/mv/armadaxp/armadaxp_mp.c b/sys/arm/mv/armadaxp/armadaxp_mp.c
index 1af598b..004f8db 100644
--- a/sys/arm/mv/armadaxp/armadaxp_mp.c
+++ b/sys/arm/mv/armadaxp/armadaxp_mp.c
@@ -96,7 +96,6 @@ platform_mp_init_secondary(void)
 {
 }
 
-void mpentry(void);
 void mptramp(void);
 
 
diff --git a/sys/arm/samsung/exynos/exynos5_mp.c b/sys/arm/samsung/exynos/exynos5_mp.c
index e99b61e..7b97a6e 100644
--- a/sys/arm/samsung/exynos/exynos5_mp.c
+++ b/sys/arm/samsung/exynos/exynos5_mp.c
@@ -39,9 +39,6 @@ __FBSDID("$FreeBSD$");
 
 #define	EXYNOS_SYSRAM			0x02020000
 
-void mpentry(void);
-void mptramp(void);
-
 void
 platform_mp_init_secondary(void)
 {
diff --git a/sys/arm/ti/omap4/omap4_mp.c b/sys/arm/ti/omap4/omap4_mp.c
index c42cae5..178db20 100644
--- a/sys/arm/ti/omap4/omap4_mp.c
+++ b/sys/arm/ti/omap4/omap4_mp.c
@@ -38,9 +38,6 @@ __FBSDID("$FreeBSD$");
 #include <arm/ti/ti_smc.h>
 #include <arm/ti/omap4/omap4_smc.h>
 
-void mpentry(void);
-void mptramp(void);
-
 void
 platform_mp_init_secondary(void)
 {
diff --git a/sys/boot/fdt/dts/vybrid-colibri-vf50.dts b/sys/boot/fdt/dts/vybrid-colibri-vf50.dts
index 618a05c..6d4d934 100644
--- a/sys/boot/fdt/dts/vybrid-colibri-vf50.dts
+++ b/sys/boot/fdt/dts/vybrid-colibri-vf50.dts
@@ -45,17 +45,26 @@
 
 		fec1: ethernet@400D1000 {
 			status = "okay";
-			iomux_config = < 54 0x1 55 0x1
-					 56 0x1 57 0x1
-					 58 0x1 59 0x1
-					 60 0x1 61 0x1
-					 62 0x1  0 0x1 >;
+			iomux_config = < 54 0x103192
+					 55 0x103193
+					 56 0x103191
+					 57 0x103191
+					 58 0x103191
+					 59 0x103191
+					 60 0x103192
+					 61 0x103192
+					 62 0x103192
+					  0 0x103191 >;
 		};
 
 		sai3: sai@40032000 {
 			status = "okay";
 		};
 
+		i2c0: i2c@40066000 {
+			status = "okay";
+		};
+
 		adc0: adc@4003B000 {
 			status = "okay";
 		};
diff --git a/sys/boot/fdt/dts/vybrid-cosmic.dts b/sys/boot/fdt/dts/vybrid-cosmic.dts
index b4e9805..c98c093 100644
--- a/sys/boot/fdt/dts/vybrid-cosmic.dts
+++ b/sys/boot/fdt/dts/vybrid-cosmic.dts
@@ -45,11 +45,16 @@
 
 		fec1: ethernet@400D1000 {
 			status = "okay";
-			iomux_config = < 54 0x1 55 0x1
-					 56 0x1 57 0x1
-					 58 0x1 59 0x1
-					 60 0x1 61 0x1
-					 62 0x1  0 0x2 >;
+			iomux_config = < 54 0x103192
+					 55 0x103193
+					 56 0x103191
+					 57 0x103191
+					 58 0x103191
+					 59 0x103191
+					 60 0x103192
+					 61 0x103192
+					 62 0x103192
+					  0 0x203191 >;
 		};
 
 		esai: esai@40062000 {
diff --git a/sys/boot/fdt/dts/vybrid-quartz.dts b/sys/boot/fdt/dts/vybrid-quartz.dts
new file mode 100644
index 0000000..d978796
--- /dev/null
+++ b/sys/boot/fdt/dts/vybrid-quartz.dts
@@ -0,0 +1,70 @@
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/include/ "vybrid.dtsi"
+
+/ {
+	model = "Device Solutions Quartz Module";
+
+	memory {
+		device_type = "memory";
+		reg = < 0x80000000 0x10000000 >;	/* 256MB RAM */
+	};
+
+	SOC: vybrid {
+		serial0: serial@40027000 {
+			status = "okay";
+		};
+
+		fec1: ethernet@400D1000 {
+			status = "okay";
+			iomux_config = < 54 0x103192
+					 55 0x103193
+					 56 0x103191
+					 57 0x103191
+					 58 0x103191
+					 59 0x103191
+					 60 0x103192
+					 61 0x103192
+					 62 0x103192
+					  0 0x203191 >;
+		};
+
+		edma1: edma@40098000 {
+			status = "okay";
+		};
+	};
+
+	chosen {
+		bootargs = "-v";
+		stdin = "serial0";
+		stdout = "serial0";
+	};
+};
diff --git a/sys/boot/fdt/dts/vybrid.dtsi b/sys/boot/fdt/dts/vybrid.dtsi
index 5c815de..154c1ab 100644
--- a/sys/boot/fdt/dts/vybrid.dtsi
+++ b/sys/boot/fdt/dts/vybrid.dtsi
@@ -205,9 +205,12 @@
 			clock-frequency = <50000000>;
 			status = "disabled";
 			clock_names = "esdhc1";
-			iomux_config = < 14 0x5 15 0x5
-					 16 0x5 17 0x5
-					 18 0x5 19 0x5 >;
+			iomux_config = < 14 0x500060
+					 15 0x500060
+					 16 0x500060
+					 17 0x500060
+					 18 0x500060
+					 19 0x500060 >;
 		};
 
 		serial0: serial@40027000 {
@@ -237,6 +240,8 @@
 			      < 0x40050800 0x100 >; /* phy */
 			interrupts = < 107 >;
 			interrupt-parent = <&GIC>;
+			iomux_config = < 134 0x0001be
+					   7 0x200060 >;
 		};
 
 		usb@400b4000 {
@@ -246,6 +251,8 @@
 			      < 0x40050C00 0x100 >; /* phy */
 			interrupts = < 108 >;
 			interrupt-parent = <&GIC>;
+			iomux_config = < 134 0x0001be
+					   7 0x200060 >;
 		};
 
 		fec0: ethernet@400D0000 {
@@ -257,11 +264,15 @@
 			phy-disable-preamble;
 			status = "disabled";
 			clock_names = "enet";
-			iomux_config = < 45 0x1 46 0x1
-					 47 0x1 48 0x1
-					 49 0x1 50 0x1
-					 51 0x1 52 0x1
-					 53 0x1 >;
+			iomux_config = < 45 0x100061
+					 46 0x100061
+					 47 0x100061
+					 48 0x100060
+					 49 0x100060
+					 50 0x100060
+					 51 0x100060
+					 52 0x100060
+					 53 0x100060 >;
 		};
 
 		fec1: ethernet@400D1000 {
@@ -273,11 +284,15 @@
 			phy-disable-preamble;
 			status = "disabled";
 			clock_names = "enet";
-			iomux_config = < 54 0x1 55 0x1
-					 56 0x1 57 0x1
-					 58 0x1 59 0x1
-					 60 0x1 61 0x1
-					 62 0x1 >;
+			iomux_config = < 54 0x103192
+					 55 0x103193
+					 56 0x103191
+					 57 0x103191
+					 58 0x103191
+					 59 0x103191
+					 60 0x103192
+					 61 0x103192
+					 62 0x103192 >;
 		};
 
 		sai0: sai@4002F000 {
@@ -315,10 +330,10 @@
 			edma-src-transmit = < 9 >;
 			edma-mux-group = < 1 >;
 			clock_names = "sai3", "cko1";
-			iomux_config = < 16 0x2
-					 19 0x2
-					 21 0x2
-					 40 0x4 >; /* CKO1 */
+			iomux_config = < 16 0x200060
+					 19 0x200060
+					 21 0x200060
+					 40 0x400061 >; /* CKO1 */
 		};
 
 		esai: esai@40062000 {
@@ -328,11 +343,16 @@
 			interrupt-parent = <&GIC>;
 			status = "disabled";
 			clock_names = "esai";
-			iomux_config = < 45 0x4 46 0x4
-					 47 0x4 48 0x4
-					 49 0x4 50 0x4
-					 51 0x4 52 0x4
-					 78 0x3 40 0x4>;
+			iomux_config = < 45 0x400061
+					 46 0x400061
+					 47 0x400061
+					 48 0x400060
+					 49 0x400060
+					 50 0x400060
+					 51 0x400060
+					 52 0x400060
+					 78 0x3038df
+					 40 0x400061 >;
 		};
 
 		spi0: spi@4002C000 {
@@ -341,9 +361,11 @@
 			interrupts = < 99 >;
 			interrupt-parent = <&GIC>;
 			status = "disabled";
-			iomux_config = < 40 0x1 41 0x1
-					 42 0x1 43 0x1
-					 44 0x1 >;
+			iomux_config = < 40 0x100061
+					 41 0x100061
+					 42 0x100060
+					 43 0x100060
+					 44 0x100061 >;
 		};
 
 		spi1: spi@4002D000 {
@@ -370,6 +392,43 @@
 			status = "disabled";
 		};
 
+		i2c0: i2c@40066000 {
+			compatible = "fsl,mvf600-i2c";
+			reg = <0x40066000 0x1000>;
+			interrupts = < 103 >;
+			interrupt-parent = <&GIC>;
+			status = "disabled";
+			clock_names = "ipg";
+			iomux_config = <  36 0x2034d3
+					  37 0x2034d3
+					 207 0x1
+					 208 0x1 >;
+		};
+
+		i2c1: i2c@40067000 {
+			compatible = "fsl,mvf600-i2c";
+			reg = <0x40067000 0x1000>;
+			interrupts = < 104 >;
+			interrupt-parent = <&GIC>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@400E6000 {
+			compatible = "fsl,mvf600-i2c";
+			reg = <0x400E6000 0x1000>;
+			interrupts = < 105 >;
+			interrupt-parent = <&GIC>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@400E7000 {
+			compatible = "fsl,mvf600-i2c";
+			reg = <0x400E7000 0x1000>;
+			interrupts = < 106 >;
+			interrupt-parent = <&GIC>;
+			status = "disabled";
+		};
+
 		adc0: adc@4003B000 {
 			compatible = "fsl,mvf600-adc";
 			reg = <0x4003B000 0x1000>;
@@ -399,21 +458,35 @@
 			interrupt-parent = <&GIC>;
 			status = "disabled";
 			clock_names = "dcu0";
-			iomux_config = < 105 0x1 106 0x1
-					 107 0x1 108 0x1
-					 109 0x1 110 0x1
-					 111 0x1 112 0x1
-					 113 0x1 114 0x1
-					 115 0x1 116 0x1
-					 117 0x1 118 0x1
-					 119 0x1 120 0x1
-					 121 0x1 122 0x1
-					 123 0x1 124 0x1
-					 125 0x1 126 0x1
-					 127 0x1 128 0x1
-					 129 0x1 130 0x1
-					 131 0x1 132 0x1
-					 133 0x1 >;
+			iomux_config = < 105 0x100044
+					 106 0x100044
+					 107 0x100060
+					 108 0x100060
+					 109 0x100060
+					 110 0x100060
+					 111 0x100060
+					 112 0x100060
+					 113 0x100060
+					 114 0x100060
+					 115 0x100060
+					 116 0x100060
+					 117 0x100060
+					 118 0x100060
+					 119 0x100060
+					 120 0x100060
+					 121 0x100060
+					 122 0x100060
+					 123 0x100060
+					 124 0x100060
+					 125 0x100060
+					 126 0x100060
+					 127 0x100060
+					 128 0x100060
+					 129 0x100060
+					 130 0x100060
+					 131 0x100060
+					 132 0x100060
+					 133 0x100060 >;
 		};
 	};
 };