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author | peter <peter@FreeBSD.org> | 1999-04-18 14:37:47 +0000 |
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committer | peter <peter@FreeBSD.org> | 1999-04-18 14:37:47 +0000 |
commit | d7c3fd16a80728beeecbc7623a5d7b8e5cd612bd (patch) | |
tree | 4434b1a9bb341d7e4d28ea16c571f4a3756c1a9c | |
parent | 8095c1f1365c32f2afa131b4749a6c806c79a933 (diff) | |
download | FreeBSD-src-d7c3fd16a80728beeecbc7623a5d7b8e5cd612bd.zip FreeBSD-src-d7c3fd16a80728beeecbc7623a5d7b8e5cd612bd.tar.gz |
Merge missing changes from i386/isa/sioreg.h (PC98 related)
-rw-r--r-- | sys/dev/sio/sioreg.h | 15 | ||||
-rw-r--r-- | sys/isa/sioreg.h | 15 |
2 files changed, 28 insertions, 2 deletions
diff --git a/sys/dev/sio/sioreg.h b/sys/dev/sio/sioreg.h index 85be4dc..cb7aa5f 100644 --- a/sys/dev/sio/sioreg.h +++ b/sys/dev/sio/sioreg.h @@ -31,12 +31,15 @@ * SUCH DAMAGE. * * from: @(#)comreg.h 7.2 (Berkeley) 5/9/91 - * $Id: sioreg.h,v 1.1 1998/09/24 02:07:28 jkh Exp $ + * $Id: sioreg.h,v 1.11 1998/09/26 14:00:29 peter Exp $ */ /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ #define COMBRD(x) (1843200 / (16*(x))) +#ifdef PC98 +#define COMBRD_RSA(x) (14745600 / (16*(x))) +#endif /* interrupt enable register */ #define IER_ERXRDY 0x1 @@ -106,6 +109,16 @@ #define MSR_DDSR 0x02 #define MSR_DCTS 0x01 +#ifdef PC98 +/* Hardware extension mode register for RSB-2000/3000. */ +#define EMR_EXBUFF 0x04 +#define EMR_CTSFLW 0x08 +#define EMR_DSRFLW 0x10 +#define EMR_RTSFLW 0x20 +#define EMR_DTRFLW 0x40 +#define EMR_EFMODE 0x80 +#endif + /* speed to initialize to during chip tests */ #define SIO_TEST_SPEED 9600 diff --git a/sys/isa/sioreg.h b/sys/isa/sioreg.h index 85be4dc..cb7aa5f 100644 --- a/sys/isa/sioreg.h +++ b/sys/isa/sioreg.h @@ -31,12 +31,15 @@ * SUCH DAMAGE. * * from: @(#)comreg.h 7.2 (Berkeley) 5/9/91 - * $Id: sioreg.h,v 1.1 1998/09/24 02:07:28 jkh Exp $ + * $Id: sioreg.h,v 1.11 1998/09/26 14:00:29 peter Exp $ */ /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ #define COMBRD(x) (1843200 / (16*(x))) +#ifdef PC98 +#define COMBRD_RSA(x) (14745600 / (16*(x))) +#endif /* interrupt enable register */ #define IER_ERXRDY 0x1 @@ -106,6 +109,16 @@ #define MSR_DDSR 0x02 #define MSR_DCTS 0x01 +#ifdef PC98 +/* Hardware extension mode register for RSB-2000/3000. */ +#define EMR_EXBUFF 0x04 +#define EMR_CTSFLW 0x08 +#define EMR_DSRFLW 0x10 +#define EMR_RTSFLW 0x20 +#define EMR_DTRFLW 0x40 +#define EMR_EFMODE 0x80 +#endif + /* speed to initialize to during chip tests */ #define SIO_TEST_SPEED 9600 |