diff options
| author | scottl <scottl@FreeBSD.org> | 2001-02-01 20:29:16 +0000 |
|---|---|---|
| committer | scottl <scottl@FreeBSD.org> | 2001-02-01 20:29:16 +0000 |
| commit | bc10e2d4b6b1b150785d517ffc32e93982cff8cd (patch) | |
| tree | 7f21d23de8af630694ac2a6269fc699d9f785e24 | |
| parent | 8c9e49b4459018cfc038bf13546bb5d34b4b9b18 (diff) | |
| download | FreeBSD-src-bc10e2d4b6b1b150785d517ffc32e93982cff8cd.zip FreeBSD-src-bc10e2d4b6b1b150785d517ffc32e93982cff8cd.tar.gz | |
Driver for the ESS Maestro3 and Allegro sound chips. Note that due to the
amount of GPL'd firmware in the driver, it will only be built as a module.
Approved by: cg
| -rw-r--r-- | sys/dev/sound/driver.c | 1 | ||||
| -rw-r--r-- | sys/dev/sound/pci/maestro3.c | 1503 | ||||
| -rw-r--r-- | sys/gnu/dev/sound/pci/maestro3_dsp.h | 214 | ||||
| -rw-r--r-- | sys/gnu/dev/sound/pci/maestro3_reg.h | 692 | ||||
| -rw-r--r-- | sys/modules/sound/driver/Makefile | 2 | ||||
| -rw-r--r-- | sys/modules/sound/driver/maestro3/Makefile | 10 |
6 files changed, 2421 insertions, 1 deletions
diff --git a/sys/dev/sound/driver.c b/sys/dev/sound/driver.c index 70f50f5..654f158 100644 --- a/sys/dev/sound/driver.c +++ b/sys/dev/sound/driver.c @@ -62,6 +62,7 @@ MODULE_DEPEND(snd_driver, snd_es1888, 1, 1, 1); MODULE_DEPEND(snd_driver, snd_ess, 1, 1, 1); MODULE_DEPEND(snd_driver, snd_gusc, 1, 1, 1); MODULE_DEPEND(snd_driver, snd_maestro, 1, 1, 1); +MODULE_DEPEND(snd_driver, snd_maestro3, 1, 1, 1); MODULE_DEPEND(snd_driver, snd_mss, 1, 1, 1); MODULE_DEPEND(snd_driver, snd_neomagic, 1, 1, 1); MODULE_DEPEND(snd_driver, snd_sb8, 1, 1, 1); diff --git a/sys/dev/sound/pci/maestro3.c b/sys/dev/sound/pci/maestro3.c new file mode 100644 index 0000000..a5bd4c0 --- /dev/null +++ b/sys/dev/sound/pci/maestro3.c @@ -0,0 +1,1503 @@ +/*- + * Copyright (c) 2001 Scott Long <scottl@freebsd.org> + * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Maestro-3/Allegro FreeBSD pcm sound driver + * + * executive status summary: + * (+) /dev/dsp multiple concurrent play channels. + * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit). + * (+) /dev/mixer sets left/right volumes. + * (+) /dev/dsp recording works. Tested successfully with the cdrom channel + * (+) apm suspend/resume works, and works properly!. + * (-) hardware volme controls don't work =-( + * (-) setblocksize() does nothing. + * + * The real credit goes to: + * + * Zach Brown for his Linux driver core and helpful technical comments. + * <zab@zabbo.net>, http://www.zabbo.net/maestro3 + * + * Cameron Grant created the pcm framework used here nearly verbatim. + * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c + * + * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference. + * <taku@cent.saitama-u.ac.jp> + * + * ESS docs explained a few magic registers and numbers. + * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz + */ + +#include <dev/sound/pcm/sound.h> +#include <dev/sound/pcm/ac97.h> + +#include <pci/pcireg.h> +#include <pci/pcivar.h> + +#include <gnu/dev/sound/pci/maestro3_reg.h> +#include <gnu/dev/sound/pci/maestro3_dsp.h> + +/* -------------------------------------------------------------------- */ + +enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1}; +#ifndef M3_DEBUG_LEVEL +#define M3_DEBUG_LEVEL NONE +#endif +#define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}} + +/* -------------------------------------------------------------------- */ +enum { + ESS_ALLEGRO_1, + ESS_MAESTRO3 +}; + +static struct m3_card_type { + u_int32_t pci_id; int which; int delay1; int delay2; char *name; +} m3_card_types[] = { + { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" }, + { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, + { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" }, + { 0, 0, 0, 0, NULL } +}; + +#define M3_BUFSIZE 4096 +#define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */ +#define M3_RCHANS 1 + +struct sc_info; + +struct sc_pchinfo { + u_int32_t spd; + u_int32_t fmt; + snd_dbuf *buffer; + pcm_channel *channel; + struct sc_info *parent; + u_int32_t bufsize; + u_int32_t dac_data; + u_int32_t dac_idx; + u_int32_t active; +}; + +struct sc_rchinfo { + u_int32_t spd; + u_int32_t fmt; + snd_dbuf *buffer; + pcm_channel *channel; + struct sc_info *parent; + u_int32_t bufsize; + u_int32_t adc_data; + u_int32_t adc_idx; + u_int32_t active; +}; + +struct sc_info { + device_t dev; + u_int32_t type; + int which; + int delay1; + int delay2; + + bus_space_tag_t st; + bus_space_handle_t sh; + bus_dma_tag_t parent_dmat; + + struct resource *reg; + struct resource *irq; + int regtype; + int regid; + int irqid; + void *ih; + + struct sc_pchinfo pch[M3_PCHANS]; + struct sc_rchinfo rch[M3_RCHANS]; + int pch_cnt; + int rch_cnt; + int pch_active_cnt; + u_int16_t *savemem; +}; + +/* -------------------------------------------------------------------- */ + +/* play channel interface */ +static void *m3_pchan_init(kobj_t, void *, snd_dbuf *, pcm_channel *, int); +static int m3_pchan_free(kobj_t, void *); +static int m3_pchan_setformat(kobj_t, void *, u_int32_t); +static int m3_pchan_setspeed(kobj_t, void *, u_int32_t); +static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t); +static int m3_pchan_trigger(kobj_t, void *, int); +static int m3_pchan_getptr(kobj_t, void *); +static pcmchan_caps *m3_pchan_getcaps(kobj_t, void *); + +/* record channel interface */ +static void *m3_rchan_init(kobj_t, void *, snd_dbuf *, pcm_channel *, int); +static int m3_rchan_free(kobj_t, void *); +static int m3_rchan_setformat(kobj_t, void *, u_int32_t); +static int m3_rchan_setspeed(kobj_t, void *, u_int32_t); +static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t); +static int m3_rchan_trigger(kobj_t, void *, int); +static int m3_rchan_getptr(kobj_t, void *); +static pcmchan_caps *m3_rchan_getcaps(kobj_t, void *); + +/* talk to the codec - called from ac97.c */ +static int m3_initcd(kobj_t, void *); +static int m3_rdcd(kobj_t, void *, int); +static int m3_wrcd(kobj_t, void *, int, u_int32_t); + +/* stuff */ +static void m3_intr(void *); +static int m3_power(struct sc_info *, int); +static int m3_init(struct sc_info *); +static int m3_uninit(struct sc_info *); +static u_int8_t m3_assp_halt(struct sc_info *); +static void m3_config(struct sc_info *); +static void m3_amp_enable(struct sc_info *); +static void m3_enable_ints(struct sc_info *); +static void m3_codec_reset(struct sc_info *); + +/* -------------------------------------------------------------------- */ +/* Codec descriptor */ +static kobj_method_t m3_codec_methods[] = { + KOBJMETHOD(ac97_init, m3_initcd), + KOBJMETHOD(ac97_read, m3_rdcd), + KOBJMETHOD(ac97_write, m3_wrcd), + { 0, 0 } +}; +AC97_DECLARE(m3_codec); + +/* -------------------------------------------------------------------- */ +/* channel descriptors */ + +static u_int32_t m3_playfmt[] = { + AFMT_U8, + AFMT_STEREO | AFMT_U8, + AFMT_S16_LE, + AFMT_STEREO | AFMT_S16_LE, + 0 +}; +static pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0}; + +static kobj_method_t m3_pch_methods[] = { + KOBJMETHOD(channel_init, m3_pchan_init), + KOBJMETHOD(channel_setformat, m3_pchan_setformat), + KOBJMETHOD(channel_setspeed, m3_pchan_setspeed), + KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize), + KOBJMETHOD(channel_trigger, m3_pchan_trigger), + KOBJMETHOD(channel_getptr, m3_pchan_getptr), + KOBJMETHOD(channel_getcaps, m3_pchan_getcaps), + KOBJMETHOD(channel_free, m3_pchan_free), + { 0, 0 } +}; +CHANNEL_DECLARE(m3_pch); + +static u_int32_t m3_recfmt[] = { + AFMT_U8, + AFMT_STEREO | AFMT_U8, + AFMT_S16_LE, + AFMT_STEREO | AFMT_S16_LE, + 0 +}; +static pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0}; + +static kobj_method_t m3_rch_methods[] = { + KOBJMETHOD(channel_init, m3_rchan_init), + KOBJMETHOD(channel_setformat, m3_rchan_setformat), + KOBJMETHOD(channel_setspeed, m3_rchan_setspeed), + KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize), + KOBJMETHOD(channel_trigger, m3_rchan_trigger), + KOBJMETHOD(channel_getptr, m3_rchan_getptr), + KOBJMETHOD(channel_getcaps, m3_rchan_getcaps), + KOBJMETHOD(channel_free, m3_rchan_free), + { 0, 0 } +}; +CHANNEL_DECLARE(m3_rch); + +/* -------------------------------------------------------------------- */ +/* some i/o convenience functions */ + +#define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno) +#define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno) +#define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno) +#define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data) +#define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data) +#define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data) +#define m3_rd_assp_code(sc, index) \ + m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index) +#define m3_wr_assp_code(sc, index, data) \ + m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data) +#define m3_rd_assp_data(sc, index) \ + m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index) +#define m3_wr_assp_data(sc, index, data) \ + m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data) + +static __inline u_int16_t +m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index) +{ + m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); + m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); + return m3_rd_2(sc, DSP_PORT_MEMORY_DATA); +} + +static __inline void +m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index, + u_int16_t data) +{ + m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK); + m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index); + m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data); +} + +static __inline int +m3_wait(struct sc_info *sc) +{ + int i; + + for (i=0 ; i<20 ; i++) { + if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) { + return 0; + } + DELAY(2); + } + return -1; +} + +/* -------------------------------------------------------------------- */ +/* ac97 codec */ + +static int +m3_initcd(kobj_t kobj, void *devinfo) +{ + struct sc_info *sc = (struct sc_info *)devinfo; + u_int32_t data; + + M3_DEBUG(CALL, ("m3_initcd\n")); + + /* init ac-link */ + + data = m3_rd_1(sc, CODEC_COMMAND); + return ((data & 0x1) ? 0 : 1); +} + +static int +m3_rdcd(kobj_t kobj, void *devinfo, int regno) +{ + struct sc_info *sc = (struct sc_info *)devinfo; + u_int32_t data; + + if (m3_wait(sc)) { + device_printf(sc->dev, "m3_rdcd timed out.\n"); + return -1; + } + m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80); + DELAY(21); /* ac97 cycle = 20.8 usec */ + if (m3_wait(sc)) { + device_printf(sc->dev, "m3_rdcd timed out.\n"); + return -1; + } + data = m3_rd_2(sc, CODEC_DATA); + return data; +} + +static int +m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data) +{ + struct sc_info *sc = (struct sc_info *)devinfo; + if (m3_wait(sc)) { + device_printf(sc->dev, "m3_wrcd timed out.\n"); + return -1;; + } + m3_wr_2(sc, CODEC_DATA, data); + m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f); + return 0; +} + +/* -------------------------------------------------------------------- */ +/* play channel interface */ + +#define LO(x) (((x) & 0x0000ffff) ) +#define HI(x) (((x) & 0xffff0000) >> 16) + +static void * +m3_pchan_init(kobj_t kobj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir) +{ + struct sc_info *sc = devinfo; + struct sc_pchinfo *ch; + u_int32_t bus_addr, i; + + int idx = sc->pch_cnt; /* dac instance number, no active reuse! */ + int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + + (MINISRC_IN_BUFFER_SIZE & ~1) + + (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; + int dac_data = 0x1100 + (data_bytes * idx); + + int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); + int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); + int dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2); + int dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1; + + M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx)); + + if (dir != PCMDIR_PLAY) { + device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n"); + return NULL; + } + ch = &sc->pch[idx]; + + ch->dac_idx = idx; + ch->dac_data = dac_data; + if (ch->dac_data + data_bytes/2 >= 0x1c00) { + device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n"); + return NULL; + } + + ch->buffer = b; + ch->parent = sc; + ch->channel = c; + ch->fmt = AFMT_U8; + ch->spd = DSP_DEFAULT_SPEED; + if (sndbuf_alloc(ch->buffer, sc->parent_dmat, M3_BUFSIZE) == -1) { + device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n"); + return NULL; + } + ch->bufsize = sndbuf_getsize(ch->buffer); + + /* host dma buffer pointers */ + bus_addr = vtophys(sndbuf_getbuf(ch->buffer)); + if (bus_addr & 3) { + device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n"); + bus_addr = (bus_addr + 4) & ~3; + } + m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); + m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); + m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L, + LO(bus_addr + ch->bufsize)); + m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H, + HI(bus_addr + ch->bufsize)); + m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL, + LO(bus_addr)); + m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH, + HI(bus_addr)); + + /* dsp buffers */ + m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); + m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1, + dsp_in_buf + dsp_in_size/2); + m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf); + m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf); + m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); + m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1, + dsp_out_buf + dsp_out_size/2); + m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); + m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); + + /* some per client initializers */ + m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12, + ch->dac_data + 40 + 8); + m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19, + 0x400 + MINISRC_COEF_LOC); + /* enable or disable low pass filter? (0xff if rate> 45000) */ + m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0); + /* tell it which way dma is going? */ + m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL, + DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + + DMAC_BLOCKF_SELECTOR); + + /* set an armload of static initializers */ + for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) { + m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val); + } + + /* put us in the packed task lists */ + m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + + (sc->pch_cnt + sc->rch_cnt), + ch->dac_data >> DP_SHIFT_COUNT); + m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), + ch->dac_data >> DP_SHIFT_COUNT); + m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt, + ch->dac_data >> DP_SHIFT_COUNT); + + m3_pchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */ + m3_pchan_trigger(NULL, ch, PCMTRIG_STOP); /* silence noise on load */ + + sc->pch_cnt++; + return ch; +} + +static int +m3_pchan_free(kobj_t kobj, void *chdata) +{ + struct sc_pchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + + M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx)); + + /* + * should remove this exact instance from the packed lists, but all + * are released at once (and in a stopped state) so this is ok. + */ + m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + + (sc->pch_cnt - 1) + sc->rch_cnt, 0); + m3_wr_assp_data(sc, KDATA_DMA_XFER0 + + (sc->pch_cnt - 1) + sc->rch_cnt, 0); + m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0); + + sc->pch_cnt--; + return 0; +} + +static int +m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) +{ + struct sc_pchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t data; + + M3_DEBUG(CHANGE, + ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n", + ch->dac_idx, format, + format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", + format & AFMT_STEREO ? "STEREO":"MONO")); + + /* mono word */ + data = (format & AFMT_STEREO) ? 0 : 1; + m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data); + + /* 8bit word */ + data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; + m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data); + + ch->fmt = format; + return format; +} + +static int +m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) +{ + struct sc_pchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t freq; + + M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n", + ch->dac_idx, speed)); + + if ((freq = ((speed << 15) + 24000) / 48000) != 0) { + freq--; + } + + m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq); + + ch->spd = speed; + return speed; /* return closest possible speed */ +} + +static int +m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) +{ + struct sc_pchinfo *ch = chdata; + + M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n", + ch->dac_idx, blocksize)); + + return blocksize; +} + +static int +m3_pchan_trigger(kobj_t kobj, void *chdata, int go) +{ + struct sc_pchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t data; + + M3_DEBUG(go == PCMTRIG_START ? CHANGE : + go == PCMTRIG_STOP ? CHANGE : + go == PCMTRIG_ABORT ? CHANGE : + CALL, + ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go, + go == PCMTRIG_START ? "PCMTRIG_START" : + go == PCMTRIG_STOP ? "PCMTRIG_STOP" : + go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); + + switch(go) { + case PCMTRIG_START: + if (ch->active) { + return 0; + } + ch->active = 1; + sc->pch_active_cnt++; + + /*[[inc_timer_users]]*/ + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); + data = m3_rd_2(sc, HOST_INT_CTRL); + m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); + + m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1); + m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, + sc->pch_active_cnt); + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + if (ch->active == 0) { + return 0; + } + ch->active = 0; + sc->pch_active_cnt--; + + /* XXX should the channel be drained? */ + /*[[dec_timer_users]]*/ + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); + data = m3_rd_2(sc, HOST_INT_CTRL); + m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); + + m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0); + m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, + sc->pch_active_cnt); + break; + + case PCMTRIG_EMLDMAWR: + /* got play irq, transfer next buffer - ignore if using dma */ + case PCMTRIG_EMLDMARD: + /* got rec irq, transfer next buffer - ignore if using dma */ + default: + break; + } + return 0; +} + +static int +m3_pchan_getptr(kobj_t kobj, void *chdata) +{ + struct sc_pchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t hi, lo, bus_crnt; + u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer)); + + hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH); + lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL); + bus_crnt = lo | (hi << 16); + + M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n", + ch->dac_idx, bus_crnt - bus_base)); + + return (bus_crnt - bus_base); /* current byte offset of channel */ +} + +static pcmchan_caps * +m3_pchan_getcaps(kobj_t kobj, void *chdata) +{ + struct sc_pchinfo *ch = chdata; + + M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx)); + + return &m3_playcaps; +} + +/* -------------------------------------------------------------------- */ +/* rec channel interface */ + +static void * +m3_rchan_init(kobj_t kobj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir) +{ + struct sc_info *sc = devinfo; + struct sc_rchinfo *ch; + u_int32_t bus_addr, i; + + int idx = sc->rch_cnt; /* adc instance number, no active reuse! */ + int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) + + (MINISRC_IN_BUFFER_SIZE & ~1) + + (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255; + int adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2; + + int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2); + int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); + int dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2); + int dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1; + + M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx)); + + if (dir != PCMDIR_REC) { + device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n"); + return NULL; + } + ch = &sc->rch[idx]; + + ch->adc_idx = idx; + ch->adc_data = adc_data; + if (ch->adc_data + data_bytes/2 >= 0x1c00) { + device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n"); + return NULL; + } + + ch->buffer = b; + ch->parent = sc; + ch->channel = c; + ch->fmt = AFMT_U8; + ch->spd = DSP_DEFAULT_SPEED; + if (sndbuf_alloc(ch->buffer, sc->parent_dmat, M3_BUFSIZE) == -1) { + device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n"); + return NULL; + } + ch->bufsize = sndbuf_getsize(ch->buffer); + + /* host dma buffer pointers */ + bus_addr = vtophys(sndbuf_getbuf(ch->buffer)); + if (bus_addr & 3) { + device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n"); + bus_addr = (bus_addr + 4) & ~3; + } + m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr)); + m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr)); + m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L, + LO(bus_addr + ch->bufsize)); + m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H, + HI(bus_addr + ch->bufsize)); + m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL, + LO(bus_addr)); + m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH, + HI(bus_addr)); + + /* dsp buffers */ + m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf); + m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1, + dsp_in_buf + dsp_in_size/2); + m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf); + m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf); + m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf); + m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1, + dsp_out_buf + dsp_out_size/2); + m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf); + m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf); + + /* some per client initializers */ + m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12, + ch->adc_data + 40 + 8); + m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL, + DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); + + /* set an armload of static initializers */ + for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) { + m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val); + } + + /* put us in the packed task lists */ + m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + + (sc->pch_cnt + sc->rch_cnt), + ch->adc_data >> DP_SHIFT_COUNT); + m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt), + ch->adc_data >> DP_SHIFT_COUNT); + m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt, + ch->adc_data >> DP_SHIFT_COUNT); + + m3_rchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */ + m3_rchan_trigger(NULL, ch, PCMTRIG_STOP); /* stop on init */ + + sc->rch_cnt++; + return ch; +} + +static int +m3_rchan_free(kobj_t kobj, void *chdata) +{ + struct sc_rchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + + M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx)); + + /* + * should remove this exact instance from the packed lists, but all + * are released at once (and in a stopped state) so this is ok. + */ + m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC + + (sc->rch_cnt - 1) + sc->pch_cnt, 0); + m3_wr_assp_data(sc, KDATA_DMA_XFER0 + + (sc->rch_cnt - 1) + sc->pch_cnt, 0); + m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0); + + sc->rch_cnt--; + return 0; +} + +static int +m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format) +{ + struct sc_rchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t data; + + M3_DEBUG(CHANGE, + ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n", + ch->adc_idx, format, + format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit", + format & AFMT_STEREO ? "STEREO":"MONO")); + + /* mono word */ + data = (format & AFMT_STEREO) ? 0 : 1; + m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data); + + /* 8bit word */ + data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0; + m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data); + + ch->fmt = format; + return format; +} + +static int +m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed) +{ + struct sc_rchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t freq; + + M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n", + ch->adc_idx, speed)); + + if ((freq = ((speed << 15) + 24000) / 48000) != 0) { + freq--; + } + + m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq); + + ch->spd = speed; + return speed; /* return closest possible speed */ +} + +static int +m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize) +{ + struct sc_rchinfo *ch = chdata; + + M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n", + ch->adc_idx, blocksize)); + + return blocksize; +} + +static int +m3_rchan_trigger(kobj_t kobj, void *chdata, int go) +{ + struct sc_rchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t data; + + M3_DEBUG(go == PCMTRIG_START ? CHANGE : + go == PCMTRIG_STOP ? CHANGE : + go == PCMTRIG_ABORT ? CHANGE : + CALL, + ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go, + go == PCMTRIG_START ? "PCMTRIG_START" : + go == PCMTRIG_STOP ? "PCMTRIG_STOP" : + go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore")); + + switch(go) { + case PCMTRIG_START: + if (ch->active) { + return 0; + } + ch->active = 1; + + /*[[inc_timer_users]]*/ + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240); + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240); + data = m3_rd_2(sc, HOST_INT_CTRL); + m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE); + + m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1); + m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1); + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + if (ch->active == 0) { + return 0; + } + ch->active = 0; + + /*[[dec_timer_users]]*/ + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0); + m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0); + data = m3_rd_2(sc, HOST_INT_CTRL); + m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE); + + m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0); + m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0); + break; + + case PCMTRIG_EMLDMAWR: + /* got play irq, transfer next buffer - ignore if using dma */ + case PCMTRIG_EMLDMARD: + /* got rec irq, transfer next buffer - ignore if using dma */ + default: + break; + } + return 0; +} + +static int +m3_rchan_getptr(kobj_t kobj, void *chdata) +{ + struct sc_rchinfo *ch = chdata; + struct sc_info *sc = ch->parent; + u_int32_t hi, lo, bus_crnt; + u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer)); + + hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH); + lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL); + bus_crnt = lo | (hi << 16); + + M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n", + ch->adc_idx, bus_crnt - bus_base)); + + return (bus_crnt - bus_base); /* current byte offset of channel */ +} + +static pcmchan_caps * +m3_rchan_getcaps(kobj_t kobj, void *chdata) +{ + struct sc_rchinfo *ch = chdata; + + M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx)); + + return &m3_reccaps; +} + +/* -------------------------------------------------------------------- */ +/* The interrupt handler */ + +static void +m3_intr(void *p) +{ + struct sc_info *sc = (struct sc_info *)p; + u_int32_t status, ctl, i; + + M3_DEBUG(INTR, ("m3_intr\n")); + + status = m3_rd_1(sc, HOST_INT_STATUS); + if (!status) + return; + + m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */ + + if (status & HV_INT_PENDING) { + u_int8_t event; + + device_printf(sc->dev, "Hardware Volume Interrupt\n"); + event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER); + switch (event) { + case 0x99: + mixer_hwvol_mute(sc->dev); + break; + case 0xaa: + mixer_hwvol_step(sc->dev, 1, 1); + break; + case 0x66: + mixer_hwvol_step(sc->dev, -1, -1); + break; + case 0x88: + break; + default: + device_printf(sc->dev, "Unknown HWVOL event\n"); + } + m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88); + + } + + if (status & ASSP_INT_PENDING) { + ctl = m3_rd_1(sc, ASSP_CONTROL_B); + if (!(ctl & STOP_ASSP_CLOCK)) { + ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS); + if (ctl & DSP2HOST_REQ_TIMER) { + m3_wr_1(sc, ASSP_HOST_INT_STATUS, + DSP2HOST_REQ_TIMER); + /*[[ess_update_ptr]]*/ + } + } + } + + for (i=0 ; i<sc->pch_cnt ; i++) { + if (sc->pch[i].active) { + chn_intr(sc->pch[i].channel); + } + } + for (i=0 ; i<sc->rch_cnt ; i++) { + if (sc->rch[i].active) { + chn_intr(sc->rch[i].channel); + } + } +} + +/* -------------------------------------------------------------------- */ +/* stuff */ + +static int +m3_power(struct sc_info *sc, int state) +{ + u_int32_t data; + + M3_DEBUG(CHANGE, ("m3_power(%d)\n", state)); + + data = pci_read_config(sc->dev, 0x34, 1); + if (pci_read_config(sc->dev, data, 1) == 1) { + pci_write_config(sc->dev, data + 4, state, 1); + } + + return 0; +} + +static int +m3_init(struct sc_info *sc) +{ + u_int32_t data, i, size; + u_int8_t reset_state; + + M3_DEBUG(CHANGE, ("m3_init\n")); + + /* diable legacy emulations. */ + data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2); + data |= DISABLE_LEGACY; + pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2); + + m3_config(sc); + + reset_state = m3_assp_halt(sc); + + m3_codec_reset(sc); + + /* [m3_assp_init] */ + /* zero kernel data */ + size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; + for(i = 0 ; i < size / 2 ; i++) { + m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0); + } + /* zero mixer data? */ + size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA; + for(i = 0 ; i < size / 2 ; i++) { + m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0); + } + /* init dma pointer */ + m3_wr_assp_data(sc, KDATA_CURRENT_DMA, + KDATA_DMA_XFER0); + /* write kernel into code memory */ + size = sizeof(assp_kernel_image); + for(i = 0 ; i < size / 2; i++) { + m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i, + assp_kernel_image[i]); + } + /* + * We only have this one client and we know that 0x400 is free in + * our kernel's mem map, so lets just drop it there. It seems that + * the minisrc doesn't need vectors, so we won't bother with them.. + */ + size = sizeof(assp_minisrc_image); + for(i = 0 ; i < size / 2; i++) { + m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]); + } + /* write the coefficients for the low pass filter? */ + size = sizeof(minisrc_lpf_image); + for(i = 0; i < size / 2 ; i++) { + m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i, + minisrc_lpf_image[i]); + } + m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000); + /* the minisrc is the only thing on our task list */ + m3_wr_assp_data(sc, KDATA_TASK0, 0x400); + /* init the mixer number */ + m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0); + /* extreme kernel master volume */ + m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); + m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); + + m3_amp_enable(sc); + + /* [m3_assp_client_init] (only one client at index 0) */ + for (i=0x1100 ; i<0x1c00 ; i++) { + m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */ + } + + m3_enable_ints(sc); + + /* [m3_assp_continue] */ + m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); + + return 0; +} + +static int +m3_uninit(struct sc_info *sc) +{ + M3_DEBUG(CHANGE, ("m3_uninit\n")); + return 0; +} + +/* -------------------------------------------------------------------- */ +/* Probe and attach the card */ + +static int +m3_pci_probe(device_t dev) +{ + struct m3_card_type *card; + + M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev))); + + for (card = m3_card_types ; card->pci_id ; card++) { + if (pci_get_devid(dev) == card->pci_id) { + device_set_desc(dev, card->name); + return 0; + } + } + return ENXIO; +} + +static int +m3_pci_attach(device_t dev) +{ + struct sc_info *sc; + struct ac97_info *codec = NULL; + u_int32_t data, i; + char status[SND_STATUSLEN]; + struct m3_card_type *card; + int len; + + M3_DEBUG(CALL, ("m3_pci_attach\n")); + + if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { + device_printf(dev, "cannot allocate softc\n"); + return ENXIO; + } + + sc->dev = dev; + sc->type = pci_get_devid(dev); + + for (card = m3_card_types ; card->pci_id ; card++) { + if (sc->type == card->pci_id) { + sc->which = card->which; + sc->delay1 = card->delay1; + sc->delay2 = card->delay2; + break; + } + } + + data = pci_read_config(dev, PCIR_COMMAND, 2); + data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); + pci_write_config(dev, PCIR_COMMAND, data, 2); + + sc->regid = PCIR_MAPS; + sc->regtype = SYS_RES_MEMORY; + sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, + 0, ~0, 1, RF_ACTIVE); + if (!sc->reg) { + sc->regtype = SYS_RES_IOPORT; + sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid, + 0, ~0, 1, RF_ACTIVE); + } + if (!sc->reg) { + device_printf(dev, "unable to allocate register space\n"); + goto bad; + } + sc->st = rman_get_bustag(sc->reg); + sc->sh = rman_get_bushandle(sc->reg); + + sc->irqid = 0; + sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, + 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); + if (!sc->irq) { + device_printf(dev, "unable to allocate interrupt\n"); + goto bad; + } + + if (bus_setup_intr(dev, sc->irq, INTR_TYPE_TTY, m3_intr, sc, + &sc->ih)) { + device_printf(dev, "unable to setup interrupt\n"); + goto bad; + } + + if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, + /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + /*maxsize*/M3_BUFSIZE, /*nsegments*/1, + /*maxsegz*/0x3ffff, + /*flags*/0, &sc->parent_dmat) != 0) { + device_printf(dev, "unable to create dma tag\n"); + goto bad; + } + + m3_power(sc, 0); /* power up */ + + /* init chip */ + if (m3_init(sc) == -1) { + device_printf(dev, "unable to initialize the card\n"); + goto bad; + } + + /* create/init mixer */ + codec = AC97_CREATE(dev, sc, m3_codec); + if (codec == NULL) { + device_printf(dev, "ac97_create error\n"); + goto bad; + } + if (mixer_init(dev, ac97_getmixerclass(), codec)) { + device_printf(dev, "mixer_init error\n"); + goto bad; + } + + if (pcm_register(dev, sc, M3_PCHANS, M3_RCHANS)) { + device_printf(dev, "pcm_register error\n"); + goto bad; + } + for (i=0 ; i<M3_PCHANS ; i++) { + if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) { + device_printf(dev, "pcm_addchan (play) error\n"); + goto bad; + } + } + for (i=0 ; i<M3_RCHANS ; i++) { + if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) { + device_printf(dev, "pcm_addchan (rec) error\n"); + goto bad; + } + } + snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld", + (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", + rman_get_start(sc->reg), rman_get_start(sc->irq)); + if (pcm_setstatus(dev, status)) { + device_printf(dev, "attach: pcm_setstatus error\n"); + goto bad; + } + + /* Create the buffer for saving the card state during suspend */ + len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH + + REV_B_DATA_MEMORY_LENGTH); + sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); + if (sc->savemem == NULL) { + device_printf(dev, "Failed to create suspend buffer\n"); + goto bad; + } + + return 0; + + bad: + if (codec) { + ac97_destroy(codec); + } + if (sc->reg) { + bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); + } + if (sc->ih) { + bus_teardown_intr(dev, sc->irq, sc->ih); + } + if (sc->irq) { + bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); + } + if (sc->parent_dmat) { + bus_dma_tag_destroy(sc->parent_dmat); + } + free(sc, M_DEVBUF); + return ENXIO; +} + +static int +m3_pci_detach(device_t dev) +{ + struct sc_info *sc = pcm_getdevinfo(dev); + int r; + + M3_DEBUG(CALL, ("m3_pci_detach\n")); + + if ((r = pcm_unregister(dev)) != 0) { + return r; + } + m3_uninit(sc); /* shutdown chip */ + m3_power(sc, 3); /* power off */ + + bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); + bus_teardown_intr(dev, sc->irq, sc->ih); + bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); + bus_dma_tag_destroy(sc->parent_dmat); + + free(sc->savemem, M_DEVBUF); + free(sc, M_DEVBUF); + return 0; +} + +static int +m3_pci_suspend(device_t dev) +{ + struct sc_info *sc = pcm_getdevinfo(dev); + int i, index = 0; + + M3_DEBUG(CHANGE, ("m3_pci_suspend\n")); + + for (i=0 ; i<sc->pch_cnt ; i++) { + if (sc->pch[i].active) { + m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_STOP); + } + } + for (i=0 ; i<sc->rch_cnt ; i++) { + if (sc->rch[i].active) { + m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_STOP); + } + } + DELAY(10 * 1000); /* give things a chance to stop */ + + /* Disable interrupts */ + m3_wr_2(sc, HOST_INT_CTRL, 0); + m3_wr_1(sc, ASSP_CONTROL_C, 0); + + m3_assp_halt(sc); + + /* Save the state of the ASSP */ + for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) + sc->savemem[index++] = m3_rd_assp_code(sc, i); + for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) + sc->savemem[index++] = m3_rd_assp_data(sc, i); + + /* Power down the card to D3 state */ + m3_power(sc, 3); + + return 0; +} + +static int +m3_pci_resume(device_t dev) +{ + struct sc_info *sc = pcm_getdevinfo(dev); + int i, index = 0; + u_int8_t reset_state; + + M3_DEBUG(CHANGE, ("m3_pci_resume\n")); + + /* Power the card back to D0 */ + m3_power(sc, 0); + + m3_config(sc); + + reset_state = m3_assp_halt(sc); + + m3_codec_reset(sc); + + /* Restore the ASSP state */ + for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) + m3_wr_assp_code(sc, i, sc->savemem[index++]); + for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++) + m3_wr_assp_data(sc, i, sc->savemem[index++]); + + /* Restart the DMA engine */ + m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0); + + /* [m3_assp_continue] */ + m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET); + + m3_enable_ints(sc); + + m3_amp_enable(sc); + + /* Turn the channels back on */ + for (i=0 ; i<sc->pch_cnt ; i++) { + if (sc->pch[i].active) { + m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_START); + } + } + for (i=0 ; i<sc->rch_cnt ; i++) { + if (sc->rch[i].active) { + m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_START); + } + } + + return 0; +} + +static int +m3_pci_shutdown(device_t dev) +{ + struct sc_info *sc = pcm_getdevinfo(dev); + + M3_DEBUG(CALL, ("m3_pci_shutdown\n")); + + m3_power(sc, 3); /* power off */ + return 0; +} + +static u_int8_t +m3_assp_halt(struct sc_info *sc) +{ + u_int8_t data, reset_state; + + data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B); + reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */ + DELAY(10 * 1000); + m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET); + DELAY(10 * 1000); /* necessary? */ + + return reset_state; +} + +static void +m3_config(struct sc_info *sc) +{ + u_int32_t data; + + data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); + data &= REDUCED_DEBOUNCE; + data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; + pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); + + m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP); + data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4); + data &= ~INT_CLK_SELECT; + if (sc->which == ESS_MAESTRO3) { + data &= ~INT_CLK_MULT_ENABLE; + data |= INT_CLK_SRC_NOT_PCI; + } + data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2); + pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4); + + if (sc->which == ESS_ALLEGRO_1) { + data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4); + data |= IN_CLK_12MHZ_SELECT; + pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4); + } + + data = m3_rd_1(sc, ASSP_CONTROL_A); + data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); + data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/ + data |= ASSP_0_WS_ENABLE; + m3_wr_1(sc, ASSP_CONTROL_A, data); + + m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP); +} + +static void +m3_enable_ints(struct sc_info *sc) +{ + u_int8_t data; + + m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE); + data = m3_rd_1(sc, ASSP_CONTROL_C); + m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE); +} + +static void +m3_amp_enable(struct sc_info *sc) +{ + u_int32_t gpo, polarity_port, polarity; + u_int16_t data; + + switch (sc->which) { + case ESS_ALLEGRO_1: + polarity_port = 0x1800; + break; + case ESS_MAESTRO3: + polarity_port = 0x1100; + break; + default: + panic("bad sc->which"); + } + gpo = (polarity_port >> 8) & 0x0f; + polarity = polarity_port >> 12; + polarity = !polarity; /* enable */ + polarity = polarity << gpo; + gpo = 1 << gpo; + m3_wr_2(sc, GPIO_MASK, ~gpo); + data = m3_rd_2(sc, GPIO_DIRECTION); + m3_wr_2(sc, GPIO_DIRECTION, data | gpo); + data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity; + m3_wr_2(sc, GPIO_DATA, data); + m3_wr_2(sc, GPIO_MASK, ~0); +} + +static void +m3_codec_reset(struct sc_info *sc) +{ + u_int16_t data, dir; + int retry = 0; + + do { + data = m3_rd_2(sc, GPIO_DIRECTION); + dir = data | 0x10; /* assuming pci bus master? */ + + /* [[remote_codec_config]] */ + data = m3_rd_2(sc, RING_BUS_CTRL_B); + m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK); + data = m3_rd_2(sc, SDO_OUT_DEST_CTRL); + m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT); + data = m3_rd_2(sc, SDO_IN_DEST_CTRL); + m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN); + + m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE); + DELAY(20); + + m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97); + m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97); + m3_wr_2(sc, GPIO_DATA, 0); + m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97); + DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/ + m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97); + DELAY(5); + m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE | + SERIAL_AC_LINK_ENABLE); + m3_wr_2(sc, GPIO_MASK, ~0); + DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/ + + /* [[try read vendor]] */ + data = m3_rdcd(NULL, sc, 0x7c); + if ((data == 0) || (data == 0xffff)) { + retry++; + if (retry > 3) { + device_printf(sc->dev, "Codec reset failed\n"); + break; + } + device_printf(sc->dev, "Codec reset retry\n"); + } else retry = 0; + } while (retry); +} + +static device_method_t m3_methods[] = { + DEVMETHOD(device_probe, m3_pci_probe), + DEVMETHOD(device_attach, m3_pci_attach), + DEVMETHOD(device_detach, m3_pci_detach), + DEVMETHOD(device_suspend, m3_pci_suspend), + DEVMETHOD(device_resume, m3_pci_resume), + DEVMETHOD(device_shutdown, m3_pci_shutdown), + { 0, 0 } +}; + +static driver_t m3_driver = { + "pcm", + m3_methods, + sizeof(snddev_info), +}; + +static devclass_t pcm_devclass; + +DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0); +MODULE_DEPEND(snd_maestro3, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); +MODULE_VERSION(snd_maestro3, 1); diff --git a/sys/gnu/dev/sound/pci/maestro3_dsp.h b/sys/gnu/dev/sound/pci/maestro3_dsp.h new file mode 100644 index 0000000..9c14f33 --- /dev/null +++ b/sys/gnu/dev/sound/pci/maestro3_dsp.h @@ -0,0 +1,214 @@ +/* $FreeBSD$ */ +/* + * ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Hacked for the maestro3 driver by zab + */ + +/* + * DSP Code images + */ + +u_int16_t assp_kernel_image[] = { + 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4, + 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, + 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, + 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4, + 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08, + 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909, + 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41, + 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308, + 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910, + 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00, + 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026, + 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0, + 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012, + 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A, + 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000, + 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05, + 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26, + 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300, + 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88, + 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008, + 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80, + 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71, + 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A, + 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100, + 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900, + 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903, + 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309, + 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B, + 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540, + 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C, + 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380, + 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340, + 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041, + 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18, + 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, + 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9, + 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8, + 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A, + 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80, + 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, + 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80, + 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A, + 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F, + 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1, + 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034, + 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E, + 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977, + 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B, + 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388, + 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, + 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473, + 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473, + 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880, + 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80, + 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6, + 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909, + 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED, + 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005, + 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, + 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4, + 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, + 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10, + 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070, + 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71, + 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A, + 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061, + 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A, + 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6, + 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A, + 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6, + 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358, + 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6, + 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9, + 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379, + 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6, + 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C, + 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166, + 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B, + 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A, + 0xBE3A, +}; + +/* + * Mini sample rate converter code image + * that is to be loaded at 0x400 on the DSP. + */ +u_int16_t assp_minisrc_image[] = { + 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412, + 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41, + 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907, + 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01, + 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904, + 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D, + 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD, + 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22, + 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0, + 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9, + 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89, + 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0, + 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484, + 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80, + 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624, + 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4, + 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027, + 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903, + 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809, + 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46, + 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47, + 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0, + 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516, + 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E, + 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C, + 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180, + 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E, + 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0, + 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0, + 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0, + 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F, + 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +}; + +u_int16_t minisrc_lpf_image[] = { + 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, + 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F +}; + +/* + * an arbitrary volume we set the internal volume settings to so that the + * ac97 volume range is a little less insane. 0x7fff is max. + */ +#define ARB_VOLUME 0x6800 + +static struct play_vals { + u_int16_t addr, val; +} pv[] = { + {CDATA_LEFT_VOLUME, ARB_VOLUME}, + {CDATA_RIGHT_VOLUME, ARB_VOLUME}, + {SRC3_DIRECTION_OFFSET, 0} , + /* +1, +2 are stereo/16 bit */ + {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ + {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ + {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ + {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ + {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ + {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ + {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ + {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ + {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ + {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ + {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ + {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ + {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ + {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ + {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ + {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ + {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ +}; + +static struct rec_vals { + u_int16_t addr, val; +} rv[] = { + {CDATA_LEFT_VOLUME, ARB_VOLUME}, + {CDATA_RIGHT_VOLUME, ARB_VOLUME}, + {SRC3_DIRECTION_OFFSET, 1}, + /* +1, +2 are stereo/16 bit */ + {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ + {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ + {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ + {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ + {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ + {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ + {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ + {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ + {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ + {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ + {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ + {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ + {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ + {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ + {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ + {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ + {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ + {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ + {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ +}; diff --git a/sys/gnu/dev/sound/pci/maestro3_reg.h b/sys/gnu/dev/sound/pci/maestro3_reg.h new file mode 100644 index 0000000..f74ed30 --- /dev/null +++ b/sys/gnu/dev/sound/pci/maestro3_reg.h @@ -0,0 +1,692 @@ +/* $FreeBSD$ */ +/* + * ESS Technology allegro audio driver. + * + * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Hacked for the maestro3 driver by zab + */ + +/* Allegro PCI configuration registers */ +#define PCI_LEGACY_AUDIO_CTRL 0x40 +#define SOUND_BLASTER_ENABLE 0x00000001 +#define FM_SYNTHESIS_ENABLE 0x00000002 +#define GAME_PORT_ENABLE 0x00000004 +#define MPU401_IO_ENABLE 0x00000008 +#define MPU401_IRQ_ENABLE 0x00000010 +#define ALIAS_10BIT_IO 0x00000020 +#define SB_DMA_MASK 0x000000C0 +#define SB_DMA_0 0x00000040 +#define SB_DMA_1 0x00000040 +#define SB_DMA_R 0x00000080 +#define SB_DMA_3 0x000000C0 +#define SB_IRQ_MASK 0x00000700 +#define SB_IRQ_5 0x00000000 +#define SB_IRQ_7 0x00000100 +#define SB_IRQ_9 0x00000200 +#define SB_IRQ_10 0x00000300 +#define MIDI_IRQ_MASK 0x00003800 +#define SERIAL_IRQ_ENABLE 0x00004000 +#define DISABLE_LEGACY 0x00008000 + +#define PCI_ALLEGRO_CONFIG 0x50 +#define SB_ADDR_240 0x00000004 +#define MPU_ADDR_MASK 0x00000018 +#define MPU_ADDR_330 0x00000000 +#define MPU_ADDR_300 0x00000008 +#define MPU_ADDR_320 0x00000010 +#define MPU_ADDR_340 0x00000018 +#define USE_PCI_TIMING 0x00000040 +#define POSTED_WRITE_ENABLE 0x00000080 +#define DMA_POLICY_MASK 0x00000700 +#define DMA_DDMA 0x00000000 +#define DMA_TDMA 0x00000100 +#define DMA_PCPCI 0x00000200 +#define DMA_WBDMA16 0x00000400 +#define DMA_WBDMA4 0x00000500 +#define DMA_WBDMA2 0x00000600 +#define DMA_WBDMA1 0x00000700 +#define DMA_SAFE_GUARD 0x00000800 +#define HI_PERF_GP_ENABLE 0x00001000 +#define PIC_SNOOP_MODE_0 0x00002000 +#define PIC_SNOOP_MODE_1 0x00004000 +#define SOUNDBLASTER_IRQ_MASK 0x00008000 +#define RING_IN_ENABLE 0x00010000 +#define SPDIF_TEST_MODE 0x00020000 +#define CLK_MULT_MODE_SELECT_2 0x00040000 +#define EEPROM_WRITE_ENABLE 0x00080000 +#define CODEC_DIR_IN 0x00100000 +#define HV_BUTTON_FROM_GD 0x00200000 +#define REDUCED_DEBOUNCE 0x00400000 +#define HV_CTRL_ENABLE 0x00800000 +#define SPDIF_ENABLE 0x01000000 +#define CLK_DIV_SELECT 0x06000000 +#define CLK_DIV_BY_48 0x00000000 +#define CLK_DIV_BY_49 0x02000000 +#define CLK_DIV_BY_50 0x04000000 +#define CLK_DIV_RESERVED 0x06000000 +#define PM_CTRL_ENABLE 0x08000000 +#define CLK_MULT_MODE_SELECT 0x30000000 +#define CLK_MULT_MODE_SHIFT 28 +#define CLK_MULT_MODE_0 0x00000000 +#define CLK_MULT_MODE_1 0x10000000 +#define CLK_MULT_MODE_2 0x20000000 +#define CLK_MULT_MODE_3 0x30000000 +#define INT_CLK_SELECT 0x40000000 +#define INT_CLK_MULT_RESET 0x80000000 + +/* M3 */ +#define INT_CLK_SRC_NOT_PCI 0x00100000 +#define INT_CLK_MULT_ENABLE 0x80000000 + +#define PCI_ACPI_CONTROL 0x54 +#define PCI_ACPI_D0 0x00000000 +#define PCI_ACPI_D1 0xB4F70000 +#define PCI_ACPI_D2 0xB4F7B4F7 + +#define PCI_USER_CONFIG 0x58 +#define EXT_PCI_MASTER_ENABLE 0x00000001 +#define SPDIF_OUT_SELECT 0x00000002 +#define TEST_PIN_DIR_CTRL 0x00000004 +#define AC97_CODEC_TEST 0x00000020 +#define TRI_STATE_BUFFER 0x00000080 +#define IN_CLK_12MHZ_SELECT 0x00000100 +#define MULTI_FUNC_DISABLE 0x00000200 +#define EXT_MASTER_PAIR_SEL 0x00000400 +#define PCI_MASTER_SUPPORT 0x00000800 +#define STOP_CLOCK_ENABLE 0x00001000 +#define EAPD_DRIVE_ENABLE 0x00002000 +#define REQ_TRI_STATE_ENABLE 0x00004000 +#define REQ_LOW_ENABLE 0x00008000 +#define MIDI_1_ENABLE 0x00010000 +#define MIDI_2_ENABLE 0x00020000 +#define SB_AUDIO_SYNC 0x00040000 +#define HV_CTRL_TEST 0x00100000 +#define SOUNDBLASTER_TEST 0x00400000 + +#define PCI_USER_CONFIG_C 0x5C + +#define PCI_DDMA_CTRL 0x60 +#define DDMA_ENABLE 0x00000001 + + +/* Allegro registers */ +#define HOST_INT_CTRL 0x18 +#define SB_INT_ENABLE 0x0001 +#define MPU401_INT_ENABLE 0x0002 +#define ASSP_INT_ENABLE 0x0010 +#define RING_INT_ENABLE 0x0020 +#define HV_INT_ENABLE 0x0040 +#define CLKRUN_GEN_ENABLE 0x0100 +#define HV_CTRL_TO_PME 0x0400 +#define SOFTWARE_RESET_ENABLE 0x8000 + +/* + * should be using the above defines, probably. + */ +#define REGB_ENABLE_RESET 0x01 +#define REGB_STOP_CLOCK 0x10 + +#define HOST_INT_STATUS 0x1A +#define SB_INT_PENDING 0x01 +#define MPU401_INT_PENDING 0x02 +#define ASSP_INT_PENDING 0x10 +#define RING_INT_PENDING 0x20 +#define HV_INT_PENDING 0x40 + +#define HARDWARE_VOL_CTRL 0x1B +#define SHADOW_MIX_REG_VOICE 0x1C +#define HW_VOL_COUNTER_VOICE 0x1D +#define SHADOW_MIX_REG_MASTER 0x1E +#define HW_VOL_COUNTER_MASTER 0x1F + +#define CODEC_COMMAND 0x30 +#define CODEC_READ_B 0x80 + +#define CODEC_STATUS 0x30 +#define CODEC_BUSY_B 0x01 + +#define CODEC_DATA 0x32 + +#define RING_BUS_CTRL_A 0x36 +#define RAC_PME_ENABLE 0x0100 +#define RAC_SDFS_ENABLE 0x0200 +#define LAC_PME_ENABLE 0x0400 +#define LAC_SDFS_ENABLE 0x0800 +#define SERIAL_AC_LINK_ENABLE 0x1000 +#define IO_SRAM_ENABLE 0x2000 +#define IIS_INPUT_ENABLE 0x8000 + +#define RING_BUS_CTRL_B 0x38 +#define SECOND_CODEC_ID_MASK 0x0003 +#define SPDIF_FUNC_ENABLE 0x0010 +#define SECOND_AC_ENABLE 0x0020 +#define SB_MODULE_INTF_ENABLE 0x0040 +#define SSPE_ENABLE 0x0040 +#define M3I_DOCK_ENABLE 0x0080 + +#define SDO_OUT_DEST_CTRL 0x3A +#define COMMAND_ADDR_OUT 0x0003 +#define PCM_LR_OUT_LOCAL 0x0000 +#define PCM_LR_OUT_REMOTE 0x0004 +#define PCM_LR_OUT_MUTE 0x0008 +#define PCM_LR_OUT_BOTH 0x000C +#define LINE1_DAC_OUT_LOCAL 0x0000 +#define LINE1_DAC_OUT_REMOTE 0x0010 +#define LINE1_DAC_OUT_MUTE 0x0020 +#define LINE1_DAC_OUT_BOTH 0x0030 +#define PCM_CLS_OUT_LOCAL 0x0000 +#define PCM_CLS_OUT_REMOTE 0x0040 +#define PCM_CLS_OUT_MUTE 0x0080 +#define PCM_CLS_OUT_BOTH 0x00C0 +#define PCM_RLF_OUT_LOCAL 0x0000 +#define PCM_RLF_OUT_REMOTE 0x0100 +#define PCM_RLF_OUT_MUTE 0x0200 +#define PCM_RLF_OUT_BOTH 0x0300 +#define LINE2_DAC_OUT_LOCAL 0x0000 +#define LINE2_DAC_OUT_REMOTE 0x0400 +#define LINE2_DAC_OUT_MUTE 0x0800 +#define LINE2_DAC_OUT_BOTH 0x0C00 +#define HANDSET_OUT_LOCAL 0x0000 +#define HANDSET_OUT_REMOTE 0x1000 +#define HANDSET_OUT_MUTE 0x2000 +#define HANDSET_OUT_BOTH 0x3000 +#define IO_CTRL_OUT_LOCAL 0x0000 +#define IO_CTRL_OUT_REMOTE 0x4000 +#define IO_CTRL_OUT_MUTE 0x8000 +#define IO_CTRL_OUT_BOTH 0xC000 + +#define SDO_IN_DEST_CTRL 0x3C +#define STATUS_ADDR_IN 0x0003 +#define PCM_LR_IN_LOCAL 0x0000 +#define PCM_LR_IN_REMOTE 0x0004 +#define PCM_LR_RESERVED 0x0008 +#define PCM_LR_IN_BOTH 0x000C +#define LINE1_ADC_IN_LOCAL 0x0000 +#define LINE1_ADC_IN_REMOTE 0x0010 +#define LINE1_ADC_IN_MUTE 0x0020 +#define MIC_ADC_IN_LOCAL 0x0000 +#define MIC_ADC_IN_REMOTE 0x0040 +#define MIC_ADC_IN_MUTE 0x0080 +#define LINE2_DAC_IN_LOCAL 0x0000 +#define LINE2_DAC_IN_REMOTE 0x0400 +#define LINE2_DAC_IN_MUTE 0x0800 +#define HANDSET_IN_LOCAL 0x0000 +#define HANDSET_IN_REMOTE 0x1000 +#define HANDSET_IN_MUTE 0x2000 +#define IO_STATUS_IN_LOCAL 0x0000 +#define IO_STATUS_IN_REMOTE 0x4000 + +#define SPDIF_IN_CTRL 0x3E +#define SPDIF_IN_ENABLE 0x0001 + +#define GPIO_DATA 0x60 +#define GPIO_DATA_MASK 0x0FFF +#define GPIO_HV_STATUS 0x3000 +#define GPIO_PME_STATUS 0x4000 + +#define GPIO_MASK 0x64 +#define GPIO_DIRECTION 0x68 +#define GPO_PRIMARY_AC97 0x0001 +#define GPI_LINEOUT_SENSE 0x0004 +#define GPO_SECONDARY_AC97 0x0008 +#define GPI_VOL_DOWN 0x0010 +#define GPI_VOL_UP 0x0020 +#define GPI_IIS_CLK 0x0040 +#define GPI_IIS_LRCLK 0x0080 +#define GPI_IIS_DATA 0x0100 +#define GPI_DOCKING_STATUS 0x0100 +#define GPI_HEADPHONE_SENSE 0x0200 +#define GPO_EXT_AMP_SHUTDOWN 0x1000 + +/* M3 */ +#define GPO_M3_EXT_AMP_SHUTDN 0x0002 + +#define ASSP_INDEX_PORT 0x80 +#define ASSP_MEMORY_PORT 0x82 +#define ASSP_DATA_PORT 0x84 + +#define MPU401_DATA_PORT 0x98 +#define MPU401_STATUS_PORT 0x99 + +#define CLK_MULT_DATA_PORT 0x9C + +#define ASSP_CONTROL_A 0xA2 +#define ASSP_0_WS_ENABLE 0x01 +#define ASSP_CTRL_A_RESERVED1 0x02 +#define ASSP_CTRL_A_RESERVED2 0x04 +#define ASSP_CLK_49MHZ_SELECT 0x08 +#define FAST_PLU_ENABLE 0x10 +#define ASSP_CTRL_A_RESERVED3 0x20 +#define DSP_CLK_36MHZ_SELECT 0x40 + +#define ASSP_CONTROL_B 0xA4 +#define RESET_ASSP 0x00 +#define RUN_ASSP 0x01 +#define ENABLE_ASSP_CLOCK 0x00 +#define STOP_ASSP_CLOCK 0x10 +#define RESET_TOGGLE 0x40 + +#define ASSP_CONTROL_C 0xA6 +#define ASSP_HOST_INT_ENABLE 0x01 +#define FM_ADDR_REMAP_DISABLE 0x02 +#define HOST_WRITE_PORT_ENABLE 0x08 + +#define ASSP_HOST_INT_STATUS 0xAC +#define DSP2HOST_REQ_PIORECORD 0x01 +#define DSP2HOST_REQ_I2SRATE 0x02 +#define DSP2HOST_REQ_TIMER 0x04 + +/* AC97 registers */ +/* XXX fix this crap up */ +/*#define AC97_RESET 0x00*/ + +#define AC97_VOL_MUTE_B 0x8000 +#define AC97_VOL_M 0x1F +#define AC97_LEFT_VOL_S 8 + +#define AC97_MASTER_VOL 0x02 +#define AC97_LINE_LEVEL_VOL 0x04 +#define AC97_MASTER_MONO_VOL 0x06 +#define AC97_PC_BEEP_VOL 0x0A +#define AC97_PC_BEEP_VOL_M 0x0F +#define AC97_SROUND_MASTER_VOL 0x38 +#define AC97_PC_BEEP_VOL_S 1 + +/*#define AC97_PHONE_VOL 0x0C +#define AC97_MIC_VOL 0x0E*/ +#define AC97_MIC_20DB_ENABLE 0x40 + +/*#define AC97_LINEIN_VOL 0x10 +#define AC97_CD_VOL 0x12 +#define AC97_VIDEO_VOL 0x14 +#define AC97_AUX_VOL 0x16*/ +#define AC97_PCM_OUT_VOL 0x18 +/*#define AC97_RECORD_SELECT 0x1A*/ +#define AC97_RECORD_MIC 0x00 +#define AC97_RECORD_CD 0x01 +#define AC97_RECORD_VIDEO 0x02 +#define AC97_RECORD_AUX 0x03 +#define AC97_RECORD_MONO_MUX 0x02 +#define AC97_RECORD_DIGITAL 0x03 +#define AC97_RECORD_LINE 0x04 +#define AC97_RECORD_STEREO 0x05 +#define AC97_RECORD_MONO 0x06 +#define AC97_RECORD_PHONE 0x07 + +/*#define AC97_RECORD_GAIN 0x1C*/ +#define AC97_RECORD_VOL_M 0x0F + +/*#define AC97_GENERAL_PURPOSE 0x20*/ +#define AC97_POWER_DOWN_CTRL 0x26 +#define AC97_ADC_READY 0x0001 +#define AC97_DAC_READY 0x0002 +#define AC97_ANALOG_READY 0x0004 +#define AC97_VREF_ON 0x0008 +#define AC97_PR0 0x0100 +#define AC97_PR1 0x0200 +#define AC97_PR2 0x0400 +#define AC97_PR3 0x0800 +#define AC97_PR4 0x1000 + +#define AC97_RESERVED1 0x28 + +#define AC97_VENDOR_TEST 0x5A + +#define AC97_CLOCK_DELAY 0x5C +#define AC97_LINEOUT_MUX_SEL 0x0001 +#define AC97_MONO_MUX_SEL 0x0002 +#define AC97_CLOCK_DELAY_SEL 0x1F +#define AC97_DAC_CDS_SHIFT 6 +#define AC97_ADC_CDS_SHIFT 11 + +#define AC97_MULTI_CHANNEL_SEL 0x74 + +/*#define AC97_VENDOR_ID1 0x7C +#define AC97_VENDOR_ID2 0x7E*/ + +/* + * ASSP control regs + */ +#define DSP_PORT_TIMER_COUNT 0x06 + +#define DSP_PORT_MEMORY_INDEX 0x80 + +#define DSP_PORT_MEMORY_TYPE 0x82 +#define MEMTYPE_INTERNAL_CODE 0x0002 +#define MEMTYPE_INTERNAL_DATA 0x0003 +#define MEMTYPE_MASK 0x0003 + +#define DSP_PORT_MEMORY_DATA 0x84 + +#define DSP_PORT_CONTROL_REG_A 0xA2 +#define DSP_PORT_CONTROL_REG_B 0xA4 +#define DSP_PORT_CONTROL_REG_C 0xA6 + +#define REV_A_CODE_MEMORY_BEGIN 0x0000 +#define REV_A_CODE_MEMORY_END 0x0FFF +#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 +#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) + +#define REV_B_CODE_MEMORY_BEGIN 0x0000 +#define REV_B_CODE_MEMORY_END 0x0BFF +#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 +#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) + +#define REV_A_DATA_MEMORY_BEGIN 0x1000 +#define REV_A_DATA_MEMORY_END 0x2FFF +#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 +#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) + +#define REV_B_DATA_MEMORY_BEGIN 0x1000 +#define REV_B_DATA_MEMORY_END 0x2BFF +#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 +#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) + + +#define NUM_UNITS_KERNEL_CODE 16 +#define NUM_UNITS_KERNEL_DATA 2 + +#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 +#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 + +/* + * Kernel data layout + */ + +#define DP_SHIFT_COUNT 7 + +#define KDATA_BASE_ADDR 0x1000 +#define KDATA_BASE_ADDR2 0x1080 + +#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) +#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) +#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) +#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) +#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) +#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) +#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) +#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) +#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) + +#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) +#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) + +#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) +#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) +#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) +#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) +#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) +#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) +#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) +#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) +#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) +#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) + +#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) +#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) + +#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) +#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) + +#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) +#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) + +#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) +#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) +#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) + +#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) +#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) +#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) +#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) +#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) + +#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) +#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) +#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) + +#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) +#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) +#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) + +#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) +#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) +#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) +#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) +#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) +#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) +#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) +#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) +#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) +#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) + +#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) +#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) +#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) + +#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) +#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) + +#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) +#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) +#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) + +#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) +#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) +#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) +#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) +#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) +#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) + +#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) +#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) +#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) +#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) +#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) +#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) + +#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) +#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) +#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) +#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) +#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) +#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) + +#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) +#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) +#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) +#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) + +#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) +#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) + +#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) +#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) + +#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) +#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) +#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) +#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) +#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) + +#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) +#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) + +#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) +#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) +#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) + +#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) +#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) + +#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) + +#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) +#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) +#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) +#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) +#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) +#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) +#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) +#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) +#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) +#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) +#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) +#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) + +#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) +#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) +#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) +#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) + +#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) +#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) + +#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) +#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) +#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) +#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) + +#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) +#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) +#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) +#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) +#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) + +/* + * second 'segment' (?) reserved for mixer + * buffers.. + */ + +#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) +#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) +#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) +#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) +#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) +#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) +#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) +#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) +#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) +#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) +#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) +#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) +#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) +#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) +#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) +#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) + +#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) +#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) +#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) +#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) +#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) +#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) +#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) +#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) +#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) +#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) +#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) + +#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) +#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) +#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) +#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) +#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) +#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) + +#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) +#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) +#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) +#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) + +/* + * client data area offsets + */ +#define CDATA_INSTANCE_READY 0x00 + +#define CDATA_HOST_SRC_ADDRL 0x01 +#define CDATA_HOST_SRC_ADDRH 0x02 +#define CDATA_HOST_SRC_END_PLUS_1L 0x03 +#define CDATA_HOST_SRC_END_PLUS_1H 0x04 +#define CDATA_HOST_SRC_CURRENTL 0x05 +#define CDATA_HOST_SRC_CURRENTH 0x06 + +#define CDATA_IN_BUF_CONNECT 0x07 +#define CDATA_OUT_BUF_CONNECT 0x08 + +#define CDATA_IN_BUF_BEGIN 0x09 +#define CDATA_IN_BUF_END_PLUS_1 0x0A +#define CDATA_IN_BUF_HEAD 0x0B +#define CDATA_IN_BUF_TAIL 0x0C +#define CDATA_OUT_BUF_BEGIN 0x0D +#define CDATA_OUT_BUF_END_PLUS_1 0x0E +#define CDATA_OUT_BUF_HEAD 0x0F +#define CDATA_OUT_BUF_TAIL 0x10 + +#define CDATA_DMA_CONTROL 0x11 +#define CDATA_RESERVED 0x12 + +#define CDATA_FREQUENCY 0x13 +#define CDATA_LEFT_VOLUME 0x14 +#define CDATA_RIGHT_VOLUME 0x15 +#define CDATA_LEFT_SUR_VOL 0x16 +#define CDATA_RIGHT_SUR_VOL 0x17 + +#define CDATA_HEADER_LEN 0x18 + +#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN +#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) +#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) +#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) +#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) +#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) +#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) +#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) + +#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) +#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) +#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) +#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) +#define MINISRC_BIQUAD_STAGE 2 +#define MINISRC_COEF_LOC 0X175 + +#define DMACONTROL_BLOCK_MASK 0x000F +#define DMAC_BLOCK0_SELECTOR 0x0000 +#define DMAC_BLOCK1_SELECTOR 0x0001 +#define DMAC_BLOCK2_SELECTOR 0x0002 +#define DMAC_BLOCK3_SELECTOR 0x0003 +#define DMAC_BLOCK4_SELECTOR 0x0004 +#define DMAC_BLOCK5_SELECTOR 0x0005 +#define DMAC_BLOCK6_SELECTOR 0x0006 +#define DMAC_BLOCK7_SELECTOR 0x0007 +#define DMAC_BLOCK8_SELECTOR 0x0008 +#define DMAC_BLOCK9_SELECTOR 0x0009 +#define DMAC_BLOCKA_SELECTOR 0x000A +#define DMAC_BLOCKB_SELECTOR 0x000B +#define DMAC_BLOCKC_SELECTOR 0x000C +#define DMAC_BLOCKD_SELECTOR 0x000D +#define DMAC_BLOCKE_SELECTOR 0x000E +#define DMAC_BLOCKF_SELECTOR 0x000F +#define DMACONTROL_PAGE_MASK 0x00F0 +#define DMAC_PAGE0_SELECTOR 0x0030 +#define DMAC_PAGE1_SELECTOR 0x0020 +#define DMAC_PAGE2_SELECTOR 0x0010 +#define DMAC_PAGE3_SELECTOR 0x0000 +#define DMACONTROL_AUTOREPEAT 0x1000 +#define DMACONTROL_STOPPED 0x2000 +#define DMACONTROL_DIRECTION 0x0100 diff --git a/sys/modules/sound/driver/Makefile b/sys/modules/sound/driver/Makefile index 888cfb7..e6f21ac 100644 --- a/sys/modules/sound/driver/Makefile +++ b/sys/modules/sound/driver/Makefile @@ -1,7 +1,7 @@ # $FreeBSD$ SUBDIR = ad1816 csa csapcm ds1 emu10k1 es137x es1888 ess fm801 gusc -SUBDIR += maestro mss neomagic sb16 sb8 sbc solo t4dwave via82c686 +SUBDIR += maestro maestro3 mss neomagic sb16 sb8 sbc solo t4dwave via82c686 SUBDIR += driver .include <bsd.subdir.mk> diff --git a/sys/modules/sound/driver/maestro3/Makefile b/sys/modules/sound/driver/maestro3/Makefile new file mode 100644 index 0000000..b644370 --- /dev/null +++ b/sys/modules/sound/driver/maestro3/Makefile @@ -0,0 +1,10 @@ +# $FreeBSD$ +.PATH: ${.CURDIR}/../../../../dev/sound/pci +KMOD = snd_maestro3 +SRCS = device_if.h bus_if.h isa_if.h pci_if.h +SRCS += maestro3.c +CFLAGS += -Wall + +CFLAGS += -DM3_DEBUG_LEVEL=-1 + +.include <bsd.kmod.mk> |
