expand CFI_ARMEDANDDANGEROUS to include writing the user segment

of the PR; this register is actually write-once so deserves the
safety-belt as much as the PLR

1 files changed, 12 insertions, 3 deletions

diff --git a/sys/dev/cfi/cfi_core.c b/sys/dev/cfi/cfi_core.c
index 4f2eebc..b19d271 100644
--- a/sys/dev/cfi/cfi_core.c
+++ b/sys/dev/cfi/cfi_core.c
@@ -438,9 +438,9 @@ cfi_write_block(struct cfi_softc *sc)
  * used for security.  There are two 64-bit segments; one is programmed
  * at the factory with a unique 64-bit number which is immutable.
  * The other segment is left blank for User (OEM) programming.
- * Once the User/OEM segment is programmed it can be locked
- * to prevent future programming by writing bit 0 of the Protection
- * Lock Register (PLR).  The PLR can written only once.
+ * The User/OEM segment is One Time Programmable (OTP).  It can also
+ * be locked to prevent any firther writes by setting bit 0 of the
+ * Protection Lock Register (PLR).  The PLR can written only once.
  */
 
 static uint16_t
@@ -496,17 +496,21 @@ cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *id)
 
 /*
  * Write the User/OEM 64-bit segment of the PR.
+ * XXX should allow writing individual words/bytes
  */
 int
 cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
 {
+#ifdef CFI_ARMEDANDDANGEROUS
 	register_t intr;
 	int i, error;
+#endif
 
 	if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
 		return EOPNOTSUPP;
 	KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
 
+#ifdef CFI_ARMEDANDDANGEROUS
 	for (i = 7; i >= 4; i--, id >>= 16) {
 		intr = intr_disable();
 		cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
@@ -519,6 +523,11 @@ cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
 	}
 	cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
 	return error;
+#else
+	device_printf(sc->sc_dev, "%s: OEM PR not set, "
+	    "CFI_ARMEDANDDANGEROUS not configured\n", __func__);
+	return ENXIO;
+#endif
 }
 
 /*