Enable KX bit, which is needed for 64 bit access, in status register

for XLR. Update exception handlers and other functions which set/change
status registers to preserve this.

Approved by:	rrs

3 files changed, 18 insertions, 6 deletions

diff --git a/sys/mips/mips/exception.S b/sys/mips/mips/exception.S
index 3949410..2da8a81 100644
--- a/sys/mips/mips/exception.S
+++ b/sys/mips/mips/exception.S
@@ -235,7 +235,7 @@ SlowFault:
 #define	SAVE_REG(reg, offs, base) \
 	REG_S	reg, CALLFRAME_SIZ + (SZREG * offs) (base)
 
-#ifdef TARGET_OCTEON
+#if defined(TARGET_OCTEON)
 #define CLEAR_STATUS \
 	mfc0    a0, COP_0_STATUS_REG    ;\
 	li      a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
@@ -244,6 +244,15 @@ SlowFault:
 	and     a0, a0, a2              ; \
         mtc0    a0, COP_0_STATUS_REG    ; \
 	ITLBNOPFIX
+#elif defined(TARGET_XLR_XLS)
+#define CLEAR_STATUS \
+	mfc0    a0, COP_0_STATUS_REG    ;\
+	li      a2, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) ; \
+	or      a0, a0, a2	        ; \
+	li      a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER)   ; \
+	and     a0, a0, a2              ; \
+        mtc0    a0, COP_0_STATUS_REG    ; \
+	ITLBNOPFIX
 #else
 #define CLEAR_STATUS \
 	mfc0    a0, COP_0_STATUS_REG    ;\
@@ -475,8 +484,10 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
 	PTR_LA	gp, _C_LABEL(_gp)	# switch to kernel GP
 # Turn off fpu and enter kernel mode
 	and	t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB)
-#ifdef TARGET_OCTEON
+#if defined(TARGET_OCTEON)
 	or      t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX)
+#elif defined(TARGET_XLR_XLS)	
+	or      t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT)
 #endif	
 	mtc0	t0, COP_0_STATUS_REG
 	PTR_ADDU a0, k1, U_PCB_REGS
@@ -693,6 +704,8 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
 	and	t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
 #ifdef TARGET_OCTEON
 	or      t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX)
+#elif defined(TARGET_XLR_XLS)	
+	or      t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT)
 #endif	
 	mtc0	t0, COP_0_STATUS_REG
 	ITLBNOPFIX
diff --git a/sys/mips/mips/locore.S b/sys/mips/mips/locore.S
index d626add..c27e777 100644
--- a/sys/mips/mips/locore.S
+++ b/sys/mips/mips/locore.S
@@ -99,7 +99,7 @@ VECTOR(_locore, unknown)
 
 	/* Reset these bits */
         li	t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE)
-#elif defined (CPU_XLR)
+#elif defined (TARGET_XLR_XLS)
 	/* Set these bits */
         li	t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX)
 
diff --git a/sys/mips/mips/vm_machdep.c b/sys/mips/mips/vm_machdep.c
index 3948480..b4534bb 100644
--- a/sys/mips/mips/vm_machdep.c
+++ b/sys/mips/mips/vm_machdep.c
@@ -148,7 +148,7 @@ cpu_fork(register struct thread *td1,register struct proc *p2,
 	pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return;
 	pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td2;
 	pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td2->td_frame;
-	pcb2->pcb_context[PCB_REG_SR] = SR_INT_MASK & mips_rd_status();
+	pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | SR_INT_MASK) & mips_rd_status();
 	/*
 	 * FREEBSD_DEVELOPERS_FIXME:
 	 * Setup any other CPU-Specific registers (Not MIPS Standard)
@@ -162,7 +162,6 @@ cpu_fork(register struct thread *td1,register struct proc *p2,
 #ifdef TARGET_OCTEON
 	pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
 #endif
-
 }
 
 /*
@@ -351,7 +350,7 @@ cpu_set_upcall(struct thread *td, struct thread *td0)
 	pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td;
 	pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame;
 	/* Dont set IE bit in SR. sched lock release will take care of it */
-	pcb2->pcb_context[PCB_REG_SR] = SR_INT_MASK & mips_rd_status();
+	pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | SR_INT_MASK) & mips_rd_status();
 
 #ifdef TARGET_OCTEON
 	pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT |