diff options
| author | peter <peter@FreeBSD.org> | 2001-08-18 04:04:45 +0000 |
|---|---|---|
| committer | peter <peter@FreeBSD.org> | 2001-08-18 04:04:45 +0000 |
| commit | 8f9d0c3e4f18972234061c0378040c8f2173b1cb (patch) | |
| tree | a15e2da30719d870dabf04c01d71b499455a99e4 | |
| parent | 77c5965e950cf42cc538f91c6788bc16f6399b7e (diff) | |
| download | FreeBSD-src-8f9d0c3e4f18972234061c0378040c8f2173b1cb.zip FreeBSD-src-8f9d0c3e4f18972234061c0378040c8f2173b1cb.tar.gz | |
There is nothing special that requires SSE to be only on 686 class cpus.
This enables 586-only SMP kernels to compile again.
Problem reported by: Jacek Jedrzejczak <jacol@ids.gda.pl>
| -rw-r--r-- | sys/amd64/amd64/initcpu.c | 10 | ||||
| -rw-r--r-- | sys/i386/i386/initcpu.c | 10 |
2 files changed, 8 insertions, 12 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 4339c62..ba14116 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -62,8 +62,8 @@ static void init_6x86(void); static void init_6x86MX(void); static void init_ppro(void); static void init_mendocino(void); -void enable_sse(void); #endif +void enable_sse(void); int hw_instruction_sse = 0; SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, @@ -507,7 +507,9 @@ init_mendocino(void) write_eflags(eflags); #endif /* CPU_PPRO2CELERON */ } - + +#endif /* I686_CPU */ + /* * Initialize CR4 (Control register 4) to enable SSE instructions. */ @@ -522,8 +524,6 @@ enable_sse(void) #endif } -#endif /* I686_CPU */ - void initializecpu(void) { @@ -571,9 +571,7 @@ initializecpu(void) default: break; } -#ifdef I686_CPU enable_sse(); -#endif #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) /* diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c index 4339c62..ba14116 100644 --- a/sys/i386/i386/initcpu.c +++ b/sys/i386/i386/initcpu.c @@ -62,8 +62,8 @@ static void init_6x86(void); static void init_6x86MX(void); static void init_ppro(void); static void init_mendocino(void); -void enable_sse(void); #endif +void enable_sse(void); int hw_instruction_sse = 0; SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, @@ -507,7 +507,9 @@ init_mendocino(void) write_eflags(eflags); #endif /* CPU_PPRO2CELERON */ } - + +#endif /* I686_CPU */ + /* * Initialize CR4 (Control register 4) to enable SSE instructions. */ @@ -522,8 +524,6 @@ enable_sse(void) #endif } -#endif /* I686_CPU */ - void initializecpu(void) { @@ -571,9 +571,7 @@ initializecpu(void) default: break; } -#ifdef I686_CPU enable_sse(); -#endif #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) /* |
