Add JMicron JMP202/JMP211 PHY driver.

3 files changed, 492 insertions, 0 deletions

diff --git a/sys/dev/mii/jmphy.c b/sys/dev/mii/jmphy.c
new file mode 100644
index 0000000..f66510a
--- /dev/null
+++ b/sys/dev/mii/jmphy.c
@@ -0,0 +1,379 @@
+/*-
+ * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Driver for the JMicron JMP211 10/100/1000, JMP202 10/100 PHY.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/bus.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include "miidevs.h"
+
+#include <dev/mii/jmphyreg.h>
+
+#include "miibus_if.h"
+
+static int 	jmphy_probe(device_t);
+static int 	jmphy_attach(device_t);
+static void	jmphy_reset(struct mii_softc *);
+static uint16_t	jmphy_anar(struct ifmedia_entry *);
+static int	jmphy_auto(struct mii_softc *, struct ifmedia_entry *);
+
+struct jmphy_softc {
+	struct mii_softc mii_sc;
+	int mii_oui;
+	int mii_model;
+	int mii_rev;
+};
+
+static device_method_t jmphy_methods[] = {
+	/* Device interface. */
+	DEVMETHOD(device_probe,		jmphy_probe),
+	DEVMETHOD(device_attach,	jmphy_attach),
+	DEVMETHOD(device_detach,	mii_phy_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	{ NULL, NULL }
+};
+
+static devclass_t jmphy_devclass;
+static driver_t jmphy_driver = {
+	"jmphy",
+	jmphy_methods,
+	sizeof(struct jmphy_softc)
+};
+
+DRIVER_MODULE(jmphy, miibus, jmphy_driver, jmphy_devclass, 0, 0);
+
+static int	jmphy_service(struct mii_softc *, struct mii_data *, int);
+static void	jmphy_status(struct mii_softc *);
+
+static const struct mii_phydesc jmphys[] = {
+	MII_PHY_DESC(JMICRON, JMP202),
+	MII_PHY_DESC(JMICRON, JMP211),
+	MII_PHY_END
+};
+
+static int
+jmphy_probe(device_t dev)
+{
+
+	return (mii_phy_dev_probe(dev, jmphys, BUS_PROBE_DEFAULT));
+}
+
+static int
+jmphy_attach(device_t dev)
+{
+	struct jmphy_softc *jsc;
+	struct mii_softc *sc;
+	struct mii_attach_args *ma;
+	struct mii_data *mii;
+
+	jsc = device_get_softc(dev);
+	sc = &jsc->mii_sc;
+	ma = device_get_ivars(dev);
+	sc->mii_dev = device_get_parent(dev);
+	mii = device_get_softc(sc->mii_dev);
+	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
+
+	sc->mii_inst = mii->mii_instance;
+	sc->mii_phy = ma->mii_phyno;
+	sc->mii_service = jmphy_service;
+	sc->mii_pdata = mii;
+
+	mii->mii_instance++;
+
+	jsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
+	jsc->mii_model = MII_MODEL(ma->mii_id2);
+	jsc->mii_rev = MII_REV(ma->mii_id2);
+	if (bootverbose)
+		device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
+		    jsc->mii_oui, jsc->mii_model, jsc->mii_rev);
+
+	jmphy_reset(sc);
+
+	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+	if (sc->mii_capabilities & BMSR_EXTSTAT)
+		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
+	device_printf(dev, " ");
+	mii_phy_add_media(sc);
+	printf("\n");
+
+	MIIBUS_MEDIAINIT(sc->mii_dev);
+	return(0);
+}
+
+static int
+jmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	uint16_t bmcr;
+
+	switch (cmd) {
+	case MII_POLLSTAT:
+		/*
+		 * If we're not polling our PHY instance, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+			return (0);
+		break;
+
+	case MII_MEDIACHG:
+		/*
+		 * If the media indicates a different PHY instance,
+		 * isolate ourselves.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+			bmcr = PHY_READ(sc, MII_BMCR);
+			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
+			return (0);
+		}
+
+		/*
+		 * If the interface is not up, don't do anything.
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			break;
+
+		if (jmphy_auto(sc, ife) != EJUSTRETURN)
+			return (EINVAL);
+		break;
+
+	case MII_TICK:
+		/*
+		 * If we're not currently selected, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+			return (0);
+
+		/*
+		 * Is the interface even up?
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			return (0);
+
+		/*
+		 * Only used for autonegotiation.
+		 */
+		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+			sc->mii_ticks = 0;
+			break;
+		}
+
+		/* Check for link. */
+		if ((PHY_READ(sc, JMPHY_SSR) & JMPHY_SSR_LINK_UP) != 0) {
+			sc->mii_ticks = 0;
+			break;
+		}
+
+		/* Announce link loss right after it happens. */
+		if (sc->mii_ticks++ == 0)
+			break;
+		if (sc->mii_ticks <= sc->mii_anegticks)
+			return (0);
+
+		sc->mii_ticks = 0;
+		jmphy_auto(sc, ife);
+		break;
+	}
+
+	/* Update the media status. */
+	jmphy_status(sc);
+
+	/* Callback if something changed. */
+	mii_phy_update(sc, cmd);
+	return (0);
+}
+
+static void
+jmphy_status(struct mii_softc *sc)
+{
+	struct mii_data *mii = sc->mii_pdata;
+	int bmcr, ssr;
+
+	mii->mii_media_status = IFM_AVALID;
+	mii->mii_media_active = IFM_ETHER;
+
+	ssr = PHY_READ(sc, JMPHY_SSR);
+	if ((ssr & JMPHY_SSR_LINK_UP) != 0)
+		mii->mii_media_status |= IFM_ACTIVE;
+
+	bmcr = PHY_READ(sc, MII_BMCR);
+	if ((bmcr & BMCR_ISO) != 0) {
+		mii->mii_media_active |= IFM_NONE;
+		mii->mii_media_status = 0;
+		return;
+	}
+
+	if ((bmcr & BMCR_LOOP) != 0)
+		mii->mii_media_active |= IFM_LOOP;
+
+	if ((ssr & JMPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
+		/* Erg, still trying, I guess... */
+		mii->mii_media_active |= IFM_NONE;
+		return;
+	}
+
+	switch ((ssr & JMPHY_SSR_SPEED_MASK)) {
+	case JMPHY_SSR_SPEED_1000:
+		mii->mii_media_active |= IFM_1000_T;
+		/*
+		 * jmphy(4) got a valid link so reset mii_ticks.
+		 * Resetting mii_ticks is needed in order to
+		 * detect link loss after auto-negotiation.
+		 */
+		sc->mii_ticks = 0;
+		break;
+	case JMPHY_SSR_SPEED_100:
+		mii->mii_media_active |= IFM_100_TX;
+		sc->mii_ticks = 0;
+		break;
+	case JMPHY_SSR_SPEED_10:
+		mii->mii_media_active |= IFM_10_T;
+		sc->mii_ticks = 0;
+		break;
+	default:
+		mii->mii_media_active |= IFM_NONE;
+		return;
+	}
+
+	if ((ssr & JMPHY_SSR_DUPLEX) != 0)
+		mii->mii_media_active |= IFM_FDX;
+	else
+		mii->mii_media_active |= IFM_HDX;
+	/* XXX Flow-control. */
+#ifdef notyet
+	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
+		if ((PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0)
+			mii->mii_media_active |= IFM_ETH_MASTER;
+	}
+#endif
+}
+
+static void
+jmphy_reset(struct mii_softc *sc)
+{
+	struct jmphy_softc *jsc;
+	int i;
+
+	jsc = (struct jmphy_softc *)sc;
+
+	/* Disable sleep mode. */
+	PHY_WRITE(sc, JMPHY_TMCTL,
+	    PHY_READ(sc, JMPHY_TMCTL) & ~JMPHY_TMCTL_SLEEP_ENB);
+	PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN);
+
+	for (i = 0; i < 1000; i++) {
+		DELAY(1);
+		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
+			break;
+	}
+}
+
+static uint16_t
+jmphy_anar(struct ifmedia_entry *ife)
+{
+	uint16_t anar;
+
+	anar = 0;
+	switch (IFM_SUBTYPE(ife->ifm_media)) {
+	case IFM_AUTO:
+		anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
+		break;
+	case IFM_1000_T:
+		break;
+	case IFM_100_TX:
+		anar |= ANAR_TX | ANAR_TX_FD;
+		break;
+	case IFM_10_T:
+		anar |= ANAR_10 | ANAR_10_FD;
+		break;
+	default:
+		break;
+	}
+
+	return (anar);
+}
+
+static int
+jmphy_auto(struct mii_softc *sc, struct ifmedia_entry *ife)
+{
+	uint16_t anar, bmcr, gig;
+
+	gig = 0;
+	bmcr = PHY_READ(sc, MII_BMCR);
+	switch (IFM_SUBTYPE(ife->ifm_media)) {
+	case IFM_AUTO:
+		gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+		break;
+	case IFM_1000_T:
+		gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+		break;
+	case IFM_100_TX:
+	case IFM_10_T:
+		break;
+	case IFM_NONE:
+		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO | BMCR_PDOWN);
+		return (EJUSTRETURN);
+	default:
+		return (EINVAL);
+	}
+
+	if ((ife->ifm_media & IFM_LOOP) != 0)
+		bmcr |= BMCR_LOOP;
+
+	anar = jmphy_anar(ife);
+	/* XXX Always advertise pause capability. */
+	anar |= (3 << 10);
+
+	if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
+#ifdef notyet
+		struct mii_data *mii;
+
+		mii = sc->mii_pdata;
+		if ((mii->mii_media.ifm_media & IFM_ETH_MASTER) != 0)
+			gig |= GTCR_MAN_MS | GTCR_MAN_ADV;
+#endif
+		PHY_WRITE(sc, MII_100T2CR, gig);
+	}
+	PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
+	PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
+
+	return (EJUSTRETURN);
+}
diff --git a/sys/dev/mii/jmphyreg.h b/sys/dev/mii/jmphyreg.h
new file mode 100644
index 0000000..743ae29
--- /dev/null
+++ b/sys/dev/mii/jmphyreg.h
@@ -0,0 +1,108 @@
+/*-
+ * Copyright (c) 2008, Pyun YongHyeon
+ * All rights reserved.
+ *              
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:             
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.  
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_DEV_MII_JMPHYREG_H_
+#define	_DEV_MII_JMPHYREG_H_
+
+/*
+ * Registers for the JMicron JMC250 Gigabit PHY.
+ */
+
+/* PHY specific status register. */
+#define JMPHY_SSR			0x11
+#define JMPHY_SSR_SPEED_1000		0x8000
+#define JMPHY_SSR_SPEED_100		0x4000
+#define JMPHY_SSR_SPEED_10		0x0000
+#define JMPHY_SSR_SPEED_MASK		0xC000
+#define JMPHY_SSR_DUPLEX		0x2000
+#define JMPHY_SSR_SPD_DPLX_RESOLVED	0x0800
+#define JMPHY_SSR_LINK_UP		0x0400
+#define JMPHY_SSR_MDI_XOVER		0x0040
+#define	JMPHY_SSR_INV_POLARITY		0x0002
+
+/* PHY specific cable length status register. */
+#define	JMPHY_SCL			0x17
+#define	JMPHY_SCL_CHAN_D_MASK		0xF000
+#define	JMPHY_SCL_CHAN_C_MASK		0x0F00
+#define	JMPHY_SCL_CHAN_B_MASK		0x00F0
+#define	JMPHY_SCL_CHAN_A_MASK		0x000F
+#define	JMPHY_SCL_LEN_35		0
+#define	JMPHY_SCL_LEN_40		1
+#define	JMPHY_SCL_LEN_50		2
+#define	JMPHY_SCL_LEN_60		3
+#define	JMPHY_SCL_LEN_70		4
+#define	JMPHY_SCL_LEN_80		5
+#define	JMPHY_SCL_LEN_90		6
+#define	JMPHY_SCL_LEN_100		7
+#define	JMPHY_SCL_LEN_110		8
+#define	JMPHY_SCL_LEN_120		9
+#define	JMPHY_SCL_LEN_130		10
+#define	JMPHY_SCL_LEN_140		11
+#define	JMPHY_SCL_LEN_150		12
+#define	JMPHY_SCL_LEN_160		13
+#define	JMPHY_SCL_LEN_170		14
+#define	JMPHY_SCL_RSVD			15
+
+/* PHY specific LED control register 1. */
+#define	JMPHY_LED_CTL1			0x18
+#define	JMPHY_LED_BLINK_42MS		0x0000
+#define	JMPHY_LED_BLINK_84MS		0x2000
+#define	JMPHY_LED_BLINK_170MS		0x4000
+#define	JMPHY_LED_BLINK_340MS		0x6000
+#define	JMPHY_LED_BLINK_670MS		0x8000
+#define	JMPHY_LED_BLINK_MASK		0xE000
+#define	JMPHY_LED_FLP_GAP_MASK		0x1F00
+#define	JMPHY_LED_FLP_GAP_DEFULT	0x1000
+#define	JMPHY_LED2_POLARITY_MASK	0x0030
+#define	JMPHY_LED1_POLARITY_MASK	0x000C
+#define	JMPHY_LED0_POLARITY_MASK	0x0003
+#define	JMPHY_LED_ON_LO_OFF_HI		0
+#define	JMPHY_LED_ON_HI_OFF_HI		1
+#define	JMPHY_LED_ON_LO_OFF_TS		2
+#define	JMPHY_LED_ON_HI_OFF_TS		3
+
+/* PHY specific LED control register 2. */
+#define	JMPHY_LED_CTL2			0x19
+#define	JMPHY_LED_NO_STRETCH		0x0000
+#define	JMPHY_LED_STRETCH_42MS		0x2000
+#define	JMPHY_LED_STRETCH_84MS		0x4000
+#define	JMPHY_LED_STRETCH_170MS		0x6000
+#define	JMPHY_LED_STRETCH_340MS		0x8000
+#define	JMPHY_LED_STRETCH_670MS		0xB000
+#define	JMPHY_LED_STRETCH_1300MS	0xC000
+#define	JMPHY_LED_STRETCH_2700MS	0xE000
+#define	JMPHY_LED2_MODE_MASK		0x0F00
+#define	JMPHY_LED1_MODE_MASK		0x00F0
+#define	JMPHY_LED0_MODE_MASK		0x000F
+
+/* PHY specific test mode control register. */
+#define	JMPHY_TMCTL			0x1A
+#define	JMPHY_TMCTL_SLEEP_ENB		0x1000
+
+#endif	/* _DEV_MII_JMPHYREG_H_ */
diff --git a/sys/dev/mii/miidevs b/sys/dev/mii/miidevs
index 0129199..ac77d51 100644
--- a/sys/dev/mii/miidevs
+++ b/sys/dev/mii/miidevs
@@ -60,6 +60,7 @@ oui ICPLUS			0x0090c3	IC Plus Corp.
 oui ICS				0x00a0be	Integrated Circuit Systems
 oui INTEL			0x00aa00	Intel
 oui JATO			0x00e083	Jato Technologies
+oui JMICRON			0x001b8c	JMicron Technologies
 oui LEVEL1			0x00207b	Level 1
 oui NATSEMI			0x080017	National Semiconductor
 oui QUALSEMI			0x006051	Quality Semiconductor
@@ -178,6 +179,10 @@ model INTEL I82553C		0x0035 i82553 10/100 media interface
 /* Jato Technologies PHYs */
 model JATO BASEX		0x0000 Jato 1000baseX media interface
 
+/* JMicron Technologies PHYs */
+model JMICRON JMP211		0x0021 JMP211 10/100/1000 media interface
+model JMICRON JMP202		0x0022 JMP202 10/100 media interface
+
 /* Level 1 PHYs */
 model xxLEVEL1 LXT970		0x0000 LXT970 10/100 media interface