- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events)

- New manpages with event lists.
- Add MSRs for the Intel Sandy Bridge microarchitecture

Reviewed by:	attilio, brueffer, fabient
Approved by:	gnn (mentor)
MFC after:	3 weeks

10 files changed, 1946 insertions, 177 deletions

diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile
index 85ddf0f..350c22f 100644
--- a/lib/libpmc/Makefile
+++ b/lib/libpmc/Makefile
@@ -35,6 +35,8 @@ MAN+=	pmc.p5.3
 MAN+=	pmc.p6.3
 MAN+=	pmc.corei7.3
 MAN+=	pmc.corei7uc.3
+MAN+=	pmc.sandybridge.3
+MAN+=	pmc.sandybridgeuc.3	
 MAN+=	pmc.westmere.3
 MAN+=	pmc.westmereuc.3
 MAN+=	pmc.tsc.3
diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c
index ba63ace..a8378e9 100644
--- a/lib/libpmc/libpmc.c
+++ b/lib/libpmc/libpmc.c
@@ -179,6 +179,11 @@ static const struct pmc_event_descr corei7_event_table[] =
 	__PMC_EV_ALIAS_COREI7()
 };
 
+static const struct pmc_event_descr sandybridge_event_table[] = 
+{
+	__PMC_EV_ALIAS_SANDYBRIDGE()
+};
+
 static const struct pmc_event_descr westmere_event_table[] =
 {
 	__PMC_EV_ALIAS_WESTMERE()
@@ -189,6 +194,11 @@ static const struct pmc_event_descr corei7uc_event_table[] =
 	__PMC_EV_ALIAS_COREI7UC()
 };
 
+static const struct pmc_event_descr sandybridgeuc_event_table[] =
+{
+	__PMC_EV_ALIAS_SANDYBRIDGEUC()
+};
+
 static const struct pmc_event_descr westmereuc_event_table[] =
 {
 	__PMC_EV_ALIAS_WESTMEREUC()
@@ -208,6 +218,7 @@ PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC);
 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC);
@@ -242,9 +253,11 @@ PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
+PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
+PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
 #endif
 #if	defined(__i386__)
@@ -530,6 +543,8 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = {
 #define	atom_aliases_without_iaf	core2_aliases_without_iaf
 #define corei7_aliases			core2_aliases
 #define corei7_aliases_without_iaf	core2_aliases_without_iaf
+#define sandybridge_aliases		core2_aliases
+#define sandybridge_aliases_without_iaf	core2_aliases_without_iaf
 #define westmere_aliases		core2_aliases
 #define westmere_aliases_without_iaf	core2_aliases_without_iaf
 
@@ -2562,6 +2577,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
 			ev = corei7_event_table;
 			count = PMC_EVENT_TABLE_SIZE(corei7);
 			break;
+		case PMC_CPU_INTEL_SANDYBRIDGE:
+			ev = sandybridge_event_table;
+			count = PMC_EVENT_TABLE_SIZE(sandybridge);
+			break;
 		case PMC_CPU_INTEL_WESTMERE:
 			ev = westmere_event_table;
 			count = PMC_EVENT_TABLE_SIZE(westmere);
@@ -2583,6 +2602,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
 			ev = corei7uc_event_table;
 			count = PMC_EVENT_TABLE_SIZE(corei7uc);
 			break;
+		case PMC_CPU_INTEL_SANDYBRIDGE:
+			ev = sandybridgeuc_event_table;
+			count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
+			break;
 		case PMC_CPU_INTEL_WESTMERE:
 			ev = westmereuc_event_table;
 			count = PMC_EVENT_TABLE_SIZE(westmereuc);
@@ -2814,6 +2837,11 @@ pmc_init(void)
 		pmc_class_table[n++] = &corei7uc_class_table_descr;
 		PMC_MDEP_INIT_INTEL_V2(corei7);
 		break;
+	case PMC_CPU_INTEL_SANDYBRIDGE:
+		pmc_class_table[n++] = &ucf_class_table_descr;
+		pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
+		PMC_MDEP_INIT_INTEL_V2(sandybridge);
+		break;
 	case PMC_CPU_INTEL_WESTMERE:
 		pmc_class_table[n++] = &ucf_class_table_descr;
 		pmc_class_table[n++] = &westmereuc_class_table_descr;
@@ -2937,6 +2965,10 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
 			ev = corei7_event_table;
 			evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
 			break;
+		case PMC_CPU_INTEL_SANDYBRIDGE:
+			ev = sandybridge_event_table;
+			evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
+			break;
 		case PMC_CPU_INTEL_WESTMERE:
 			ev = westmere_event_table;
 			evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
@@ -2953,6 +2985,10 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
 			ev = corei7uc_event_table;
 			evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
 			break;
+		case PMC_CPU_INTEL_SANDYBRIDGE:
+			ev = sandybridgeuc_event_table;
+			evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc);
+			break;
 		case PMC_CPU_INTEL_WESTMERE:
 			ev = westmereuc_event_table;
 			evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
diff --git a/lib/libpmc/pmc.sandybridge.3 b/lib/libpmc/pmc.sandybridge.3
new file mode 100644
index 0000000..c636c4f
--- /dev/null
+++ b/lib/libpmc/pmc.sandybridge.3
@@ -0,0 +1,932 @@
+.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org>  
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd February 12, 2012
+.Dt PMC.SANDYBRIDGE 3 
+.Os 
+.Sh NAME
+.Nm pmc.sandybridge
+.Nd measurement events for 
+.Tn Intel
+.Tn Sandy Bridge
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+.Tn Intel
+.Tn "Sandy Bridge"
+CPUs contain PMCs conforming to the version 3 of the
+.Tn Intel
+performance measurement architecture.
+These CPUs may contain up to three classes of PMCs:
+.Bl -tag -width "Li PMC_CLASS_IAP"
+.It Li PMC_CLASS_IAF
+Fixed-function counters that count only one hardware event per counter.
+.It Li PMC_CLASS_IAP
+Programmable counters that may be configured to count one of a defined
+set of hardware events.
+.It Li PMC_CLASS_TSC
+These PMCs are documented in
+.Xr pmc.tsc 3 .
+.El
+.Pp
+The number of PMCs available in each class and their widths need to be
+determined at run time by calling 
+.Xr pmc_cpuinfo 3 .
+.Pp
+Intel Sandy Bridge PMCs are documented in 
+.Rs
+.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
+.%T "Volume 3B: System Programming Guide, Part 2"
+.%N "Order Number: 253669-039US"
+.%D May 2011
+.%Q "Intel Corporation"
+.Re
+.Ss SANDY BRIDGE FIXED FUNCTION PMCS
+These PMCs and their supported events are documented in
+.Xr pmc.iaf 3 .
+.Ss SANDY BRIDGE PROGRAMMABLE PMCS
+The programmable PMCs support the following capabilities:
+.Bl -column "PMC_CAP_INTERRUPT" "Support"
+.It Em Capability Ta Em Support
+.It PMC_CAP_CASCADE Ta \&No
+.It PMC_CAP_EDGE Ta Yes 
+.It PMC_CAP_INTERRUPT Ta Yes
+.It PMC_CAP_INVERT Ta Yes
+.It PMC_CAP_READ Ta Yes
+.It PMC_CAP_PRECISE Ta \&No
+.It PMC_CAP_SYSTEM Ta Yes
+.It PMC_CAP_TAGGING Ta \&No
+.It PMC_CAP_THRESHOLD Ta Yes
+.It PMC_CAP_USER Ta Yes
+.It PMC_CAP_WRITE Ta Yes
+.El
+.Ss Event Qualifiers
+Event specifiers for these PMCs support the following common
+qualifiers:
+.Bl -tag -width indent
+.It Li rsp= Ns Ar value
+Configure the Off-core Response bits.
+.Bl -tag -width indent
+.It Li DMND_DATA_RD
+Counts the number of demand and DCU prefetch data reads of full
+and partial cachelines as well as demand data page table entry
+cacheline reads. 
+Does not count L2 data read prefetches or instruction fetches.
+.It Li DMND_RFO
+Counts the number of demand and DCU prefetch reads for ownership
+(RFO) requests generated by a write to data cacheline. 
+Does not count L2 RFO.
+.It Li DMND_IFETCH
+Counts the number of demand and DCU prefetch instruction cacheline
+reads. 
+Does not count L2 code read prefetches.
+.It Li WB
+Counts the number of writeback (modified to exclusive) transactions.
+.It Li PF_DATA_RD
+Counts the number of data cacheline reads generated by L2 prefetchers.
+.It Li PF_RFO
+Counts the number of RFO requests generated by L2 prefetchers.
+.It Li PF_IFETCH
+Counts the number of code reads generated by L2 prefetchers.
+.It Li OTHER
+Counts one of the following transaction types, including L3 invalidate,
+I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
+lock, unlock, split lock.
+.It Li UNCORE_HIT
+L3 Hit: local or remote home requests that hit L3 cache in the uncore
+with no coherency actions required (snooping).
+.It Li OTHER_CORE_HIT_SNP
+L3 Hit: local or remote home requests that hit L3 cache in the uncore
+and was serviced by another core with a cross core snoop where no modified
+copies were found (clean).
+.It Li OTHER_CORE_HITM
+L3 Hit: local or remote home requests that hit L3 cache in the uncore
+and was serviced by another core with a cross core snoop where modified
+copies were found (HITM).
+.It Li REMOTE_CACHE_FWD
+L3 Miss: local homed requests that missed the L3 cache and was serviced
+by forwarded data following a cross package snoop where no modified
+copies found. 
+(Remote home requests are not counted)
+.It Li REMOTE_DRAM
+L3 Miss: remote home requests that missed the L3 cache and were serviced
+by remote DRAM.
+.It Li LOCAL_DRAM
+L3 Miss: local home requests that missed the L3 cache and were serviced
+by local DRAM.
+.It Li NON_DRAM
+Non-DRAM requests that were serviced by IOH.
+.El
+.It Li cmask= Ns Ar value
+Configure the PMC to increment only if the number of configured
+events measured in a cycle is greater than or equal to
+.Ar value .
+.It Li edge
+Configure the PMC to count the number of de-asserted to asserted
+transitions of the conditions expressed by the other qualifiers.
+If specified, the counter will increment only once whenever a
+condition becomes true, irrespective of the number of clocks during
+which the condition remains true.
+.It Li inv
+Invert the sense of comparison when the
+.Dq Li cmask
+qualifier is present, making the counter increment when the number of
+events per cycle is less than the value specified by the
+.Dq Li cmask
+qualifier.
+.It Li os
+Configure the PMC to count events happening at processor privilege
+level 0.
+.It Li usr
+Configure the PMC to count events occurring at privilege levels 1, 2
+or 3.
+.El
+.Pp
+If neither of the
+.Dq Li os
+or
+.Dq Li usr
+qualifiers are specified, the default is to enable both.
+.Ss Event Specifiers (Programmable PMCs)
+Sandy Bridge programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li LD_BLOCKS.DATA_UNKNOWN
+.Pq EVENT_03H, Umask 01H 
+Blocked loads due to store buffer blocks with unknown data.
+.It Li LD_BLOCKS.STORE_FORWARD
+.Pq Event 03H, Umask 02H 
+Loads blocked by overlapping with store buffer that cannot be forwarded.
+.It Li LD_BLOCKS.NO_SR
+.Pq Event 03H, Umask 08H 
+# of Split loads blocked due to resource not available.
+.It Li LD_BLOCKS.ALL_BLOCK 
+.Pq EVENT_03H, Umask 10H 
+Number of cases where any load is blocked but has no DCU miss.
+.It Li  MISALIGN_MEM_REF.LOADS 
+.Pq Event 05H, Umask  01H 
+Speculative cache-line split load uops dispatched to L1D.
+.It Li MISALIGN_MEM_REF.STORES
+.Pq Event 05H, Umask  02H 
+Speculative cache-line split Store-address uops dispatched to L1D.
+.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
+.Pq Event 07H, Umask  01H 
+False dependencies in MOB due to partial compare on address.
+.It Li LD_BLOCKS_PARTIAL.ALL_STA_BLOCK 
+.Pq Event 07H, Umask 08H 
+The number of times that load operations are temporarily blocked because of 
+older stores, with addresses that are not yet known. 
+A load operation may incur more than one block of this type.
+.It LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 08H, Umask 01H 
+Misses in all TLB levels that cause a page walk of any page size.
+.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 
+.Pq Event 08H, Umask 02H 
+Misses in all TLB levels that caused page walk completed of any size.
+.It Li DTLB_LOAD_MISSES.WALK_DURATION 
+.Pq Event 08H, Umask 04H 
+Cycle PMH is busy with a walk.
+.It Li DTLB_LOAD_MISSES.STLB_HIT
+.Pq Event 08H, Umask 10H 
+Number of cache load STLB hits. 
+No page walk.
+.It Li INT_MISC.RECOVERY_CYCLES 
+.Pq Event 0DH, Umask 03H 
+Cycles waiting to recover after Machine Clears or JEClear. 
+Set Cmask = 1.
+Set Edge to count occurrences
+.It Li INT_MISC.RAT_STALL_CYCLES 
+.Pq Event 0DH, Umask 40H 
+Cycles RAT external stall is sent to IDQ for this thread.
+.It Li UOPS_ISSUED.ANY
+.Pq Event 0EH, Umask 01H 
+Increments each cycle the # of Uops issued by the RAT to RS. 
+Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core.
+Set Cmask = 1, Inv = 1 to count stalled cycles
+.It Li FP_COMP_OPS_EXE.X87 
+.Pq Event 10H, Umask 01H 
+Counts number of X87 uops executed.
+.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE 
+.Pq Event 10H, Umask 10H 
+Counts number of SSE* double precision FP packed uops executed.
+.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE
+.Pq Event 10H, Umask 20H 
+Counts number of SSE* single precision FP scalar uops executed.
+.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE
+.Pq Event 10H, Umask 40H
+Counts number of SSE* single precision FP packed uops executed.
+.It LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE 
+.Pq Event 10H, Umask 80H
+Counts number of SSE* double precision FP scalar uops executed.
+.It Li SIMD_FP_256.PACKED_SINGLE
+.Pq Event 11H, Umask 01H 
+Counts 256-bit packed single-precision floating-point instructions.
+.It Li SIMD_FP_256.PACKED_DOUBLE
+.Pq Event 11H, Umask 02H
+Counts 256-bit packed double-precision floating-point instructions.
+.It Li ARITH.FPU_DIV_ACTIVE
+.Pq Event 14H, Umask 01H 
+Cycles that the divider is active, includes INT and FP.
+Set 'edge =1, cmask=1' to count the number of divides.
+.It Li INSTS_WRITTEN_TO_IQ.INSTS 
+.Pq Event 17H, Umask 01H 
+Counts the number of instructions written into the IQ every cycle.
+.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 
+.Pq Event 24H, Umask 01H 
+Demand Data Read requests that hit L2 cache.
+.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
+.Pq Event 24H, Umask 03H 
+Counts any demand and L1 HW prefetch data load requests to L2.
+.It Li L2_RQSTS.RFO_HITS
+.Pq Event 24H, Umask 04H
+Counts the number of store RFO requests that hit the L2 cache.
+.It Li L2_RQSTS.RFO_MISS 
+.Pq Event 24H, Umask 08H
+Counts the number of store RFO requests that miss the L2 cache.
+.It Li L2_RQSTS.ALL_RFO 
+.Pq Event 24H, Umask 0CH 
+Counts all L2 store RFO requests.
+.It Li L2_RQSTS.CODE_RD_HIT 
+.Pq Event 24H, Umask 10H
+Number of instruction fetches that hit the L2 cache.
+.It Li L2_RQSTS.CODE_RD_MISS 
+.Pq Event 24H, Umask 20H
+Number of instruction fetches that missed the L2 cache.
+.It Li L2_RQSTS.ALL_CODE_RD 
+.Pq Event 24H, Umask 30H 
+Counts all L2 code requests.
+.It Li L2_RQSTS.PF_HIT 
+.Pq Event 24H, Umask 40H 
+Requests from L2 Hardware prefetcher that hit L2.
+.It Li L2_RQSTS.PF_MISS 
+.Pq Event 24H, Umask 80H
+Requests from L2 Hardware prefetcher that missed L2.
+.It Li L2_RQSTS.ALL_PF 
+.Pq Event 24H, Umask C0H
+Any requests from L2 Hardware prefetchers.
+.It Li L2_STORE_LOCK_RQSTS.MISS 
+.Pq Event 27H, Umask 01H 
+RFOs that miss cache lines.
+.It Li L2_STORE_LOCK_RQSTS.HIT_E 
+.Pq Event 27H, Umask 04H 
+RFOs that hit cache lines in E state.
+.It Li L2_STORE_LOCK_RQSTS.HIT_M
+.Pq EVENT_27H, Umask 08H
+RFOs that hit cache lines in M state.
+.It Li L2_STORE_LOCK_RQSTS.ALL 
+.Pq EVENT_27H, Umask 0FH 
+RFOs that access cache lines in any state.
+.It Li L2_L1D_WB_RQSTS.HIT_E 
+.Pq Event 28H, Umask 04H 
+Not rejected writebacks from L1D to L2 cache lines in E state.
+.It Li L2_L1D_WB_RQSTS.HIT_M 
+.Pq Event 28H, Umask 08H 
+Not rejected writebacks from L1D to L2 cache lines in M state.
+.It Li LONGEST_LAT_CACHE.REFERENCE 
+.Pq Event 2EH, Umask 4FH
+This event counts requests originating from the core that reference a cache 
+line in the last level cache.
+.It Li LONGEST_LAT_CACHE.MISS 
+.Pq Event 2EH, Umask 41H 
+This event counts each cache miss condition for references to the last level 
+cache.
+.It Li CPU_CLK_UNHALTED.THREAD_P 
+.Pq Event 3CH, Umask 00H 
+Counts the number of thread cycles while the thread is not in a halt state. 
+The thread enters the halt state when it is running the HLT instruction. 
+The core frequency may change from time to time due to power or thermal 
+throttling.
+.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 
+.Pq Event 3CH, Umask 01H 
+Increments at the frequency of XCLK (100 MHz) when not halted.
+.It Li L1D_PEND_MISS.PENDING 
+.Pq Event 48H, Umask 01H 
+Increments the number of outstanding L1D misses every cycle. 
+Set Cmask = 1 and Edge =1  to count occurrences.
+Counter 2 only; Set Cmask = 1 to count cycles.
+.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 
+.Pq Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any 
+page size (4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED 
+.Pq Event 49H, Umask 02H 
+Miss in all TLB levels causes a page walk that completes of any page size 
+(4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_DURATION 
+.Pq Event 49H, Umask 04H 
+Cycles PMH is busy with this walk.
+.It Li DTLB_STORE_MISSES.STLB_HIT 
+.Pq Event 49H, Umask 10H 
+Store operations that miss the first TLB level but hit the second and do not 
+cause page walks.
+.It Li LOAD_HIT_PRE.SW_PF 
+.Pq Event 4CH, Umask 01H 
+Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
+.It Li LOAD_HIT_PER.HW_PF 
+.Pq Event 4CH, Umask 02H 
+Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
+.It Li HW_PRE_REQ.DL1_MISS 
+.Pq Event 4EH, Umask 02H 
+Hardware Prefetch requests that miss the L1D cache.  
+A request is being counted each time it access the cache & miss it, including 
+if a block is applicable or if hit the Fill Buffer for example.
+This accounts for both L1 streamer and IP-based (IPP) HW prefetchers.
+.It Li L1D.REPLACEMENT 
+.Pq Event 51H, Umask 01H
+Counts the number of lines brought into the L1 data cache.
+.It Li L1D.ALLOCATED_IN_M 
+.Pq Event 51H, Umask 02H 
+Counts the number of allocations of modified L1D cache lines.
+.It Li L1D.EVICTION
+.Pq Event 51H, Umask 04H
+Counts the number of modified lines evicted from the L1 data cache due to 
+replacement.
+.It Li L1D.ALL_M_REPLACEMENT
+.Pq Event 51H, Umask 08H 
+Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line 
+replacement.
+.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP
+.Pq Event 59H, Umask 20H 
+Increments the number of flags-merge uops in flight each cycle.
+Set Cmask = 1 to count cycles.
+.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW
+.Pq Event 59H, Umask 40H 
+Cycles with at least one slow LEA uop allocated.
+.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP
+.Pq Event 59H, Umask 80H 
+Number of Multiply packed/scalar single precision uops allocated.
+.It Li RESOURCE_STALLS2.ALL_FL_EMPTY 
+.Pq Event 5BH, Umask 0CH 
+Cycles stalled due to free list empty.
+.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL 
+.Pq Event 5BH, Umask 0FH 
+Cycles stalled due to control structures full for physical registers.
+.It Li RESOURCE_STALLS2.BOB_FULL 
+.Pq Event 5BH, Umask 40H 
+Cycles Allocator is stalled due to Branch Order Buffer.
+.It Li RESOURCE_STALLS2.OOO_RSRC
+.Pq Event 5BH, Umask 4FH 
+Cycles stalled due to out of order resources full.
+.It Li CPL_CYCLES.RING0
+.Pq Event 5CH, Umask 01H 
+Unhalted core cycles when the thread is in ring 0.
+Use Edge to count transition
+.It Li CPL_CYCLES.RING123
+.Pq Event 5CH, Umask 02H
+Unhalted core cycles when the thread is not in ring 0.
+.It Li RS_EVENTS.EMPTY_CYCLES
+.Pq Event 5EH, Umask 01H 
+Cycles the RS is empty for the thread.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
+.Pq Event 60H, Umask 01H 
+Offcore outstanding Demand Data Read transactions in SQ to uncore.
+Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
+.Pq Event 60H, Umask 04H 
+Offcore outstanding RFO store transactions in SQ to uncore.
+Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
+.Pq Event 60H, Umask 08H 
+Offcore outstanding cacheable data read transactions in SQ to uncore.
+Set Cmask=1 to count cycles.
+.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
+.Pq Event 63H, Umask 01H 
+Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
+.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
+.Pq Event 63H, Umask 02H
+Cycles in which the L1D is locked.
+.It Li IDQ.EMPTY
+.Pq Event 79H, Umask 02H 
+Counts cycles the IDQ is empty.
+.It Li IQD.MITE_UOPS 
+.Pq Event 79H, Umask 04H 
+Increment each cycle # of uops delivered to IDQ from MITE path. 
+Set Cmask = 1 to count cycles.
+Can combine Umask 04H and 20H
+.It Li IDQ.DSB_UOPS
+.Pq Event 79H, Umask 08H 
+Increment each cycle. 
+# of uops delivered to IDQ from DSB path. 
+Set Cmask = 1 to count cycles.
+Can combine Umask 08H and 10H
+.It Li IDQ.MS_DSB_UOPS 
+.Pq Event 79H, Umask 10H 
+Increment each cycle # of uops delivered to IDQ when MS busy by DSB. 
+Set Cmask = 1 to count cycles MS is busy. 
+Set Cmask=1 and Edge=1 to count MS activations.
+Can combine Umask 08H and 10H
+.It Li IDQ.MS_MITE_UOPS
+.Pq Event 79H, Umask 20H 
+Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. 
+Set Cmask = 1 to count cycles.
+Can combine Umask 04H and 20H
+.It Li IDQ.MS_UOPS 
+.Pq Event 79H, Umask 30H 
+Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. 
+Set Cmask = 1 to count cycles.
+Can combine Umask 04H, 08H and 30H
+.It Li ICACHE.MISSES
+.Pq Event 80H, Umask 02H
+Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
+Includes UC accesses.
+.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 85H, Umask 01H
+Misses in all ITLB levels that cause page walks.
+.It Li ITLB_MISSES.WALK_COMPLETED
+.Pq Event 85H, Umask 02H 
+Misses in all ITLB levels that cause completed page walks.
+.It Li ITLB_MISSES.WALK_DURATION 
+.Pq Event 85H, Umask 04H 
+Cycle PMH is busy with a walk.
+.It Li ITLB_MISSES.STLB_HIT
+.Pq Event 85H, Umask 10H 
+Number of cache load STLB hits. 
+No page walk.
+.It Li ILD_STALL.LCP
+.Pq Event 87H, Umask 01H 
+Stalls caused by changing prefix length of the instruction.
+.It Li ILD_STALL.IQ_FULL
+.Pq Event 87H, Umask 04H 
+Stall cycles due to IQ is full.
+.It Li BR_INST_EXEC.COND
+.Pq Event 88H, Umask 01H 
+Qualify conditional near branch instructions executed, but not necessarily 
+retired.
+Must combine with umask 40H, 80H
+.It Li BR_INST_EXEC.DIRECT_JMP 
+.Pq Event 88H, Umask 02H 
+Qualify all unconditional near branch instructions excluding calls and indirect 
+branches.
+Must combine with umask 80H
+.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 88H, Umask 04H 
+Qualify executed indirect near branch instructions that are not calls nor 
+returns.
+Must combine with umask 80H
+.It Li BR_INST_EXEC.RETURN_NEAR
+.Pq Event 88H, Umask 08H 
+Qualify indirect near branches that have a return mnemonic.
+Must combine with umask 80H
+.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
+.Pq Event 88H, Umask 10H
+Qualify unconditional near call branch instructions, excluding non call branch,
+executed.
+Must combine with umask 80H
+.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 88H, Umask 20H 
+Qualify indirect near calls, including both register and memory indirect, 
+executed.
+Must combine with umask 80H
+.It Li BR_INST_EXEC.NONTAKEN
+.Pq Event 88H, Umask 40H 
+Qualify non-taken near branches executed.
+Applicable to umask 01H only
+.It Li BR_INST_EXEC.TAKEN
+.Pq Event 88H, Umask 80H 
+Qualify taken near branches executed.  
+Must combine with 01H,02H, 04H, 08H, 10H, 20H
+.It Li BR_INST_EXE.ALL_BRANCHES
+.Pq Event 88H, Umask FFH 
+Counts all near executed branches (not necessarily retired).
+.It Li BR_MISP_EXEC.COND
+.Pq Event 89H, Umask 01H 
+Qualify conditional near branch instructions mispredicted. 
+Must combine with umask 40H, 80H
+.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 89H, Umask 04H 
+Qualify mispredicted indirect near branch instructions that are not calls nor 
+returns.
+Must combine with umask 80H
+.It Li BR_MISP_EXEC.RETURN_NEAR 
+.Pq Event 89H, Umask 08H 
+Qualify mispredicted indirect near branches that have a return mnemonic.
+Must combine with umask 80H
+.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
+.Pq Event 89H, Umask 10H 
+Qualify mispredicted unconditional near call branch instructions, excluding non 
+call branch, executed.
+Must combine with umask 80H
+.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 89H, Umask 20H 
+Qualify mispredicted indirect near calls, including both register and memory 
+indirect, executed.
+Must combine with umask 80H
+.It Li BR_MISP_EXEC.NONTAKEN
+.Pq Event 89H, Umask 40H 
+Qualify mispredicted non-taken near branches executed.
+Applicable to umask 01H only
+.It Li BR_MISP_EXEC.TAKEN 
+.Pq Event 89H, Umask 80H
+Qualify mispredicted taken near branches executed.
+Must combine with 01H,02H, 04H, 08H, 10H, 20H
+.It Li BR_MISP_EXEC.ALL_BRANCHES
+.Pq Event 89H, Umask FFH
+Counts all near executed branches (not necessarily retired).
+.It Li IDQ_UOPS_NOT_DELIVERED.CORE
+.Pq Event 9CH, Umask 01H 
+Count number of non-delivered uops to RAT per thread.
+Use Cmask to qualify uop b/w
+.It Li UOPS_DISPATCHED_PORT.PORT_0
+.Pq Event A1H, Umask 01H
+Cycles which a Uop is dispatched on port 0.
+.It Li UOPS_DISPATCHED_PORT.PORT_1
+.Pq Event A1H, Umask 02H
+Cycles which a Uop is dispatched on port 1.
+.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
+.Pq Event A1H, Umask 04H 
+Cycles which a load uop is dispatched on port 2.
+.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
+.Pq Event A1H, Umask 08H
+Cycles which a store address uop is dispatched on port 2.
+.It Li UOPS_DISPATCHED_PORT.PORT_2
+.Pq Event A1H, Umask 0CH 
+Cycles which a Uop is dispatched on port 2.
+.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
+.Pq Event A1H, Umask 10H 
+Cycles which a load uop is dispatched on port 3.
+.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 
+.Pq Event A1H, Umask 20H 
+Cycles which a store address uop is dispatched on port 3.
+.It Li UOPS_DISPATCHED_PORT.PORT_3 
+.Pq Event A1H, Umask 30H 
+.Pq Cycles which a Uop is dispatched on port 3.
+.It Li UOPS_DISPATCHED_PORT.PORT_4 
+.Pq Event A1H, Umask 40H
+Cycles which a Uop is dispatched on port 4.
+.It Li UOPS_DISPATCHED_PORT.PORT_5
+.Pq Event A1H, Umask 80H 
+Cycles which a Uop is dispatched on port 5.
+.It Li RESOURCE_STALLS.ANY
+.Pq Event A2H, Umask 01H
+Cycles Allocation is stalled due to Resource Related reason.
+.It Li RESOURCE_STALLS.LB
+.Pq Event A2H, Umask 02H
+Counts the cycles of stall due to lack of load buffers.
+.It Li RESOURCE_STALLS.LB
+.Pq Event A2H, Umask 04H 
+Cycles stalled due to no eligible RS entry available.
+.It Li RESOURCE_STALLS.SB
+.Pq Event A2H, Umask 08H 
+Cycles stalled due to no store buffers available. 
+(not including draining form sync)
+.It Li RESOURCE_STALLS.ROB
+.Pq Event A2H, Umask 10H
+Cycles stalled due to re-order buffer full.
+.It Li RESOURCE_STALLS.FCSW
+.Pq Event A2H, Umask 20H 
+Cycles stalled due to writing the FPU control word.
+.It Li RESOURCE_STALLS.MXCSR
+.Pq Event A2H, Umask 40H
+Cycles stalled due to the MXCSR register rename occurring to close to a previous 
+MXCSR rename.
+.It Li RESOURCE_STALLS.OTHER
+.Pq Event A2H, Umask 80H 
+Cycles stalled while execution was stalled due to other resource issues.
+.It Li DSB2MITE_SWITCHES.COUNT
+.Pq Event ABH, Umask 01H
+Number of DSB to MITE switches.
+.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
+.Pq Event ABH, Umask 02H 
+Cycles DSB to MITE switches caused delay.
+.It Li DSB_FILL.OTHER_CANCEL
+.Pq Event ACH, Umask 02H
+Cases of cancelling valid DSB fill not because of exceeding way limit.
+.It Li DSB_FILL.EXCEED_DSB_LINES
+.Pq Event ACH, Umask 08H
+DSB Fill encountered > 3 DSB lines.
+.It Li DSB_FILL.ALL_CANCEL
+.Pq Event ACH, Umask 0AH 
+Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding 
+way limit.
+.It Li ITLB.ITLB_FLUSH
+.Pq Event AEH, Umask 01H
+Counts the number of ITLB flushes, includes 4k/2M/4M pages.
+.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
+.Pq Event B0H, Umask 01H 
+Demand data read requests sent to uncore.
+.It Li OFFCORE_REQUESTS.DEMAND_RFO 
+.Pq Event B0H, Umask 04H 
+Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.
+.It Li OFFCORE_REQUESTS.ALL_DATA_RD
+.Pq Event B0H, Umask 08H 
+Data read requests sent to uncore (demand and prefetch).
+.It Li UOPS_DISPATCHED.THREAD
+.Pq Event B1H, Umask 01H 
+Counts total number of uops to be dispatched per-thread each cycle.
+Set Cmask = 1, INV =1 to count stall cycles.
+.It Li UOPS_DISPATCHED.CORE
+.Pq Event B1H, Umask 02H 
+Counts total number of uops to be dispatched per-core each cycle.
+Do not need to set ANY
+.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL
+.Pq Event B2H, Umask 01H 
+Offcore requests buffer cannot take more entries for this thread core.
+.It Li AGU_BYPASS_CANCEL.COUNT
+.Pq Event B6H, Umask 01H 
+Counts executed load operations with all the following traits: 1. addressing 
+of the format [base + offset], 2. the offset is between 1 and 2047, 3. the 
+address specified in the base register is in one page and the address 
+[base+offset] is in another page.
+.It Li OFF_CORE_RESPONSE_0 
+.Pq Event B7H, Umask 01H
+Off-core Response Performance Monitoring; PMC0 only.
+Requires programming MSR 01A6H
+.It Li OFF_CORE_RESPONSE_1 
+.Pq Event BBH, Umask 01H
+Off-core Response Performance Monitoring. PMC3 only.
+Requires programming MSR 01A7H
+.It Li TLB_FLUSH.DTLB_THREAD
+.Pq Event BDH, Umask 01H
+DTLB flush attempts of the thread-specific entries.
+.It Li TLB_FLUSH.STLB_ANY
+.Pq Event BDH, Umask 20H 
+Count number of STLB flush attempts.
+.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES
+.Pq Event BFH, Umask 05H 
+Cycles when dispatched loads are cancelled due to L1D bank conflicts with other
+load ports.
+cmask=1
+.It Li INST_RETIRED.ANY_P
+.Pq Event C0H, Umask 00H 
+Number of instructions at retirement.
+.It Li INST_RETIRED.PREC_DIST
+.Pq Event C0H, Umask 01H
+Precise instruction retired event with HW to reduce effect of PEBS shadow in IP 
+distribution PMC1 only; Must quiesce other PMCs.
+.It Li INST_RETIRED.X87
+.Pq Event C0H, Umask 02H 
+X87 instruction retired event.
+.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED
+.Pq Event C1H, Umask 02H 
+Instructions that experienced an ITLB miss.
+.It Li OTHER_ASSISTS.AVX_STORE
+.Pq Event C1H, Umask 08H  
+Number of assists associated with 256-bit AVX store operations.
+.It Li OTHER_ASSISTS.AVX_TO_SSE
+.Pq Event C1H, Umask 10H 
+Number of transitions from AVX256 to legacy SSE when penalty applicable.
+.It Li OTHER_ASSISTS.SSE_TO_AVX
+.Pq Event C1H, Umask 20H 
+Number of transitions from SSE to AVX-256 when penalty applicable.
+.It Li UOPS_RETIRED.ALL
+.Pq Event C2H, Umask 01H 
+Counts the number of micro-ops retired.
+Use cmask=1 and invert to count active cycles or stalled cycles.
+.It Li UOPS_RETIRED.RETIRE_SLOTS
+.Pq Event C2H, Umask 02H 
+Counts the number of retirement slots used each cycle.
+.It Li MACHINE_CLEARS.MEMORY_ORDERING
+.Pq Event C3H, Umask 02H 
+Counts the number of machine clears due to memory order conflicts.
+.It Li MACHINE_CLEARS.SMC 
+.Pq Event C3H, Umask 04H
+Counts the number of times that a program writes to a code section.
+.It Li MACHINE_CLEARS.MASKMOV
+.Pq Event C3H, Umask 20H
+Counts the number of executed AVX masked load operations that refer to an 
+illegal address range with the mask bits set to 0.
+.It Li BR_INST_RETIRED.ALL_BRANCH
+.Pq Event C4H, Umask 00H
+Branch instructions at retirement.
+.It Li BR_INST_RETIRED.CONDITIONAL
+.Pq Event C4H, Umask 01H 
+Counts the number of conditional branch instructions retired.
+.It Li BR_INST_RETIRED.NEAR_CALL
+.Pq Event C4H, Umask 02H 
+Direct and indirect near call instructions retired.
+.It Li BR_INST_RETIRED.ALL_BRANCHES
+.Pq Event C4H, Umask 04H
+Counts the number of branch instructions retired.
+.It Li BR_INST_RETIRED.NEAR_RETURN
+.Pq Event C4H, Umask 08H 
+Counts the number of near return instructions retired.
+.It Li BR_INST_RETIRED.NOT_TAKEN
+.Pq Event C4H, Umask 10H 
+Counts the number of not taken branch instructions retired.
+.It Li BR_INST_RETIRED.NEAR_TAKEN
+.Pq Event C4H, Umask 20H 
+Number of near taken branches retired.
+.It Li BR_INST_RETIRED.FAR_BRANCH
+.Pq Event C4H, Umask 40H 
+Number of far branches retired.
+.It Li BR_MISP_RETIRED.ALL_BRANCHES
+.Pq Event C5H, Umask 00H 
+Mispredicted branch instructions at retirement.
+.It Li BR_MISP_RETIRED.CONDITIONAL
+.Pq Event C5H, Umask 01H 
+Mispredicted conditional branch instructions retired.
+.It Li BR_MISP_RETIRED.NEAR_CALL
+.Pq Event C5H, Umask 02H 
+Direct and indirect mispredicted near call instructions retired.
+.It Li BR_MISP_RETIRED.ALL_BRANCH
+.Pq Event C5H, Umask 04H 
+Mispredicted macro branch instructions retired.
+.It Li BR_MISP_RETIRED.NOT_TAKEN
+.Pq Event C5H, Umask 10H 
+Mispredicted not taken branch instructions retired.
+.It Li BR_MISP_RETIRED.TAKEN
+.Pq Event C5H, Umask 20H 
+Mispredicted taken branch instructions retired.
+.It Li FP_ASSIST.X87_OUTPUT
+.Pq Event CAH, Umask 02H 
+Number of X87 assists due to output value.
+.It Li FP_ASSIST.X87_INPUT
+.Pq Event CAH, Umask 04H
+Number of X87 assists due to input value.
+.It Li FP_ASSIST.SIMD_OUTPUT
+.Pq Event CAH, Umask 08H
+Number of SIMD FP assists due to Output values.
+.It Li FP_ASSIST.SIMD_INPUT
+.Pq Event CAH, Umask 10H 
+Number of SIMD FP assists due to input values.
+.It Li FP_ASSIST.ANY
+.Pq Event CAH, Umask 1EH 
+Cycles with any input/output SSE* or FP assists.
+.It Li ROB_MISC_EVENTS.LBR_INSERTS
+.Pq Event CCH, Umask 20H 
+Count cases of saving new LBR records by hardware.
+.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
+.Pq Event CDH, Umask 01H
+Sample loads with specified latency threshold. 
+PMC3 only. 
+Specify threshold in MSR 0x3F6.
+.It Li MEM_TRANS_RETIRED.PRECISE_STORE
+.Pq Event CDH, Umask 02H 
+Sample stores and collect precise store operation via PEBS record. 
+PMC3 only.
+.It Li MEM_UOP_RETIRED.LOADS
+.Pq Event D0H, Umask 01H
+Qualify retired memory uops that are loads. 
+Combine with umask 10H, 20H, 40H, 80H.
+.It Li MEM_UOP_RETIRED.STORES
+.Pq Event D0H, Umask 02H
+Qualify retired memory uops that are stores. 
+Combine with umask 10H, 20H, 40H, 80H.
+.It Li MEM_UOP_RETIRED.STLB_MISS
+.Pq Event D0H, Umask 10H
+Qualify retired memory uops with STLB miss.
+Must combine with umask 01H, 02H, to produce counts.
+.It Li MEM_UOP_RETIRED.LOCK
+.Pq Event D0H, Umask 20H
+Qualify retired memory uops with lock.
+Must combine with umask 01H, 02H, to produce counts.
+.It Li MEM_UOP_RETIRED.SPLIT
+.Pq Event D0H, Umask 40H
+Qualify retired memory uops with line split.
+Must combine with umask 01H, 02H, to produce counts. 
+.It Li MEM_UOP_RETIRED_ALL
+.Pq Event D0H, Umask 80H 
+Qualify any retired memory uops.
+Must combine with umask 01H, 02H, to produce counts.
+.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
+.Pq Event D1H, Umask 01H 
+Retired load uops with L1 cache hits as data sources.
+Must combine with umask 01H, 02H, to produce counts.
+.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
+.Pq Event D1H, Umask 02H 
+Retired load uops with L2 cache hits as data sources.
+.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
+.Pq Event D1H, Umask 04H 
+Retired load uops which data sources were data hits in LLC without snoops 
+required.
+.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
+.Pq Event D1H, Umask 40H 
+Retired load uops which data sources were load uops missed L1 but hit FB due 
+to preceding miss to the same cache line with data not ready.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
+.Pq Event D2H, Umask 01H 
+Retired load uops which data sources were LLC hit and cross-core snoop missed in 
+on-pkg core cache.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
+.Pq Event D2H, Umask 02H 
+Retired load uops which data sources were LLC and cross-core snoop hits in 
+on-pkg core cache.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
+.Pq Event D2H, Umask 04H 
+Retired load uops which data sources were HitM responses from shared LLC.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
+.Pq Event D2H, Umask 08H
+Retired load uops which data sources were hits in LLC without snoops required.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS
+.Pq Event D4H, Umask 02H 
+Retired load uops with unknown information as data source in cache serviced the load.
+.It Li L2_TRANS.DEMAND_DATA_RD
+.Pq Event F0H, Umask 01H 
+Demand Data Read requests that access L2 cache.
+.It Li L2_TRANS.RF0
+.Pq Event F0H, Umask 02H 
+RFO requests that access L2 cache.
+.It Li L2_TRANS.CODE_RD
+.Pq Event F0H, Umask 04H 
+L2 cache accesses when fetching instructions.
+.It Li L2_TRANS.ALL_PF
+.Pq Event F0H, Umask 08H 
+L2 or LLC HW prefetches that access L2 cache.
+.It Li L2_TRANS.L1D_WB
+.Pq Event F0H, Umask 10H 
+L1D writebacks that access L2 cache.
+.It Li L2_TRANS.L2_FILL
+.Pq Event F0H, Umask 20H 
+L2 fill requests that access L2 cache.
+.It Li L2_TRANS.L2_WB
+.Pq Event F0H, Umask 40H 
+L2 writebacks that access L2 cache.
+.It Li L2_TRANS.ALL_REQUESTS
+.Pq Event F0H, Umask 80H 
+Transactions accessing L2 pipe.
+.It Li L2_LINES_IN.I
+.Pq Event F1H, Umask 01H
+L2 cache lines in I state filling L2. 
+Counting does not cover rejects.
+.It Li L2_LINES_IN.S
+.Pq Event F1H, Umask 02H 
+L2 cache lines in S state filling L2. 
+Counting does not cover rejects.
+.It Li L2_LINES_IN.E
+.Pq Event F1H, Umask 04H 
+L2 cache lines in E state filling L2. 
+Counting does not cover rejects.
+.It Li L2_LINES-IN.ALL
+.Pq Event F1H, Umask 07H 
+L2 cache lines filling L2. 
+Counting does not cover rejects.
+.It Li L2_LINES_OUT.DEMAND_CLEAN
+.Pq Event F2H, Umask 01H 
+Clean L2 cache lines evicted by demand.
+.It Li L2_LINES_OUT.DEMAND_DIRTY
+.Pq Event F2H, Umask 02H 
+Dirty L2 cache lines evicted by demand.
+.It Li L2_LINES_OUT.PF_CLEAN
+.Pq Event F2H, Umask 04H
+Clean L2 cache lines evicted by L2 prefetch.
+.It Li L2_LINES_OUT.PF_DIRTY
+.Pq Event F2H, Umask 08H 
+Dirty L2 cache lines evicted by L2 prefetch.
+.It Li L2_LINES_OUT.DIRTY_ALL
+.Pq Event F2H, Umask 0AH
+Dirty L2 cache lines filling the L2. 
+Counting does not cover rejects.
+.It Li SQ_MISC.SPLIT_LOCK
+.Pq Event F4H, Umask 10H 
+Split locks in SQ.
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.corei7 3 ,
+.Xr pmc.corei7uc 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.sandybridgeuc 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc.ucf 3 ,
+.Xr pmc.westmere 3 ,
+.Xr pmc.westmereuc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+The
+.Nm pmc
+library first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy@FreeBSD.org.
+The support for the 
+.Lb Sandy Bridge
+microarchitecture was written by
+.An "Davide Italiano"
+.Aq davide@FreeBSD.org .
diff --git a/lib/libpmc/pmc.sandybridgeuc.3 b/lib/libpmc/pmc.sandybridgeuc.3
new file mode 100644
index 0000000..9b15922
--- /dev/null
+++ b/lib/libpmc/pmc.sandybridgeuc.3
@@ -0,0 +1,233 @@
+.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org> 
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd February 12, 2012
+.Dt PMC.SANDYBRIDGEUC 3
+.Os
+.Sh NAME
+.Nm pmc.sandybridgeuc
+.Nd uncore measurement events for
+.Tn Intel
+.Tn Sandy Bridge
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+.Tn Intel
+.Tn "Sandy Bridge"
+CPUs contain PMCs conforming to version 3 of the
+.Tn Intel
+performance measurement architecture.
+These CPUs contain two classes of PMCs:
+.Bl -tag -width "Li PMC_CLASS_UCP"
+.It Li PMC_CLASS_UCF
+Fixed-function counters that count only one hardware event per counter.
+.It Li PMC_CLASS_UCP
+Programmable counters that may be configured to count one of a defined
+set of hardware events.
+.El
+.Pp
+The number of PMCs available in each class and their widths need to be
+determined at run time by calling
+.Xr pmc_cpuinfo 3 .
+.Pp
+Intel Sandy Bridge PMCs are documented in
+.Rs
+.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
+.%T "Volume 3B: System Programming Guide, Part 2"
+.%N "Order Number: 253669-039US"
+.%D May 2011
+.%Q "Intel Corporation"
+.Re
+.Ss SANDYBRIDGE UNCORE FIXED FUNCTION PMCS
+These PMCs and their supported events are documented in
+.Xr pmc.ucf 3 .
+Not all CPUs in this family implement fixed-function counters.
+.Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS
+The programmable PMCs support the following capabilities:
+.Bl -column "PMC_CAP_INTERRUPT" "Support"
+.It Em Capability Ta Em Support
+.It PMC_CAP_CASCADE Ta \&No
+.It PMC_CAP_EDGE Ta Yes
+.It PMC_CAP_INTERRUPT Ta \&No
+.It PMC_CAP_INVERT Ta Yes
+.It PMC_CAP_READ Ta Yes
+.It PMC_CAP_PRECISE Ta \&No
+.It PMC_CAP_SYSTEM Ta \&No
+.It PMC_CAP_TAGGING Ta \&No
+.It PMC_CAP_THRESHOLD Ta Yes
+.It PMC_CAP_USER Ta \&No
+.It PMC_CAP_WRITE Ta Yes
+.El
+.Ss Event Qualifiers
+Event specifiers for these PMCs support the following common
+qualifiers:
+.Bl -tag -width indent
+.It Li cmask= Ns Ar value
+Configure the PMC to increment only if the number of configured
+events measured in a cycle is greater than or equal to
+.Ar value .
+.It Li edge
+Configure the PMC to count the number of de-asserted to asserted
+transitions of the conditions expressed by the other qualifiers.
+If specified, the counter will increment only once whenever a
+condition becomes true, irrespective of the number of clocks during
+which the condition remains true.
+.It Li inv
+Invert the sense of comparison when the
+.Dq Li cmask
+qualifier is present, making the counter increment when the number of
+events per cycle is less than the value specified by the
+.Dq Li cmask
+qualifier.
+.El
+.Ss Event Specifiers (Programmable PMCs)
+Sandy Bridge programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li CBO_XSNP_RESPONSE.RSPIHITI
+.Pq Event 22H, Umask 01H
+Snoop responses received from processor cores to requests initiated by this 
+Cbox.
+Must combine with one of the umask values of 20H, 40H, 80H
+.It Li CBO_XSNP_RESPONSE.RSPIHITFSE
+.Pq Event 22H, Umask 02H
+Must combine with one of the umask values of 20H, 40H, 80H
+.It Li CBO_XSNP_RESPONSE.RSPSHITFSE
+.Pq Event 22H, Umask 04H
+Must combine with one of the umask values of 20H, 40H, 80H
+.It Li CBO_XSNP_RESPONSE.RSPSFWDM
+.Pq Event 22H, Umask 08H
+.It Li CBO_XSNP_RESPONSE.RSPIFWDM
+.Pq Event 22H, Umask 01H
+.It Li CBO_XSNP_RESPONSE.AND_EXTERNAL
+.Pq Event 22H, Umask 20H
+Filter on cross-core snoops resulted in external snoop request. 
+Must combine with at least one of 01H, 02H, 04H, 08H, 10H
+.It Li CBO_XSNP_RESPONSE.AND_XCORE
+.Pq Event 22H, Umask 40H
+Filter on cross-core snoops resulted in core request. 
+Must combine with at least one of 01H, 02H, 04H, 08H, 10H
+.It Li CBO_XSNP_RESPONSE.AND_XCORE
+.Pq Event 22H, Umask 80H
+Filter on cross-core snoops resulted in LLC evictions. 
+Must combine with at least one of 01H, 02H, 04H, 08H, 10H
+.It Li CBO_CACHE_LOOKUP.M
+.Pq Event 34H, Umask 01H
+LLC lookup request that access cache and found line in M-state.
+Must combine with one of the umask values of 10H, 20H, 40H, 80H
+.It Li CBO_CACHE_LOOKUP.E
+.Pq Event 34H, Umask 02H 
+LLC lookup request that access cache and found line in E-state.
+Must combine with one of the umask values of 10H, 20H, 40H, 80H
+.It Li CBO_CACHE_LOOKUP.S
+.Pq Event 34H, Umask 04H 
+LLC lookup request that access cache and found line in S-state.
+Must combine with one of the umask values of 10H, 20H, 40H, 80H
+.It Li CBO_CACHE_LOOKUP.I
+.Pq Event 34H, Umask 08H 
+LLC lookup request that access cache and found line in I-state.
+Must combine with one of the umask values of 10H, 20H, 40H, 80H
+.It Li CBO_CACHE_LOOKUP.AND_READ
+.Pq Event 34H, Umask 10H
+Filter on processor core initiated cacheable read requests. 
+Must combine with at least one of 01H, 02H, 04H, 08H
+.It Li CBO_CACHE_LOOKUP_AND_READ2
+.Pq Event 34H, Umask 20H
+Filter on processor core initiated cacheable write requests. 
+Must combine with at least one of 01H, 02H, 04H, 08H
+.It Li CBO_CACHE_LOOKUP.AND_EXTSNP
+.Pq Event 34H, Umask 40H
+Filter on external snoop requests. 
+Must combine with at least one of 01H, 02H, 04H, 08H
+.It Li CBO_CACHE_LOOKUP.AND_ANY
+.Pq Event 34H, Umask 80H
+Filter on any IRQ or IPQ initiated requests including uncacheable, 
+noncoherent requests. 
+Must combine with at least one of 01H, 02H, 04H, 08H
+.It Li IMPH_CBO_TRK_OCCUPANCY.ALL
+.Pq Event 80H, Umask 01H
+Counts cycles weighted by the number of core-outgoing valid entries. 
+Valid entries are between allocation to the first of IDIO or DRSO messages. 
+Accounts for coherent and incoherent traffic.
+Counter 0 only
+.It Li IMPH_CBO_TRK_REQUEST.ALL
+.Pq Event 81H, Umask 01H
+Counts the number of core-outgoing entries. 
+Accounts for coherent and incoherent traffic.
+.It Li IMPH_CBO_TRK_REQUEST.WRITES
+.Pq Event 81H, Umask 20H
+Counts the number of allocated write entries, include full, partial, and 
+evictions.
+.It Li IMPH_CBO_TRK_REQUEST.EVICTIONS
+.Pq Event 81H, Umask 80H
+Counts the number of evictions allocated.
+.It Li IMPH_COH_TRK_OCCUPANCY.ALL
+.Pq Event 83H, Umask 01H
+Counts cycles weighted by the
+number of core-outgoing valid entries in the coherent tracker queue.
+Counter 0 only
+.It Li IMPH_COH_TRK_REQUEST.ALL
+.Pq Event 84H, Umask 01H
+Counts the number of core-outgoing entries in the coherent tracker queue.
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.corei7 3 ,
+.Xr pmc.corei7uc 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.sandybridge 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc.ucf 3 ,
+.Xr pmc.westmere 3 ,
+.Xr pmc.westmereuc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+The
+.Nm pmc
+library first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy@FreeBSD.org .
+The support for the 
+.Lb Sandy Bridge
+microarchitecture was added by
+.An "Davide Italiano"
+.Aq davide@FreeBSD.org .
diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c
index 4dea06a..a3e3cb9 100644
--- a/sys/dev/hwpmc/hwpmc_core.c
+++ b/sys/dev/hwpmc/hwpmc_core.c
@@ -556,7 +556,8 @@ struct iap_event_descr {
 #define	IAP_F_I7	(1 << 4)	/* CPU: Core i7 */
 #define	IAP_F_I7O	(1 << 4)	/* CPU: Core i7 (old) */
 #define	IAP_F_WM	(1 << 5)	/* CPU: Westmere */
-#define	IAP_F_FM	(1 << 6)	/* Fixed mask */
+#define	IAP_F_SB	(1 << 6)	/* CPU: Sandy Brdige */
+#define	IAP_F_FM	(1 << 7)	/* Fixed mask */
 
 #define	IAP_F_ALLCPUSCORE2					\
     (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
@@ -596,11 +597,12 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
 
     IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
-    IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O),
-    IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM),
+    IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
+    IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 
+	IAP_F_WM | IAP_F_SB),
     IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
-    IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
+    IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
     IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
@@ -610,8 +612,8 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
-    IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O),
-    IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM),
+    IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
+    IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB),
     IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
@@ -623,24 +625,25 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
-    IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
-    IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB),
 
     IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_WM),
+	IAP_F_WM | IAP_F_SB),
     IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
     IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
     IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
     IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
-    IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7),
@@ -659,7 +662,10 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
     IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
 
-    IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB),
+
+    IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
@@ -670,18 +676,20 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 
+	IAP_F_WM | IAP_F_SB),
     IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
 
     IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
-    IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB),
+    IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB),
     IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
 
     IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
@@ -702,10 +710,11 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
 
     IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
-    IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 
+	 IAP_F_WM | IAP_F_SB),
     IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
-    IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
 
     IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -727,18 +736,18 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
-    IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
@@ -758,12 +767,12 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
-    IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O),
-    IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
+    IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -774,8 +783,8 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
     IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
@@ -788,8 +797,10 @@ static struct iap_event_descr iap_events[] = {
 	IAP_F_ALLCPUSCORE2),
     IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
     IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
-    IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
-    IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
+    IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
+	IAP_F_SB),
+    IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
+	IAP_F_SB),
 
     IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
 	IAP_F_ALLCPUSCORE2),
@@ -802,9 +813,9 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-        IAP_F_I7 | IAP_F_WM),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-        IAP_F_I7 | IAP_F_WM),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
@@ -845,15 +856,17 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB),
     IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-        IAP_F_I7 | IAP_F_WM),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-        IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM),
-    IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+        IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+        IAP_F_SB),
     IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7),
     IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7),
@@ -865,12 +878,15 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
 
     IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
@@ -880,19 +896,41 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
 
-    IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
     IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+
     IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
+    IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB),
+
+    IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB),
+
+    IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB),
+    
+    IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB),
+
     IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
-    IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
+	IAP_F_SB),
     IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
-    IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
-    IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
+	IAP_F_SB),
+    IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
+	IAP_F_SB),
 
     IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
     IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
@@ -903,8 +941,10 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
 	IAP_F_CA | IAP_F_CC2),
     IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
-    IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
     IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
     IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
@@ -945,6 +985,13 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
     IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
 
+    IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB),
+ 
     IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
@@ -959,7 +1006,7 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
-	IAP_F_WM),
+	IAP_F_WM | IAP_F_SB),
     IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
 	IAP_F_WM),
     IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -979,10 +1026,13 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
-    IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
-    IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
+	IAP_F_SB),
+    IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
     IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
@@ -990,35 +1040,54 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
     IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
@@ -1033,26 +1102,46 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
 
+    IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB), 
+
     IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
-    IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-
+    IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB),
+    
     IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
-    IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
     IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1063,24 +1152,36 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
     IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
 
-    IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+
+    IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB),
 
-    IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
     IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
+	IAP_F_SB),
     IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
-    IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
-    IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
+    IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
+	IAP_F_SB),
+    IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
+	IAP_F_SB),
     IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
     IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
 
     IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1091,7 +1192,8 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
 	IAP_F_WM),
 
-    IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
     IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
 	IAP_F_WM | IAP_F_I7O),
@@ -1113,7 +1215,10 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
     IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
 
-    IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB),
+
+    IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
     IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
     IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
@@ -1122,26 +1227,37 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
 
-    IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
-    IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB),
+
+    IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB),
+
+    IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
+	IAP_F_SB),
     IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
 
     IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB),
     IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
@@ -1152,28 +1268,37 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
+    IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
     IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
+    IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
-	IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM),
-    IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
@@ -1199,9 +1324,14 @@ static struct iap_event_descr iap_events[] = {
 
     IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
     IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
-    IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
+    IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
@@ -1222,34 +1352,48 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
+    IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB), 
+
     IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
     IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
 
     IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
-    IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-
-    IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM),
-    IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB),
+ 
+    IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB),
+    IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
     IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB),
 
     IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-	IAP_F_I7 | IAP_F_WM),
+	IAP_F_I7 | IAP_F_WM | IAP_F_SB),
     IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
     IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
 
     IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
 	IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
+    IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
+	IAP_F_SB),
     IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
     IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
@@ -1311,23 +1455,40 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
 
     IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
-    IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-
-    IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-
-    IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
-    IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+
+    IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB),
+    IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+
+    IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
+    IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB),
     IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
     IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
@@ -1341,7 +1502,8 @@ static struct iap_event_descr iap_events[] = {
     IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
     IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
     IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
-    IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
+    IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
+	IAP_F_SB),
 
     IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
 
@@ -1513,6 +1675,25 @@ iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
 }
 
 static int
+iap_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri)
+{
+	uint32_t mask;
+	
+	switch (pe) {
+		/*
+		 * Events valid only on counter 2.
+		 */
+	case PMC_EV_IAP_EVENT_48H_01H:
+		mask = 0x2;
+		break;
+	default:
+		mask = ~0;	/* Any row index is ok. */
+	}
+	
+	return (mask & (1 << ri));
+}
+
+static int
 iap_event_ok_on_counter(enum pmc_event pe, int ri)
 {
 	uint32_t mask;
@@ -1588,6 +1769,10 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 		if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
 			return (EINVAL);
 		break;
+	case PMC_CPU_INTEL_SANDYBRIDGE:
+		if (iap_event_sandybridge_ok_on_counter(ev, ri) == 0)
+			return (EINVAL);
+		break;
 	case PMC_CPU_INTEL_WESTMERE:
 		if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
 			return (EINVAL);
@@ -1619,6 +1804,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 	case PMC_CPU_INTEL_COREI7:
 		cpuflag = IAP_F_I7;
 		break;
+	case PMC_CPU_INTEL_SANDYBRIDGE:	
+		cpuflag = IAP_F_SB;
+		break;
 	case PMC_CPU_INTEL_WESTMERE:
 		cpuflag = IAP_F_WM;
 		break;
@@ -1703,9 +1891,10 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 	}
 
 	/*
-	 * Only Atom CPUs support the 'ANY' qualifier.
+	 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
 	 */
-	if (core_cputype == PMC_CPU_INTEL_ATOM)
+	if (core_cputype == PMC_CPU_INTEL_ATOM ||
+		core_cputype == PMC_CPU_INTEL_SANDYBRIDGE)
 		evsel |= (config & IAP_ANY);
 	else if (config & IAP_ANY)
 		return (EINVAL);
diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
index 82d5079..20f29dc 100644
--- a/sys/dev/hwpmc/hwpmc_intel.c
+++ b/sys/dev/hwpmc/hwpmc_intel.c
@@ -142,6 +142,11 @@ pmc_intel_initialize(void)
 			cputype = PMC_CPU_INTEL_WESTMERE;
 			nclasses = 5;
 			break;
+		case 0x2A:	/* Per Intel document 253669-039US 05/2011. */
+		case 0x2D:	/* Per Intel document 253669-041US 12/2011. */	
+			cputype = PMC_CPU_INTEL_SANDYBRIDGE;
+			nclasses = 5;
+			break;
 		}
 		break;
 #if	defined(__i386__) || defined(__amd64__)
@@ -182,6 +187,7 @@ pmc_intel_initialize(void)
 	case PMC_CPU_INTEL_CORE2:
 	case PMC_CPU_INTEL_CORE2EXTREME:
 	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
 		error = pmc_core_initialize(pmc_mdep, ncpus);
 		break;
@@ -242,6 +248,7 @@ pmc_intel_initialize(void)
 		 * Intel Corei7 and Westmere processors.
 		 */
 	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
 		error = pmc_uncore_initialize(pmc_mdep, ncpus);
 		break;
@@ -271,6 +278,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
 	case PMC_CPU_INTEL_CORE2:
 	case PMC_CPU_INTEL_CORE2EXTREME:
 	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
 		pmc_core_finalize(md);
 		break;
@@ -301,6 +309,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
 #if	defined(__i386__) || defined(__amd64__)
 	switch (md->pmd_cputype) {
 	case PMC_CPU_INTEL_COREI7:
+	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
 		pmc_uncore_finalize(md);
 		break;
diff --git a/sys/dev/hwpmc/hwpmc_uncore.c b/sys/dev/hwpmc/hwpmc_uncore.c
index 9a6e739..007aa6a 100644
--- a/sys/dev/hwpmc/hwpmc_uncore.c
+++ b/sys/dev/hwpmc/hwpmc_uncore.c
@@ -50,6 +50,12 @@ __FBSDID("$FreeBSD$");
     (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
     PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
 
+#define	SELECTSEL(x) \
+	(((x) == PMC_CPU_INTEL_SANDYBRIDGE) ? UCP_CB0_EVSEL0 : UCP_EVSEL0)
+
+#define SELECTOFF(x) \
+	(((x) == PMC_CPU_INTEL_SANDYBRIDGE) ? UCF_OFFSET_SB : UCF_OFFSET)
+
 static enum pmc_cputype	uncore_cputype;
 
 struct uncore_cpu {
@@ -140,8 +146,8 @@ uncore_pcpu_fini(struct pmc_mdep *md, int cpu)
 	npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
 	uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
 
-	for (n = 0; n < npmc; n++)
-		wrmsr(UCP_EVSEL0 + n, 0);
+	for (n = 0; n < npmc; n++) 
+		wrmsr(SELECTSEL(uncore_cputype) + n, 0);
 
 	wrmsr(UCF_CTRL, 0);
 	npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
@@ -327,7 +333,7 @@ ucf_start_pmc(int cpu, int ri)
 
 	do {
 		ucfc->pc_resync = 0;
-		ucfc->pc_globalctrl |= (1ULL << (ri + UCF_OFFSET));
+		ucfc->pc_globalctrl |= (1ULL << (ri + SELECTOFF(uncore_cputype)));
 		wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
 	} while (ucfc->pc_resync != 0);
 
@@ -362,7 +368,7 @@ ucf_stop_pmc(int cpu, int ri)
 
 	do {
 		ucfc->pc_resync = 0;
-		ucfc->pc_globalctrl &= ~(1ULL << (ri + UCF_OFFSET));
+		ucfc->pc_globalctrl &= ~(1ULL << (ri + SELECTOFF(uncore_cputype)));
 		wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
 	} while (ucfc->pc_resync != 0);
 
@@ -462,7 +468,8 @@ struct ucp_event_descr {
 
 #define	UCP_F_I7	(1 << 0)	/* CPU: Core i7 */
 #define	UCP_F_WM	(1 << 1)	/* CPU: Westmere */
-#define	UCP_F_FM	(1 << 2)	/* Fixed mask */
+#define	UCP_F_SB	(1 << 2)	/* CPU: Sandy Bridge */
+#define	UCP_F_FM	(1 << 3)	/* Fixed mask */
 
 #define	UCP_F_ALLCPUS					\
     (UCP_F_I7 | UCP_F_WM)
@@ -565,9 +572,16 @@ static struct ucp_event_descr ucp_events[] = {
     UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
     UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
 
-    UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
-    UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
-    UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
+    UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM |
+	UCP_F_SB),
+    UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM |
+	UCP_F_SB),
+    UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM |
+	UCP_F_SB),
+    UCPDESCR(22H_08H, 0x22, 0x08, UCP_F_FM | UCP_F_SB),
+    UCPDESCR(22H_20H, 0x22, 0x20, UCP_F_FM | UCP_F_SB),
+    UCPDESCR(22H_40H, 0x22, 0x40, UCP_F_FM | UCP_F_SB),
+    UCPDESCR(22H_80H, 0x22, 0x80, UCP_F_FM | UCP_F_SB),
 
     UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
     UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
@@ -657,12 +671,14 @@ static struct ucp_event_descr ucp_events[] = {
     UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
     UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM),
 
-    UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB),
+    UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM | UCP_F_SB),
+    UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM | UCP_F_SB),
+    UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM | UCP_F_SB),
+    UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM | UCP_F_SB),
+    UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM | UCP_F_SB),
+    UCPDESCR(34H_40H, 0x34, 0x40, UCP_F_FM | UCP_F_SB),
+    UCPDESCR(34H_80H, 0x34, 0x80, UCP_F_FM | UCP_F_SB),
 
     UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM),
     UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM),
@@ -729,20 +745,27 @@ static struct ucp_event_descr ucp_events[] = {
     UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
 
     UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM),
+    
+    UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB),
     UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM),
     UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM),
     UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM),
+    
+    UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB),
     UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM),
     UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM),
     UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM),
+    UCPDESCR(81H_20H, 0x81, 0x20, UCP_F_FM | UCP_F_SB),
+    UCPDESCR(81H_80H, 0x81, 0x80, UCP_F_FM | UCP_F_SB),
+
     UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM),
+ 
+    UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB),
     UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM),
     UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM),
     UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM),
-    UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM),
+ 
+    UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB),
     UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM),
     UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM),
     UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM),
@@ -766,6 +789,27 @@ ucp_reload_count_to_perfctr_value(pmc_value_t rlc)
 }
 
 static int
+ucp_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri)
+{
+	uint32_t mask;
+	
+	switch (pe) {
+		/*	
+		 * Events valid only on counter 0.
+		 */
+	case PMC_EV_UCP_EVENT_80H_01H:
+	case PMC_EV_UCP_EVENT_83H_01H:
+		mask = (1 << 0);
+		break;
+	
+	default:
+		mask = ~0;	/* Any row index is ok. */
+	}
+	
+	return (mask & (1 << ri));
+}
+
+static int
 ucp_allocate_pmc(int cpu, int ri, struct pmc *pm,
     const struct pmc_op_pmcallocate *a)
 {
@@ -786,6 +830,16 @@ ucp_allocate_pmc(int cpu, int ri, struct pmc *pm,
 
 	ev = pm->pm_event;
 
+	switch (uncore_cputype) {
+	case PMC_CPU_INTEL_SANDYBRIDGE:
+		if (ucp_event_sandybridge_ok_on_counter(ev, ri) == 0)
+			return (EINVAL);
+		break;
+	default:
+		break;
+	}
+	
+
 	/*
 	 * Look for an event descriptor with matching CPU and event id
 	 * fields.
@@ -795,6 +849,9 @@ ucp_allocate_pmc(int cpu, int ri, struct pmc *pm,
 	case PMC_CPU_INTEL_COREI7:
 		cpuflag = UCP_F_I7;
 		break;
+	case PMC_CPU_INTEL_SANDYBRIDGE:
+		cpuflag = UCP_F_SB;
+		break;
 	case PMC_CPU_INTEL_WESTMERE:
 		cpuflag = UCP_F_WM;
 		break;
@@ -968,8 +1025,9 @@ ucp_start_pmc(int cpu, int ri)
 
 	evsel = pm->pm_md.pm_ucp.pm_ucp_evsel;
 
-	PMCDBG(MDP,STA,2, "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
-	    cpu, ri, UCP_EVSEL0 + ri, evsel);
+	PMCDBG(MDP,STA,2, 
+	    "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 
+	    cpu, ri, SELECTSEL(uncore_cputype) + ri, evsel); 
 
 	/* Event specific configuration. */
 	switch (pm->pm_event) {
@@ -993,8 +1051,8 @@ ucp_start_pmc(int cpu, int ri)
 		break;
 	}
 
-	wrmsr(UCP_EVSEL0 + ri, evsel);
-
+	wrmsr(SELECTSEL(uncore_cputype) + ri, evsel);
+	
 	do {
 		cc->pc_resync = 0;
 		cc->pc_globalctrl |= (1ULL << ri);
@@ -1024,7 +1082,8 @@ ucp_stop_pmc(int cpu, int ri)
 
 	PMCDBG(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri);
 
-	wrmsr(UCP_EVSEL0 + ri, 0);	/* stop hw */
+	/* stop hw. */
+	wrmsr(SELECTSEL(uncore_cputype) + ri, 0);
 
 	do {
 		cc->pc_resync = 0;
@@ -1128,7 +1187,7 @@ pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu)
 	uncore_ucf_width = 48;
 
 	ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width);
-	uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << UCF_OFFSET;
+	uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << SELECTOFF(uncore_cputype);
 
 	PMCDBG(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask,
 	    uncore_ucf_ri);
diff --git a/sys/dev/hwpmc/hwpmc_uncore.h b/sys/dev/hwpmc/hwpmc_uncore.h
index 6c3b4cf..c1f8259 100644
--- a/sys/dev/hwpmc/hwpmc_uncore.h
+++ b/sys/dev/hwpmc/hwpmc_uncore.h
@@ -68,6 +68,7 @@ struct pmc_md_ucp_op_pmcallocate {
 #define	UCF_CTR0				0x394
 
 #define	UCF_OFFSET				32
+#define UCF_OFFSET_SB				29
 #define	UCF_CTRL				0x395
 
 /*
@@ -77,6 +78,7 @@ struct pmc_md_ucp_op_pmcallocate {
 #define	UCP_PMC0				0x3B0
 #define	UCP_EVSEL0				0x3C0
 #define UCP_OPCODE_MATCH			0x396
+#define UCP_CB0_EVSEL0				0x700
 
 /*
  * Simplified programming interface in Intel Performance Architecture
diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h
index 095e79c..bc3eef8 100644
--- a/sys/dev/hwpmc/pmc_events.h
+++ b/sys/dev/hwpmc/pmc_events.h
@@ -520,6 +520,8 @@ __PMC_EV(IAP, EVENT_0BH_10H)			\
 __PMC_EV(IAP, EVENT_0CH_01H)			\
 __PMC_EV(IAP, EVENT_0CH_02H)			\
 __PMC_EV(IAP, EVENT_0CH_03H)			\
+__PMC_EV(IAP, EVENT_0DH_03H)			\
+__PMC_EV(IAP, EVENT_0DH_40H)			\
 __PMC_EV(IAP, EVENT_0EH_01H)			\
 __PMC_EV(IAP, EVENT_0EH_02H)			\
 __PMC_EV(IAP, EVENT_0FH_01H)			\
@@ -540,6 +542,7 @@ __PMC_EV(IAP, EVENT_10H_80H)			\
 __PMC_EV(IAP, EVENT_10H_81H)			\
 __PMC_EV(IAP, EVENT_11H_00H)			\
 __PMC_EV(IAP, EVENT_11H_01H)			\
+__PMC_EV(IAP, EVENT_11H_02H)			\
 __PMC_EV(IAP, EVENT_11H_81H)			\
 __PMC_EV(IAP, EVENT_12H_00H)			\
 __PMC_EV(IAP, EVENT_12H_01H)			\
@@ -664,6 +667,7 @@ __PMC_EV(IAP, EVENT_45H_0FH)			\
 __PMC_EV(IAP, EVENT_46H_00H)			\
 __PMC_EV(IAP, EVENT_47H_00H)			\
 __PMC_EV(IAP, EVENT_48H_00H)			\
+__PMC_EV(IAP, EVENT_48H_01H)			\
 __PMC_EV(IAP, EVENT_48H_02H)			\
 __PMC_EV(IAP, EVENT_49H_00H)			\
 __PMC_EV(IAP, EVENT_49H_01H)			\
@@ -680,6 +684,7 @@ __PMC_EV(IAP, EVENT_4BH_03H)			\
 __PMC_EV(IAP, EVENT_4BH_08H)			\
 __PMC_EV(IAP, EVENT_4CH_00H)			\
 __PMC_EV(IAP, EVENT_4CH_01H)			\
+__PMC_EV(IAP, EVENT_4CH_02H)			\
 __PMC_EV(IAP, EVENT_4DH_01H)			\
 __PMC_EV(IAP, EVENT_4EH_01H)			\
 __PMC_EV(IAP, EVENT_4EH_02H)			\
@@ -696,6 +701,16 @@ __PMC_EV(IAP, EVENT_51H_04H)			\
 __PMC_EV(IAP, EVENT_51H_08H)			\
 __PMC_EV(IAP, EVENT_52H_01H)			\
 __PMC_EV(IAP, EVENT_53H_01H)			\
+__PMC_EV(IAP, EVENT_59H_20H)			\
+__PMC_EV(IAP, EVENT_59H_40H)			\
+__PMC_EV(IAP, EVENT_59H_80H)			\
+__PMC_EV(IAP, EVENT_5BH_0CH)			\
+__PMC_EV(IAP, EVENT_5BH_0FH)			\
+__PMC_EV(IAP, EVENT_5BH_40H)			\
+__PMC_EV(IAP, EVENT_5BH_4FH)			\
+__PMC_EV(IAP, EVENT_5CH_01H)			\
+__PMC_EV(IAP, EVENT_5CH_02H)			\
+__PMC_EV(IAP, EVENT_5EH_01H)			\
 __PMC_EV(IAP, EVENT_60H)			\
 __PMC_EV(IAP, EVENT_60H_01H)			\
 __PMC_EV(IAP, EVENT_60H_02H)			\
@@ -725,6 +740,12 @@ __PMC_EV(IAP, EVENT_6FH)			\
 __PMC_EV(IAP, EVENT_70H)			\
 __PMC_EV(IAP, EVENT_77H)			\
 __PMC_EV(IAP, EVENT_78H)			\
+__PMC_EV(IAP, EVENT_79H_02H)			\
+__PMC_EV(IAP, EVENT_79H_04H)			\
+__PMC_EV(IAP, EVENT_79H_08H)			\
+__PMC_EV(IAP, EVENT_79H_10H)			\
+__PMC_EV(IAP, EVENT_79H_20H)			\
+__PMC_EV(IAP, EVENT_79H_30H)			\
 __PMC_EV(IAP, EVENT_7AH)			\
 __PMC_EV(IAP, EVENT_7BH)			\
 __PMC_EV(IAP, EVENT_7DH)			\
@@ -773,7 +794,9 @@ __PMC_EV(IAP, EVENT_88H_10H)			\
 __PMC_EV(IAP, EVENT_88H_20H)			\
 __PMC_EV(IAP, EVENT_88H_30H)			\
 __PMC_EV(IAP, EVENT_88H_40H)			\
+__PMC_EV(IAP, EVENT_88H_80H)			\
 __PMC_EV(IAP, EVENT_88H_7FH)			\
+__PMC_EV(IAP, EVENT_88H_FFH)			\
 __PMC_EV(IAP, EVENT_89H_00H)			\
 __PMC_EV(IAP, EVENT_89H_01H)			\
 __PMC_EV(IAP, EVENT_89H_02H)			\
@@ -784,7 +807,9 @@ __PMC_EV(IAP, EVENT_89H_10H)			\
 __PMC_EV(IAP, EVENT_89H_20H)			\
 __PMC_EV(IAP, EVENT_89H_30H)			\
 __PMC_EV(IAP, EVENT_89H_40H)			\
+__PMC_EV(IAP, EVENT_89H_80H)			\
 __PMC_EV(IAP, EVENT_89H_7FH)			\
+__PMC_EV(IAP, EVENT_89H_FFH)			\
 __PMC_EV(IAP, EVENT_8AH_00H)			\
 __PMC_EV(IAP, EVENT_8BH_00H)			\
 __PMC_EV(IAP, EVENT_8CH_00H)			\
@@ -798,13 +823,18 @@ __PMC_EV(IAP, EVENT_93H_00H)			\
 __PMC_EV(IAP, EVENT_94H_00H)			\
 __PMC_EV(IAP, EVENT_97H_00H)			\
 __PMC_EV(IAP, EVENT_98H_00H)			\
+__PMC_EV(IAP, EVENT_9CH_01H)			\
 __PMC_EV(IAP, EVENT_A0H_00H)			\
 __PMC_EV(IAP, EVENT_A1H_01H)			\
 __PMC_EV(IAP, EVENT_A1H_02H)			\
 __PMC_EV(IAP, EVENT_A1H_04H)			\
 __PMC_EV(IAP, EVENT_A1H_08H)			\
+__PMC_EV(IAP, EVENT_A1H_0CH)			\
 __PMC_EV(IAP, EVENT_A1H_10H)			\
 __PMC_EV(IAP, EVENT_A1H_20H)			\
+__PMC_EV(IAP, EVENT_A1H_30H)			\
+__PMC_EV(IAP, EVENT_A1H_40H)			\
+__PMC_EV(IAP, EVENT_A1H_80H)			\
 __PMC_EV(IAP, EVENT_A2H_00H)			\
 __PMC_EV(IAP, EVENT_A2H_01H)			\
 __PMC_EV(IAP, EVENT_A2H_02H)			\
@@ -823,6 +853,9 @@ __PMC_EV(IAP, EVENT_AAH_03H)			\
 __PMC_EV(IAP, EVENT_AAH_08H)			\
 __PMC_EV(IAP, EVENT_ABH_01H)			\
 __PMC_EV(IAP, EVENT_ABH_02H)			\
+__PMC_EV(IAP, EVENT_ACH_02H)			\
+__PMC_EV(IAP, EVENT_ACH_08H)			\
+__PMC_EV(IAP, EVENT_ACH_0AH)			\
 __PMC_EV(IAP, EVENT_AEH_01H)			\
 __PMC_EV(IAP, EVENT_B0H_00H)			\
 __PMC_EV(IAP, EVENT_B0H_01H)			\
@@ -860,6 +893,7 @@ __PMC_EV(IAP, EVENT_B3H_A0H)			\
 __PMC_EV(IAP, EVENT_B4H_01H)			\
 __PMC_EV(IAP, EVENT_B4H_02H)			\
 __PMC_EV(IAP, EVENT_B4H_04H)			\
+__PMC_EV(IAP, EVENT_B6H_01H)			\
 __PMC_EV(IAP, EVENT_B7H_01H)			\
 __PMC_EV(IAP, EVENT_B8H_01H)			\
 __PMC_EV(IAP, EVENT_B8H_02H)			\
@@ -867,6 +901,9 @@ __PMC_EV(IAP, EVENT_B8H_04H)			\
 __PMC_EV(IAP, EVENT_BAH_01H)			\
 __PMC_EV(IAP, EVENT_BAH_02H)			\
 __PMC_EV(IAP, EVENT_BBH_01H)			\
+__PMC_EV(IAP, EVENT_BDH_01H)			\
+__PMC_EV(IAP, EVENT_BDH_20H)			\
+__PMC_EV(IAP, EVENT_BFH_05H)			\
 __PMC_EV(IAP, EVENT_C0H_00H)			\
 __PMC_EV(IAP, EVENT_C0H_01H)			\
 __PMC_EV(IAP, EVENT_C0H_02H)			\
@@ -874,6 +911,10 @@ __PMC_EV(IAP, EVENT_C0H_04H)			\
 __PMC_EV(IAP, EVENT_C0H_08H)			\
 __PMC_EV(IAP, EVENT_C1H_00H)			\
 __PMC_EV(IAP, EVENT_C1H_01H)			\
+__PMC_EV(IAP, EVENT_C1H_02H)			\
+__PMC_EV(IAP, EVENT_C1H_08H)			\
+__PMC_EV(IAP, EVENT_C1H_10H)			\
+__PMC_EV(IAP, EVENT_C1H_20H)			\
 __PMC_EV(IAP, EVENT_C1H_FEH)			\
 __PMC_EV(IAP, EVENT_C2H_00H)			\
 __PMC_EV(IAP, EVENT_C2H_01H)			\
@@ -888,6 +929,7 @@ __PMC_EV(IAP, EVENT_C3H_01H)			\
 __PMC_EV(IAP, EVENT_C3H_02H)			\
 __PMC_EV(IAP, EVENT_C3H_04H)			\
 __PMC_EV(IAP, EVENT_C3H_10H)			\
+__PMC_EV(IAP, EVENT_C3H_20H)			\
 __PMC_EV(IAP, EVENT_C4H_00H)			\
 __PMC_EV(IAP, EVENT_C4H_01H)			\
 __PMC_EV(IAP, EVENT_C4H_02H)			\
@@ -895,10 +937,15 @@ __PMC_EV(IAP, EVENT_C4H_04H)			\
 __PMC_EV(IAP, EVENT_C4H_08H)			\
 __PMC_EV(IAP, EVENT_C4H_0CH)			\
 __PMC_EV(IAP, EVENT_C4H_0FH)			\
+__PMC_EV(IAP, EVENT_C4H_10H)			\
+__PMC_EV(IAP, EVENT_C4H_20H)			\
+__PMC_EV(IAP, EVENT_C4H_40H)			\
 __PMC_EV(IAP, EVENT_C5H_00H)			\
 __PMC_EV(IAP, EVENT_C5H_01H)			\
 __PMC_EV(IAP, EVENT_C5H_02H)			\
 __PMC_EV(IAP, EVENT_C5H_04H)			\
+__PMC_EV(IAP, EVENT_C5H_10H)			\
+__PMC_EV(IAP, EVENT_C5H_20H)			\
 __PMC_EV(IAP, EVENT_C6H_00H)			\
 __PMC_EV(IAP, EVENT_C6H_01H)			\
 __PMC_EV(IAP, EVENT_C6H_02H)			\
@@ -917,6 +964,8 @@ __PMC_EV(IAP, EVENT_CAH_01H)			\
 __PMC_EV(IAP, EVENT_CAH_02H)			\
 __PMC_EV(IAP, EVENT_CAH_04H)			\
 __PMC_EV(IAP, EVENT_CAH_08H)			\
+__PMC_EV(IAP, EVENT_CAH_10H)			\
+__PMC_EV(IAP, EVENT_CAH_1EH)			\
 __PMC_EV(IAP, EVENT_CBH_01H)			\
 __PMC_EV(IAP, EVENT_CBH_02H)			\
 __PMC_EV(IAP, EVENT_CBH_04H)			\
@@ -928,15 +977,24 @@ __PMC_EV(IAP, EVENT_CCH_00H)			\
 __PMC_EV(IAP, EVENT_CCH_01H)			\
 __PMC_EV(IAP, EVENT_CCH_02H)			\
 __PMC_EV(IAP, EVENT_CCH_03H)			\
+__PMC_EV(IAP, EVENT_CCH_20H)			\
 __PMC_EV(IAP, EVENT_CDH_00H)			\
+__PMC_EV(IAP, EVENT_CDH_01H)			\
+__PMC_EV(IAP, EVENT_CDH_02H)			\
 __PMC_EV(IAP, EVENT_CEH_00H)			\
 __PMC_EV(IAP, EVENT_CFH_00H)			\
 __PMC_EV(IAP, EVENT_D0H_00H)			\
 __PMC_EV(IAP, EVENT_D0H_01H)			\
+__PMC_EV(IAP, EVENT_D0H_02H)			\
+__PMC_EV(IAP, EVENT_D0H_10H)			\
+__PMC_EV(IAP, EVENT_D0H_20H)			\
+__PMC_EV(IAP, EVENT_D0H_40H)			\
+__PMC_EV(IAP, EVENT_D0H_80H)			\
 __PMC_EV(IAP, EVENT_D1H_01H)			\
 __PMC_EV(IAP, EVENT_D1H_02H)			\
 __PMC_EV(IAP, EVENT_D1H_04H)			\
 __PMC_EV(IAP, EVENT_D1H_08H)			\
+__PMC_EV(IAP, EVENT_D1H_40H)			\
 __PMC_EV(IAP, EVENT_D2H_01H)			\
 __PMC_EV(IAP, EVENT_D2H_02H)			\
 __PMC_EV(IAP, EVENT_D2H_04H)			\
@@ -996,6 +1054,7 @@ __PMC_EV(IAP, EVENT_F0H_10H)			\
 __PMC_EV(IAP, EVENT_F0H_20H)			\
 __PMC_EV(IAP, EVENT_F0H_40H)			\
 __PMC_EV(IAP, EVENT_F0H_80H)			\
+__PMC_EV(IAP, EVENT_F1H_01H)			\
 __PMC_EV(IAP, EVENT_F1H_02H)			\
 __PMC_EV(IAP, EVENT_F1H_04H)			\
 __PMC_EV(IAP, EVENT_F1H_07H)			\
@@ -1003,6 +1062,7 @@ __PMC_EV(IAP, EVENT_F2H_01H)			\
 __PMC_EV(IAP, EVENT_F2H_02H)			\
 __PMC_EV(IAP, EVENT_F2H_04H)			\
 __PMC_EV(IAP, EVENT_F2H_08H)			\
+__PMC_EV(IAP, EVENT_F2H_0AH)			\
 __PMC_EV(IAP, EVENT_F2H_0FH)			\
 __PMC_EV(IAP, EVENT_F3H_01H)			\
 __PMC_EV(IAP, EVENT_F3H_02H)			\
@@ -2318,6 +2378,220 @@ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H)		\
 __PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H)		\
 __PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H)
 
+/*
+ *  Aliases for Sandy Bridge PMC events (253669-039US May 2011) 
+ */
+
+#define __PMC_EV_ALIAS_SANDYBRIDGE()						\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()						\
+__PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H)			\
+__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H)			\
+__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H)				\
+__PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H)			\
+__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H)			\
+__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H)			\
+__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H)		\
+__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)	\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H)		\
+__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H)			\
+__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H)			\
+__PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H)			\
+__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H)				\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H)			\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", IAP_EVENT_10H_10H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", IAP_EVENT_10H_20H)	\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H)		\
+__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H)		\
+__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H)			\
+__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H)			\
+__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H)			\
+__PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H)			\
+__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H)		\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H)		\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H)				\
+__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H)				\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH)				\
+__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H)			\
+__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H)			\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H)			\
+__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H)				\
+__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H)				\
+__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H)				\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H)			\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H)			\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H)			\
+__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH)			\
+__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H)			\
+__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H)			\
+__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH)		\
+__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H)			\
+__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H)			\
+__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H)		\
+__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H)			\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_49H_01H)	\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H)		\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H)		\
+__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H)			\
+__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H)				\
+__PMC_EV_ALIAS("LOAD_HIT_PER.HW_PF", IAP_EVENT_4CH_02H)				\
+__PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H)			\
+__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H)				\
+__PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H)				\
+__PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H)				\
+__PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H)			\
+__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H)		\
+__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H)		\
+__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H)			\
+__PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH)			\
+__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H)				\
+__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H)				\
+__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H)			\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", IAP_EVENT_60H_01H)\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", IAP_EVENT_60H_04H)	\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", IAP_EVENT_60H_08H)	\
+__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", IAP_EVENT_63H_01H)	\
+__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H)		\
+__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H)					\
+__PMC_EV_ALIAS("IQD.MITE_UOPS", IAP_EVENT_79H_04H)				\
+__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H)				\
+__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H)				\
+__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H)				\
+__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H)				\
+__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H)				\
+__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H)		\
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H)			\
+__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H)			\
+__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H)			\
+__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H)				\
+__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H)				\
+__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H)				\
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_88H_04H)	\
+__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H)		\
+__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H)			\
+__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H)				\
+__PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H)				\
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_89H_04H)	\
+__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H)		\
+__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H)			\
+__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H)				\
+__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH)			\
+__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H)		\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H)			\
+__PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_04H)				\
+__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H)				\
+__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H)			\
+__PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H)			\
+__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H)			\
+__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H)			\
+__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H)			\
+__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H)		\
+__PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H)			\
+__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H)			\
+__PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH)			\
+__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H)				\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H)		\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H)		\
+__PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H)			\
+__PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H)			\
+__PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H)		\
+__PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H)			\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H)			\
+__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H)			\
+__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H)			\
+__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H)				\
+__PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H)		\
+__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H)				\
+__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H)			\
+__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H)				\
+__PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H)		\
+__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H)			\
+__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H)			\
+__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H)			\
+__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H)				\
+__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H)			\
+__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H)		\
+__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H)				\
+__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H)			\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H)		 	\
+__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H)		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H)			\
+__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) 		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H)		\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H)			\
+__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H)			\
+__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H)			\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H)		\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H)		\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H)			\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H)		\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H)			\
+__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H)			\
+__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H)			\
+__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H)			\
+__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H)			\
+__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H)			\
+__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH)				\
+__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H)		\
+__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H)		\
+__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H)		\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H)			\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H)			\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H)			\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H)			\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H)			\
+__PMC_EV_ALIAS("MEM_UOP_RETIRED_ALL", IAP_EVENT_D0H_80H)			\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H)		\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H)		\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H)		\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H)		\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", IAP_EVENT_D2H_01H)	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", IAP_EVENT_D2H_02H)	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", IAP_EVENT_D2H_04H)	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", IAP_EVENT_D2H_08H)	\
+__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS", IAP_EVENT_D4H_02H)	\
+__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H)			\
+__PMC_EV_ALIAS("L2_TRANS.RF0", IAP_EVENT_F0H_02H)				\
+__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H)				\
+__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H)				\
+__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H)				\
+__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H)				\
+__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H)				\
+__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H)			\
+__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H)				\
+__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H)				\
+__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H)				\
+__PMC_EV_ALIAS("L2_LINES-IN.ALL", IAP_EVENT_F1H_07H)				\
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H)			\
+__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H)			\
+__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H)			\
+__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H)			\
+__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH)			\
+__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H)				
+
+
+
 /* timestamp counters. */
 #define	__PMC_EV_TSC()							\
 	__PMC_EV(TSC, TSC)
@@ -2408,6 +2682,10 @@ __PMC_EV(UCP, EVENT_21H_04H)			\
 __PMC_EV(UCP, EVENT_22H_01H)			\
 __PMC_EV(UCP, EVENT_22H_02H)			\
 __PMC_EV(UCP, EVENT_22H_04H)			\
+__PMC_EV(UCP, EVENT_22H_08H)			\
+__PMC_EV(UCP, EVENT_22H_20H)			\
+__PMC_EV(UCP, EVENT_22H_40H)			\
+__PMC_EV(UCP, EVENT_22H_80H)			\
 __PMC_EV(UCP, EVENT_23H_01H)			\
 __PMC_EV(UCP, EVENT_23H_02H)			\
 __PMC_EV(UCP, EVENT_23H_04H)			\
@@ -2485,6 +2763,8 @@ __PMC_EV(UCP, EVENT_34H_04H)			\
 __PMC_EV(UCP, EVENT_34H_08H)			\
 __PMC_EV(UCP, EVENT_34H_10H)			\
 __PMC_EV(UCP, EVENT_34H_20H)			\
+__PMC_EV(UCP, EVENT_34H_40H)			\
+__PMC_EV(UCP, EVENT_34H_80H)			\
 __PMC_EV(UCP, EVENT_35H_01H)			\
 __PMC_EV(UCP, EVENT_35H_02H)			\
 __PMC_EV(UCP, EVENT_35H_04H)			\
@@ -2546,6 +2826,8 @@ __PMC_EV(UCP, EVENT_81H_01H)			\
 __PMC_EV(UCP, EVENT_81H_02H)			\
 __PMC_EV(UCP, EVENT_81H_04H)			\
 __PMC_EV(UCP, EVENT_81H_08H)			\
+__PMC_EV(UCP, EVENT_81H_20H)			\
+__PMC_EV(UCP, EVENT_81H_80H)			\
 __PMC_EV(UCP, EVENT_82H_01H)			\
 __PMC_EV(UCP, EVENT_83H_01H)			\
 __PMC_EV(UCP, EVENT_83H_02H)			\
@@ -2959,6 +3241,30 @@ __PMC_EV_ALIAS("TURBO_MODE.CORE_3", UCP_EVENT_84H_08H)	\
 __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_ENABLE", UCP_EVENT_85H_02H)	\
 __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H)
 
+
+#define	__PMC_EV_ALIAS_SANDYBRIDGEUC()						\
+__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITI", UCP_EVENT_22H_01H)			\
+__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITFSE", UCP_EVENT_22H_02H)		\
+__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSHITFSE", UCP_EVENT_22H_04H)		\
+__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSFWDM", UCP_EVENT_22H_08H)			\
+__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_EXTERNAL", UCP_EVENT_22H_20H)		\
+__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_XCORE", UCP_EVENT_22H_40H)		\
+__PMC_EV_ALIAS("CB0_XSNP_RESPONSE_AND_XCORE2", UCP_EVENT_22H_80H)  		\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.M", UCP_EVENT_34H_01H)				\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.E", UCP_EVENT_34H_02H)				\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.S", UCP_EVENT_34H_04H)				\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.I", UCP_EVENT_34H_08H)				\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_READ", UCP_EVENT_34H_10H)			\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP_AND_READ2", UCP_EVENT_34H_20H)	   	 	\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_EXTSNP", UCP_EVENT_34H_40H)		\
+__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_ANY", UCP_EVENT_34H_80H)			\
+__PMC_EV_ALIAS("IMPH_CB0_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H)			\
+__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.ALL", UCP_EVENT_81H_01H)			\
+__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H)		\
+__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H)		\
+__PMC_EV_ALIAS("IMPH_C0H_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H)			\
+__PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H)		 
+
 /*
  * Intel XScale events from:
  *
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
index 53827b4..e2d60e6 100644
--- a/sys/sys/pmc.h
+++ b/sys/sys/pmc.h
@@ -86,6 +86,7 @@
 	__PMC_CPU(INTEL_ATOM,	0x8A,	"Intel Atom") \
 	__PMC_CPU(INTEL_COREI7, 0x8B,   "Intel Core i7") \
 	__PMC_CPU(INTEL_WESTMERE, 0x8C,   "Intel Westmere") \
+	__PMC_CPU(INTEL_SANDYBRIDGE, 0x8D,   "Intel Sandy Bridge") \
 	__PMC_CPU(INTEL_XSCALE,	0x100,	"Intel XScale") \
 	__PMC_CPU(MIPS_24K,     0x200,  "MIPS 24K")  \
 	__PMC_CPU(PPC_7450,     0x300,  "PowerPC MPC7450")