Use _lapic+offset to access the local apic from assembly language

files, rather than the symbols in globals.s.  The offsets are
generated by genassym.

10 files changed, 74 insertions, 60 deletions

diff --git a/sys/amd64/amd64/apic_vector.S b/sys/amd64/amd64/apic_vector.S
index a23ccff..988e5e6 100644
--- a/sys/amd64/amd64/apic_vector.S
+++ b/sys/amd64/amd64/apic_vector.S
@@ -52,7 +52,7 @@ IDTVEC(vec_name) ;							\
 	pushl	_intr_unit + (irq_num) * 4 ;				\
 	call	*_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
 	addl	$4, %esp ;						\
-	movl	$0, lapic_eoi ;						\
+	movl	$0, _lapic+LA_EOI ;					\
 	lock ; 								\
 	incl	_cnt+V_INTR ;	/* book-keeping can wait */		\
 	movl	_intr_countp + (irq_num) * 4, %eax ;			\
@@ -95,15 +95,15 @@ IDTVEC(vec_name) ;							\
 	movl	(%eax), %eax ;						\
 	testl	_apic_isrbit_location + 4 + 8 * (irq_num), %eax ;	\
 	jz	9f ;				/* not active */	\
-	movl	$0, lapic_eoi ;						\
+	movl	$0, _lapic+LA_EOI ;					\
 	APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ;	\
 9:
 
 #else
 #define EOI_IRQ(irq_num)						\
-	testl	$IRQ_BIT(irq_num), lapic_isr1;				\
+	testl	$IRQ_BIT(irq_num), _lapic+LA_ISR1;			\
 	jz	9f	;			/* not active */	\
-	movl	$0, lapic_eoi;						\
+	movl	$0, _lapic+LA_EOI;					\
 	APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ;	\
 9:
 #endif
@@ -273,7 +273,7 @@ _Xinvltlb:
 	movl	%eax, %cr3
 
 	ss				/* stack segment, avoid %ds load */
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	popl	%eax
 	iret
@@ -310,7 +310,7 @@ _Xcpucheckstate:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	movl	$0, %ebx		
 	movl	20(%esp), %eax	
@@ -362,7 +362,7 @@ _Xcpuast:
 	movl	PCPU(CPUID), %eax
 	lock				/* checkstate_need_ast &= ~(1<<id) */
 	btrl	%eax, _checkstate_need_ast
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	lock
 	btsl	%eax, _checkstate_pending_ast
@@ -409,7 +409,7 @@ _Xforward_irq:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	FAKE_MCOUNT(13*4(%esp))
 
@@ -452,21 +452,21 @@ forward_irq:
 	shrl	$24,%eax
 	movl	_cpu_num_to_apic_id(,%eax,4),%ecx
 	shll	$24,%ecx
-	movl	lapic_icr_hi, %eax
+	movl	_lapic+LA_ICR_HI, %eax
 	andl	$~APIC_ID_MASK, %eax
 	orl	%ecx, %eax
-	movl	%eax, lapic_icr_hi
+	movl	%eax, _lapic+LA_ICR_HI
 
 2:
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_DELSTAT_MASK,%eax
 	jnz	2b
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_RESV2_MASK, %eax
 	orl	$(APIC_DEST_DESTFLD|APIC_DELMODE_FIXED|XFORWARD_IRQ_OFFSET), %eax
-	movl	%eax, lapic_icr_lo
+	movl	%eax, _lapic+LA_ICR_LO
 3:
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_DELSTAT_MASK,%eax
 	jnz	3b
 4:		
@@ -498,7 +498,7 @@ _Xcpustop:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	movl	PCPU(CPUID), %eax
 	imull	$PCB_SIZE, %eax
@@ -628,7 +628,7 @@ _Xrendezvous:
 
 	call	_smp_rendezvous_action
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 	POP_FRAME
 	iret
 	
diff --git a/sys/amd64/amd64/cpu_switch.S b/sys/amd64/amd64/cpu_switch.S
index c2cfa5e..6d2e30d 100644
--- a/sys/amd64/amd64/cpu_switch.S
+++ b/sys/amd64/amd64/cpu_switch.S
@@ -260,9 +260,9 @@ sw1b:
 #ifdef SMP
 #ifdef GRAB_LOPRIO				/* hold LOPRIO for INTs */
 #ifdef CHEAP_TPR
-	movl	$0, lapic_tpr
+	movl	$0, _lapic+LA_TPR
 #else
-	andl	$~APIC_TPR_PRIO, lapic_tpr
+	andl	$~APIC_TPR_PRIO, _lapic+LA_TPR
 #endif /** CHEAP_TPR */
 #endif /** GRAB_LOPRIO */
 	movl	PCPU(CPUID),%eax
diff --git a/sys/amd64/amd64/genassym.c b/sys/amd64/amd64/genassym.c
index 0f6fdfd..6f04558 100644
--- a/sys/amd64/amd64/genassym.c
+++ b/sys/amd64/amd64/genassym.c
@@ -212,6 +212,13 @@ ASSYM(GD_PRV_CADDR3, offsetof(struct globaldata, gd_prv_CADDR3));
 ASSYM(GD_PRV_PADDR1, offsetof(struct globaldata, gd_prv_PADDR1));
 ASSYM(PS_IDLESTACK, offsetof(struct privatespace, idlestack));
 ASSYM(PS_IDLESTACK_TOP, sizeof(struct privatespace));
+
+ASSYM(LA_VER, offsetof(struct LAPIC, version));
+ASSYM(LA_TPR, offsetof(struct LAPIC, tpr));
+ASSYM(LA_EOI, offsetof(struct LAPIC, eoi));
+ASSYM(LA_SVR, offsetof(struct LAPIC, svr));
+ASSYM(LA_ICR_LO, offsetof(struct LAPIC, icr_lo));
+ASSYM(LA_ICR_HI, offsetof(struct LAPIC, icr_hi));
 #endif
 
 ASSYM(KCSEL, GSEL(GCODE_SEL, SEL_KPL));
diff --git a/sys/amd64/amd64/mpboot.S b/sys/amd64/amd64/mpboot.S
index 9ede02c..fbd347b 100644
--- a/sys/amd64/amd64/mpboot.S
+++ b/sys/amd64/amd64/mpboot.S
@@ -103,12 +103,12 @@ mp_begin:	/* now running relocated at KERNBASE */
 1:
 
 	/* disable the APIC, just to be SURE */
-	movl	lapic_svr, %eax			/* get spurious vector reg. */
+	movl	_lapic+LA_SVR, %eax		/* get spurious vector reg. */
 	andl	$~APIC_SVR_SWEN, %eax		/* clear software enable bit */
-	movl	%eax, lapic_svr
+	movl	%eax, _lapic+LA_SVR
 
 	/* signal our startup to the BSP */
-	movl	lapic_ver, %eax			/* our version reg contents */
+	movl	_lapic+LA_VER, %eax		/* our version reg contents */
 	movl	%eax, _cpu_apic_versions	/* into [ 0 ] */
 	incl	_mp_ncpus			/* signal BSP */
 
diff --git a/sys/amd64/amd64/swtch.s b/sys/amd64/amd64/swtch.s
index c2cfa5e..6d2e30d 100644
--- a/sys/amd64/amd64/swtch.s
+++ b/sys/amd64/amd64/swtch.s
@@ -260,9 +260,9 @@ sw1b:
 #ifdef SMP
 #ifdef GRAB_LOPRIO				/* hold LOPRIO for INTs */
 #ifdef CHEAP_TPR
-	movl	$0, lapic_tpr
+	movl	$0, _lapic+LA_TPR
 #else
-	andl	$~APIC_TPR_PRIO, lapic_tpr
+	andl	$~APIC_TPR_PRIO, _lapic+LA_TPR
 #endif /** CHEAP_TPR */
 #endif /** GRAB_LOPRIO */
 	movl	PCPU(CPUID),%eax
diff --git a/sys/i386/i386/apic_vector.s b/sys/i386/i386/apic_vector.s
index a23ccff..988e5e6 100644
--- a/sys/i386/i386/apic_vector.s
+++ b/sys/i386/i386/apic_vector.s
@@ -52,7 +52,7 @@ IDTVEC(vec_name) ;							\
 	pushl	_intr_unit + (irq_num) * 4 ;				\
 	call	*_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
 	addl	$4, %esp ;						\
-	movl	$0, lapic_eoi ;						\
+	movl	$0, _lapic+LA_EOI ;					\
 	lock ; 								\
 	incl	_cnt+V_INTR ;	/* book-keeping can wait */		\
 	movl	_intr_countp + (irq_num) * 4, %eax ;			\
@@ -95,15 +95,15 @@ IDTVEC(vec_name) ;							\
 	movl	(%eax), %eax ;						\
 	testl	_apic_isrbit_location + 4 + 8 * (irq_num), %eax ;	\
 	jz	9f ;				/* not active */	\
-	movl	$0, lapic_eoi ;						\
+	movl	$0, _lapic+LA_EOI ;					\
 	APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ;	\
 9:
 
 #else
 #define EOI_IRQ(irq_num)						\
-	testl	$IRQ_BIT(irq_num), lapic_isr1;				\
+	testl	$IRQ_BIT(irq_num), _lapic+LA_ISR1;			\
 	jz	9f	;			/* not active */	\
-	movl	$0, lapic_eoi;						\
+	movl	$0, _lapic+LA_EOI;					\
 	APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ;	\
 9:
 #endif
@@ -273,7 +273,7 @@ _Xinvltlb:
 	movl	%eax, %cr3
 
 	ss				/* stack segment, avoid %ds load */
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	popl	%eax
 	iret
@@ -310,7 +310,7 @@ _Xcpucheckstate:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	movl	$0, %ebx		
 	movl	20(%esp), %eax	
@@ -362,7 +362,7 @@ _Xcpuast:
 	movl	PCPU(CPUID), %eax
 	lock				/* checkstate_need_ast &= ~(1<<id) */
 	btrl	%eax, _checkstate_need_ast
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	lock
 	btsl	%eax, _checkstate_pending_ast
@@ -409,7 +409,7 @@ _Xforward_irq:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	FAKE_MCOUNT(13*4(%esp))
 
@@ -452,21 +452,21 @@ forward_irq:
 	shrl	$24,%eax
 	movl	_cpu_num_to_apic_id(,%eax,4),%ecx
 	shll	$24,%ecx
-	movl	lapic_icr_hi, %eax
+	movl	_lapic+LA_ICR_HI, %eax
 	andl	$~APIC_ID_MASK, %eax
 	orl	%ecx, %eax
-	movl	%eax, lapic_icr_hi
+	movl	%eax, _lapic+LA_ICR_HI
 
 2:
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_DELSTAT_MASK,%eax
 	jnz	2b
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_RESV2_MASK, %eax
 	orl	$(APIC_DEST_DESTFLD|APIC_DELMODE_FIXED|XFORWARD_IRQ_OFFSET), %eax
-	movl	%eax, lapic_icr_lo
+	movl	%eax, _lapic+LA_ICR_LO
 3:
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_DELSTAT_MASK,%eax
 	jnz	3b
 4:		
@@ -498,7 +498,7 @@ _Xcpustop:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	movl	PCPU(CPUID), %eax
 	imull	$PCB_SIZE, %eax
@@ -628,7 +628,7 @@ _Xrendezvous:
 
 	call	_smp_rendezvous_action
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 	POP_FRAME
 	iret
 	
diff --git a/sys/i386/i386/genassym.c b/sys/i386/i386/genassym.c
index 0f6fdfd..6f04558 100644
--- a/sys/i386/i386/genassym.c
+++ b/sys/i386/i386/genassym.c
@@ -212,6 +212,13 @@ ASSYM(GD_PRV_CADDR3, offsetof(struct globaldata, gd_prv_CADDR3));
 ASSYM(GD_PRV_PADDR1, offsetof(struct globaldata, gd_prv_PADDR1));
 ASSYM(PS_IDLESTACK, offsetof(struct privatespace, idlestack));
 ASSYM(PS_IDLESTACK_TOP, sizeof(struct privatespace));
+
+ASSYM(LA_VER, offsetof(struct LAPIC, version));
+ASSYM(LA_TPR, offsetof(struct LAPIC, tpr));
+ASSYM(LA_EOI, offsetof(struct LAPIC, eoi));
+ASSYM(LA_SVR, offsetof(struct LAPIC, svr));
+ASSYM(LA_ICR_LO, offsetof(struct LAPIC, icr_lo));
+ASSYM(LA_ICR_HI, offsetof(struct LAPIC, icr_hi));
 #endif
 
 ASSYM(KCSEL, GSEL(GCODE_SEL, SEL_KPL));
diff --git a/sys/i386/i386/mpboot.s b/sys/i386/i386/mpboot.s
index 9ede02c..fbd347b 100644
--- a/sys/i386/i386/mpboot.s
+++ b/sys/i386/i386/mpboot.s
@@ -103,12 +103,12 @@ mp_begin:	/* now running relocated at KERNBASE */
 1:
 
 	/* disable the APIC, just to be SURE */
-	movl	lapic_svr, %eax			/* get spurious vector reg. */
+	movl	_lapic+LA_SVR, %eax		/* get spurious vector reg. */
 	andl	$~APIC_SVR_SWEN, %eax		/* clear software enable bit */
-	movl	%eax, lapic_svr
+	movl	%eax, _lapic+LA_SVR
 
 	/* signal our startup to the BSP */
-	movl	lapic_ver, %eax			/* our version reg contents */
+	movl	_lapic+LA_VER, %eax		/* our version reg contents */
 	movl	%eax, _cpu_apic_versions	/* into [ 0 ] */
 	incl	_mp_ncpus			/* signal BSP */
 
diff --git a/sys/i386/i386/swtch.s b/sys/i386/i386/swtch.s
index c2cfa5e..6d2e30d 100644
--- a/sys/i386/i386/swtch.s
+++ b/sys/i386/i386/swtch.s
@@ -260,9 +260,9 @@ sw1b:
 #ifdef SMP
 #ifdef GRAB_LOPRIO				/* hold LOPRIO for INTs */
 #ifdef CHEAP_TPR
-	movl	$0, lapic_tpr
+	movl	$0, _lapic+LA_TPR
 #else
-	andl	$~APIC_TPR_PRIO, lapic_tpr
+	andl	$~APIC_TPR_PRIO, _lapic+LA_TPR
 #endif /** CHEAP_TPR */
 #endif /** GRAB_LOPRIO */
 	movl	PCPU(CPUID),%eax
diff --git a/sys/i386/isa/apic_vector.s b/sys/i386/isa/apic_vector.s
index a23ccff..988e5e6 100644
--- a/sys/i386/isa/apic_vector.s
+++ b/sys/i386/isa/apic_vector.s
@@ -52,7 +52,7 @@ IDTVEC(vec_name) ;							\
 	pushl	_intr_unit + (irq_num) * 4 ;				\
 	call	*_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
 	addl	$4, %esp ;						\
-	movl	$0, lapic_eoi ;						\
+	movl	$0, _lapic+LA_EOI ;					\
 	lock ; 								\
 	incl	_cnt+V_INTR ;	/* book-keeping can wait */		\
 	movl	_intr_countp + (irq_num) * 4, %eax ;			\
@@ -95,15 +95,15 @@ IDTVEC(vec_name) ;							\
 	movl	(%eax), %eax ;						\
 	testl	_apic_isrbit_location + 4 + 8 * (irq_num), %eax ;	\
 	jz	9f ;				/* not active */	\
-	movl	$0, lapic_eoi ;						\
+	movl	$0, _lapic+LA_EOI ;					\
 	APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ;	\
 9:
 
 #else
 #define EOI_IRQ(irq_num)						\
-	testl	$IRQ_BIT(irq_num), lapic_isr1;				\
+	testl	$IRQ_BIT(irq_num), _lapic+LA_ISR1;			\
 	jz	9f	;			/* not active */	\
-	movl	$0, lapic_eoi;						\
+	movl	$0, _lapic+LA_EOI;					\
 	APIC_ITRACE(apic_itrace_eoi, irq_num, APIC_ITRACE_EOI) ;	\
 9:
 #endif
@@ -273,7 +273,7 @@ _Xinvltlb:
 	movl	%eax, %cr3
 
 	ss				/* stack segment, avoid %ds load */
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	popl	%eax
 	iret
@@ -310,7 +310,7 @@ _Xcpucheckstate:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	movl	$0, %ebx		
 	movl	20(%esp), %eax	
@@ -362,7 +362,7 @@ _Xcpuast:
 	movl	PCPU(CPUID), %eax
 	lock				/* checkstate_need_ast &= ~(1<<id) */
 	btrl	%eax, _checkstate_need_ast
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	lock
 	btsl	%eax, _checkstate_pending_ast
@@ -409,7 +409,7 @@ _Xforward_irq:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	FAKE_MCOUNT(13*4(%esp))
 
@@ -452,21 +452,21 @@ forward_irq:
 	shrl	$24,%eax
 	movl	_cpu_num_to_apic_id(,%eax,4),%ecx
 	shll	$24,%ecx
-	movl	lapic_icr_hi, %eax
+	movl	_lapic+LA_ICR_HI, %eax
 	andl	$~APIC_ID_MASK, %eax
 	orl	%ecx, %eax
-	movl	%eax, lapic_icr_hi
+	movl	%eax, _lapic+LA_ICR_HI
 
 2:
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_DELSTAT_MASK,%eax
 	jnz	2b
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_RESV2_MASK, %eax
 	orl	$(APIC_DEST_DESTFLD|APIC_DELMODE_FIXED|XFORWARD_IRQ_OFFSET), %eax
-	movl	%eax, lapic_icr_lo
+	movl	%eax, _lapic+LA_ICR_LO
 3:
-	movl	lapic_icr_lo, %eax
+	movl	_lapic+LA_ICR_LO, %eax
 	andl	$APIC_DELSTAT_MASK,%eax
 	jnz	3b
 4:		
@@ -498,7 +498,7 @@ _Xcpustop:
 	movl	$KPSEL, %eax
 	mov	%ax, %fs
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 
 	movl	PCPU(CPUID), %eax
 	imull	$PCB_SIZE, %eax
@@ -628,7 +628,7 @@ _Xrendezvous:
 
 	call	_smp_rendezvous_action
 
-	movl	$0, lapic_eoi		/* End Of Interrupt to APIC */
+	movl	$0, _lapic+LA_EOI	/* End Of Interrupt to APIC */
 	POP_FRAME
 	iret