Added support for 82545EM and 82546EB based adapters.

Added Vlan support.

MFC after:	1 week

9 files changed, 7205 insertions, 1761 deletions

diff --git a/sys/conf/files.i386 b/sys/conf/files.i386
index 16810c4..f3bf1bb 100644
--- a/sys/conf/files.i386
+++ b/sys/conf/files.i386
@@ -106,8 +106,7 @@ dev/cm/if_cm_isa.c		optional	cm isa
 dev/ed/if_ed_isa.c		optional	ed isa
 dev/eisa/eisaconf.c		optional	eisa
 dev/em/if_em.c			optional	em
-dev/em/if_em_fxhw.c		optional	em
-dev/em/if_em_phy.c		optional	em
+dev/em/if_em_hw.c		optional	em
 dev/fb/fb.c			optional	fb
 dev/fb/fb.c			optional	vga
 dev/fb/splash.c			optional	splash
diff --git a/sys/conf/files.pc98 b/sys/conf/files.pc98
index 3295a42..20de2f1 100644
--- a/sys/conf/files.pc98
+++ b/sys/conf/files.pc98
@@ -104,8 +104,7 @@ dev/ct/ct.c			optional	ct
 dev/ct/ct_isa.c			optional	ct isa
 dev/ed/if_ed_cbus.c		optional	ed isa
 dev/em/if_em.c			optional	em
-dev/em/if_em_fxhw.c		optional	em
-dev/em/if_em_phy.c		optional	em
+dev/em/if_em_hw.c		optional	em
 dev/fb/fb.c			optional	fb
 dev/fb/fb.c			optional	gdc
 dev/fb/splash.c			optional	splash
diff --git a/sys/dev/em/README b/sys/dev/em/README
new file mode 100644
index 0000000..cb3c8b9
--- /dev/null
+++ b/sys/dev/em/README
@@ -0,0 +1,281 @@
+$FreeBSD$
+
+FreeBSD* Driver for the Intel(R) PRO/1000 Family of Adapters
+============================================================
+
+April 3, 2002
+
+
+Contents
+========
+
+- In This Release
+- Supported Adapters
+- Building and Installation
+- Speed and Duplex Configuration
+- Additional Configurations
+- Known Limitations
+- Support
+- License
+
+
+In This Release
+===============
+
+This file describes the FreeBSD* driver, version 1.3.x, for the Intel(R)
+PRO/1000 Family of Adapters. This driver has been developed for use with 
+FreeBSD, version 4.5.
+
+The driver supports Transmit/Receive Checksum Offload and Jumbo Frames on 
+all but the 82542-based adapters. For specific adapters, refer to the 
+Supported Adapters section below.
+
+Support for VLANs has been added as a new feature in this driver version.
+
+For questions related to hardware requirements, refer to the documentation 
+supplied with your Intel PRO/1000 adapter. All hardware requirements listed 
+apply to use with FreeBSD.
+
+
+Supported Adapters
+==================
+
+The following Intel network adapters are compatible with the drivers in this 
+release:
+
+   Controller  Adapter Name                         Board IDs
+   ----------  ------------                         ---------
+
+   82542       PRO/1000 Gigabit Server Adapter      700262-xxx, 717037-xxx
+
+   82543       PRO/1000 F Server Adapter            738640-xxx, A38888-xxx,
+                                                    A06512-xxx
+
+   82543       PRO/1000 T Server Adapter            A19845-xxx, A33948-xxx
+
+   82544       PRO/1000 XT Server Adapter           A51580-xxx
+
+   82544       PRO/1000 XF Server Adapter           A50484-xxx
+
+   82544       PRO/1000 T Desktop Adapter           A62947-xxx
+
+   82540       PRO/1000 MT Desktop Adapter          A78708-xxx
+
+   82545       PRO/1000 MT Server Adapter           A92165-xxx
+
+   82545       PRO/1000 MF Server Adapter           A91622-xxx
+
+   82545       PRO/1000 MF Server Adapter(LX)       A91624-xxx
+
+   82546       PRO/1000 MT Dual Port Server Adapter A92111-xxx
+
+   82546       PRO/1000 MF Dual Port Server Adapter A91620-xxx
+
+
+To verify your Intel adapter is supported, find the board ID number on the
+adapter. Look for a label that has a barcode and a number in the format of
+123456-001 (six digits hyphen three digits). Match this to the list of 
+numbers above.
+
+For more information on how to identify your adapter, go to the Adapter &
+Driver ID Guide at:
+
+    http://support.intel.com/support/network/adapter/pro100/21397.htm
+
+For the latest Intel network drivers for FreeBSD, see:
+
+    http://appsr.intel.com/scripts-df/support_intel.asp
+
+
+Building and Installation
+=========================
+
+NOTE: You must have kernel sources installed in order to compile the driver
+      module.
+
+      In the instructions below, x.x.x is the driver version as indicated in
+      the name of the driver tar.
+
+
+1. Move the base driver tar file to the directory of your choice. For 
+   example, use /home/username/em or /usr/local/src/em.
+
+2. Untar/unzip the archive:
+
+        tar xfz em-x.x.x.tar.gz
+
+3. To load the driver onto a running system:
+
+        cd em-x.x.x/modules
+        kldload ./if_em.ko
+
+4. To assign an IP address to the interface, enter the following:
+
+        ifconfig em<interface_num> <IP_address>
+
+5. Verify that the interface works. Enter the following, where <IP_address>
+   is the IP address for another machine on the same subnet as the interface
+   that is being tested:
+
+        ping <IP_address>
+
+6. If you want the driver to load automatically when the system is booted:
+
+        cd em-x.x.x/modules
+        cp if_em.ko /modules
+        
+   Edit /boot/loader.conf, and add the following line:
+        
+             if_em_load="YES"
+
+               OR
+
+        compile the driver into the kernel (see item 7).
+
+
+   Edit /etc/rc.conf, and create the appropriate ifconfig_em<interface_num> 
+   entry:
+
+        ifconfig_em<interface_num>="<ifconfig_settings>"
+
+     Example usage:
+
+        ifconfig_em0="inet 192.168.10.1 netmask 255.255.255.0"
+
+     NOTE: For assistance, see the ifconfig man page.
+
+7. If you want to compile the driver into the kernel, enter:
+
+        mkdir /usr/src/sys/dev/em       
+        cd em-x.x.x/src
+        cp if_em* /usr/src/sys/dev/em   
+        mkdir /usr/src/sys/modules/em
+        cp Makefile /usr/src/sys/modules/em
+
+   Edit Makefile at /usr/src/sys/modules to add the em subdirectory.
+
+   Edit your config file and add the following line, if it is not already
+   in the file:
+
+        device em
+
+   Edit your config file, and remove the 'device wx' line from the file.
+        
+   Edit the /usr/src/sys/conf/files.i386 file, and add the following lines:
+
+        dev/em/if_em.c optional em
+        dev/em/if_em_hw.c optional em
+
+   Remove the following files from the /usr/src/sys/conf/files.i386 file, if 
+   they exist:
+
+        /dev/em/if_em_fxhw.c
+        /dev/em/if_em_phy.c
+
+   Compile and install the kernel.
+
+
+Speed and Duplex Configuration
+==============================
+
+By default, the adapter auto-negotiates the speed and duplex of the 
+connection. If there is a specific need, the ifconfig utility can be used to 
+configure the speed and duplex settings on the adapter. Example usage:
+
+        ifconfig em<interface_num> <IP_address> media 100baseTX mediaopt 
+            full-duplex
+
+   NOTE: Only use mediaopt to set the driver to full-duplex. If mediaopt is 
+         not specified and you are not running at gigabit speed, the driver 
+         defaults to half-duplex.
+
+
+This driver supports the following media type options:
+
+   autoselect      -  Enables auto-negotiation for speed and duplex.
+
+   10baseT/UTP     -  Sets speed to 10 Mbps. Use the ifconfig mediaopt 
+                      option to select full-duplex mode.
+
+   100baseTX       -  Sets speed to 100 Mbps. Use the ifconfig mediaopt
+                      option to select full-duplex mode.
+
+   1000baseTX      -  Sets speed to 1000 Mbps. In this case, the driver
+                      supports only full-duplex mode.
+
+   1000baseSX      -  Sets speed to 1000 Mbps. In this case, the driver
+                      supports only full-duplex mode.
+
+For more information on the ifconfig utility, see the ifconfig man page.
+
+
+Additional Configurations
+=========================
+
+  Jumbo Frames
+  ------------
+
+  To enable Jumbo Frames, use the ifconfig utility to increase the MTU 
+  beyond 1500 bytes. 
+
+  NOTE: Only enable Jumbo Frames if your network infrastructure supports 
+        them.
+
+  The MTU range for Jumbo Frames is 1500 to 16114. For example, enter the 
+  following:
+
+        ifconfig em<interface_num> mtu 9000
+
+  VLANs
+  -----
+
+  To enable VLANs in the kernel, modify the config file as follows:
+
+        pseudo-device  vlan <num_VLANs>
+
+  Then, recompile the kernel and reboot.
+
+  To see the VLAN device entries, use ifconfig.
+
+  To attach a VLAN to the driver enter the following:
+
+        ifconfig vlan0 inet 10.0.0.1 netmask 255.255.255.0 vlan 1 vlandev 
+             em0 mtu 1500 up
+
+  Also, bring the driver up by entering:
+
+        ifconfig em0 up
+
+
+Known Limitations
+=================
+ 
+There are known performance problems with this driver when running UDP 
+traffic with Jumbo Frames. Intel recommends not using Jumbo Frames for UDP
+traffic.
+
+
+Support
+=======
+
+For general information and support, go to the Intel support website at:
+
+        http://support.intel.com
+
+If an issue is identified with the released source code on the supported
+kernel with a supported adapter, email the specific information related to 
+the issue to freebsdnic@mailbox.intel.com.
+
+
+License
+=======
+
+This software program is released under the terms of a license agreement 
+between you ('Licensee') and Intel. Do not use or load this software or any 
+associated materials (collectively, the 'Software') until you have carefully 
+read the full terms and conditions of the LICENSE located in this software 
+package. By loading or using the Software, you agree to the terms of this 
+Agreement. If you do not agree with the terms of this Agreement, do not 
+install or use the Software.
+
+* Other names and brands may be claimed as the property of others.
diff --git a/sys/dev/em/if_em.c b/sys/dev/em/if_em.c
index 3a34e22..e91abd6 100644
--- a/sys/dev/em/if_em.c
+++ b/sys/dev/em/if_em.c
@@ -53,7 +53,7 @@ struct adapter *em_adapter_list = NULL;
  *  Driver version
  *********************************************************************/
 
-char em_driver_version[] = "1.2.7";
+char em_driver_version[] = "1.3.8";
 
 
 /*********************************************************************
@@ -67,17 +67,21 @@ char em_driver_version[] = "1.2.7";
  *********************************************************************/
 static em_vendor_info_t em_vendor_info_array[] =
 {
-   /* Intel(R) PRO/1000 Network Connection */
-    { 0x8086, 0x1000, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    { 0x8086, 0x1001, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    { 0x8086, 0x1004, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    { 0x8086, 0x1008, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    { 0x8086, 0x1009, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    { 0x8086, 0x100C, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    { 0x8086, 0x100D, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    { 0x8086, 0x100E, PCI_ANY_ID, PCI_ANY_ID, 0 },
-    /* required last entry */
-    { 0, 0, 0, 0, 0}
+	/* Intel(R) PRO/1000 Network Connection */
+	{ 0x8086, 0x1000, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x1001, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x1004, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x1008, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x1009, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x100C, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x100D, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x100E, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x100F, PCI_ANY_ID, PCI_ANY_ID, 0},    
+	{ 0x8086, 0x1010, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0},
+	{ 0x8086, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0},
+	/* required last entry */
+	{ 0, 0, 0, 0, 0}
 };
 
 
@@ -86,7 +90,7 @@ static em_vendor_info_t em_vendor_info_array[] =
  *********************************************************************/
 
 static char *em_strings[] = {
-    "Intel(R) PRO/1000 Network Connection"
+	"Intel(R) PRO/1000 Network Connection"
 };
 
 /*********************************************************************
@@ -109,7 +113,6 @@ static int  em_allocate_pci_resources(struct adapter *);
 static void em_free_pci_resources(struct adapter *);
 static void em_local_timer(void *);
 static int  em_hardware_init(struct adapter *);
-static void em_read_mac_address(struct adapter *, u_int8_t *);
 static void em_setup_interface(device_t, struct adapter *);
 static int  em_setup_transmit_structures(struct adapter *);
 static void em_initialize_transmit_unit(struct adapter *);
@@ -125,35 +128,37 @@ static int  em_allocate_receive_structures(struct adapter *);
 static int  em_allocate_transmit_structures(struct adapter *);
 static void em_process_receive_interrupts(struct adapter *);
 static void em_receive_checksum(struct adapter *, 
-                                struct em_rx_desc * rx_desc,
-                                struct mbuf *);
+				struct em_rx_desc * rx_desc,
+				struct mbuf *);
 static void em_transmit_checksum_setup(struct adapter *,
-                                       struct mbuf *,
-                                       struct em_tx_buffer *,
-                                       u_int32_t *,
-                                       u_int32_t *);
+				       struct mbuf *,
+				       struct em_tx_buffer *,
+				       u_int32_t *,
+				       u_int32_t *);
 static void em_set_promisc(struct adapter *);
 static void em_disable_promisc(struct adapter *);
 static void em_set_multi(struct adapter *);
 static void em_print_hw_stats(struct adapter *);
 static void em_print_link_status(struct adapter *);
 static int  em_get_buf(struct em_rx_buffer *, struct adapter *,
-                       struct mbuf *);
+		       struct mbuf *);
+static void em_enable_vlans(struct adapter *adapter);
+
 /*********************************************************************
  *  FreeBSD Device Interface Entry Points                    
  *********************************************************************/
 
 static device_method_t em_methods[] = {
-   /* Device interface */
-   DEVMETHOD(device_probe, em_probe),
-   DEVMETHOD(device_attach, em_attach),
-   DEVMETHOD(device_detach, em_detach),
-   DEVMETHOD(device_shutdown, em_shutdown),
-   {0, 0}
+	/* Device interface */
+	DEVMETHOD(device_probe, em_probe),
+	DEVMETHOD(device_attach, em_attach),
+	DEVMETHOD(device_detach, em_detach),
+	DEVMETHOD(device_shutdown, em_shutdown),
+	{0, 0}
 };
 
 static driver_t em_driver = {
-   "em", em_methods, sizeof(struct adapter ),
+	"em", em_methods, sizeof(struct adapter ),
 };
 
 static devclass_t em_devclass;
@@ -171,45 +176,44 @@ DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0);
 static int
 em_probe(device_t dev)
 {
-   em_vendor_info_t *ent;
-
-   u_int16_t       pci_vendor_id = 0;
-   u_int16_t       pci_device_id = 0;
-   u_int16_t       pci_subvendor_id = 0;
-   u_int16_t       pci_subdevice_id = 0;
-   char            adapter_name[60];
-
-   INIT_DEBUGOUT("em_probe: begin");
-
-   pci_vendor_id = pci_get_vendor(dev);
-   if (pci_vendor_id != EM_VENDOR_ID)
-      return (ENXIO);
-
-   pci_device_id = pci_get_device(dev);
-   pci_subvendor_id = pci_get_subvendor(dev);
-   pci_subdevice_id = pci_get_subdevice(dev);
-
-   ent = em_vendor_info_array;
-   while(ent->vendor_id != 0) {
-      if ((pci_vendor_id == ent->vendor_id) &&
-          (pci_device_id == ent->device_id) &&
-          
-          ((pci_subvendor_id == ent->subvendor_id) ||
-           (ent->subvendor_id == PCI_ANY_ID)) &&
-
-          ((pci_subdevice_id == ent->subdevice_id) ||
-           (ent->subdevice_id == PCI_ANY_ID))) {
-         INIT_DEBUGOUT1("em_probe: Found PRO/1000  (pci_device_id=0x%x)",
-                        pci_device_id);
-         sprintf(adapter_name, "%s, Version - %s", em_strings[ent->index], 
-                 em_driver_version);
-         device_set_desc_copy(dev, adapter_name);
-         return(0);
-      }
-      ent++;
-   }
-
-   return (ENXIO);
+	em_vendor_info_t *ent;
+
+	u_int16_t       pci_vendor_id = 0;
+	u_int16_t       pci_device_id = 0;
+	u_int16_t       pci_subvendor_id = 0;
+	u_int16_t       pci_subdevice_id = 0;
+	char            adapter_name[60];
+
+	INIT_DEBUGOUT("em_probe: begin");
+
+	pci_vendor_id = pci_get_vendor(dev);
+	if (pci_vendor_id != EM_VENDOR_ID)
+		return(ENXIO);
+
+	pci_device_id = pci_get_device(dev);
+	pci_subvendor_id = pci_get_subvendor(dev);
+	pci_subdevice_id = pci_get_subdevice(dev);
+
+	ent = em_vendor_info_array;
+	while (ent->vendor_id != 0) {
+		if ((pci_vendor_id == ent->vendor_id) &&
+		    (pci_device_id == ent->device_id) &&
+
+		    ((pci_subvendor_id == ent->subvendor_id) ||
+		     (ent->subvendor_id == PCI_ANY_ID)) &&
+
+		    ((pci_subdevice_id == ent->subdevice_id) ||
+		     (ent->subdevice_id == PCI_ANY_ID))) {
+			sprintf(adapter_name, "%s, Version - %s", 
+				em_strings[ent->index], 
+				em_driver_version);
+			device_set_desc_copy(dev, adapter_name);
+			return(0);
+		}
+		ent++;
+	}
+
+	return(ENXIO);
 }
 
 /*********************************************************************
@@ -225,133 +229,140 @@ em_probe(device_t dev)
 static int
 em_attach(device_t dev)
 {
-   struct adapter * adapter;
-   int             s;
-   int             tsize, rsize;
-
-   INIT_DEBUGOUT("em_attach: begin");
-   s = splimp();
-
-   /* Allocate, clear, and link in our adapter structure */
-   if (!(adapter = device_get_softc(dev))) {
-      printf("em: adapter structure allocation failed\n");
-      splx(s);
-      return(ENOMEM);
-   }
-   bzero(adapter, sizeof(struct adapter ));
-   adapter->dev = dev;
-   adapter->osdep.dev = dev;
-   adapter->unit = device_get_unit(dev);
-
-   if (em_adapter_list != NULL)
-      em_adapter_list->prev = adapter;
-   adapter->next = em_adapter_list;
-   em_adapter_list = adapter;
-
-   callout_handle_init(&adapter->timer_handle);
-
-   /* Determine hardware revision */
-   em_identify_hardware(adapter);
-
-   /* Parameters (to be read from user) */
-   adapter->num_tx_desc = MAX_TXD;
-   adapter->num_rx_desc = MAX_RXD;
-   adapter->tx_int_delay = TIDV;
-   adapter->rx_int_delay = RIDV;
-   adapter->shared.autoneg = DO_AUTO_NEG;
-   adapter->shared.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
-   adapter->shared.autoneg_advertised = AUTONEG_ADV_DEFAULT;
-   adapter->shared.tbi_compatibility_en = TRUE;
-   adapter->rx_buffer_len = EM_RXBUFFER_2048;
-   adapter->rx_checksum = EM_ENABLE_RXCSUM_OFFLOAD;
-   
-   adapter->shared.fc_high_water = FC_DEFAULT_HI_THRESH;
-   adapter->shared.fc_low_water  = FC_DEFAULT_LO_THRESH;
-   adapter->shared.fc_pause_time = FC_DEFAULT_TX_TIMER;
-   adapter->shared.fc_send_xon   = TRUE;
-   adapter->shared.fc = em_fc_full;
-
-   /* Set the max frame size assuming standard ethernet sized frames */   
-   adapter->shared.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
-   adapter->shared.min_frame_size = MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
-
-   /* This controls when hardware reports transmit completion status. */
-   if ((EM_REPORT_TX_EARLY == 0) || (EM_REPORT_TX_EARLY == 1)) {
-      adapter->shared.report_tx_early = EM_REPORT_TX_EARLY;
-   } else {
-      if(adapter->shared.mac_type < em_82543) {
-         adapter->shared.report_tx_early = 0;
-      } else {
-         adapter->shared.report_tx_early = 1;
-      }
-   }
-
-   if (em_allocate_pci_resources(adapter)) {
-      printf("em%d: Allocation of PCI resources failed\n", adapter->unit);
-      em_free_pci_resources(adapter);
-      splx(s);
-      return(ENXIO);
-   }
-
-   tsize = EM_ROUNDUP(adapter->num_tx_desc *
-                      sizeof(struct em_tx_desc), 4096);
-
-   /* Allocate Transmit Descriptor ring */
-   if (!(adapter->tx_desc_base = (struct em_tx_desc *)
-         contigmalloc(tsize, M_DEVBUF, M_NOWAIT, 0, ~0, PAGE_SIZE, 0))) {
-      printf("em%d: Unable to allocate TxDescriptor memory\n", adapter->unit);
-      em_free_pci_resources(adapter);
-      splx(s);
-      return(ENOMEM);
-   }
-
-   rsize = EM_ROUNDUP(adapter->num_rx_desc *
-                      sizeof(struct em_rx_desc), 4096);
-
-   /* Allocate Receive Descriptor ring */
-   if (!(adapter->rx_desc_base = (struct em_rx_desc *)
-        contigmalloc(rsize, M_DEVBUF, M_NOWAIT, 0, ~0, PAGE_SIZE, 0))) {
-      printf("em%d: Unable to allocate rx_desc memory\n", adapter->unit);
-      em_free_pci_resources(adapter);
-      contigfree(adapter->tx_desc_base, tsize, M_DEVBUF);
-      splx(s);
-      return(ENOMEM);
-   }
-
-   /* Initialize the hardware */
-   if (em_hardware_init(adapter)) {
-      printf("em%d: Unable to initialize the hardware\n",adapter->unit);
-      em_free_pci_resources(adapter);
-      contigfree(adapter->tx_desc_base, tsize, M_DEVBUF);
-      contigfree(adapter->rx_desc_base, rsize, M_DEVBUF);
-      splx(s);
-      return(EIO);
-   }
-
-   /* Setup OS specific network interface */
-   em_setup_interface(dev, adapter);
-
-   /* Initialize statistics */
-   em_clear_hw_cntrs(&adapter->shared);
-   em_update_stats_counters(adapter);
-   adapter->shared.get_link_status = 1;
-   em_check_for_link(&adapter->shared);
-
-   /* Print the link status */
-   if (adapter->link_active == 1) {
-      em_get_speed_and_duplex(&adapter->shared, &adapter->link_speed, &adapter->link_duplex);
-      printf("em%d:  Speed:%d Mbps  Duplex:%s\n",
-             adapter->unit,
-             adapter->link_speed,
-             adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half");
-   }
-   else
-      printf("em%d:  Speed:N/A  Duplex:N/A\n", adapter->unit);
-
-
-   INIT_DEBUGOUT("em_attach: end");
-   splx(s);
-   return(0);
+	struct adapter * adapter;
+	int             s;
+	int             tsize, rsize;
+
+	INIT_DEBUGOUT("em_attach: begin");
+	s = splimp();
+
+	/* Allocate, clear, and link in our adapter structure */
+	if (!(adapter = device_get_softc(dev))) {
+		printf("em: adapter structure allocation failed\n");
+		splx(s);
+		return(ENOMEM);
+	}
+	bzero(adapter, sizeof(struct adapter ));
+	adapter->dev = dev;
+	adapter->osdep.dev = dev;
+	adapter->unit = device_get_unit(dev);
+
+	if (em_adapter_list != NULL)
+		em_adapter_list->prev = adapter;
+	adapter->next = em_adapter_list;
+	em_adapter_list = adapter;
+
+	callout_handle_init(&adapter->timer_handle);
+
+	/* Determine hardware revision */
+	em_identify_hardware(adapter);
+
+	/* Parameters (to be read from user) */
+	adapter->num_tx_desc = MAX_TXD;
+	adapter->num_rx_desc = MAX_RXD;
+	adapter->tx_int_delay = TIDV;
+	adapter->rx_int_delay = RIDV;
+	adapter->hw.autoneg = DO_AUTO_NEG;
+	adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
+	adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
+	adapter->hw.tbi_compatibility_en = TRUE;
+	adapter->rx_buffer_len = EM_RXBUFFER_2048;
+	adapter->rx_checksum = EM_ENABLE_RXCSUM_OFFLOAD;
+
+	adapter->hw.fc_high_water = FC_DEFAULT_HI_THRESH;
+	adapter->hw.fc_low_water  = FC_DEFAULT_LO_THRESH;
+	adapter->hw.fc_pause_time = FC_DEFAULT_TX_TIMER;
+	adapter->hw.fc_send_xon   = TRUE;
+	adapter->hw.fc = em_fc_full;
+
+	/* Set the max frame size assuming standard ethernet sized frames */   
+	adapter->hw.max_frame_size = 
+	ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
+
+	adapter->hw.min_frame_size = 
+	MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
+
+	/* This controls when hardware reports transmit completion status. */
+	if ((EM_REPORT_TX_EARLY == 0) || (EM_REPORT_TX_EARLY == 1)) {
+		adapter->hw.report_tx_early = EM_REPORT_TX_EARLY;
+	} else {
+		if (adapter->hw.mac_type < em_82543) {
+			adapter->hw.report_tx_early = 0;
+		} else {
+			adapter->hw.report_tx_early = 1;
+		}
+	}
+
+	if (em_allocate_pci_resources(adapter)) {
+		printf("em%d: Allocation of PCI resources failed\n", 
+		       adapter->unit);
+		em_free_pci_resources(adapter);
+		splx(s);
+		return(ENXIO);
+	}
+
+	tsize = EM_ROUNDUP(adapter->num_tx_desc *
+			   sizeof(struct em_tx_desc), 4096);
+
+	/* Allocate Transmit Descriptor ring */
+	if (!(adapter->tx_desc_base = (struct em_tx_desc *)
+	      contigmalloc(tsize, M_DEVBUF, M_NOWAIT, 0, ~0, PAGE_SIZE, 0))) {
+		printf("em%d: Unable to allocate TxDescriptor memory\n", 
+		       adapter->unit);
+		em_free_pci_resources(adapter);
+		splx(s);
+		return(ENOMEM);
+	}
+
+	rsize = EM_ROUNDUP(adapter->num_rx_desc *
+			   sizeof(struct em_rx_desc), 4096);
+
+	/* Allocate Receive Descriptor ring */
+	if (!(adapter->rx_desc_base = (struct em_rx_desc *)
+	      contigmalloc(rsize, M_DEVBUF, M_NOWAIT, 0, ~0, PAGE_SIZE, 0))) {
+		printf("em%d: Unable to allocate rx_desc memory\n", 
+		       adapter->unit);
+		em_free_pci_resources(adapter);
+		contigfree(adapter->tx_desc_base, tsize, M_DEVBUF);
+		splx(s);
+		return(ENOMEM);
+	}
+
+	/* Initialize the hardware */
+	if (em_hardware_init(adapter)) {
+		printf("em%d: Unable to initialize the hardware\n",
+		       adapter->unit);
+		em_free_pci_resources(adapter);
+		contigfree(adapter->tx_desc_base, tsize, M_DEVBUF);
+		contigfree(adapter->rx_desc_base, rsize, M_DEVBUF);
+		splx(s);
+		return(EIO);
+	}
+
+	/* Setup OS specific network interface */
+	em_setup_interface(dev, adapter);
+
+	/* Initialize statistics */
+	em_clear_hw_cntrs(&adapter->hw);
+	em_update_stats_counters(adapter);
+	adapter->hw.get_link_status = 1;
+	em_check_for_link(&adapter->hw);
+
+	/* Print the link status */
+	if (adapter->link_active == 1) {
+		em_get_speed_and_duplex(&adapter->hw, &adapter->link_speed, 
+					&adapter->link_duplex);
+		printf("em%d:  Speed:%d Mbps  Duplex:%s\n",
+		       adapter->unit,
+		       adapter->link_speed,
+		       adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half");
+	} else
+		printf("em%d:  Speed:N/A  Duplex:N/A\n", adapter->unit);
+
+
+	INIT_DEBUGOUT("em_attach: end");
+	splx(s);
+	return(0);
 }
 
 /*********************************************************************
@@ -367,60 +378,58 @@ em_attach(device_t dev)
 static int
 em_detach(device_t dev)
 {
-   struct adapter * adapter = device_get_softc(dev);
-   struct ifnet   *ifp = &adapter->interface_data.ac_if;
-   int             s;
-   int             size;
-
-   INIT_DEBUGOUT("em_detach: begin");
-   s = splimp();
-
-   em_stop(adapter);
-   em_phy_hw_reset(&adapter->shared);
-   ether_ifdetach(&adapter->interface_data.ac_if, ETHER_BPF_SUPPORTED);
-   em_free_pci_resources(adapter);
-
-   size = EM_ROUNDUP(adapter->num_tx_desc *
-                     sizeof(struct em_tx_desc), 4096);
-
-   /* Free Transmit Descriptor ring */
-   if (adapter->tx_desc_base) {
-      contigfree(adapter->tx_desc_base, size, M_DEVBUF);
-      adapter->tx_desc_base = NULL;
-   }
-
-   size = EM_ROUNDUP(adapter->num_rx_desc *
-                     sizeof(struct em_rx_desc), 4096);
-
-   /* Free Receive Descriptor ring */
-   if (adapter->rx_desc_base) {
-      contigfree(adapter->rx_desc_base, size, M_DEVBUF);
-      adapter->rx_desc_base = NULL;
-   }
-
-   /* Remove from the adapter list */
-   if(em_adapter_list == adapter)
-      em_adapter_list = adapter->next;
-   if(adapter->next != NULL)
-      adapter->next->prev = adapter->prev;
-   if(adapter->prev != NULL)
-      adapter->prev->next = adapter->next;
-
-   ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
-   ifp->if_timer = 0;
-
-   splx(s);
-   return(0);
+	struct adapter * adapter = device_get_softc(dev);
+	struct ifnet   *ifp = &adapter->interface_data.ac_if;
+	int             s;
+	int             size;
+
+	INIT_DEBUGOUT("em_detach: begin");
+	s = splimp();
+
+	em_stop(adapter);
+	em_phy_hw_reset(&adapter->hw);
+	ether_ifdetach(&adapter->interface_data.ac_if, ETHER_BPF_SUPPORTED);
+	em_free_pci_resources(adapter);
+
+	size = EM_ROUNDUP(adapter->num_tx_desc *
+			  sizeof(struct em_tx_desc), 4096);
+
+	/* Free Transmit Descriptor ring */
+	if (adapter->tx_desc_base) {
+		contigfree(adapter->tx_desc_base, size, M_DEVBUF);
+		adapter->tx_desc_base = NULL;
+	}
+
+	size = EM_ROUNDUP(adapter->num_rx_desc *
+			  sizeof(struct em_rx_desc), 4096);
+
+	/* Free Receive Descriptor ring */
+	if (adapter->rx_desc_base) {
+		contigfree(adapter->rx_desc_base, size, M_DEVBUF);
+		adapter->rx_desc_base = NULL;
+	}
+
+	/* Remove from the adapter list */
+	if (em_adapter_list == adapter)
+		em_adapter_list = adapter->next;
+	if (adapter->next != NULL)
+		adapter->next->prev = adapter->prev;
+	if (adapter->prev != NULL)
+		adapter->prev->next = adapter->next;
+
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+	ifp->if_timer = 0;
+
+	splx(s);
+	return(0);
 }
 
 static int
 em_shutdown(device_t dev)
 {
-   struct adapter * adapter = device_get_softc(dev);
-   
-   /* Issue a global reset */
-   em_adapter_stop(&adapter->shared);
-   return(0);
+	struct adapter *adapter = device_get_softc(dev);
+	em_stop(adapter);
+	return(0);
 }
 
 
@@ -437,111 +446,130 @@ em_shutdown(device_t dev)
 static void
 em_start(struct ifnet *ifp)
 {
-   int             s;
-   struct mbuf    *m_head, *mp;
-   vm_offset_t     virtual_addr;
-   u_int32_t       txd_upper; 
-   u_int32_t       txd_lower;
-   struct em_tx_buffer   *tx_buffer;
-   struct em_tx_desc *current_tx_desc = NULL;
-   struct adapter * adapter = ifp->if_softc;
-
-   if (!adapter->link_active)
-      return;
-
-   s = splimp();      
-   while (ifp->if_snd.ifq_head != NULL) {
-
-      IF_DEQUEUE(&ifp->if_snd, m_head);
-      
-      if(m_head == NULL) break;
-
-      if (adapter->num_tx_desc_avail <= TX_CLEANUP_THRESHOLD)
-         em_clean_transmit_interrupts(adapter);
-
-      if (adapter->num_tx_desc_avail <= TX_CLEANUP_THRESHOLD) {
-         ifp->if_flags |= IFF_OACTIVE;
-         IF_PREPEND(&ifp->if_snd, m_head);
-         adapter->no_tx_desc_avail++;
-         break;
-      }
-
-      tx_buffer =  STAILQ_FIRST(&adapter->free_tx_buffer_list);
-      if (!tx_buffer) {
-         adapter->no_tx_buffer_avail1++;
-         
-         /* 
-          * OK so we should not get here but I've seen it so lets try to 
-          * clean up and then try to get a SwPacket again and only break 
-          * if we still don't get one 
-          */
-         em_clean_transmit_interrupts(adapter);
-         tx_buffer = STAILQ_FIRST(&adapter->free_tx_buffer_list);
-         if (!tx_buffer) {
-            ifp->if_flags |= IFF_OACTIVE;
-            IF_PREPEND(&ifp->if_snd, m_head);
-            adapter->no_tx_buffer_avail2++;
-            break;
-         }
-      }
-      STAILQ_REMOVE_HEAD(&adapter->free_tx_buffer_list, em_tx_entry);
-
-      tx_buffer->num_tx_desc_used = 0;
-      tx_buffer->m_head = m_head;
-
-      if (ifp->if_hwassist > 0) {
-         em_transmit_checksum_setup(adapter,  m_head, tx_buffer, &txd_upper, &txd_lower);
-      } else {
-         txd_upper = 0;
-         txd_lower = 0;
-      }
-
-      for (mp = m_head; mp != NULL; mp = mp->m_next) {
-         if (mp->m_len == 0)
-            continue;
-         current_tx_desc = adapter->next_avail_tx_desc;
-         virtual_addr = mtod(mp, vm_offset_t);
-         current_tx_desc->buffer_addr = vtophys(virtual_addr);
- 
-         current_tx_desc->lower.data = (txd_lower | mp->m_len);
-         current_tx_desc->upper.data = (txd_upper);
-
-         if (current_tx_desc == adapter->last_tx_desc)
-            adapter->next_avail_tx_desc =
-            adapter->first_tx_desc;
-         else
-            adapter->next_avail_tx_desc++;
-
-         adapter->num_tx_desc_avail--;
-         tx_buffer->num_tx_desc_used++;
-      }
-
-      /* Put this tx_buffer at the end in the "in use" list */
-      STAILQ_INSERT_TAIL(&adapter->used_tx_buffer_list, tx_buffer, em_tx_entry);
-
-      /* 
-       * Last Descriptor of Packet needs End Of Packet (EOP), Report Status
-       * (RS) and append Ethernet CRC (IFCS) bits set.
-       */
-      current_tx_desc->lower.data |= (adapter->txd_cmd | E1000_TXD_CMD_EOP);
-
-      /* Send a copy of the frame to the BPF listener */
-      if (ifp->if_bpf)
-         bpf_mtap(ifp, m_head);
-      /* 
-       * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
-       * that this frame is available to transmit.
-       */
-      E1000_WRITE_REG(&adapter->shared, TDT, (((uintptr_t) adapter->next_avail_tx_desc -
-                             (uintptr_t) adapter->first_tx_desc) >> 4));
-   } /* end of while loop */
-
-   splx(s);
-
-   /* Set timeout in case chip has problems transmitting */
-   ifp->if_timer = EM_TX_TIMEOUT;
-   
-   return;
+	int             s;
+	struct mbuf    *m_head, *mp;
+	vm_offset_t     virtual_addr;
+	u_int32_t       txd_upper; 
+	u_int32_t       txd_lower;
+	struct em_tx_buffer   *tx_buffer;
+	struct em_tx_desc *current_tx_desc = NULL;
+	struct adapter * adapter = ifp->if_softc;
+
+	if (!adapter->link_active)
+		return;
+
+	s = splimp();      
+	while (ifp->if_snd.ifq_head != NULL) {
+		struct ifvlan *ifv = NULL;
+
+		IF_DEQUEUE(&ifp->if_snd, m_head);
+
+		if (m_head == NULL) break;
+
+		if (adapter->num_tx_desc_avail <= TX_CLEANUP_THRESHOLD)
+			em_clean_transmit_interrupts(adapter);
+
+		if (adapter->num_tx_desc_avail <= TX_CLEANUP_THRESHOLD) {
+			ifp->if_flags |= IFF_OACTIVE;
+			IF_PREPEND(&ifp->if_snd, m_head);
+			adapter->no_tx_desc_avail++;
+			break;
+		}
+
+		tx_buffer =  STAILQ_FIRST(&adapter->free_tx_buffer_list);
+		if (!tx_buffer) {
+			adapter->no_tx_buffer_avail1++;
+			/* 
+			 * OK so we should not get here but I've seen it so let 
+			 * us try to clean up and then try to get a tx_buffer 
+			 * again and only break if we still don't get one.
+			 */
+			em_clean_transmit_interrupts(adapter);
+			tx_buffer = STAILQ_FIRST(&adapter->free_tx_buffer_list);
+			if (!tx_buffer) {
+				ifp->if_flags |= IFF_OACTIVE;
+				IF_PREPEND(&ifp->if_snd, m_head);
+				adapter->no_tx_buffer_avail2++;
+				break;
+			}
+		}
+		STAILQ_REMOVE_HEAD(&adapter->free_tx_buffer_list, em_tx_entry);
+
+		tx_buffer->num_tx_desc_used = 0;
+		tx_buffer->m_head = m_head;
+
+		if (ifp->if_hwassist > 0) {
+			em_transmit_checksum_setup(adapter,  m_head, tx_buffer, 
+						   &txd_upper, &txd_lower);
+		} else {
+			txd_upper = 0;
+			txd_lower = 0;
+		}
+
+		/* Find out if we are in vlan mode */
+		if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
+		    m_head->m_pkthdr.rcvif != NULL &&
+		    m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
+			ifv = m_head->m_pkthdr.rcvif->if_softc;
+
+
+		for (mp = m_head; mp != NULL; mp = mp->m_next) {
+			if (mp->m_len == 0)
+				continue;
+			current_tx_desc = adapter->next_avail_tx_desc;
+			virtual_addr = mtod(mp, vm_offset_t);
+			current_tx_desc->buffer_addr = vtophys(virtual_addr);
+
+			current_tx_desc->lower.data = (txd_lower | mp->m_len);
+			current_tx_desc->upper.data = (txd_upper);
+
+			if (current_tx_desc == adapter->last_tx_desc)
+				adapter->next_avail_tx_desc =
+				adapter->first_tx_desc;
+			else
+				adapter->next_avail_tx_desc++;
+
+			adapter->num_tx_desc_avail--;
+			tx_buffer->num_tx_desc_used++;
+		}
+
+		/* Put this tx_buffer at the end in the "in use" list */
+		STAILQ_INSERT_TAIL(&adapter->used_tx_buffer_list, tx_buffer, 
+				   em_tx_entry);
+
+		if (ifv != NULL) {
+			/* Tell hardware to add tag */
+			current_tx_desc->lower.data |= E1000_TXD_CMD_VLE;
+
+			/* Set the vlan id */
+			current_tx_desc->upper.fields.special = ifv->ifv_tag;
+		}
+
+		/* 
+		 * Last Descriptor of Packet needs End Of Packet (EOP), Report Status
+		 * (RS) and append Ethernet CRC (IFCS) bits set.
+		 */
+		current_tx_desc->lower.data |= (adapter->txd_cmd | E1000_TXD_CMD_EOP);
+
+		/* Send a copy of the frame to the BPF listener */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp, m_head);
+
+		/* 
+		 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
+		 * that this frame is available to transmit.
+		 */
+		E1000_WRITE_REG(&adapter->hw, TDT, 
+				(((uintptr_t) adapter->next_avail_tx_desc -
+				  (uintptr_t) adapter->first_tx_desc) >> 4));
+	} /* end of while loop */
+
+	splx(s);
+
+	/* Set timeout in case chip has problems transmitting */
+	ifp->if_timer = EM_TX_TIMEOUT;
+
+	return;
 }
 
 /*********************************************************************
@@ -556,115 +584,115 @@ em_start(struct ifnet *ifp)
 static int
 em_ioctl(struct ifnet *ifp, IOCTL_CMD_TYPE command, caddr_t data)
 {
-   int             s, mask, error = 0;
-   struct ifreq   *ifr = (struct ifreq *) data;
-   struct adapter * adapter = ifp->if_softc;
-
-   s = splimp();
-   switch (command) {
-   case SIOCSIFADDR:
-   case SIOCGIFADDR:
-      IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)");
-      ether_ioctl(ifp, command, data);
-      break;
-   case SIOCSIFMTU:
-      IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
-      if (ifr->ifr_mtu > MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN) {
-         error = EINVAL;
-      } else {
-         ifp->if_mtu = ifr->ifr_mtu;
-         adapter->shared.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
-         em_init(adapter);
-      }
-      break;
-   case SIOCSIFFLAGS:
-      IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)");
-      if (ifp->if_flags & IFF_UP) {
-         if (ifp->if_flags & IFF_RUNNING &&
-             ifp->if_flags & IFF_PROMISC) {
-            em_set_promisc(adapter);
-         } else if (ifp->if_flags & IFF_RUNNING &&
-                    !(ifp->if_flags & IFF_PROMISC)) {
-            em_disable_promisc(adapter);
-         } else
-            em_init(adapter);
-      } else {
-         if (ifp->if_flags & IFF_RUNNING) {
-            em_stop(adapter);
-         }
-      }
-      break;
-   case SIOCADDMULTI:
-   case SIOCDELMULTI:
-      IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
-      if (ifp->if_flags & IFF_RUNNING) {
-         em_disable_intr(adapter);
-         em_set_multi(adapter);
-         if(adapter->shared.mac_type == em_82542_rev2_0)
-            em_initialize_receive_unit(adapter);
-         em_enable_intr(adapter);
-      }
-      break;
-   case SIOCSIFMEDIA:
-   case SIOCGIFMEDIA:
-      IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)");
-      error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
-      break;
-   case SIOCSIFCAP:
-      IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
-      mask = ifr->ifr_reqcap ^ ifp->if_capenable;
-      if (mask & IFCAP_HWCSUM) {
-         if (IFCAP_HWCSUM & ifp->if_capenable)
-            ifp->if_capenable &= ~IFCAP_HWCSUM;
-         else
-            ifp->if_capenable |= IFCAP_HWCSUM;
-         if (ifp->if_flags & IFF_RUNNING)
-            em_init(adapter);
-      }
-      break;
-   default:
-      IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%d)\n", (int)command);
-      error = EINVAL;
-   }
-
-   splx(s);
-   return(error);
+	int             s, mask, error = 0;
+	struct ifreq   *ifr = (struct ifreq *) data;
+	struct adapter * adapter = ifp->if_softc;
+
+	s = splimp();
+	switch (command) {
+	case SIOCSIFADDR:
+	case SIOCGIFADDR:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)");
+		ether_ioctl(ifp, command, data);
+		break;
+	case SIOCSIFMTU:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
+		if (ifr->ifr_mtu > MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN) {
+			error = EINVAL;
+		} else {
+			ifp->if_mtu = ifr->ifr_mtu;
+			adapter->hw.max_frame_size = 
+			ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
+			em_init(adapter);
+		}
+		break;
+	case SIOCSIFFLAGS:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)");
+		if (ifp->if_flags & IFF_UP) {
+			if (ifp->if_flags & IFF_RUNNING &&
+			    ifp->if_flags & IFF_PROMISC) {
+				em_set_promisc(adapter);
+			} else if (ifp->if_flags & IFF_RUNNING &&
+				   !(ifp->if_flags & IFF_PROMISC)) {
+				em_disable_promisc(adapter);
+			} else
+				em_init(adapter);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING) {
+				em_stop(adapter);
+			}
+		}
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
+		if (ifp->if_flags & IFF_RUNNING) {
+			em_disable_intr(adapter);
+			em_set_multi(adapter);
+			if (adapter->hw.mac_type == em_82542_rev2_0)
+				em_initialize_receive_unit(adapter);
+			em_enable_intr(adapter);
+		}
+		break;
+	case SIOCSIFMEDIA:
+	case SIOCGIFMEDIA:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)");
+		error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
+		break;
+	case SIOCSIFCAP:
+		IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
+		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+		if (mask & IFCAP_HWCSUM) {
+			if (IFCAP_HWCSUM & ifp->if_capenable)
+				ifp->if_capenable &= ~IFCAP_HWCSUM;
+			else
+				ifp->if_capenable |= IFCAP_HWCSUM;
+			if (ifp->if_flags & IFF_RUNNING)
+				em_init(adapter);
+		}
+		break;
+	default:
+		IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%d)\n", (int)command);
+		error = EINVAL;
+	}
+
+	splx(s);
+	return(error);
 }
 
 static void
 em_set_promisc(struct adapter * adapter)
 {
 
-   u_int32_t       reg_rctl;
-   struct ifnet   *ifp = &adapter->interface_data.ac_if;
+	u_int32_t       reg_rctl;
+	struct ifnet   *ifp = &adapter->interface_data.ac_if;
 
-   reg_rctl = E1000_READ_REG(&adapter->shared, RCTL);
+	reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
 
-   if(ifp->if_flags & IFF_PROMISC) {
-      reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
-      E1000_WRITE_REG(&adapter->shared, RCTL, reg_rctl);
-   }
-   else if (ifp->if_flags & IFF_ALLMULTI) {
-      reg_rctl |= E1000_RCTL_MPE;
-      reg_rctl &= ~E1000_RCTL_UPE;
-      E1000_WRITE_REG(&adapter->shared, RCTL, reg_rctl);
-   }
+	if (ifp->if_flags & IFF_PROMISC) {
+		reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
+		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+	} else if (ifp->if_flags & IFF_ALLMULTI) {
+		reg_rctl |= E1000_RCTL_MPE;
+		reg_rctl &= ~E1000_RCTL_UPE;
+		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+	}
 
-   return;
+	return;
 }
 
 static void
 em_disable_promisc(struct adapter * adapter)
 {
-   u_int32_t       reg_rctl;
+	u_int32_t       reg_rctl;
 
-   reg_rctl = E1000_READ_REG(&adapter->shared, RCTL);
+	reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
 
-   reg_rctl &=  (~E1000_RCTL_UPE);
-   reg_rctl &=  (~E1000_RCTL_MPE);
-   E1000_WRITE_REG(&adapter->shared, RCTL, reg_rctl);
+	reg_rctl &=  (~E1000_RCTL_UPE);
+	reg_rctl &=  (~E1000_RCTL_MPE);
+	E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
 
-   return;
+	return;
 }
 
 
@@ -678,58 +706,59 @@ em_disable_promisc(struct adapter * adapter)
 static void
 em_set_multi(struct adapter * adapter)
 {
-   u_int32_t reg_rctl = 0;
-   u_int8_t  mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
-   u_int16_t pci_cmd_word;
-   struct ifmultiaddr  *ifma;
-   int mcnt = 0;
-   struct ifnet   *ifp = &adapter->interface_data.ac_if;
-
-   IOCTL_DEBUGOUT("em_set_multi: begin");
-   
-    if(adapter->shared.mac_type == em_82542_rev2_0) {
-       reg_rctl = E1000_READ_REG(&adapter->shared, RCTL);
-       if(adapter->shared.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
-          pci_cmd_word = adapter->shared.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
-          pci_write_config(adapter->dev, PCIR_COMMAND, pci_cmd_word, 2);
-       }
-       reg_rctl |= E1000_RCTL_RST;
-       E1000_WRITE_REG(&adapter->shared, RCTL, reg_rctl);
-       msec_delay(5);
-    }
+	u_int32_t reg_rctl = 0;
+	u_int8_t  mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
+	u_int16_t pci_cmd_word;
+	struct ifmultiaddr  *ifma;
+	int mcnt = 0;
+	struct ifnet   *ifp = &adapter->interface_data.ac_if;
+
+	IOCTL_DEBUGOUT("em_set_multi: begin");
+
+	if (adapter->hw.mac_type == em_82542_rev2_0) {
+		reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
+		if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
+			pci_cmd_word = adapter->hw.pci_cmd_word & 
+				       ~CMD_MEM_WRT_INVALIDATE;
+			pci_write_config(adapter->dev, PCIR_COMMAND, pci_cmd_word, 2);
+		}
+		reg_rctl |= E1000_RCTL_RST;
+		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+		msec_delay(5);
+	}
 
 #if __FreeBSD_version < 500000 
-    LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+	LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 #else
-    TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 #endif
-       if (ifma->ifma_addr->sa_family != AF_LINK)
-          continue;
-       
-       bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
-             &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
-       mcnt++;
-    }
-
-    if (mcnt > MAX_NUM_MULTICAST_ADDRESSES) {
-       reg_rctl = E1000_READ_REG(&adapter->shared, RCTL);
-       reg_rctl |= E1000_RCTL_MPE;
-       E1000_WRITE_REG(&adapter->shared, RCTL, reg_rctl);
-    }
-    else
-       em_mc_addr_list_update(&adapter->shared, mta, mcnt, 0);
-
-    if(adapter->shared.mac_type == em_82542_rev2_0) {
-       reg_rctl = E1000_READ_REG(&adapter->shared, RCTL);
-       reg_rctl &= ~E1000_RCTL_RST;
-       E1000_WRITE_REG(&adapter->shared, RCTL, reg_rctl);
-       msec_delay(5);
-       if(adapter->shared.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
-          pci_write_config(adapter->dev, PCIR_COMMAND, adapter->shared.pci_cmd_word, 2);
-       }
-    }
-
-    return;
+		if (ifma->ifma_addr->sa_family != AF_LINK)
+			continue;
+
+		bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
+		      &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
+		mcnt++;
+	}
+
+	if (mcnt > MAX_NUM_MULTICAST_ADDRESSES) {
+		reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
+		reg_rctl |= E1000_RCTL_MPE;
+		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+	} else
+		em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0);
+
+	if (adapter->hw.mac_type == em_82542_rev2_0) {
+		reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
+		reg_rctl &= ~E1000_RCTL_RST;
+		E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+		msec_delay(5);
+		if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
+			pci_write_config(adapter->dev, PCIR_COMMAND, 
+					 adapter->hw.pci_cmd_word, 2);
+		}
+	}
+
+	return;
 }
 
 /*********************************************************************
@@ -742,26 +771,26 @@ em_set_multi(struct adapter * adapter)
 static void
 em_watchdog(struct ifnet *ifp)
 {
-   struct adapter * adapter;
-   adapter = ifp->if_softc;
- 
-   /* If we are in this routine because of pause frames, then
-    * don't reset the hardware.
-    */
-   if(E1000_READ_REG(&adapter->shared, STATUS) & E1000_STATUS_TXOFF) {
-      ifp->if_timer = EM_TX_TIMEOUT;
-      return;
-   }
-
-   printf("em%d: watchdog timeout -- resetting\n", adapter->unit);
-
-   ifp->if_flags &= ~IFF_RUNNING;
-
-   em_stop(adapter);
-   em_init(adapter);
-
-   ifp->if_oerrors++;
-   return;
+	struct adapter * adapter;
+	adapter = ifp->if_softc;
+
+	/* If we are in this routine because of pause frames, then
+	 * don't reset the hardware.
+	 */
+	if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) {
+		ifp->if_timer = EM_TX_TIMEOUT;
+		return;
+	}
+
+	printf("em%d: watchdog timeout -- resetting\n", adapter->unit);
+
+	ifp->if_flags &= ~IFF_RUNNING;
+
+	em_stop(adapter);
+	em_init(adapter);
+
+	ifp->if_oerrors++;
+	return;
 }
 
 /*********************************************************************
@@ -774,48 +803,50 @@ em_watchdog(struct ifnet *ifp)
 static void
 em_local_timer(void *arg)
 {
-   int s;
-   struct ifnet   *ifp;
-   struct adapter * adapter = arg;
-   ifp = &adapter->interface_data.ac_if;
-
-   s = splimp();
-
-   em_check_for_link(&adapter->shared);
-   em_print_link_status(adapter);
-   em_update_stats_counters(adapter);   
-   if(em_display_debug_stats && ifp->if_flags & IFF_RUNNING) {
-      em_print_hw_stats(adapter);
-   }
-   adapter->timer_handle = timeout(em_local_timer, adapter, 2*hz);
-
-   splx(s);
-   return;
+	int s;
+	struct ifnet   *ifp;
+	struct adapter * adapter = arg;
+	ifp = &adapter->interface_data.ac_if;
+
+	s = splimp();
+
+	em_check_for_link(&adapter->hw);
+	em_print_link_status(adapter);
+	em_update_stats_counters(adapter);   
+	if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING) {
+		em_print_hw_stats(adapter);
+	}
+	adapter->timer_handle = timeout(em_local_timer, adapter, 2*hz);
+
+	splx(s);
+	return;
 }
 
 static void
 em_print_link_status(struct adapter * adapter)
 {
-   if(E1000_READ_REG(&adapter->shared, STATUS) & E1000_STATUS_LU) {
-      if(adapter->link_active == 0) {
-         em_get_speed_and_duplex(&adapter->shared, &adapter->link_speed, &adapter->link_duplex);
-         printf("em%d: Link is up %d Mbps %s\n",
-                adapter->unit,
-                adapter->link_speed,
-                ((adapter->link_duplex == FULL_DUPLEX) ?
-                 "Full Duplex" : "Half Duplex"));
-         adapter->link_active = 1;
-      }
-   } else {
-      if(adapter->link_active == 1) {
-         adapter->link_speed = 0;
-         adapter->link_duplex = 0;
-         printf("em%d: Link is Down\n", adapter->unit);
-         adapter->link_active = 0;
-      }
-   }
-
-   return;
+	if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
+		if (adapter->link_active == 0) {
+			em_get_speed_and_duplex(&adapter->hw, 
+						&adapter->link_speed, 
+						&adapter->link_duplex);
+			printf("em%d: Link is up %d Mbps %s\n",
+			       adapter->unit,
+			       adapter->link_speed,
+			       ((adapter->link_duplex == FULL_DUPLEX) ?
+				"Full Duplex" : "Half Duplex"));
+			adapter->link_active = 1;
+		}
+	} else {
+		if (adapter->link_active == 1) {
+			adapter->link_speed = 0;
+			adapter->link_duplex = 0;
+			printf("em%d: Link is Down\n", adapter->unit);
+			adapter->link_active = 0;
+		}
+	}
+
+	return;
 }
 
 /*********************************************************************
@@ -832,60 +863,66 @@ em_print_link_status(struct adapter * adapter)
 static void
 em_init(void *arg)
 {
-   int             s;
-   struct ifnet   *ifp;
-   struct adapter * adapter = arg;
-
-   INIT_DEBUGOUT("em_init: begin");
-
-   s = splimp();
-
-   em_stop(adapter);
-
-   /* Initialize the hardware */
-   if (em_hardware_init(adapter)) {
-      printf("em%d: Unable to initialize the hardware\n", adapter->unit);
-      splx(s);
-      return;
-   }
-   adapter->shared.adapter_stopped = FALSE;
-   
-   /* Prepare transmit descriptors and buffers */
-   if (em_setup_transmit_structures(adapter)) {
-      printf("em%d: Could not setup transmit structures\n", adapter->unit);
-      em_stop(adapter); 
-      splx(s);
-      return;
-   }
-   em_initialize_transmit_unit(adapter);
-
-   /* Setup Multicast table */
-   em_set_multi(adapter);
-
-   /* Prepare receive descriptors and buffers */
-   if (em_setup_receive_structures(adapter)) {
-      printf("em%d: Could not setup receive structures\n", adapter->unit);
-      em_stop(adapter);
-      splx(s);
-      return;
-   }
-   em_initialize_receive_unit(adapter);
-
-   ifp = &adapter->interface_data.ac_if;
-   ifp->if_flags |= IFF_RUNNING;
-   ifp->if_flags &= ~IFF_OACTIVE;
-
-   if(adapter->shared.mac_type >= em_82543) {
-      if (ifp->if_capenable & IFCAP_TXCSUM)
-         ifp->if_hwassist = EM_CHECKSUM_FEATURES;
-   }
-
-   adapter->timer_handle = timeout(em_local_timer, adapter, 2*hz);
-   em_clear_hw_cntrs(&adapter->shared);
-   em_enable_intr(adapter);
-
-   splx(s);
-   return;
+	int             s;
+	struct ifnet   *ifp;
+	struct adapter * adapter = arg;
+
+	INIT_DEBUGOUT("em_init: begin");
+
+	s = splimp();
+
+	em_stop(adapter);
+
+	/* Initialize the hardware */
+	if (em_hardware_init(adapter)) {
+		printf("em%d: Unable to initialize the hardware\n", 
+		       adapter->unit);
+		splx(s);
+		return;
+	}
+
+	em_enable_vlans(adapter);
+
+	/* Prepare transmit descriptors and buffers */
+	if (em_setup_transmit_structures(adapter)) {
+		printf("em%d: Could not setup transmit structures\n", 
+		       adapter->unit);
+		em_stop(adapter); 
+		splx(s);
+		return;
+	}
+	em_initialize_transmit_unit(adapter);
+
+	/* Setup Multicast table */
+	em_set_multi(adapter);
+
+	/* Prepare receive descriptors and buffers */
+	if (em_setup_receive_structures(adapter)) {
+		printf("em%d: Could not setup receive structures\n", 
+		       adapter->unit);
+		em_stop(adapter);
+		splx(s);
+		return;
+	}
+	em_initialize_receive_unit(adapter);
+
+	ifp = &adapter->interface_data.ac_if;
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	if (adapter->hw.mac_type >= em_82543) {
+		if (ifp->if_capenable & IFCAP_TXCSUM)
+			ifp->if_hwassist = EM_CHECKSUM_FEATURES;
+		else
+			ifp->if_hwassist = 0;
+	}
+
+	adapter->timer_handle = timeout(em_local_timer, adapter, 2*hz);
+	em_clear_hw_cntrs(&adapter->hw);
+	em_enable_intr(adapter);
+
+	splx(s);
+	return;
 }
 
 
@@ -899,22 +936,22 @@ em_init(void *arg)
 static void
 em_stop(void *arg)
 {
-   struct ifnet   *ifp;
-   struct adapter * adapter = arg;
-   ifp = &adapter->interface_data.ac_if;
+	struct ifnet   *ifp;
+	struct adapter * adapter = arg;
+	ifp = &adapter->interface_data.ac_if;
 
-   INIT_DEBUGOUT("em_stop: begin\n");
-   em_disable_intr(adapter);
-   em_adapter_stop(&adapter->shared);
-   untimeout(em_local_timer, adapter, adapter->timer_handle);
-   em_free_transmit_structures(adapter);
-   em_free_receive_structures(adapter);
+	INIT_DEBUGOUT("em_stop: begin\n");
+	em_disable_intr(adapter);
+	em_reset_hw(&adapter->hw);
+	untimeout(em_local_timer, adapter, adapter->timer_handle);
+	em_free_transmit_structures(adapter);
+	em_free_receive_structures(adapter);
 
 
-   /* Tell the stack that the interface is no longer active */
-   ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+	/* Tell the stack that the interface is no longer active */
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 
-   return;
+	return;
 }
 
 /*********************************************************************
@@ -926,38 +963,41 @@ em_stop(void *arg)
 static void
 em_intr(void *arg)
 {
-   u_int32_t       loop_cnt = EM_MAX_INTR;
-   u_int32_t       reg_icr;
-   struct ifnet    *ifp;
-   struct adapter  *adapter = arg;
-
-   ifp = &adapter->interface_data.ac_if;
-
-   em_disable_intr(adapter);
-   while(loop_cnt > 0 && (reg_icr = E1000_READ_REG(&adapter->shared, ICR)) != 0) {
-
-      /* Link status change */
-      if(reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
-         untimeout(em_local_timer, adapter, adapter->timer_handle);
-         adapter->shared.get_link_status = 1;
-         em_check_for_link(&adapter->shared);
-         em_print_link_status(adapter);
-         adapter->timer_handle = timeout(em_local_timer, adapter, 2*hz);      
-      }
-
-      if (ifp->if_flags & IFF_RUNNING) {
-         em_process_receive_interrupts(adapter);
-         em_clean_transmit_interrupts(adapter);
-      }
-      loop_cnt--;
-   }
-
-   em_enable_intr(adapter);
-
-   if(ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
-      em_start(ifp);
-   
-   return;
+	u_int32_t       loop_cnt = EM_MAX_INTR;
+	u_int32_t       reg_icr;
+	struct ifnet    *ifp;
+	struct adapter  *adapter = arg;
+
+	ifp = &adapter->interface_data.ac_if;
+
+	em_disable_intr(adapter);
+	while (loop_cnt > 0 && 
+	       (reg_icr = E1000_READ_REG(&adapter->hw, ICR)) != 0) {
+
+		/* Link status change */
+		if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
+			untimeout(em_local_timer, adapter, 
+				  adapter->timer_handle);
+			adapter->hw.get_link_status = 1;
+			em_check_for_link(&adapter->hw);
+			em_print_link_status(adapter);
+			adapter->timer_handle = 
+			timeout(em_local_timer, adapter, 2*hz); 
+		}
+
+		if (ifp->if_flags & IFF_RUNNING) {
+			em_process_receive_interrupts(adapter);
+			em_clean_transmit_interrupts(adapter);
+		}
+		loop_cnt--;
+	}
+
+	em_enable_intr(adapter);
+
+	if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
+		em_start(ifp);
+
+	return;
 }
 
 
@@ -972,53 +1012,54 @@ em_intr(void *arg)
 static void
 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 {
-   struct adapter * adapter = ifp->if_softc;
-
-   INIT_DEBUGOUT("em_media_status: begin");
-
-   em_check_for_link(&adapter->shared);
-   if(E1000_READ_REG(&adapter->shared, STATUS) & E1000_STATUS_LU) {
-      if(adapter->link_active == 0) {
-         em_get_speed_and_duplex(&adapter->shared, &adapter->link_speed, &adapter->link_duplex);
-         adapter->link_active = 1;
-      }
-   }
-   else {
-      if(adapter->link_active == 1) {
-         adapter->link_speed = 0;
-         adapter->link_duplex = 0;
-         adapter->link_active = 0;
-      }
-   }
-
-   ifmr->ifm_status = IFM_AVALID;
-   ifmr->ifm_active = IFM_ETHER;
-
-   if (!adapter->link_active)
-      return;
-
-   ifmr->ifm_status |= IFM_ACTIVE;
-
-   if (adapter->shared.media_type == em_media_type_fiber) {
-      ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
-   } else {
-      switch (adapter->link_speed) {
-      case 10:
-         ifmr->ifm_active |= IFM_10_T;
-         break;
-      case 100:
-         ifmr->ifm_active |= IFM_100_TX;
-         break;
-      case 1000:
-         ifmr->ifm_active |= IFM_1000_T;
-         break;
-      }
-      if (adapter->link_duplex == FULL_DUPLEX)
-         ifmr->ifm_active |= IFM_FDX;
-      else
-         ifmr->ifm_active |= IFM_HDX;
-   }
-   return;
+	struct adapter * adapter = ifp->if_softc;
+
+	INIT_DEBUGOUT("em_media_status: begin");
+
+	em_check_for_link(&adapter->hw);
+	if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
+		if (adapter->link_active == 0) {
+			em_get_speed_and_duplex(&adapter->hw, 
+						&adapter->link_speed, 
+						&adapter->link_duplex);
+			adapter->link_active = 1;
+		}
+	} else {
+		if (adapter->link_active == 1) {
+			adapter->link_speed = 0;
+			adapter->link_duplex = 0;
+			adapter->link_active = 0;
+		}
+	}
+
+	ifmr->ifm_status = IFM_AVALID;
+	ifmr->ifm_active = IFM_ETHER;
+
+	if (!adapter->link_active)
+		return;
+
+	ifmr->ifm_status |= IFM_ACTIVE;
+
+	if (adapter->hw.media_type == em_media_type_fiber) {
+		ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
+	} else {
+		switch (adapter->link_speed) {
+		case 10:
+			ifmr->ifm_active |= IFM_10_T;
+			break;
+		case 100:
+			ifmr->ifm_active |= IFM_100_TX;
+			break;
+		case 1000:
+			ifmr->ifm_active |= IFM_1000_T;
+			break;
+		}
+		if (adapter->link_duplex == FULL_DUPLEX)
+			ifmr->ifm_active |= IFM_FDX;
+		else
+			ifmr->ifm_active |= IFM_HDX;
+	}
+	return;
 }
 
 /*********************************************************************
@@ -1032,51 +1073,47 @@ em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 static int
 em_media_change(struct ifnet *ifp)
 {
-   struct adapter * adapter = ifp->if_softc;
-   struct ifmedia  *ifm = &adapter->media;
-   
-   INIT_DEBUGOUT("em_media_change: begin");
-
-   if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
-      return(EINVAL);
-
-   switch(IFM_SUBTYPE(ifm->ifm_media)) {
-   case IFM_AUTO:
-      if (adapter->shared.autoneg)
-         return 0;
-      else {
-         adapter->shared.autoneg = DO_AUTO_NEG;
-         adapter->shared.autoneg_advertised = AUTONEG_ADV_DEFAULT;
-      }
-      break;
-   case IFM_1000_SX:
-   case IFM_1000_T:
-      adapter->shared.autoneg = DO_AUTO_NEG;
-      adapter->shared.autoneg_advertised = ADVERTISE_1000_FULL;
-      break;
-   case IFM_100_TX:
-      adapter->shared.autoneg = FALSE;
-      adapter->shared.autoneg_advertised = 0;
-      if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
-         adapter->shared.forced_speed_duplex = em_100_full;
-      else
-         adapter->shared.forced_speed_duplex = em_100_half;
-      break;
-   case IFM_10_T:
-     adapter->shared.autoneg = FALSE;
-     adapter->shared.autoneg_advertised = 0;
-     if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
-        adapter->shared.forced_speed_duplex = em_10_full;
-     else
-        adapter->shared.forced_speed_duplex = em_10_half;
-     break;
-   default:
-      printf("em%d: Unsupported media type\n", adapter->unit);
-   }
-
-   em_init(adapter);
-
-   return(0);
+	struct adapter * adapter = ifp->if_softc;
+	struct ifmedia  *ifm = &adapter->media;
+
+	INIT_DEBUGOUT("em_media_change: begin");
+
+	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+		return(EINVAL);
+
+	switch (IFM_SUBTYPE(ifm->ifm_media)) {
+	case IFM_AUTO:
+		adapter->hw.autoneg = DO_AUTO_NEG;
+		adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
+		break;
+	case IFM_1000_SX:
+	case IFM_1000_T:
+		adapter->hw.autoneg = DO_AUTO_NEG;
+		adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
+		break;
+	case IFM_100_TX:
+		adapter->hw.autoneg = FALSE;
+		adapter->hw.autoneg_advertised = 0;
+		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
+			adapter->hw.forced_speed_duplex = em_100_full;
+		else
+			adapter->hw.forced_speed_duplex	= em_100_half;
+		break;
+	case IFM_10_T:
+		adapter->hw.autoneg = FALSE;
+		adapter->hw.autoneg_advertised = 0;
+		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
+			adapter->hw.forced_speed_duplex = em_10_full;
+		else
+			adapter->hw.forced_speed_duplex	= em_10_half;
+		break;
+	default:
+		printf("em%d: Unsupported media type\n", adapter->unit);
+	}
+
+	em_init(adapter);
+
+	return(0);
 }
 /* Section end: Other registered entry points */
 
@@ -1089,100 +1126,118 @@ em_media_change(struct ifnet *ifp)
 static void
 em_identify_hardware(struct adapter * adapter)
 {
-   device_t dev = adapter->dev;
-
-   /* Make sure our PCI config space has the necessary stuff set */
-   adapter->shared.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
-   if (!((adapter->shared.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
-         (adapter->shared.pci_cmd_word & PCIM_CMD_MEMEN))) {
-      printf("em%d: Memory Access and/or Bus Master bits were not set!\n", 
-             adapter->unit);
-      adapter->shared.pci_cmd_word |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
-      pci_write_config(dev, PCIR_COMMAND, adapter->shared.pci_cmd_word, 2);
-   }
-
-   /* Save off the information about this board */
-   adapter->shared.vendor_id = pci_get_vendor(dev);
-   adapter->shared.device_id = pci_get_device(dev);
-   adapter->shared.revision_id = pci_read_config(dev, PCIR_REVID, 1);
-   adapter->shared.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
-   adapter->shared.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
-
-   
-   /* Set MacType, etc. based on this PCI info */
-   switch (adapter->shared.device_id) {
-   case E1000_DEV_ID_82542:
-      adapter->shared.mac_type = (adapter->shared.revision_id == 3) ?
-         em_82542_rev2_1 : em_82542_rev2_0;
-      break;
-   case E1000_DEV_ID_82543GC_FIBER:
-   case E1000_DEV_ID_82543GC_COPPER:
-      adapter->shared.mac_type = em_82543;
-      break;
-   case E1000_DEV_ID_82544EI_FIBER:
-   case E1000_DEV_ID_82544EI_COPPER:
-   case E1000_DEV_ID_82544GC_COPPER:
-   case E1000_DEV_ID_82544GC_LOM:
-      adapter->shared.mac_type = em_82544;
-      break;
-   case E1000_DEV_ID_82540EM:
-      adapter->shared.mac_type = em_82540;
-   default:
-      INIT_DEBUGOUT1("Unknown device id 0x%x", adapter->shared.device_id);
-   }
-   return;
+	device_t dev = adapter->dev;
+
+	/* Make sure our PCI config space has the necessary stuff set */
+	adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
+	if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
+	      (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) {
+		printf("em%d: Memory Access and/or Bus Master bits were not set!\n", 
+		       adapter->unit);
+		adapter->hw.pci_cmd_word |= 
+		(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
+		pci_write_config(dev, PCIR_COMMAND, adapter->hw.pci_cmd_word, 2);
+	}
+
+	/* Save off the information about this board */
+	adapter->hw.vendor_id = pci_get_vendor(dev);
+	adapter->hw.device_id = pci_get_device(dev);
+	adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
+	adapter->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
+	adapter->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
+
+
+	/* Set MacType, etc. based on this PCI info */
+	switch (adapter->hw.device_id) {
+	case E1000_DEV_ID_82542:
+		adapter->hw.mac_type = (adapter->hw.revision_id == 3) ?
+				       em_82542_rev2_1 : em_82542_rev2_0;
+		break;
+	case E1000_DEV_ID_82543GC_FIBER:
+	case E1000_DEV_ID_82543GC_COPPER:
+		adapter->hw.mac_type = em_82543;
+		break;
+	case E1000_DEV_ID_82544EI_FIBER:
+	case E1000_DEV_ID_82544EI_COPPER:
+	case E1000_DEV_ID_82544GC_COPPER:
+	case E1000_DEV_ID_82544GC_LOM:
+		adapter->hw.mac_type = em_82544;
+		break;
+	case E1000_DEV_ID_82540EM:
+		adapter->hw.mac_type = em_82540;
+		break;
+	case E1000_DEV_ID_82545EM_FIBER:
+	case E1000_DEV_ID_82545EM_COPPER:
+		adapter->hw.mac_type = em_82545;
+		break;
+	case E1000_DEV_ID_82546EB_FIBER:
+	case E1000_DEV_ID_82546EB_COPPER:
+		adapter->hw.mac_type = em_82546;
+		break;
+	default:
+		INIT_DEBUGOUT1("Unknown device id 0x%x", adapter->hw.device_id);
+	}
+	return;
 }
 
 static int
 em_allocate_pci_resources(struct adapter * adapter)
 {
-   int             resource_id = EM_MMBA;
-   device_t        dev = adapter->dev;
-
-   adapter->res_memory = bus_alloc_resource(dev, SYS_RES_MEMORY,
-                                            &resource_id, 0, ~0, 1,
-                                            RF_ACTIVE);
-   if (!(adapter->res_memory)) {
-      printf("em%d: Unable to allocate bus resource: memory\n", adapter->unit);
-      return(ENXIO);
-   }
-   adapter->osdep.bus_space_tag = rman_get_bustag(adapter->res_memory);
-   adapter->osdep.bus_space_handle = rman_get_bushandle(adapter->res_memory);
-   adapter->shared.hw_addr = (uint8_t *)adapter->osdep.bus_space_handle;
-
-   resource_id = 0x0;
-   adapter->res_interrupt = bus_alloc_resource(dev, SYS_RES_IRQ,
-                                               &resource_id, 0, ~0, 1,
-                                               RF_SHAREABLE | RF_ACTIVE);
-   if (!(adapter->res_interrupt)) {
-      printf("em%d: Unable to allocate bus resource: interrupt\n", adapter->unit);
-      return(ENXIO);
-   }
-   if (bus_setup_intr(dev, adapter->res_interrupt, INTR_TYPE_NET,
-                  (void (*)(void *)) em_intr, adapter,
-                  &adapter->int_handler_tag)) {
-      printf("em%d: Error registering interrupt handler!\n", adapter->unit);
-      return(ENXIO);
-   }
-
-   adapter->shared.back = &adapter->osdep;
-
-   return(0);
+	int             resource_id = EM_MMBA;
+	device_t        dev = adapter->dev;
+
+	adapter->res_memory = bus_alloc_resource(dev, SYS_RES_MEMORY,
+						 &resource_id, 0, ~0, 1,
+						 RF_ACTIVE);
+	if (!(adapter->res_memory)) {
+		printf("em%d: Unable to allocate bus resource: memory\n", 
+		       adapter->unit);
+		return(ENXIO);
+	}
+	adapter->osdep.bus_space_tag = 
+	rman_get_bustag(adapter->res_memory);
+	adapter->osdep.bus_space_handle = 
+	rman_get_bushandle(adapter->res_memory);
+	adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.bus_space_handle;
+
+	resource_id = 0x0;
+	adapter->res_interrupt = bus_alloc_resource(dev, SYS_RES_IRQ,
+						    &resource_id, 0, ~0, 1,
+						    RF_SHAREABLE | RF_ACTIVE);
+	if (!(adapter->res_interrupt)) {
+		printf("em%d: Unable to allocate bus resource: interrupt\n", 
+		       adapter->unit);
+		return(ENXIO);
+	}
+	if (bus_setup_intr(dev, adapter->res_interrupt, INTR_TYPE_NET,
+			   (void (*)(void *)) em_intr, adapter,
+			   &adapter->int_handler_tag)) {
+		printf("em%d: Error registering interrupt handler!\n", 
+		       adapter->unit);
+		return(ENXIO);
+	}
+
+	adapter->hw.back = &adapter->osdep;
+
+	return(0);
 }
 
 static void
 em_free_pci_resources(struct adapter * adapter)
 {
-   device_t dev = adapter->dev;
-
-   if(adapter->res_interrupt != NULL) {
-      bus_teardown_intr(dev, adapter->res_interrupt, adapter->int_handler_tag);
-      bus_release_resource(dev, SYS_RES_IRQ, 0, adapter->res_interrupt);
-   }
-   if (adapter->res_memory != NULL) {
-      bus_release_resource(dev, SYS_RES_MEMORY, EM_MMBA, adapter->res_memory);
-   }
-   return;
+	device_t dev = adapter->dev;
+
+	if (adapter->res_interrupt != NULL) {
+		bus_teardown_intr(dev, adapter->res_interrupt, 
+				  adapter->int_handler_tag);
+		bus_release_resource(dev, SYS_RES_IRQ, 0, 
+				     adapter->res_interrupt);
+	}
+	if (adapter->res_memory != NULL) {
+		bus_release_resource(dev, SYS_RES_MEMORY, EM_MMBA, 
+				     adapter->res_memory);
+	}
+	return;
 }
 
 /*********************************************************************
@@ -1196,57 +1251,54 @@ em_free_pci_resources(struct adapter * adapter)
 static int
 em_hardware_init(struct adapter * adapter)
 {
-   /* Issue a global reset */
-   adapter->shared.adapter_stopped = FALSE;
-   em_adapter_stop(&adapter->shared);
-   adapter->shared.adapter_stopped = FALSE;
-
-   /* Make sure we have a good EEPROM before we read from it */
-   if (!em_validate_eeprom_checksum(&adapter->shared)) {
-      printf("em%d: The EEPROM Checksum Is Not Valid\n", adapter->unit);
-      return EIO;
-   }
-   /* Copy the permanent MAC address and part number out of the EEPROM */
-   em_read_mac_address(adapter, adapter->interface_data.ac_enaddr);
-   memcpy(adapter->shared.mac_addr, adapter->interface_data.ac_enaddr,
-         ETH_LENGTH_OF_ADDRESS);
-   em_read_part_num(&adapter->shared, &(adapter->part_num));
-
-   if (!em_init_hw(&adapter->shared)) {
-      printf("em%d: Hardware Initialization Failed", adapter->unit);
-      return EIO;
-   }
-
-   em_check_for_link(&adapter->shared);
-   if (E1000_READ_REG(&adapter->shared, STATUS) & E1000_STATUS_LU)
-      adapter->link_active = 1;
-   else
-      adapter->link_active = 0;
- 
-   if (adapter->link_active) {
-      em_get_speed_and_duplex(&adapter->shared, &adapter->link_speed, &adapter->link_duplex);
-   } else {
-      adapter->link_speed = 0;
-      adapter->link_duplex = 0;
-   }
-
-   return 0;
-}
-
-static void
-em_read_mac_address(struct adapter * adapter, u_int8_t * NodeAddress)
-{
-   u_int16_t       EepromWordValue;
-   int             i;
-
-   for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
-      EepromWordValue =
-         em_read_eeprom(&adapter->shared, EEPROM_NODE_ADDRESS_BYTE_0 + (i / 2));
-      NodeAddress[i] = (uint8_t) (EepromWordValue & 0x00FF);
-      NodeAddress[i + 1] = (uint8_t) (EepromWordValue >> 8);
-   }
-
-   return;
+	/* Issue a global reset */
+	em_reset_hw(&adapter->hw);
+
+	/* Make sure we have a good EEPROM before we read from it */
+	if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
+		printf("em%d: The EEPROM Checksum Is Not Valid\n",
+		       adapter->unit);
+		return(EIO);
+	}
+	/* Copy the permanent MAC address and part number out of the EEPROM */
+	if (em_read_mac_addr(&adapter->hw) < 0) {
+		printf("em%d: EEPROM read error while reading mac address\n",
+		       adapter->unit);
+		return(EIO);
+	}
+
+	memcpy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr,
+	       ETH_LENGTH_OF_ADDRESS);
+
+
+	if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) {
+		printf("em%d: EEPROM read error while reading part number\n",
+		       adapter->unit);
+		return(EIO);
+	}
+
+	if (em_init_hw(&adapter->hw) < 0) {
+		printf("em%d: Hardware Initialization Failed",
+		       adapter->unit);
+		return(EIO);
+	}
+
+	em_check_for_link(&adapter->hw);
+	if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)
+		adapter->link_active = 1;
+	else
+		adapter->link_active = 0;
+
+	if (adapter->link_active) {
+		em_get_speed_and_duplex(&adapter->hw, 
+					&adapter->link_speed, 
+					&adapter->link_duplex);
+	} else {
+		adapter->link_speed = 0;
+		adapter->link_duplex = 0;
+	}
+
+	return(0);
 }
 
 /*********************************************************************
@@ -1257,54 +1309,56 @@ em_read_mac_address(struct adapter * adapter, u_int8_t * NodeAddress)
 static void
 em_setup_interface(device_t dev, struct adapter * adapter)
 {
-   struct ifnet   *ifp;
-   INIT_DEBUGOUT("em_setup_interface: begin");
-
-   ifp = &adapter->interface_data.ac_if;
-   ifp->if_unit = adapter->unit;
-   ifp->if_name = "em";
-   ifp->if_mtu = ETHERMTU;
-   ifp->if_output = ether_output;
-   ifp->if_baudrate = 1000000000;
-   ifp->if_init =  em_init;
-   ifp->if_softc = adapter;
-   ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
-   ifp->if_ioctl = em_ioctl;
-   ifp->if_start = em_start;
-   ifp->if_watchdog = em_watchdog;
-   ifp->if_snd.ifq_maxlen = adapter->num_tx_desc - 1;
-   ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
-
-   if (adapter->shared.mac_type >= em_82543) {
-      ifp->if_capabilities = IFCAP_HWCSUM;
-      ifp->if_capenable = ifp->if_capabilities;
-   }
-
-   /* 
-    * Specify the media types supported by this adapter and register
-    * callbacks to update media and link information
-    */
-   ifmedia_init(&adapter->media, IFM_IMASK, em_media_change,
-                em_media_status);
-   if (adapter->shared.media_type == em_media_type_fiber) {
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 0,
-                  NULL);
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX , 0, NULL);
-   } else {
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0,
-                  NULL);
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
-                  NULL);
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0,
-                  NULL);
-      ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
-   }
-   ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
-   ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
-
-   return;
+	struct ifnet   *ifp;
+	INIT_DEBUGOUT("em_setup_interface: begin");
+
+	ifp = &adapter->interface_data.ac_if;
+	ifp->if_unit = adapter->unit;
+	ifp->if_name = "em";
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_output = ether_output;
+	ifp->if_baudrate = 1000000000;
+	ifp->if_init =  em_init;
+	ifp->if_softc = adapter;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = em_ioctl;
+	ifp->if_start = em_start;
+	ifp->if_watchdog = em_watchdog;
+	ifp->if_snd.ifq_maxlen = adapter->num_tx_desc - 1;
+	ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
+
+	if (adapter->hw.mac_type >= em_82543) {
+		ifp->if_capabilities = IFCAP_HWCSUM;
+		ifp->if_capenable = ifp->if_capabilities;
+	}
+
+	/* 
+	 * Specify the media types supported by this adapter and register
+	 * callbacks to update media and link information
+	 */
+	ifmedia_init(&adapter->media, IFM_IMASK, em_media_change,
+		     em_media_status);
+	if (adapter->hw.media_type == em_media_type_fiber) {
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 
+			    0, NULL);
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_SX, 
+			    0, NULL);
+	} else {
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 
+			    0, NULL);
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 
+			    0, NULL);
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 
+			    0, NULL);
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 
+			    0, NULL);
+		ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
+	}
+	ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
+	ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
+
+	return;
 }
 
 
@@ -1317,18 +1371,19 @@ em_setup_interface(device_t dev, struct adapter * adapter)
 static int
 em_allocate_transmit_structures(struct adapter * adapter)
 {
-   if (!(adapter->tx_buffer_area =
-         (struct em_tx_buffer *) malloc(sizeof(struct em_tx_buffer) *
-                                        adapter->num_tx_desc, M_DEVBUF,
-                                        M_NOWAIT))) {
-      printf("em%d: Unable to allocate tx_buffer memory\n", adapter->unit);
-      return ENOMEM;
-   }
-
-   bzero(adapter->tx_buffer_area,
-         sizeof(struct em_tx_buffer) * adapter->num_tx_desc);
-
-   return 0;
+	if (!(adapter->tx_buffer_area =
+	      (struct em_tx_buffer *) malloc(sizeof(struct em_tx_buffer) *
+					     adapter->num_tx_desc, M_DEVBUF,
+					     M_NOWAIT))) {
+		printf("em%d: Unable to allocate tx_buffer memory\n", 
+		       adapter->unit);
+		return ENOMEM;
+	}
+
+	bzero(adapter->tx_buffer_area,
+	      sizeof(struct em_tx_buffer) * adapter->num_tx_desc);
+
+	return 0;
 }
 
 /*********************************************************************
@@ -1339,42 +1394,43 @@ em_allocate_transmit_structures(struct adapter * adapter)
 static int
 em_setup_transmit_structures(struct adapter * adapter)
 {
-   struct em_tx_buffer   *tx_buffer;
-   int             i;
+	struct em_tx_buffer   *tx_buffer;
+	int             i;
+
+	if (em_allocate_transmit_structures(adapter))
+		return ENOMEM;
 
-   if (em_allocate_transmit_structures(adapter))
-      return ENOMEM;
+	adapter->first_tx_desc = adapter->tx_desc_base;
+	adapter->last_tx_desc =
+	adapter->first_tx_desc + (adapter->num_tx_desc - 1);
 
-   adapter->first_tx_desc = adapter->tx_desc_base;
-   adapter->last_tx_desc =
-      adapter->first_tx_desc + (adapter->num_tx_desc - 1);
 
-   
-   STAILQ_INIT(&adapter->free_tx_buffer_list);
-   STAILQ_INIT(&adapter->used_tx_buffer_list);
+	STAILQ_INIT(&adapter->free_tx_buffer_list);
+	STAILQ_INIT(&adapter->used_tx_buffer_list);
 
-   tx_buffer = adapter->tx_buffer_area;
+	tx_buffer = adapter->tx_buffer_area;
 
-   /* Setup the linked list of the tx_buffer's */
-   for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
-      bzero((void *) tx_buffer, sizeof(struct em_tx_buffer));
-      STAILQ_INSERT_TAIL(&adapter->free_tx_buffer_list, tx_buffer, em_tx_entry);
-   }
+	/* Setup the linked list of the tx_buffer's */
+	for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
+		bzero((void *) tx_buffer, sizeof(struct em_tx_buffer));
+		STAILQ_INSERT_TAIL(&adapter->free_tx_buffer_list, 
+				   tx_buffer, em_tx_entry);
+	}
 
-   bzero((void *) adapter->first_tx_desc,
-        (sizeof(struct em_tx_desc)) * adapter->num_tx_desc);
+	bzero((void *) adapter->first_tx_desc,
+	      (sizeof(struct em_tx_desc)) * adapter->num_tx_desc);
 
-   /* Setup TX descriptor pointers */
-   adapter->next_avail_tx_desc = adapter->first_tx_desc;
-   adapter->oldest_used_tx_desc = adapter->first_tx_desc;
+	/* Setup TX descriptor pointers */
+	adapter->next_avail_tx_desc = adapter->first_tx_desc;
+	adapter->oldest_used_tx_desc = adapter->first_tx_desc;
 
-   /* Set number of descriptors available */
-   adapter->num_tx_desc_avail = adapter->num_tx_desc;
+	/* Set number of descriptors available */
+	adapter->num_tx_desc_avail = adapter->num_tx_desc;
 
-   /* Set checksum context */
-   adapter->active_checksum_context = OFFLOAD_NONE;
+	/* Set checksum context */
+	adapter->active_checksum_context = OFFLOAD_NONE;
 
-   return 0;
+	return 0;
 }
 
 /*********************************************************************
@@ -1385,70 +1441,75 @@ em_setup_transmit_structures(struct adapter * adapter)
 static void
 em_initialize_transmit_unit(struct adapter * adapter)
 {
-   u_int32_t       reg_tctl;
-   u_int32_t       reg_tipg = 0;
-
-   /* Setup the Base and Length of the Tx Descriptor Ring */
-   E1000_WRITE_REG(&adapter->shared, TDBAL, vtophys((vm_offset_t) adapter->tx_desc_base));
-   E1000_WRITE_REG(&adapter->shared, TDBAH, 0);
-   E1000_WRITE_REG(&adapter->shared, TDLEN, adapter->num_tx_desc *
-               sizeof(struct em_tx_desc));
-
-   /* Setup the HW Tx Head and Tail descriptor pointers */
-   E1000_WRITE_REG(&adapter->shared, TDH, 0);
-   E1000_WRITE_REG(&adapter->shared, TDT, 0);
-
-
-   HW_DEBUGOUT2("Base = %x, Length = %x\n", E1000_READ_REG(&adapter->shared, TDBAL),
-                E1000_READ_REG(&adapter->shared, TDLEN));
-
-   
-   /* Set the default values for the Tx Inter Packet Gap timer */
-   switch (adapter->shared.mac_type) {
-   case em_82543:
-   case em_82544:
-   case em_82540:
-      if (adapter->shared.media_type == em_media_type_fiber)
-         reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
-      else
-         reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
-      reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
-      reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
-      break;
-   case em_82542_rev2_0:
-   case em_82542_rev2_1:
-      reg_tipg = DEFAULT_82542_TIPG_IPGT;
-      reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
-      reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
-      break;
-   default:
-      printf("em%d: Invalid mac type detected\n", adapter->unit);
-   }
-   E1000_WRITE_REG(&adapter->shared, TIPG, reg_tipg);
-   E1000_WRITE_REG(&adapter->shared, TIDV, adapter->tx_int_delay);
-
-   /* Program the Transmit Control Register */
-   reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
-      (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
-   if (adapter->link_duplex == 1) {
-      reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
-   } else {
-      reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
-   }
-   E1000_WRITE_REG(&adapter->shared, TCTL, reg_tctl);
-
-   /* Setup Transmit Descriptor Settings for this adapter */   
-   adapter->txd_cmd = E1000_TXD_CMD_IFCS;
-
-   if(adapter->tx_int_delay > 0)
-      adapter->txd_cmd |= E1000_TXD_CMD_IDE;
-   
-   if(adapter->shared.report_tx_early == 1)
-      adapter->txd_cmd |= E1000_TXD_CMD_RS;
-   else
-      adapter->txd_cmd |= E1000_TXD_CMD_RPS;
-
-   return;
+	u_int32_t       reg_tctl;
+	u_int32_t       reg_tipg = 0;
+
+	/* Setup the Base and Length of the Tx Descriptor Ring */
+	E1000_WRITE_REG(&adapter->hw, TDBAL, 
+			vtophys((vm_offset_t) adapter->tx_desc_base));
+	E1000_WRITE_REG(&adapter->hw, TDBAH, 0);
+	E1000_WRITE_REG(&adapter->hw, TDLEN, 
+			adapter->num_tx_desc *
+			sizeof(struct em_tx_desc));
+
+	/* Setup the HW Tx Head and Tail descriptor pointers */
+	E1000_WRITE_REG(&adapter->hw, TDH, 0);
+	E1000_WRITE_REG(&adapter->hw, TDT, 0);
+
+
+	HW_DEBUGOUT2("Base = %x, Length = %x\n", 
+		     E1000_READ_REG(&adapter->hw, TDBAL),
+		     E1000_READ_REG(&adapter->hw, TDLEN));
+
+
+	/* Set the default values for the Tx Inter Packet Gap timer */
+	switch (adapter->hw.mac_type) {
+	case em_82543:
+	case em_82544:
+	case em_82540:
+	case em_82545:
+	case em_82546:
+		if (adapter->hw.media_type == em_media_type_fiber)
+			reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
+		else
+			reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
+		reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
+		reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
+		break;
+	case em_82542_rev2_0:
+	case em_82542_rev2_1:
+		reg_tipg = DEFAULT_82542_TIPG_IPGT;
+		reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
+		reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
+		break;
+	default:
+		printf("em%d: Invalid mac type detected\n", adapter->unit);
+	}
+	E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg);
+	E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay);
+
+	/* Program the Transmit Control Register */
+	reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
+		   (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
+	if (adapter->link_duplex == 1) {
+		reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
+	} else {
+		reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
+	}
+	E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl);
+
+	/* Setup Transmit Descriptor Settings for this adapter */   
+	adapter->txd_cmd = E1000_TXD_CMD_IFCS;
+
+	if (adapter->tx_int_delay > 0)
+		adapter->txd_cmd |= E1000_TXD_CMD_IDE;
+
+	if (adapter->hw.report_tx_early == 1)
+		adapter->txd_cmd |= E1000_TXD_CMD_RS;
+	else
+		adapter->txd_cmd |= E1000_TXD_CMD_RPS;
+
+	return;
 }
 
 /*********************************************************************
@@ -1459,24 +1520,24 @@ em_initialize_transmit_unit(struct adapter * adapter)
 static void
 em_free_transmit_structures(struct adapter * adapter)
 {
-   struct em_tx_buffer   *tx_buffer;
-   int             i;
-
-   INIT_DEBUGOUT("free_transmit_structures: begin");
-
-   if (adapter->tx_buffer_area != NULL) {
-      tx_buffer = adapter->tx_buffer_area;
-      for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
-         if (tx_buffer->m_head != NULL)
-            m_freem(tx_buffer->m_head);
-         tx_buffer->m_head = NULL;
-      }
-   }
-   if (adapter->tx_buffer_area != NULL) {
-      free(adapter->tx_buffer_area, M_DEVBUF);
-      adapter->tx_buffer_area = NULL;
-   }
-   return;
+	struct em_tx_buffer   *tx_buffer;
+	int             i;
+
+	INIT_DEBUGOUT("free_transmit_structures: begin");
+
+	if (adapter->tx_buffer_area != NULL) {
+		tx_buffer = adapter->tx_buffer_area;
+		for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
+			if (tx_buffer->m_head != NULL)
+				m_freem(tx_buffer->m_head);
+			tx_buffer->m_head = NULL;
+		}
+	}
+	if (adapter->tx_buffer_area != NULL) {
+		free(adapter->tx_buffer_area, M_DEVBUF);
+		adapter->tx_buffer_area = NULL;
+	}
+	return;
 }
 
 /*********************************************************************
@@ -1488,76 +1549,80 @@ em_free_transmit_structures(struct adapter * adapter)
  **********************************************************************/
 static void
 em_transmit_checksum_setup(struct adapter * adapter,
-                struct mbuf *mp,
-                struct em_tx_buffer *tx_buffer,
-                u_int32_t *txd_upper,
-                u_int32_t *txd_lower) 
+			   struct mbuf *mp,
+			   struct em_tx_buffer *tx_buffer,
+			   u_int32_t *txd_upper,
+			   u_int32_t *txd_lower) 
 {
-   struct em_context_desc *TXD;
-   struct em_tx_desc * current_tx_desc;
-     
-   if (mp->m_pkthdr.csum_flags) {
-
-      if(mp->m_pkthdr.csum_flags & CSUM_TCP) {
-         *txd_upper = E1000_TXD_POPTS_TXSM << 8;
-         *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
-         if(adapter->active_checksum_context == OFFLOAD_TCP_IP)
-            return;
-         else 
-            adapter->active_checksum_context = OFFLOAD_TCP_IP;
-
-      } else if(mp->m_pkthdr.csum_flags & CSUM_UDP) {
-         *txd_upper = E1000_TXD_POPTS_TXSM << 8;
-         *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
-         if(adapter->active_checksum_context == OFFLOAD_UDP_IP)
-            return;
-         else 
-            adapter->active_checksum_context = OFFLOAD_UDP_IP;
-      } else {
-         *txd_upper = 0;
-         *txd_lower = 0;
-         return;
-      }
-   }
-   else {
-      *txd_upper = 0;
-      *txd_lower = 0;
-      return;
-   }
-
-   /* If we reach this point, the checksum offload context
-    * needs to be reset.
-    */
-   current_tx_desc = adapter->next_avail_tx_desc;
-   TXD = (struct em_context_desc *)current_tx_desc;
-
-   TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
-   TXD->lower_setup.ip_fields.ipcso = ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
-   TXD->lower_setup.ip_fields.ipcse = ETHER_HDR_LEN + sizeof(struct ip) - 1;
-
-   TXD->upper_setup.tcp_fields.tucss = ETHER_HDR_LEN + sizeof(struct ip);
-   TXD->upper_setup.tcp_fields.tucse = 0;
-
-   if(adapter->active_checksum_context == OFFLOAD_TCP_IP) {
-      TXD->upper_setup.tcp_fields.tucso = ETHER_HDR_LEN + sizeof(struct ip) + 
-         offsetof(struct tcphdr, th_sum);
-   } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) {
-      TXD->upper_setup.tcp_fields.tucso = ETHER_HDR_LEN + sizeof(struct ip) + 
-         offsetof(struct udphdr, uh_sum);
-   }
-
-   TXD->tcp_seg_setup.data = 0;
-   TXD->cmd_and_length = E1000_TXD_CMD_DEXT;
-
-   if (current_tx_desc == adapter->last_tx_desc)
-      adapter->next_avail_tx_desc = adapter->first_tx_desc;
-   else
-      adapter->next_avail_tx_desc++;
-
-   adapter->num_tx_desc_avail--;
-    
-   tx_buffer->num_tx_desc_used++;
-   return;
+	struct em_context_desc *TXD;
+	struct em_tx_desc * current_tx_desc;
+
+	if (mp->m_pkthdr.csum_flags) {
+
+		if (mp->m_pkthdr.csum_flags & CSUM_TCP) {
+			*txd_upper = E1000_TXD_POPTS_TXSM << 8;
+			*txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
+			if (adapter->active_checksum_context == OFFLOAD_TCP_IP)
+				return;
+			else
+				adapter->active_checksum_context = OFFLOAD_TCP_IP;
+
+		} else if (mp->m_pkthdr.csum_flags & CSUM_UDP) {
+			*txd_upper = E1000_TXD_POPTS_TXSM << 8;
+			*txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
+			if (adapter->active_checksum_context == OFFLOAD_UDP_IP)
+				return;
+			else
+				adapter->active_checksum_context = OFFLOAD_UDP_IP;
+		} else {
+			*txd_upper = 0;
+			*txd_lower = 0;
+			return;
+		}
+	} else {
+		*txd_upper = 0;
+		*txd_lower = 0;
+		return;
+	}
+
+	/* If we reach this point, the checksum offload context
+	 * needs to be reset.
+	 */
+	current_tx_desc = adapter->next_avail_tx_desc;
+	TXD = (struct em_context_desc *)current_tx_desc;
+
+	TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
+	TXD->lower_setup.ip_fields.ipcso = 
+	ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
+	TXD->lower_setup.ip_fields.ipcse = 
+	ETHER_HDR_LEN + sizeof(struct ip) - 1;
+
+	TXD->upper_setup.tcp_fields.tucss = 
+	ETHER_HDR_LEN + sizeof(struct ip);
+	TXD->upper_setup.tcp_fields.tucse = 0;
+
+	if (adapter->active_checksum_context == OFFLOAD_TCP_IP) {
+		TXD->upper_setup.tcp_fields.tucso = 
+		ETHER_HDR_LEN + sizeof(struct ip) + 
+		offsetof(struct tcphdr, th_sum);
+	} else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) {
+		TXD->upper_setup.tcp_fields.tucso = 
+		ETHER_HDR_LEN + sizeof(struct ip) + 
+		offsetof(struct udphdr, uh_sum);
+	}
+
+	TXD->tcp_seg_setup.data = 0;
+	TXD->cmd_and_length = E1000_TXD_CMD_DEXT;
+
+	if (current_tx_desc == adapter->last_tx_desc)
+		adapter->next_avail_tx_desc = adapter->first_tx_desc;
+	else
+		adapter->next_avail_tx_desc++;
+
+	adapter->num_tx_desc_avail--;
+
+	tx_buffer->num_tx_desc_used++;
+	return;
 }
 
 
@@ -1568,41 +1633,41 @@ em_transmit_checksum_setup(struct adapter * adapter,
  **********************************************************************/
 static int
 em_get_buf(struct em_rx_buffer *rx_buffer, struct adapter *adapter,
-           struct mbuf *mp)
+	   struct mbuf *mp)
 {
-   struct mbuf    *nmp;
-   struct ifnet   *ifp;
-
-   ifp = &adapter->interface_data.ac_if;
-
-   if (mp == NULL) {
-      MGETHDR(nmp, M_DONTWAIT, MT_DATA);
-      if (nmp == NULL) {
-         adapter->mbuf_alloc_failed++;
-         return (ENOBUFS);
-      }
-      MCLGET(nmp, M_DONTWAIT);
-      if ((nmp->m_flags & M_EXT) == 0) {
-         m_freem(nmp);
-         adapter->mbuf_cluster_failed++;
-         return (ENOBUFS);
-      }
-      nmp->m_len = nmp->m_pkthdr.len = MCLBYTES;
-   } else {
-      nmp = mp;
-      nmp->m_len = nmp->m_pkthdr.len = MCLBYTES;
-      nmp->m_data = nmp->m_ext.ext_buf;
-      nmp->m_next = NULL;
-   }
-
-   if (ifp->if_mtu <= ETHERMTU) {
-      m_adj(nmp, ETHER_ALIGN);
-   }
-
-   rx_buffer->m_head = nmp;
-   rx_buffer->buffer_addr = vtophys(mtod(nmp, vm_offset_t));
-
-   return (0);
+	struct mbuf    *nmp;
+	struct ifnet   *ifp;
+
+	ifp = &adapter->interface_data.ac_if;
+
+	if (mp == NULL) {
+		MGETHDR(nmp, M_DONTWAIT, MT_DATA);
+		if (nmp == NULL) {
+			adapter->mbuf_alloc_failed++;
+			return(ENOBUFS);
+		}
+		MCLGET(nmp, M_DONTWAIT);
+		if ((nmp->m_flags & M_EXT) == 0) {
+			m_freem(nmp);
+			adapter->mbuf_cluster_failed++;
+			return(ENOBUFS);
+		}
+		nmp->m_len = nmp->m_pkthdr.len = MCLBYTES;
+	} else {
+		nmp = mp;
+		nmp->m_len = nmp->m_pkthdr.len = MCLBYTES;
+		nmp->m_data = nmp->m_ext.ext_buf;
+		nmp->m_next = NULL;
+	}
+
+	if (ifp->if_mtu <= ETHERMTU) {
+		m_adj(nmp, ETHER_ALIGN);
+	}
+
+	rx_buffer->m_head = nmp;
+	rx_buffer->buffer_addr = vtophys(mtod(nmp, vm_offset_t));
+
+	return(0);
 }
 
 /*********************************************************************
@@ -1616,30 +1681,31 @@ em_get_buf(struct em_rx_buffer *rx_buffer, struct adapter *adapter,
 static int
 em_allocate_receive_structures(struct adapter * adapter)
 {
-   int             i;
-   struct em_rx_buffer   *rx_buffer;
-
-   if (!(adapter->rx_buffer_area =
-        (struct em_rx_buffer *) malloc(sizeof(struct em_rx_buffer) *
-                                       adapter->num_rx_desc, M_DEVBUF,
-                                       M_NOWAIT))) {
-      printf("em%d: Unable to allocate rx_buffer memory\n", adapter->unit);
-      return (ENOMEM);
-   }
-
-   bzero(adapter->rx_buffer_area,
-         sizeof(struct em_rx_buffer) * adapter->num_rx_desc);
-
-   for (i = 0, rx_buffer = adapter->rx_buffer_area;
-       i < adapter->num_rx_desc; i++, rx_buffer++) {
-
-      if (em_get_buf(rx_buffer, adapter, NULL) == ENOBUFS) {
-         rx_buffer->m_head = NULL;
-         return (ENOBUFS);
-      }
-   }
-
-   return (0);
+	int             i;
+	struct em_rx_buffer   *rx_buffer;
+
+	if (!(adapter->rx_buffer_area =
+	      (struct em_rx_buffer *) malloc(sizeof(struct em_rx_buffer) *
+					     adapter->num_rx_desc, M_DEVBUF,
+					     M_NOWAIT))) {
+		printf("em%d: Unable to allocate rx_buffer memory\n", 
+		       adapter->unit);
+		return(ENOMEM);
+	}
+
+	bzero(adapter->rx_buffer_area,
+	      sizeof(struct em_rx_buffer) * adapter->num_rx_desc);
+
+	for (i = 0, rx_buffer = adapter->rx_buffer_area;
+	    i < adapter->num_rx_desc; i++, rx_buffer++) {
+
+		if (em_get_buf(rx_buffer, adapter, NULL) == ENOBUFS) {
+			rx_buffer->m_head = NULL;
+			return(ENOBUFS);
+		}
+	}
+
+	return(0);
 }
 
 /*********************************************************************
@@ -1650,41 +1716,43 @@ em_allocate_receive_structures(struct adapter * adapter)
 static int
 em_setup_receive_structures(struct adapter * adapter)
 {
-   struct em_rx_buffer   *rx_buffer;
-   struct em_rx_desc     *rx_desc;
-   int             i;
-
-   if(em_allocate_receive_structures(adapter))
-      return ENOMEM;
-
-   STAILQ_INIT(&adapter->rx_buffer_list);
-
-   adapter->first_rx_desc =
-      (struct em_rx_desc *) adapter->rx_desc_base;
-   adapter->last_rx_desc =
-      adapter->first_rx_desc + (adapter->num_rx_desc - 1);
-
-   rx_buffer = (struct em_rx_buffer *) adapter->rx_buffer_area;
-
-   bzero((void *) adapter->first_rx_desc,
-        (sizeof(struct em_rx_desc)) * adapter->num_rx_desc);
-
-   /* Build a linked list of rx_buffer's */
-   for (i = 0, rx_desc = adapter->first_rx_desc;
-       i < adapter->num_rx_desc;
-       i++, rx_buffer++, rx_desc++) {
-      if (rx_buffer->m_head == NULL)
-         printf("em%d: Receive buffer memory not allocated", adapter->unit);
-      else {
-         rx_desc->buffer_addr = rx_buffer->buffer_addr;
-         STAILQ_INSERT_TAIL(&adapter->rx_buffer_list, rx_buffer, em_rx_entry);
-      }
-   }
-
-   /* Setup our descriptor pointers */
-   adapter->next_rx_desc_to_check = adapter->first_rx_desc;
-
-   return(0);
+	struct em_rx_buffer   *rx_buffer;
+	struct em_rx_desc     *rx_desc;
+	int             i;
+
+	if (em_allocate_receive_structures(adapter))
+		return ENOMEM;
+
+	STAILQ_INIT(&adapter->rx_buffer_list);
+
+	adapter->first_rx_desc =
+	(struct em_rx_desc *) adapter->rx_desc_base;
+	adapter->last_rx_desc =
+	adapter->first_rx_desc + (adapter->num_rx_desc - 1);
+
+	rx_buffer = (struct em_rx_buffer *) adapter->rx_buffer_area;
+
+	bzero((void *) adapter->first_rx_desc,
+	      (sizeof(struct em_rx_desc)) * adapter->num_rx_desc);
+
+	/* Build a linked list of rx_buffer's */
+	for (i = 0, rx_desc = adapter->first_rx_desc;
+	    i < adapter->num_rx_desc;
+	    i++, rx_buffer++, rx_desc++) {
+		if (rx_buffer->m_head == NULL)
+			printf("em%d: Receive buffer memory not allocated", 
+			       adapter->unit);
+		else {
+			rx_desc->buffer_addr = rx_buffer->buffer_addr;
+			STAILQ_INSERT_TAIL(&adapter->rx_buffer_list, 
+					   rx_buffer, em_rx_entry);
+		}
+	}
+
+	/* Setup our descriptor pointers */
+	adapter->next_rx_desc_to_check = adapter->first_rx_desc;
+
+	return(0);
 }
 
 /*********************************************************************
@@ -1695,67 +1763,70 @@ em_setup_receive_structures(struct adapter * adapter)
 static void
 em_initialize_receive_unit(struct adapter * adapter)
 {
-   u_int32_t       reg_rctl;
-   u_int32_t       reg_rxcsum;
-   struct ifnet    *ifp;
-   
-   ifp = &adapter->interface_data.ac_if;
-
-   /* Make sure receives are disabled while setting up the descriptor ring */
-   E1000_WRITE_REG(&adapter->shared, RCTL, 0);
-
-   /* Set the Receive Delay Timer Register */
-   E1000_WRITE_REG(&adapter->shared, RDTR, adapter->rx_int_delay | E1000_RDT_FPDB);
-
-   /* Setup the Base and Length of the Rx Descriptor Ring */
-   E1000_WRITE_REG(&adapter->shared, RDBAL, vtophys((vm_offset_t) adapter->rx_desc_base));
-   E1000_WRITE_REG(&adapter->shared, RDBAH, 0);
-   E1000_WRITE_REG(&adapter->shared, RDLEN, adapter->num_rx_desc *
-               sizeof(struct em_rx_desc));
-
-   /* Setup the HW Rx Head and Tail Descriptor Pointers */
-   E1000_WRITE_REG(&adapter->shared, RDH, 0);
-   E1000_WRITE_REG(&adapter->shared, RDT,
-               (((uintptr_t) adapter->last_rx_desc -
-                 (uintptr_t) adapter->first_rx_desc) >> 4));
-   
-   /* Setup the Receive Control Register */
-   reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
-      E1000_RCTL_RDMTS_HALF |
-      (adapter->shared.mc_filter_type << E1000_RCTL_MO_SHIFT);
-
-   if (adapter->shared.tbi_compatibility_on == TRUE)
-      reg_rctl |= E1000_RCTL_SBP;
-
-
-   switch (adapter->rx_buffer_len) {
-   case EM_RXBUFFER_2048:
-      reg_rctl |= E1000_RCTL_SZ_2048 | E1000_RCTL_LPE;
-      break;
-   case EM_RXBUFFER_4096:
-      reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
-      break;            
-   case EM_RXBUFFER_8192:
-      reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
-      break;
-   case EM_RXBUFFER_16384:
-      reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
-      break;
-   default:
-      reg_rctl |= E1000_RCTL_SZ_2048;
-   }
-
-   /* Enable 82543 Receive Checksum Offload for TCP and UDP */
-   if((adapter->shared.mac_type >= em_82543) && (ifp->if_capenable & IFCAP_RXCSUM)) {
-      reg_rxcsum = E1000_READ_REG(&adapter->shared, RXCSUM);
-      reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
-      E1000_WRITE_REG(&adapter->shared, RXCSUM, reg_rxcsum);
-   }
-
-   /* Enable Receives */
-   E1000_WRITE_REG(&adapter->shared, RCTL, reg_rctl);
-
-   return;
+	u_int32_t       reg_rctl;
+	u_int32_t       reg_rxcsum;
+	struct ifnet    *ifp;
+
+	ifp = &adapter->interface_data.ac_if;
+
+	/* Make sure receives are disabled while setting up the descriptor ring */
+	E1000_WRITE_REG(&adapter->hw, RCTL, 0);
+
+	/* Set the Receive Delay Timer Register */
+	E1000_WRITE_REG(&adapter->hw, RDTR, 
+			adapter->rx_int_delay | E1000_RDT_FPDB);
+
+	/* Setup the Base and Length of the Rx Descriptor Ring */
+	E1000_WRITE_REG(&adapter->hw, RDBAL, 
+			vtophys((vm_offset_t) adapter->rx_desc_base));
+	E1000_WRITE_REG(&adapter->hw, RDBAH, 0);
+	E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc *
+			sizeof(struct em_rx_desc));
+
+	/* Setup the HW Rx Head and Tail Descriptor Pointers */
+	E1000_WRITE_REG(&adapter->hw, RDH, 0);
+	E1000_WRITE_REG(&adapter->hw, RDT,
+			(((uintptr_t) adapter->last_rx_desc -
+			  (uintptr_t) adapter->first_rx_desc) >> 4));
+
+	/* Setup the Receive Control Register */
+	reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
+		   E1000_RCTL_RDMTS_HALF |
+		   (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
+
+	if (adapter->hw.tbi_compatibility_on == TRUE)
+		reg_rctl |= E1000_RCTL_SBP;
+
+
+	switch (adapter->rx_buffer_len) {
+	case EM_RXBUFFER_2048:
+		reg_rctl |= E1000_RCTL_SZ_2048 | E1000_RCTL_LPE;
+		break;
+	case EM_RXBUFFER_4096:
+		reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
+		break;            
+	case EM_RXBUFFER_8192:
+		reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
+		break;
+	case EM_RXBUFFER_16384:
+		reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
+		break;
+	default:
+		reg_rctl |= E1000_RCTL_SZ_2048;
+	}
+
+	/* Enable 82543 Receive Checksum Offload for TCP and UDP */
+	if ((adapter->hw.mac_type >= em_82543) && 
+	    (ifp->if_capenable & IFCAP_RXCSUM)) {
+		reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
+		reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
+		E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum);
+	}
+
+	/* Enable Receives */
+	E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+
+	return;
 }
 
 /*********************************************************************
@@ -1766,24 +1837,24 @@ em_initialize_receive_unit(struct adapter * adapter)
 static void
 em_free_receive_structures(struct adapter * adapter)
 {
-   struct em_rx_buffer   *rx_buffer;
-   int             i;
-
-   INIT_DEBUGOUT("free_receive_structures: begin");
-
-   if (adapter->rx_buffer_area != NULL) {
-      rx_buffer = adapter->rx_buffer_area;
-      for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
-         if (rx_buffer->m_head != NULL)
-            m_freem(rx_buffer->m_head);
-         rx_buffer->m_head = NULL;
-      }
-   }
-   if (adapter->rx_buffer_area != NULL) {
-      free(adapter->rx_buffer_area, M_DEVBUF);
-      adapter->rx_buffer_area = NULL;
-   }
-   return;
+	struct em_rx_buffer   *rx_buffer;
+	int             i;
+
+	INIT_DEBUGOUT("free_receive_structures: begin");
+
+	if (adapter->rx_buffer_area != NULL) {
+		rx_buffer = adapter->rx_buffer_area;
+		for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
+			if (rx_buffer->m_head != NULL)
+				m_freem(rx_buffer->m_head);
+			rx_buffer->m_head = NULL;
+		}
+	}
+	if (adapter->rx_buffer_area != NULL) {
+		free(adapter->rx_buffer_area, M_DEVBUF);
+		adapter->rx_buffer_area = NULL;
+	}
+	return;
 }
 
 /*********************************************************************
@@ -1796,147 +1867,155 @@ em_free_receive_structures(struct adapter * adapter)
 static void
 em_process_receive_interrupts(struct adapter * adapter)
 {
-   struct mbuf         *mp;
-   struct ifnet        *ifp;
-   struct ether_header *eh;
-   u_int16_t           len;
-   u_int8_t            last_byte;
-   u_int8_t            accept_frame = 0;
-   u_int8_t            eop = 0;
-   u_int32_t           pkt_len = 0;
-
-   /* Pointer to the receive descriptor being examined. */
-   struct em_rx_desc   *current_desc;
-   struct em_rx_desc   *last_desc_processed;
-   struct em_rx_buffer *rx_buffer;
-
-   ifp = &adapter->interface_data.ac_if;
-   current_desc = adapter->next_rx_desc_to_check;
-
-   if (!((current_desc->status) & E1000_RXD_STAT_DD)) {
+	struct mbuf         *mp;
+	struct ifnet        *ifp;
+	struct ether_header *eh;
+	u_int16_t           len;
+	u_int8_t            last_byte;
+	u_int8_t            accept_frame = 0;
+	u_int8_t            eop = 0;
+	u_int32_t           pkt_len = 0;
+
+	/* Pointer to the receive descriptor being examined. */
+	struct em_rx_desc   *current_desc;
+	struct em_rx_desc   *last_desc_processed;
+	struct em_rx_buffer *rx_buffer;
+
+	ifp = &adapter->interface_data.ac_if;
+	current_desc = adapter->next_rx_desc_to_check;
+
+	if (!((current_desc->status) & E1000_RXD_STAT_DD)) {
 #ifdef DBG_STATS
-      adapter->no_pkts_avail++;
+		adapter->no_pkts_avail++;
 #endif
-      return;
-   }
-   
-   while (current_desc->status & E1000_RXD_STAT_DD) {
-
-      /* Get a pointer to the actual receive buffer */
-      rx_buffer = STAILQ_FIRST(&adapter->rx_buffer_list);
-
-      if(rx_buffer == NULL) {
-         printf("em%d: Found null rx_buffer\n", adapter->unit);
-         return;
-      }
-
-      mp = rx_buffer->m_head;      
-      accept_frame = 1;
-
-      if (current_desc->status & E1000_RXD_STAT_EOP) {
-         eop = 1;
-         len = current_desc->length - ETHER_CRC_LEN;
-      }
-      else {
-         eop = 0;
-         len = current_desc->length;
-      }
-
-      if(current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
-         
-         /* Compute packet length for tbi_accept macro */
-         pkt_len = current_desc->length;
-         if (adapter->fmp != NULL) {
-            pkt_len += adapter->fmp->m_pkthdr.len; 
-         }
-
-         last_byte = *(mtod(rx_buffer->m_head,caddr_t) + current_desc->length - 1);
-
-         if (TBI_ACCEPT(&adapter->shared, current_desc->status, 
-                        current_desc->errors, 
-                        pkt_len, last_byte)) {  
-            pkt_len = em_tbi_adjust_stats(&adapter->shared, &adapter->stats, 
-                                               pkt_len, adapter->shared.mac_addr);
-            len--;
-         } else {  
-            accept_frame = 0;
-         }
-      }
-
-      if (accept_frame) {
-
-         if (em_get_buf(rx_buffer, adapter, NULL) == ENOBUFS) {
-            adapter->dropped_pkts++;
-            em_get_buf(rx_buffer, adapter, mp);
-            if(adapter->fmp != NULL) m_freem(adapter->fmp);
-            adapter->fmp = NULL;
-            adapter->lmp = NULL;
-            break;
-         }
-
-         /* Assign correct length to the current fragment */
-         mp->m_len = len;
-
-         if(adapter->fmp == NULL) {
-            mp->m_pkthdr.len = len;
-            adapter->fmp = mp;       /* Store the first mbuf */
-            adapter->lmp = mp;
-         }
-         else {
-            /* Chain mbuf's together */
-            mp->m_flags &= ~M_PKTHDR;
-            adapter->lmp->m_next = mp;
-            adapter->lmp = adapter->lmp->m_next;
-            adapter->fmp->m_pkthdr.len += len;
-         }
-
-         if (eop) {
-            adapter->fmp->m_pkthdr.rcvif = ifp;
-
-            eh = mtod(adapter->fmp, struct ether_header *);
-
-            /* Remove ethernet header from mbuf */
-            m_adj(adapter->fmp, sizeof(struct ether_header));
-            em_receive_checksum(adapter, current_desc, adapter->fmp);
-            ether_input(ifp, eh, adapter->fmp);
-      
-            adapter->fmp = NULL;
-            adapter->lmp = NULL;
-         }
-      } else {
-         adapter->dropped_pkts++;
-         em_get_buf(rx_buffer, adapter, mp);
-         if(adapter->fmp != NULL) m_freem(adapter->fmp);
-         adapter->fmp = NULL;
-         adapter->lmp = NULL;
-      }
-      
-      /* Zero out the receive descriptors status  */
-      current_desc->status = 0;
-      
-      if (rx_buffer->m_head != NULL) {
-         current_desc->buffer_addr = rx_buffer->buffer_addr;
-      }
-
-      /* Advance our pointers to the next descriptor (checking for wrap). */
-      if (current_desc == adapter->last_rx_desc)
-         adapter->next_rx_desc_to_check = adapter->first_rx_desc;
-      else
-         ((adapter)->next_rx_desc_to_check)++;
-
-      last_desc_processed = current_desc;
-      current_desc = adapter->next_rx_desc_to_check;
-      /* 
-       * Put the buffer that we just indicated back at the end of our list
-       */
-      STAILQ_REMOVE_HEAD(&adapter->rx_buffer_list, em_rx_entry);
-      STAILQ_INSERT_TAIL(&adapter->rx_buffer_list, rx_buffer, em_rx_entry);
-
-      /* Advance the E1000's Receive Queue #0  "Tail Pointer". */
-      E1000_WRITE_REG(&adapter->shared, RDT, (((u_int32_t) last_desc_processed -
-                        (u_int32_t) adapter->first_rx_desc) >> 4));
-   }
-   return;
+		return;
+	}
+
+	while (current_desc->status & E1000_RXD_STAT_DD) {
+
+		/* Get a pointer to the actual receive buffer */
+		rx_buffer = STAILQ_FIRST(&adapter->rx_buffer_list);
+
+		if (rx_buffer == NULL) {
+			printf("em%d: Found null rx_buffer\n", adapter->unit);
+			return;
+		}
+
+		mp = rx_buffer->m_head;      
+		accept_frame = 1;
+
+		if (current_desc->status & E1000_RXD_STAT_EOP) {
+			eop = 1;
+			len = current_desc->length - ETHER_CRC_LEN;
+		} else {
+			eop = 0;
+			len = current_desc->length;
+		}
+
+		if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
+
+			/* Compute packet length for tbi_accept macro */
+			pkt_len = current_desc->length;
+			if (adapter->fmp != NULL) {
+				pkt_len += adapter->fmp->m_pkthdr.len; 
+			}
+
+			last_byte = *(mtod(rx_buffer->m_head,caddr_t) + 
+				      current_desc->length - 1);
+
+			if (TBI_ACCEPT(&adapter->hw, current_desc->status, 
+				       current_desc->errors, 
+				       pkt_len, last_byte)) {
+				em_tbi_adjust_stats(&adapter->hw, 
+						    &adapter->stats, 
+						    pkt_len, 
+						    adapter->hw.mac_addr);
+				len--;
+			} else {
+				accept_frame = 0;
+			}
+		}
+
+		if (accept_frame) {
+
+			if (em_get_buf(rx_buffer, adapter, NULL) == ENOBUFS) {
+				adapter->dropped_pkts++;
+				em_get_buf(rx_buffer, adapter, mp);
+				if (adapter->fmp != NULL) m_freem(adapter->fmp);
+				adapter->fmp = NULL;
+				adapter->lmp = NULL;
+				break;
+			}
+
+			/* Assign correct length to the current fragment */
+			mp->m_len = len;
+
+			if (adapter->fmp == NULL) {
+				mp->m_pkthdr.len = len;
+				adapter->fmp = mp;	 /* Store the first mbuf */
+				adapter->lmp = mp;
+			} else {
+				/* Chain mbuf's together */
+				mp->m_flags &= ~M_PKTHDR;
+				adapter->lmp->m_next = mp;
+				adapter->lmp = adapter->lmp->m_next;
+				adapter->fmp->m_pkthdr.len += len;
+			}
+
+			if (eop) {
+				adapter->fmp->m_pkthdr.rcvif = ifp;
+
+				eh = mtod(adapter->fmp, struct ether_header *);
+
+				/* Remove ethernet header from mbuf */
+				m_adj(adapter->fmp, sizeof(struct ether_header));
+				em_receive_checksum(adapter, current_desc, 
+						    adapter->fmp);
+				if (current_desc->status & E1000_RXD_STAT_VP)
+					VLAN_INPUT_TAG(eh, adapter->fmp, 
+						       current_desc->special);
+				else
+					ether_input(ifp, eh, adapter->fmp);
+
+				adapter->fmp = NULL;
+				adapter->lmp = NULL;
+			}
+		} else {
+			adapter->dropped_pkts++;
+			em_get_buf(rx_buffer, adapter, mp);
+			if (adapter->fmp != NULL) m_freem(adapter->fmp);
+			adapter->fmp = NULL;
+			adapter->lmp = NULL;
+		}
+
+		/* Zero out the receive descriptors status  */
+		current_desc->status = 0;
+
+		if (rx_buffer->m_head != NULL) {
+			current_desc->buffer_addr = rx_buffer->buffer_addr;
+		}
+
+		/* Advance our pointers to the next descriptor (checking for wrap). */
+		if (current_desc == adapter->last_rx_desc)
+			adapter->next_rx_desc_to_check = adapter->first_rx_desc;
+		else
+			((adapter)->next_rx_desc_to_check)++;
+
+		last_desc_processed = current_desc;
+		current_desc = adapter->next_rx_desc_to_check;
+		/* 
+		 * Put the buffer that we just indicated back at the end of our list
+		 */
+		STAILQ_REMOVE_HEAD(&adapter->rx_buffer_list, em_rx_entry);
+		STAILQ_INSERT_TAIL(&adapter->rx_buffer_list, 
+				   rx_buffer, em_rx_entry);
+
+		/* Advance the E1000's Receive Queue #0  "Tail Pointer". */
+		E1000_WRITE_REG(&adapter->hw, RDT, 
+				(((u_long) last_desc_processed -
+				  (u_long) adapter->first_rx_desc) >> 4));
+	}
+	return;
 }
 
 /*********************************************************************
@@ -1948,61 +2027,76 @@ em_process_receive_interrupts(struct adapter * adapter)
  *********************************************************************/
 static void
 em_receive_checksum(struct adapter *adapter,
-                    struct em_rx_desc *rx_desc,
-                    struct mbuf *mp)
+		    struct em_rx_desc *rx_desc,
+		    struct mbuf *mp)
 {
-   /* 82543 or newer only */
-   if((adapter->shared.mac_type < em_82543) ||
-      /* Ignore Checksum bit is set */
-      (rx_desc->status & E1000_RXD_STAT_IXSM)) {
-      mp->m_pkthdr.csum_flags = 0;
-      return;
-   }
-
-   if (rx_desc->status & E1000_RXD_STAT_IPCS) {
-      /* Did it pass? */
-      if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
-         /* IP Checksum Good */
-         mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
-         mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
-
-      }
-      else {
-         mp->m_pkthdr.csum_flags = 0;
-      }
-   }
-
-   if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
-      /* Did it pass? */        
-      if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
-         mp->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
-         mp->m_pkthdr.csum_data = htons(0xffff);
-      }
-   }
-
-   return;
+	/* 82543 or newer only */
+	if ((adapter->hw.mac_type < em_82543) ||
+	    /* Ignore Checksum bit is set */
+	    (rx_desc->status & E1000_RXD_STAT_IXSM)) {
+		mp->m_pkthdr.csum_flags = 0;
+		return;
+	}
+
+	if (rx_desc->status & E1000_RXD_STAT_IPCS) {
+		/* Did it pass? */
+		if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
+			/* IP Checksum Good */
+			mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
+			mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
+
+		} else {
+			mp->m_pkthdr.csum_flags = 0;
+		}
+	}
+
+	if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
+		/* Did it pass? */        
+		if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
+			mp->m_pkthdr.csum_flags |= 
+			(CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
+			mp->m_pkthdr.csum_data = htons(0xffff);
+		}
+	}
+
+	return;
 }
 
 
+static void em_enable_vlans(struct adapter *adapter)
+{
+	uint32_t ctrl;
+
+	E1000_WRITE_REG(&adapter->hw, VET, QTAG_TYPE);
+
+	ctrl = E1000_READ_REG(&adapter->hw, CTRL);
+	ctrl |= E1000_CTRL_VME; 
+	E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
+
+	return;
+}
+
 static void
 em_enable_intr(struct adapter * adapter)
 {
-   E1000_WRITE_REG(&adapter->shared, IMS, (IMS_ENABLE_MASK));
-   return;
+	E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK));
+	return;
 }
 
 static void
-em_disable_intr(struct adapter * adapter)
+em_disable_intr(struct adapter *adapter)
 {
-   E1000_WRITE_REG(&adapter->shared, IMC, (0xffffffff & ~E1000_IMC_RXSEQ));
-   return;
+	E1000_WRITE_REG(&adapter->hw, IMC, 
+			(0xffffffff & ~E1000_IMC_RXSEQ));
+	return;
 }
 
-void em_write_pci_cfg(struct em_shared_adapter *adapter,
-                      uint32_t reg,
-                      uint16_t * value)
+void em_write_pci_cfg(struct em_hw *adapter,
+		      uint32_t reg,
+		      uint16_t *value)
 {
-   pci_write_config(((struct em_osdep *)adapter->back)->dev, reg, *value, 2);
+	pci_write_config(((struct em_osdep *)adapter->back)->dev, reg, 
+			 *value, 2);
 }
 
 
@@ -2012,96 +2106,102 @@ void em_write_pci_cfg(struct em_shared_adapter *adapter,
  *
  **********************************************************************/
 static void
-em_update_stats_counters(struct adapter * adapter)
+em_update_stats_counters(struct adapter *adapter)
 {
-   struct ifnet   *ifp;
-
-   adapter->stats.crcerrs += E1000_READ_REG(&adapter->shared, CRCERRS);
-   adapter->stats.symerrs += E1000_READ_REG(&adapter->shared, SYMERRS);
-   adapter->stats.mpc += E1000_READ_REG(&adapter->shared, MPC);
-   adapter->stats.scc += E1000_READ_REG(&adapter->shared, SCC);
-   adapter->stats.ecol += E1000_READ_REG(&adapter->shared, ECOL);
-   adapter->stats.mcc += E1000_READ_REG(&adapter->shared, MCC);
-   adapter->stats.latecol += E1000_READ_REG(&adapter->shared, LATECOL);
-   adapter->stats.colc += E1000_READ_REG(&adapter->shared, COLC);
-   adapter->stats.dc += E1000_READ_REG(&adapter->shared, DC);
-   adapter->stats.sec += E1000_READ_REG(&adapter->shared, SEC);
-   adapter->stats.rlec += E1000_READ_REG(&adapter->shared, RLEC);
-   adapter->stats.xonrxc += E1000_READ_REG(&adapter->shared, XONRXC);
-   adapter->stats.xontxc += E1000_READ_REG(&adapter->shared, XONTXC);
-   adapter->stats.xoffrxc += E1000_READ_REG(&adapter->shared, XOFFRXC);
-   adapter->stats.xofftxc += E1000_READ_REG(&adapter->shared, XOFFTXC);
-   adapter->stats.fcruc += E1000_READ_REG(&adapter->shared, FCRUC);
-   adapter->stats.prc64 += E1000_READ_REG(&adapter->shared, PRC64);
-   adapter->stats.prc127 += E1000_READ_REG(&adapter->shared, PRC127);
-   adapter->stats.prc255 += E1000_READ_REG(&adapter->shared, PRC255);
-   adapter->stats.prc511 += E1000_READ_REG(&adapter->shared, PRC511);
-   adapter->stats.prc1023 += E1000_READ_REG(&adapter->shared, PRC1023);
-   adapter->stats.prc1522 += E1000_READ_REG(&adapter->shared, PRC1522);
-   adapter->stats.gprc += E1000_READ_REG(&adapter->shared, GPRC);
-   adapter->stats.bprc += E1000_READ_REG(&adapter->shared, BPRC);
-   adapter->stats.mprc += E1000_READ_REG(&adapter->shared, MPRC);
-   adapter->stats.gptc += E1000_READ_REG(&adapter->shared, GPTC);
-
-   /* For the 64-bit byte counters the low dword must be read first. */
-   /* Both registers clear on the read of the high dword */
-
-   adapter->stats.gorcl += E1000_READ_REG(&adapter->shared, GORCL); 
-   adapter->stats.gorch += E1000_READ_REG(&adapter->shared, GORCH);
-   adapter->stats.gotcl += E1000_READ_REG(&adapter->shared, GOTCL);
-   adapter->stats.gotch += E1000_READ_REG(&adapter->shared, GOTCH);
-
-   adapter->stats.rnbc += E1000_READ_REG(&adapter->shared, RNBC);
-   adapter->stats.ruc += E1000_READ_REG(&adapter->shared, RUC);
-   adapter->stats.rfc += E1000_READ_REG(&adapter->shared, RFC);
-   adapter->stats.roc += E1000_READ_REG(&adapter->shared, ROC);
-   adapter->stats.rjc += E1000_READ_REG(&adapter->shared, RJC);
-
-   adapter->stats.torl += E1000_READ_REG(&adapter->shared, TORL);
-   adapter->stats.torh += E1000_READ_REG(&adapter->shared, TORH);
-   adapter->stats.totl += E1000_READ_REG(&adapter->shared, TOTL);
-   adapter->stats.toth += E1000_READ_REG(&adapter->shared, TOTH);
-
-   adapter->stats.tpr += E1000_READ_REG(&adapter->shared, TPR);
-   adapter->stats.tpt += E1000_READ_REG(&adapter->shared, TPT);
-   adapter->stats.ptc64 += E1000_READ_REG(&adapter->shared, PTC64);
-   adapter->stats.ptc127 += E1000_READ_REG(&adapter->shared, PTC127);
-   adapter->stats.ptc255 += E1000_READ_REG(&adapter->shared, PTC255);
-   adapter->stats.ptc511 += E1000_READ_REG(&adapter->shared, PTC511);
-   adapter->stats.ptc1023 += E1000_READ_REG(&adapter->shared, PTC1023);
-   adapter->stats.ptc1522 += E1000_READ_REG(&adapter->shared, PTC1522);
-   adapter->stats.mptc += E1000_READ_REG(&adapter->shared, MPTC);
-   adapter->stats.bptc += E1000_READ_REG(&adapter->shared, BPTC);
-
-   if (adapter->shared.mac_type >= em_82543) {
-      adapter->stats.algnerrc += E1000_READ_REG(&adapter->shared, ALGNERRC);
-      adapter->stats.rxerrc += E1000_READ_REG(&adapter->shared, RXERRC);
-      adapter->stats.tncrs += E1000_READ_REG(&adapter->shared, TNCRS);
-      adapter->stats.cexterr += E1000_READ_REG(&adapter->shared, CEXTERR);
-      adapter->stats.tsctc += E1000_READ_REG(&adapter->shared, TSCTC);
-      adapter->stats.tsctfc += E1000_READ_REG(&adapter->shared, TSCTFC);
-   }
-   ifp = &adapter->interface_data.ac_if;
-
-   /* Fill out the OS statistics structure */
-   ifp->if_ipackets = adapter->stats.gprc;
-   ifp->if_opackets = adapter->stats.gptc;
-   ifp->if_ibytes = adapter->stats.gorcl;
-   ifp->if_obytes = adapter->stats.gotcl;
-   ifp->if_imcasts = adapter->stats.mprc;
-   ifp->if_collisions = adapter->stats.colc;
-
-   /* Rx Errors */
-   ifp->if_ierrors =
-      adapter->dropped_pkts +
-      adapter->stats.rxerrc +
-      adapter->stats.crcerrs +
-      adapter->stats.algnerrc +
-      adapter->stats.rlec + adapter->stats.rnbc + 
-      adapter->stats.mpc + adapter->stats.cexterr;
-
-   /* Tx Errors */
-   ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol;
+	struct ifnet   *ifp;
+
+	adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS);
+	adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS);
+	adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC);
+	adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC);
+	adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL);
+	adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC);
+	adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL);
+	adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC);
+	adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC);
+	adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC);
+	adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC);
+	adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC);
+	adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC);
+	adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC);
+	adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC);
+	adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC);
+	adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64);
+	adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127);
+	adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255);
+	adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511);
+	adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023);
+	adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522);
+	adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC);
+	adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC);
+	adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC);
+	adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC);
+
+	/* For the 64-bit byte counters the low dword must be read first. */
+	/* Both registers clear on the read of the high dword */
+
+	adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL); 
+	adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH);
+	adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL);
+	adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH);
+
+	adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC);
+	adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC);
+	adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC);
+	adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC);
+	adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC);
+
+	adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL);
+	adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH);
+	adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL);
+	adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH);
+
+	adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR);
+	adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT);
+	adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64);
+	adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127);
+	adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255);
+	adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511);
+	adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023);
+	adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522);
+	adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC);
+	adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC);
+
+	if (adapter->hw.mac_type >= em_82543) {
+		adapter->stats.algnerrc += 
+		E1000_READ_REG(&adapter->hw, ALGNERRC);
+		adapter->stats.rxerrc += 
+		E1000_READ_REG(&adapter->hw, RXERRC);
+		adapter->stats.tncrs += 
+		E1000_READ_REG(&adapter->hw, TNCRS);
+		adapter->stats.cexterr += 
+		E1000_READ_REG(&adapter->hw, CEXTERR);
+		adapter->stats.tsctc += 
+		E1000_READ_REG(&adapter->hw, TSCTC);
+		adapter->stats.tsctfc += 
+		E1000_READ_REG(&adapter->hw, TSCTFC);
+	}
+	ifp = &adapter->interface_data.ac_if;
+
+	/* Fill out the OS statistics structure */
+	ifp->if_ipackets = adapter->stats.gprc;
+	ifp->if_opackets = adapter->stats.gptc;
+	ifp->if_ibytes = adapter->stats.gorcl;
+	ifp->if_obytes = adapter->stats.gotcl;
+	ifp->if_imcasts = adapter->stats.mprc;
+	ifp->if_collisions = adapter->stats.colc;
+
+	/* Rx Errors */
+	ifp->if_ierrors =
+	adapter->dropped_pkts +
+	adapter->stats.rxerrc +
+	adapter->stats.crcerrs +
+	adapter->stats.algnerrc +
+	adapter->stats.rlec + adapter->stats.rnbc + 
+	adapter->stats.mpc + adapter->stats.cexterr;
+
+	/* Tx Errors */
+	ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol;
 
 }
 
@@ -2114,42 +2214,67 @@ em_update_stats_counters(struct adapter * adapter)
  *
  **********************************************************************/
 static void
-em_print_hw_stats(struct adapter * adapter)
+em_print_hw_stats(struct adapter *adapter)
 {
-   int unit = adapter->unit;
+	int unit = adapter->unit;
 
 #ifdef DBG_STATS
-   printf("em%d: Packets not Avail = %ld\n", unit, adapter->no_pkts_avail);
-   printf("em%d: clean_tx_interrupts = %ld\n", unit, adapter->clean_tx_interrupts); 
+	printf("em%d: Packets not Avail = %ld\n", unit, 
+	       adapter->no_pkts_avail);
+	printf("em%d: CleanTxInterrupts = %ld\n", unit, 
+	       adapter->clean_tx_interrupts);
 #endif
-   
-   printf("em%d: Tx Descriptors not Avail = %ld\n", unit, adapter->no_tx_desc_avail);
-   printf("em%d: Tx Buffer not avail1 = %ld\n", unit, adapter->no_tx_buffer_avail1);
-   printf("em%d: Tx Buffer not avail2 = %ld\n", unit, adapter->no_tx_buffer_avail2);
-   printf("em%d: Std Mbuf Failed = %ld\n",unit, adapter->mbuf_alloc_failed);
-   printf("em%d: Std Cluster Failed = %ld\n",unit, adapter->mbuf_cluster_failed);
-   printf("em%d: Xmit Pullup = %ld\n",unit, adapter->xmit_pullup);
-
-   printf("em%d: Symbol errors = %lld\n", unit, adapter->stats.symerrs);
-   printf("em%d: Sequence errors = %lld\n", unit, adapter->stats.sec);
-   printf("em%d: Defer count = %lld\n", unit, adapter->stats.dc);
-
-   printf("em%d: Missed Packets = %lld\n", unit, adapter->stats.mpc);
-   printf("em%d: Receive No Buffers = %lld\n", unit, adapter->stats.rnbc);
-   printf("em%d: Receive length errors = %lld\n", unit, adapter->stats.rlec);
-   printf("em%d: Receive errors = %lld\n", unit, adapter->stats.rxerrc);
-   printf("em%d: Crc errors = %lld\n", unit, adapter->stats.crcerrs);
-   printf("em%d: Alignment errors = %lld\n", unit, adapter->stats.algnerrc);
-   printf("em%d: Carrier extension errors = %lld\n", unit, adapter->stats.cexterr);
-   printf("em%d: Driver dropped packets = %ld\n", unit, adapter->dropped_pkts);
-
-   printf("em%d: XON Rcvd = %lld\n", unit, adapter->stats.xonrxc);
-   printf("em%d: XON Xmtd = %lld\n", unit, adapter->stats.xontxc);
-   printf("em%d: XOFF Rcvd = %lld\n", unit, adapter->stats.xoffrxc);
-   printf("em%d: XOFF Xmtd = %lld\n", unit, adapter->stats.xofftxc);
-
-   printf("em%d: Good Packets Rcvd = %lld\n", unit, adapter->stats.gprc);
-   printf("em%d: Good Packets Xmtd = %lld\n", unit, adapter->stats.gptc);
+
+	printf("em%d: Tx Descriptors not Avail = %ld\n", unit, 
+	       adapter->no_tx_desc_avail);
+	printf("em%d: Tx Buffer not avail1 = %ld\n", unit, 
+	       adapter->no_tx_buffer_avail1);
+	printf("em%d: Tx Buffer not avail2 = %ld\n", unit, 
+	       adapter->no_tx_buffer_avail2);
+	printf("em%d: Std Mbuf Failed = %ld\n",unit, 
+	       adapter->mbuf_alloc_failed);
+	printf("em%d: Std Cluster Failed = %ld\n",unit, 
+	       adapter->mbuf_cluster_failed);
+
+	printf("em%d: Symbol errors = %lld\n", unit, 
+	       (long long)adapter->stats.symerrs);
+	printf("em%d: Sequence errors = %lld\n", unit, 
+	       (long long)adapter->stats.sec);
+	printf("em%d: Defer count = %lld\n", unit, 
+	       (long long)adapter->stats.dc);
+
+	printf("em%d: Missed Packets = %lld\n", unit, 
+	       (long long)adapter->stats.mpc);
+	printf("em%d: Receive No Buffers = %lld\n", unit, 
+	       (long long)adapter->stats.rnbc);
+	printf("em%d: Receive length errors = %lld\n", unit, 
+	       (long long)adapter->stats.rlec);
+	printf("em%d: Receive errors = %lld\n", unit, 
+	       (long long)adapter->stats.rxerrc);
+	printf("em%d: Crc errors = %lld\n", unit, 
+	       (long long)adapter->stats.crcerrs);
+	printf("em%d: Alignment errors = %lld\n", unit, 
+	       (long long)adapter->stats.algnerrc);
+	printf("em%d: Carrier extension errors = %lld\n", unit,
+	       (long long)adapter->stats.cexterr);
+	printf("em%d: Driver dropped packets = %ld\n", unit, 
+	       adapter->dropped_pkts);
+
+	printf("em%d: XON Rcvd = %lld\n", unit, 
+	       (long long)adapter->stats.xonrxc);
+	printf("em%d: XON Xmtd = %lld\n", unit, 
+	       (long long)adapter->stats.xontxc);
+	printf("em%d: XOFF Rcvd = %lld\n", unit, 
+	       (long long)adapter->stats.xoffrxc);
+	printf("em%d: XOFF Xmtd = %lld\n", unit, 
+	       (long long)adapter->stats.xofftxc);
+
+	printf("em%d: Good Packets Rcvd = %lld\n", unit,
+	       (long long)adapter->stats.gprc);
+	printf("em%d: Good Packets Xmtd = %lld\n", unit,
+	       (long long)adapter->stats.gptc);
+
+	return;
 }
 
 
@@ -2163,80 +2288,81 @@ em_print_hw_stats(struct adapter * adapter)
 static void
 em_clean_transmit_interrupts(struct adapter * adapter)
 {
-   struct em_tx_buffer *tx_buffer;
-   struct em_tx_desc   *tx_desc;
-   int             s;
-   struct ifnet   *ifp;
+	struct em_tx_buffer *tx_buffer;
+	struct em_tx_desc   *tx_desc;
+	int             s;
+	struct ifnet   *ifp;
 
-   s = splimp();
+	s = splimp();
 #ifdef DBG_STATS
-   adapter->clean_tx_interrupts++;
+	adapter->clean_tx_interrupts++;
 #endif
 
-   for (tx_buffer = STAILQ_FIRST(&adapter->used_tx_buffer_list);
-        tx_buffer; 
-        tx_buffer = STAILQ_FIRST(&adapter->used_tx_buffer_list)) {
-
-      /* 
-       * Get hold of the next descriptor that the em will report status
-       * back to (this will be the last descriptor of a given tx_buffer). We
-       * only want to free the tx_buffer (and it resources) if the driver is
-       * done with ALL of the descriptors.  If the driver is done with the
-       * last one then it is done with all of them.
-       */
-
-      tx_desc = adapter->oldest_used_tx_desc +
-         (tx_buffer->num_tx_desc_used - 1);
-
-      /* Check for wrap case */
-      if (tx_desc > adapter->last_tx_desc)
-         tx_desc -= adapter->num_tx_desc;
-
-
-      /* 
-       * If the descriptor done bit is set free tx_buffer and associated
-       * resources
-       */
-      if (tx_desc->upper.fields.status &
-         E1000_TXD_STAT_DD) {
-
-         STAILQ_REMOVE_HEAD(&adapter->used_tx_buffer_list, em_tx_entry);
-
-         if ((tx_desc == adapter->last_tx_desc))
-            adapter->oldest_used_tx_desc =
-               adapter->first_tx_desc;
-         else
-            adapter->oldest_used_tx_desc = (tx_desc + 1);
-
-         /* Make available the descriptors that were previously used */
-         adapter->num_tx_desc_avail +=
-            tx_buffer->num_tx_desc_used;
-
-         tx_buffer->num_tx_desc_used = 0;
-
-         if (tx_buffer->m_head) {
-            m_freem(tx_buffer->m_head);
-            tx_buffer->m_head = NULL;
-         }
-         /* Return this "Software packet" back to the "free" list */
-         STAILQ_INSERT_TAIL(&adapter->free_tx_buffer_list, tx_buffer, em_tx_entry);
-      } else {
-         /* 
-          * Found a tx_buffer that the em is not done with then there is
-          * no reason to check the rest of the queue.
-          */
-         break;
-      }
-   }                     /* end for each tx_buffer */
-
-   ifp = &adapter->interface_data.ac_if;
-
-   /* Tell the stack that it is OK to send packets */
-   if (adapter->num_tx_desc_avail > TX_CLEANUP_THRESHOLD) {
-      ifp->if_timer = 0;
-      ifp->if_flags &= ~IFF_OACTIVE;
-   }
-   splx(s);
-   return;
+	for (tx_buffer = STAILQ_FIRST(&adapter->used_tx_buffer_list);
+	    tx_buffer; 
+	    tx_buffer = STAILQ_FIRST(&adapter->used_tx_buffer_list)) {
+
+		/* 
+		 * Get hold of the next descriptor that the em will report status
+		 * back to (this will be the last descriptor of a given tx_buffer). We
+		 * only want to free the tx_buffer (and it resources) if the driver is
+		 * done with ALL of the descriptors.  If the driver is done with the
+		 * last one then it is done with all of them.
+		 */
+
+		tx_desc = adapter->oldest_used_tx_desc +
+			  (tx_buffer->num_tx_desc_used - 1);
+
+		/* Check for wrap case */
+		if (tx_desc > adapter->last_tx_desc)
+			tx_desc -= adapter->num_tx_desc;
+
+
+		/* 
+		 * If the descriptor done bit is set free tx_buffer and associated
+		 * resources
+		 */
+		if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
+
+			STAILQ_REMOVE_HEAD(&adapter->used_tx_buffer_list, 
+					   em_tx_entry);
+
+			if ((tx_desc == adapter->last_tx_desc))
+				adapter->oldest_used_tx_desc =
+				adapter->first_tx_desc;
+			else
+				adapter->oldest_used_tx_desc = (tx_desc + 1);
+
+			/* Make available the descriptors that were previously used */
+			adapter->num_tx_desc_avail +=
+			tx_buffer->num_tx_desc_used;
+
+			tx_buffer->num_tx_desc_used = 0;
+
+			if (tx_buffer->m_head) {
+				m_freem(tx_buffer->m_head);
+				tx_buffer->m_head = NULL;
+			}
+			/* Return this "Software packet" back to the "free" list */
+			STAILQ_INSERT_TAIL(&adapter->free_tx_buffer_list, 
+					   tx_buffer, em_tx_entry);
+		} else {
+			/* 
+			 * Found a tx_buffer that the em is not done with then there is
+			 * no reason to check the rest of the queue.
+			 */
+			break;
+		}
+	}		      /* end for each tx_buffer */
+
+	ifp = &adapter->interface_data.ac_if;
+
+	/* Tell the stack that it is OK to send packets */
+	if (adapter->num_tx_desc_avail > TX_CLEANUP_THRESHOLD) {
+		ifp->if_timer = 0;
+		ifp->if_flags &= ~IFF_OACTIVE;
+	}
+	splx(s);
+	return;
 }
 
diff --git a/sys/dev/em/if_em.h b/sys/dev/em/if_em.h
index f3859bd..3dc8b44 100644
--- a/sys/dev/em/if_em.h
+++ b/sys/dev/em/if_em.h
@@ -46,14 +46,17 @@ SUCH DAMAGE.
 #include <sys/socket.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
+#include <sys/sockio.h>
 
 #include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
+
 #include <net/bpf.h>
-#include <net/ethernet.h>
-#include <net/if_arp.h>
-#include <sys/sockio.h>
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
 
 #include <netinet/in_systm.h>
 #include <netinet/in.h>
@@ -72,8 +75,7 @@ SUCH DAMAGE.
 #include <pci/pcireg.h>
 #include "opt_bdg.h"
 
-#include <dev/em/if_em_fxhw.h>
-#include <dev/em/if_em_phy.h>
+#include <dev/em/if_em_hw.h>
 
 /* Tunables */
 #define MAX_TXD                         256
@@ -103,6 +105,7 @@ SUCH DAMAGE.
 #define MAX_NUM_MULTICAST_ADDRESSES     128
 #define PCI_ANY_ID                      (~0U)
 #define ETHER_ALIGN                     2
+#define QTAG_TYPE                       0x8100
 
 /* Defines for printing debug information */
 #define DEBUG_INIT  0
@@ -127,8 +130,8 @@ SUCH DAMAGE.
 #define EM_RXBUFFER_16384      16384
 
 #ifdef __alpha__
-#undef vtophys
-#define vtophys(va)     alpha_XXX_dmamap((vm_offset_t)(va))
+	#undef vtophys
+	#define vtophys(va)     alpha_XXX_dmamap((vm_offset_t)(va))
 #endif /* __alpha__ */
 
 /* ******************************************************************************
@@ -140,18 +143,18 @@ SUCH DAMAGE.
  * ******************************************************************************/
 typedef struct _em_vendor_info_t
 {
-        unsigned int vendor_id;
-        unsigned int device_id;
-        unsigned int subvendor_id;
-        unsigned int subdevice_id;
-        unsigned int index;
+	unsigned int vendor_id;
+	unsigned int device_id;
+	unsigned int subvendor_id;
+	unsigned int subdevice_id;
+	unsigned int index;
 } em_vendor_info_t;
 
 
 struct em_tx_buffer {
-        STAILQ_ENTRY(em_tx_buffer) em_tx_entry;
-        struct mbuf    *m_head;
-        u_int32_t       num_tx_desc_used;
+	STAILQ_ENTRY(em_tx_buffer) em_tx_entry;
+	struct mbuf    *m_head;
+	u_int32_t       num_tx_desc_used;
 };
 
 
@@ -160,88 +163,88 @@ struct em_tx_buffer {
  * into which the E1000 DMA's frames. 
  * ******************************************************************************/
 struct em_rx_buffer {
-        STAILQ_ENTRY(em_rx_buffer) em_rx_entry;
-        struct mbuf    *m_head;
-        u_int64_t      buffer_addr;
+	STAILQ_ENTRY(em_rx_buffer) em_rx_entry;
+	struct mbuf    *m_head;
+	u_int64_t      buffer_addr;
 };
 
 typedef enum _XSUM_CONTEXT_T {
-        OFFLOAD_NONE,
-        OFFLOAD_TCP_IP,
-        OFFLOAD_UDP_IP
+	OFFLOAD_NONE,
+	OFFLOAD_TCP_IP,
+	OFFLOAD_UDP_IP
 } XSUM_CONTEXT_T;
 
 /* Our adapter structure */
 struct adapter {
-        struct arpcom   interface_data;
-        struct adapter *next;
-        struct adapter *prev;
-        struct em_shared_adapter shared;
-
-        /* FreeBSD operating-system-specific structures */
-        struct em_osdep osdep;
-        struct device   *dev;
-        struct resource *res_memory;
-        struct resource *res_interrupt;
-        void            *int_handler_tag;
-        struct ifmedia  media;
-        struct callout_handle timer_handle;
-        u_int8_t        unit;
-
-        /* Info about the board itself */
-        u_int32_t       part_num;
-        u_int8_t        link_active;
-        u_int16_t       link_speed;
-        u_int16_t       link_duplex;
-        u_int32_t       tx_int_delay;
-        u_int32_t       rx_int_delay;
-
-        u_int8_t        rx_checksum;
-        XSUM_CONTEXT_T  active_checksum_context;
-
-        /* Transmit definitions */
-        struct em_tx_desc *first_tx_desc;
-        struct em_tx_desc *last_tx_desc;
-        struct em_tx_desc *next_avail_tx_desc;
-        struct em_tx_desc *oldest_used_tx_desc;
-        struct em_tx_desc *tx_desc_base;
-        volatile u_int16_t num_tx_desc_avail;
-        u_int16_t       num_tx_desc;
-        u_int32_t       txd_cmd;
-        struct em_tx_buffer   *tx_buffer_area;
-        STAILQ_HEAD(__em_tx_buffer_free, em_tx_buffer)  free_tx_buffer_list;
-        STAILQ_HEAD(__em_tx_buffer_used, em_tx_buffer)  used_tx_buffer_list;
-
-        /* Receive definitions */
-        struct em_rx_desc *first_rx_desc;
-        struct em_rx_desc *last_rx_desc;
-        struct em_rx_desc *next_rx_desc_to_check;
-        struct em_rx_desc *rx_desc_base;
-        u_int16_t       num_rx_desc;
-        u_int32_t       rx_buffer_len;
-        struct em_rx_buffer   *rx_buffer_area;
-        STAILQ_HEAD(__em_rx_buffer, em_rx_buffer)  rx_buffer_list;
-
-        /* Jumbo frame */
-        struct mbuf     *fmp;
-        struct mbuf     *lmp;
-
-
-        /* Misc stats maintained by the driver */
-        unsigned long   dropped_pkts;
-        unsigned long   mbuf_alloc_failed;
-        unsigned long   mbuf_cluster_failed;
-        unsigned long   xmit_pullup;
-        unsigned long   no_tx_desc_avail;
-        unsigned long   no_tx_buffer_avail1;
-        unsigned long   no_tx_buffer_avail2;
-#ifdef DBG_STATS 
-        unsigned long   no_pkts_avail;
-        unsigned long   clean_tx_interrupts;
+	struct arpcom   interface_data;
+	struct adapter *next;
+	struct adapter *prev;
+	struct em_hw    hw;
+
+	/* FreeBSD operating-system-specific structures */
+	struct em_osdep osdep;
+	struct device   *dev;
+	struct resource *res_memory;
+	struct resource *res_interrupt;
+	void            *int_handler_tag;
+	struct ifmedia  media;
+	struct callout_handle timer_handle;
+	u_int8_t        unit;
+
+	/* Info about the board itself */
+	u_int32_t       part_num;
+	u_int8_t        link_active;
+	u_int16_t       link_speed;
+	u_int16_t       link_duplex;
+	u_int32_t       tx_int_delay;
+	u_int32_t       rx_int_delay;
+
+	u_int8_t        rx_checksum;
+	XSUM_CONTEXT_T  active_checksum_context;
+
+	/* Transmit definitions */
+	struct em_tx_desc *first_tx_desc;
+	struct em_tx_desc *last_tx_desc;
+	struct em_tx_desc *next_avail_tx_desc;
+	struct em_tx_desc *oldest_used_tx_desc;
+	struct em_tx_desc *tx_desc_base;
+	volatile u_int16_t num_tx_desc_avail;
+	u_int16_t       num_tx_desc;
+	u_int32_t       txd_cmd;
+	struct em_tx_buffer   *tx_buffer_area;
+	STAILQ_HEAD(__em_tx_buffer_free, em_tx_buffer)  free_tx_buffer_list;
+	STAILQ_HEAD(__em_tx_buffer_used, em_tx_buffer)  used_tx_buffer_list;
+
+	/* Receive definitions */
+	struct em_rx_desc *first_rx_desc;
+	struct em_rx_desc *last_rx_desc;
+	struct em_rx_desc *next_rx_desc_to_check;
+	struct em_rx_desc *rx_desc_base;
+	u_int16_t       num_rx_desc;
+	u_int32_t       rx_buffer_len;
+	struct em_rx_buffer   *rx_buffer_area;
+	STAILQ_HEAD(__em_rx_buffer, em_rx_buffer)  rx_buffer_list;
+
+	/* Jumbo frame */
+	struct mbuf     *fmp;
+	struct mbuf     *lmp;
+
+
+	/* Misc stats maintained by the driver */
+	unsigned long   dropped_pkts;
+	unsigned long   mbuf_alloc_failed;
+	unsigned long   mbuf_cluster_failed;
+	unsigned long   xmit_pullup;
+	unsigned long   no_tx_desc_avail;
+	unsigned long   no_tx_buffer_avail1;
+	unsigned long   no_tx_buffer_avail2;
+#ifdef DBG_STATS
+	unsigned long   no_pkts_avail;
+	unsigned long   clean_tx_interrupts;
 
 #endif
 
-        struct em_shared_stats stats;
+	struct em_hw_stats stats;
 };
 
 #endif                                                  /* _EM_H_DEFINED_ */
diff --git a/sys/dev/em/if_em_hw.c b/sys/dev/em/if_em_hw.c
new file mode 100644
index 0000000..17135f1
--- /dev/null
+++ b/sys/dev/em/if_em_hw.c
@@ -0,0 +1,3281 @@
+/*******************************************************************************
+
+  Copyright (c) 2001-2002 Intel Corporation 
+  All rights reserved. 
+  
+  Redistribution and use in source and binary forms of the Software, with or 
+  without modification, are permitted provided that the following conditions 
+  are met: 
+  
+   1. Redistributions of source code of the Software may retain the above 
+      copyright notice, this list of conditions and the following disclaimer.
+   
+   2. Redistributions in binary form of the Software may reproduce the above 
+      copyright notice, this list of conditions and the following disclaimer 
+      in the documentation and/or other materials provided with the 
+      distribution. 
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors shall be used to endorse or promote products derived from 
+      this Software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS CONTRIBUTORS BE LIABLE 
+  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
+  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+  SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*$FreeBSD$*/
+/* if_em_hw.c
+ * Shared functions for accessing and configuring the MAC
+ */
+
+#include <dev/em/if_em_hw.h>
+
+static int32_t em_setup_fiber_link(struct em_hw *hw);
+static int32_t em_setup_copper_link(struct em_hw *hw);
+static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
+static int32_t em_config_mac_to_phy(struct em_hw *hw);
+static int32_t em_force_mac_fc(struct em_hw *hw);
+static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
+static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
+static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count);
+static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
+static int32_t em_phy_reset_dsp(struct em_hw *hw);
+static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
+static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
+static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count);
+static uint16_t em_shift_in_ee_bits(struct em_hw *hw);
+static void em_setup_eeprom(struct em_hw *hw);
+static void em_standby_eeprom(struct em_hw *hw);
+static int32_t em_id_led_init(struct em_hw * hw);
+
+/******************************************************************************
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+em_reset_hw(struct em_hw *hw)
+{
+    uint32_t ctrl;
+    uint32_t ctrl_ext;
+    uint32_t icr;
+    uint32_t manc;
+    uint16_t pci_cmd_word;
+
+    DEBUGFUNC("em_reset_hw");
+    
+    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
+    if(hw->mac_type == em_82542_rev2_0) {
+        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
+            DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+            pci_cmd_word = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
+            em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &pci_cmd_word);
+        }
+    }
+
+    /* Clear interrupt mask to stop board from generating interrupts */
+    DEBUGOUT("Masking off all interrupts\n");
+    E1000_WRITE_REG(hw, IMC, 0xffffffff);
+
+    /* Disable the Transmit and Receive units.  Then delay to allow
+     * any pending transactions to complete before we hit the MAC with
+     * the global reset.
+     */
+    E1000_WRITE_REG(hw, RCTL, 0);
+    E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
+
+    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
+    hw->tbi_compatibility_on = FALSE;
+
+    /* Delay to allow any outstanding PCI transactions to complete before
+     * resetting the device
+     */ 
+    msec_delay(10);
+
+    /* Issue a global reset to the MAC.  This will reset the chip's
+     * transmit, receive, DMA, and link units.  It will not effect
+     * the current PCI configuration.  The global reset bit is self-
+     * clearing, and should clear within a microsecond.
+     */
+    DEBUGOUT("Issuing a global reset to MAC\n");
+    ctrl = E1000_READ_REG(hw, CTRL);
+    E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
+
+    /* Force a reload from the EEPROM if necessary */
+    if(hw->mac_type < em_82540) {
+        /* Wait for reset to complete */
+        usec_delay(10);
+        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+        ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+        /* Wait for EEPROM reload */
+        msec_delay(2);
+    } else {
+        /* Wait for EEPROM reload (it happens automatically) */
+        msec_delay(4);
+        /* Dissable HW ARPs on ASF enabled adapters */
+        manc = E1000_READ_REG(hw, MANC);
+        manc &= ~(E1000_MANC_ARP_EN);
+        E1000_WRITE_REG(hw, MANC, manc);
+    }
+    
+    /* Clear interrupt mask to stop board from generating interrupts */
+    DEBUGOUT("Masking off all interrupts\n");
+    E1000_WRITE_REG(hw, IMC, 0xffffffff);
+
+    /* Clear any pending interrupt events. */
+    icr = E1000_READ_REG(hw, ICR);
+
+    /* If MWI was previously enabled, reenable it. */
+    if(hw->mac_type == em_82542_rev2_0) {
+        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
+            em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->pci_cmd_word);
+    }
+}
+
+/******************************************************************************
+ * Performs basic configuration of the adapter.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * 
+ * Assumes that the controller has previously been reset and is in a 
+ * post-reset uninitialized state. Initializes the receive address registers,
+ * multicast table, and VLAN filter table. Calls routines to setup link
+ * configuration and flow control settings. Clears all on-chip counters. Leaves
+ * the transmit and receive units disabled and uninitialized.
+ *****************************************************************************/
+int32_t
+em_init_hw(struct em_hw *hw)
+{
+    uint32_t ctrl, status;
+    uint32_t i;
+    int32_t ret_val;
+    uint16_t pci_cmd_word;
+
+    DEBUGFUNC("em_init_hw");
+
+    /* Initialize Identification LED */
+    ret_val = em_id_led_init(hw);
+    if(ret_val < 0) {
+	DEBUGOUT("Error Initializing Identification LED\n");
+	return ret_val;
+    }
+    
+    /* Set the Media Type and exit with error if it is not valid. */
+    if(hw->mac_type != em_82543) {
+        /* tbi_compatibility is only valid on 82543 */
+        hw->tbi_compatibility_en = FALSE;
+    }
+
+    if(hw->mac_type >= em_82543) {
+        status = E1000_READ_REG(hw, STATUS);
+        if(status & E1000_STATUS_TBIMODE) {
+            hw->media_type = em_media_type_fiber;
+            /* tbi_compatibility not valid on fiber */
+            hw->tbi_compatibility_en = FALSE;
+        } else {
+            hw->media_type = em_media_type_copper;
+        }
+    } else {
+        /* This is an 82542 (fiber only) */
+        hw->media_type = em_media_type_fiber;
+    }
+
+    /* Disabling VLAN filtering. */
+    DEBUGOUT("Initializing the IEEE VLAN\n");
+    E1000_WRITE_REG(hw, VET, 0);
+
+    em_clear_vfta(hw);
+
+    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
+    if(hw->mac_type == em_82542_rev2_0) {
+        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
+            DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+            pci_cmd_word = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
+            em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &pci_cmd_word);
+        }
+        E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
+        msec_delay(5);
+    }
+
+    /* Setup the receive address. This involves initializing all of the Receive
+     * Address Registers (RARs 0 - 15).
+     */
+    em_init_rx_addrs(hw);
+
+    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
+    if(hw->mac_type == em_82542_rev2_0) {
+        E1000_WRITE_REG(hw, RCTL, 0);
+        msec_delay(1);
+        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
+            em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->pci_cmd_word);
+    }
+
+    /* Zero out the Multicast HASH table */
+    DEBUGOUT("Zeroing the MTA\n");
+    for(i = 0; i < E1000_MC_TBL_SIZE; i++)
+        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
+
+    /* Set the PCI priority bit correctly in the CTRL register.  This
+     * determines if the adapter gives priority to receives, or if it
+     * gives equal priority to transmits and receives.
+     */
+    if(hw->dma_fairness) {
+        ctrl = E1000_READ_REG(hw, CTRL);
+        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
+    }
+
+    /* Call a subroutine to configure the link and setup flow control. */
+    ret_val = em_setup_link(hw);
+
+    /* Clear all of the statistics registers (clear on read).  It is
+     * important that we do this after we have tried to establish link
+     * because the symbol error count will increment wildly if there
+     * is no link.
+     */
+    em_clear_hw_cntrs(hw);
+
+    return ret_val;
+}
+
+/******************************************************************************
+ * Configures flow control and link settings.
+ * 
+ * hw - Struct containing variables accessed by shared code
+ * 
+ * Determines which flow control settings to use. Calls the apropriate media-
+ * specific link configuration function. Configures the flow control settings.
+ * Assuming the adapter has a valid link partner, a valid link should be
+ * established. Assumes the hardware has previously been reset and the 
+ * transmitter and receiver are not enabled.
+ *****************************************************************************/
+int32_t
+em_setup_link(struct em_hw *hw)
+{
+    uint32_t ctrl_ext;
+    int32_t ret_val;
+    uint16_t eeprom_data;
+
+    DEBUGFUNC("em_setup_link");
+
+    /* Read and store word 0x0F of the EEPROM. This word contains bits
+     * that determine the hardware's default PAUSE (flow control) mode,
+     * a bit that determines whether the HW defaults to enabling or
+     * disabling auto-negotiation, and the direction of the
+     * SW defined pins. If there is no SW over-ride of the flow
+     * control setting, then the variable hw->fc will
+     * be initialized based on a value in the EEPROM.
+     */
+    if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
+        DEBUGOUT("EEPROM Read Error\n");
+        return -E1000_ERR_EEPROM;
+    }
+
+    if(hw->fc == em_fc_default) {
+        if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
+            hw->fc = em_fc_none;
+        else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
+                EEPROM_WORD0F_ASM_DIR)
+            hw->fc = em_fc_tx_pause;
+        else
+            hw->fc = em_fc_full;
+    }
+
+    /* We want to save off the original Flow Control configuration just
+     * in case we get disconnected and then reconnected into a different
+     * hub or switch with different Flow Control capabilities.
+     */
+    if(hw->mac_type == em_82542_rev2_0)
+        hw->fc &= (~em_fc_tx_pause);
+
+    if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
+        hw->fc &= (~em_fc_rx_pause);
+
+    hw->original_fc = hw->fc;
+
+    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
+
+    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
+     * polarity value for the SW controlled pins, and setup the
+     * Extended Device Control reg with that info.
+     * This is needed because one of the SW controlled pins is used for
+     * signal detection.  So this should be done before em_setup_pcs_link()
+     * or em_phy_setup() is called.
+     */
+    if(hw->mac_type == em_82543) {
+        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
+                    SWDPIO__EXT_SHIFT);
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+    }
+
+    /* Call the necessary subroutine to configure the link. */
+    ret_val = (hw->media_type == em_media_type_fiber) ?
+              em_setup_fiber_link(hw) :
+              em_setup_copper_link(hw);
+
+    /* Initialize the flow control address, type, and PAUSE timer
+     * registers to their default values.  This is done even if flow
+     * control is disabled, because it does not hurt anything to
+     * initialize these registers.
+     */
+    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
+
+    E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
+    E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
+    E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
+    E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
+
+    /* Set the flow control receive threshold registers.  Normally,
+     * these registers will be set to a default threshold that may be
+     * adjusted later by the driver's runtime code.  However, if the
+     * ability to transmit pause frames in not enabled, then these
+     * registers will be set to 0. 
+     */
+    if(!(hw->fc & em_fc_tx_pause)) {
+        E1000_WRITE_REG(hw, FCRTL, 0);
+        E1000_WRITE_REG(hw, FCRTH, 0);
+    } else {
+        /* We need to set up the Receive Threshold high and low water marks
+         * as well as (optionally) enabling the transmission of XON frames.
+         */
+        if(hw->fc_send_xon) {
+            E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
+            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
+        } else {
+            E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
+            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
+        }
+    }
+    return ret_val;
+}
+
+/******************************************************************************
+ * Sets up link for a fiber based adapter
+ *
+ * hw - Struct containing variables accessed by shared code
+ * ctrl - Current value of the device control register
+ *
+ * Manipulates Physical Coding Sublayer functions in order to configure
+ * link. Assumes the hardware has been previously reset and the transmitter
+ * and receiver are not enabled.
+ *****************************************************************************/
+static int32_t 
+em_setup_fiber_link(struct em_hw *hw)
+{
+    uint32_t ctrl;
+    uint32_t status;
+    uint32_t txcw = 0;
+    uint32_t i;
+    uint32_t signal;
+    int32_t ret_val;
+
+    DEBUGFUNC("em_setup_fiber_link");
+
+    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
+     * set when the optics detect a signal. On older adapters, it will be 
+     * cleared when there is a signal
+     */
+    ctrl = E1000_READ_REG(hw, CTRL);
+    if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
+    else signal = 0;
+   
+    /* Take the link out of reset */
+    ctrl &= ~(E1000_CTRL_LRST);
+    
+    em_config_collision_dist(hw);
+
+    /* Check for a software override of the flow control settings, and setup
+     * the device accordingly.  If auto-negotiation is enabled, then software
+     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
+     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
+     * auto-negotiation is disabled, then software will have to manually 
+     * configure the two flow control enable bits in the CTRL register.
+     *
+     * The possible values of the "fc" parameter are:
+     *      0:  Flow control is completely disabled
+     *      1:  Rx flow control is enabled (we can receive pause frames, but 
+     *          not send pause frames).
+     *      2:  Tx flow control is enabled (we can send pause frames but we do
+     *          not support receiving pause frames).
+     *      3:  Both Rx and TX flow control (symmetric) are enabled.
+     */
+    switch (hw->fc) {
+    case em_fc_none:
+        /* Flow control is completely disabled by a software over-ride. */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
+        break;
+    case em_fc_rx_pause:
+        /* RX Flow control is enabled and TX Flow control is disabled by a 
+         * software over-ride. Since there really isn't a way to advertise 
+         * that we are capable of RX Pause ONLY, we will advertise that we
+         * support both symmetric and asymmetric RX PAUSE. Later, we will
+         *  disable the adapter's ability to send PAUSE frames.
+         */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+        break;
+    case em_fc_tx_pause:
+        /* TX Flow control is enabled, and RX Flow control is disabled, by a 
+         * software over-ride.
+         */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
+        break;
+    case em_fc_full:
+        /* Flow control (both RX and TX) is enabled by a software over-ride. */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+        break;
+    default:
+        DEBUGOUT("Flow control param set incorrectly\n");
+        return -E1000_ERR_CONFIG;
+        break;
+    }
+
+    /* Since auto-negotiation is enabled, take the link out of reset (the link
+     * will be in reset, because we previously reset the chip). This will
+     * restart auto-negotiation.  If auto-neogtiation is successful then the
+     * link-up status bit will be set and the flow control enable bits (RFCE
+     * and TFCE) will be set according to their negotiated value.
+     */
+    DEBUGOUT("Auto-negotiation enabled\n");
+
+    E1000_WRITE_REG(hw, TXCW, txcw);
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+
+    hw->txcw = txcw;
+    msec_delay(1);
+
+    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
+     * indication in the Device Status Register.  Time-out if a link isn't 
+     * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
+     * less than 500 milliseconds even if the other end is doing it in SW).
+     */
+    if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
+        DEBUGOUT("Looking for Link\n");
+        for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
+            msec_delay(10);
+            status = E1000_READ_REG(hw, STATUS);
+            if(status & E1000_STATUS_LU) break;
+        }
+        if(i == (LINK_UP_TIMEOUT / 10)) {
+            /* AutoNeg failed to achieve a link, so we'll call 
+             * em_check_for_link. This routine will force the link up if we
+             * detect a signal. This will allow us to communicate with
+             * non-autonegotiating link partners.
+             */
+            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
+            hw->autoneg_failed = 1;
+            ret_val = em_check_for_link(hw);
+            if(ret_val < 0) {
+                DEBUGOUT("Error while checking for link\n");
+                return ret_val;
+            }
+            hw->autoneg_failed = 0;
+        } else {
+            hw->autoneg_failed = 0;
+            DEBUGOUT("Valid Link Found\n");
+        }
+    } else {
+        DEBUGOUT("No Signal Detected\n");
+    }
+    return 0;
+}
+
+/******************************************************************************
+* Detects which PHY is present and the speed and duplex
+*
+* hw - Struct containing variables accessed by shared code
+* ctrl - current value of the device control register
+******************************************************************************/
+static int32_t 
+em_setup_copper_link(struct em_hw *hw)
+{
+    uint32_t ctrl;
+    int32_t ret_val;
+    uint16_t i;
+    uint16_t phy_data;
+
+    DEBUGFUNC("em_setup_copper_link");
+
+    ctrl = E1000_READ_REG(hw, CTRL);
+    /* With 82543, we need to force speed and duplex on the MAC equal to what
+     * the PHY speed and duplex configuration is. In addition, we need to
+     * perform a hardware reset on the PHY to take it out of reset.
+     */
+    if(hw->mac_type > em_82543) {
+        ctrl |= E1000_CTRL_SLU;
+        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+    } else {
+        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        em_phy_hw_reset(hw);
+    }
+
+    /* Make sure we have a valid PHY */
+    ret_val = em_detect_gig_phy(hw);
+    if(ret_val < 0) {
+        DEBUGOUT("Error, did not detect valid phy.\n");
+        return ret_val;
+    }
+    DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
+
+    /* Enable CRS on TX. This must be set for half-duplex operation. */
+    if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+
+    /* Options:
+     *   MDI/MDI-X = 0 (default)
+     *   0 - Auto for all speeds
+     *   1 - MDI mode
+     *   2 - MDI-X mode
+     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+     */
+    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+
+    switch (hw->mdix) {
+    case 1:
+        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
+        break;
+    case 2:
+        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
+        break;
+    case 3:
+        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
+        break;
+    case 0:
+    default:
+        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
+        break;
+    }
+
+    /* Options:
+     *   disable_polarity_correction = 0 (default)
+     *       Automatic Correction for Reversed Cable Polarity
+     *   0 - Disabled
+     *   1 - Enabled
+     */
+    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
+    if(hw->disable_polarity_correction == 1)
+        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
+    if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    /* Force TX_CLK in the Extended PHY Specific Control Register
+     * to 25MHz clock.
+     */
+    if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    phy_data |= M88E1000_EPSCR_TX_CLK_25;
+    /* Configure Master and Slave downshift values */
+    phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
+                  M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+    phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
+                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+    if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    /* SW Reset the PHY so all changes take effect */
+    ret_val = em_phy_reset(hw);
+    if(ret_val < 0) {
+        DEBUGOUT("Error Resetting the PHY\n");
+        return ret_val;
+    }
+    
+    /* Options:
+     *   autoneg = 1 (default)
+     *      PHY will advertise value(s) parsed from
+     *      autoneg_advertised and fc
+     *   autoneg = 0
+     *      PHY will be set to 10H, 10F, 100H, or 100F
+     *      depending on value parsed from forced_speed_duplex.
+     */
+
+    /* Is autoneg enabled?  This is enabled by default or by software override.
+     * If so, call em_phy_setup_autoneg routine to parse the
+     * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
+     * user should have provided a speed/duplex override.  If so, then call
+     * em_phy_force_speed_duplex to parse and set this up.
+     */
+    if(hw->autoneg) {
+        /* Perform some bounds checking on the hw->autoneg_advertised
+         * parameter.  If this variable is zero, then set it to the default.
+         */
+        hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+        /* If autoneg_advertised is zero, we assume it was not defaulted
+         * by the calling code so we set to advertise full capability.
+         */
+        if(hw->autoneg_advertised == 0)
+            hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+        DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
+        ret_val = em_phy_setup_autoneg(hw);
+        if(ret_val < 0) {
+            DEBUGOUT("Error Setting up Auto-Negotiation\n");
+            return ret_val;
+        }
+        DEBUGOUT("Restarting Auto-Neg\n");
+
+        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
+         * the Auto Neg Restart bit in the PHY control register.
+         */
+        if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
+            DEBUGOUT("PHY Read Error\n");
+            return -E1000_ERR_PHY;
+        }
+        phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
+        if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
+            DEBUGOUT("PHY Write Error\n");
+            return -E1000_ERR_PHY;
+        }
+
+        /* Does the user want to wait for Auto-Neg to complete here, or
+         * check at a later time (for example, callback routine).
+         */
+        if(hw->wait_autoneg_complete) {
+            ret_val = em_wait_autoneg(hw);
+            if(ret_val < 0) {
+                DEBUGOUT("Error while waiting for autoneg to complete\n");
+                return ret_val;
+            }
+        }
+    } else {
+        DEBUGOUT("Forcing speed and duplex\n");
+        ret_val = em_phy_force_speed_duplex(hw);
+        if(ret_val < 0) {
+            DEBUGOUT("Error Forcing Speed and Duplex\n");
+            return ret_val;
+        }
+    }
+
+    /* Check link status. Wait up to 100 microseconds for link to become
+     * valid.
+     */
+    for(i = 0; i < 10; i++) {
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
+            DEBUGOUT("PHY Read Error\n");
+            return -E1000_ERR_PHY;
+        }
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
+            DEBUGOUT("PHY Read Error\n");
+            return -E1000_ERR_PHY;
+        }
+        if(phy_data & MII_SR_LINK_STATUS) {
+            /* We have link, so we need to finish the config process:
+             *   1) Set up the MAC to the current PHY speed/duplex
+             *      if we are on 82543.  If we
+             *      are on newer silicon, we only need to configure
+             *      collision distance in the Transmit Control Register.
+             *   2) Set up flow control on the MAC to that established with
+             *      the link partner.
+             */
+            if(hw->mac_type >= em_82544) {
+                em_config_collision_dist(hw);
+            } else {
+                ret_val = em_config_mac_to_phy(hw);
+                if(ret_val < 0) {
+                    DEBUGOUT("Error configuring MAC to PHY settings\n");
+                    return ret_val;
+                  }
+            }
+            ret_val = em_config_fc_after_link_up(hw);
+            if(ret_val < 0) {
+                DEBUGOUT("Error Configuring Flow Control\n");
+                return ret_val;
+            }
+            DEBUGOUT("Valid link established!!!\n");
+            return 0;
+        }
+        usec_delay(10);
+    }
+
+    DEBUGOUT("Unable to establish link!!!\n");
+    return 0;
+}
+
+/******************************************************************************
+* Configures PHY autoneg and flow control advertisement settings
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+int32_t
+em_phy_setup_autoneg(struct em_hw *hw)
+{
+    uint16_t mii_autoneg_adv_reg;
+    uint16_t mii_1000t_ctrl_reg;
+
+    DEBUGFUNC("em_phy_setup_autoneg");
+
+    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
+    if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    /* Read the MII 1000Base-T Control Register (Address 9). */
+    if(em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    /* Need to parse both autoneg_advertised and fc and set up
+     * the appropriate PHY registers.  First we will parse for
+     * autoneg_advertised software override.  Since we can advertise
+     * a plethora of combinations, we need to check each bit
+     * individually.
+     */
+
+    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
+     * Advertisement Register (Address 4) and the 1000 mb speed bits in
+     * the  1000Base-T Control Register (Address 9).
+     */
+    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
+    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
+
+    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
+
+    /* Do we want to advertise 10 Mb Half Duplex? */
+    if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
+        DEBUGOUT("Advertise 10mb Half duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
+    }
+
+    /* Do we want to advertise 10 Mb Full Duplex? */
+    if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
+        DEBUGOUT("Advertise 10mb Full duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
+    }
+
+    /* Do we want to advertise 100 Mb Half Duplex? */
+    if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
+        DEBUGOUT("Advertise 100mb Half duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
+    }
+
+    /* Do we want to advertise 100 Mb Full Duplex? */
+    if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
+        DEBUGOUT("Advertise 100mb Full duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
+    }
+
+    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
+    if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
+        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
+    }
+
+    /* Do we want to advertise 1000 Mb Full Duplex? */
+    if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
+        DEBUGOUT("Advertise 1000mb Full duplex\n");
+        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
+    }
+
+    /* Check for a software override of the flow control settings, and
+     * setup the PHY advertisement registers accordingly.  If
+     * auto-negotiation is enabled, then software will have to set the
+     * "PAUSE" bits to the correct value in the Auto-Negotiation
+     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
+     *
+     * The possible values of the "fc" parameter are:
+     *      0:  Flow control is completely disabled
+     *      1:  Rx flow control is enabled (we can receive pause frames
+     *          but not send pause frames).
+     *      2:  Tx flow control is enabled (we can send pause frames
+     *          but we do not support receiving pause frames).
+     *      3:  Both Rx and TX flow control (symmetric) are enabled.
+     *  other:  No software override.  The flow control configuration
+     *          in the EEPROM is used.
+     */
+    switch (hw->fc) {
+    case em_fc_none: /* 0 */
+        /* Flow control (RX & TX) is completely disabled by a
+         * software over-ride.
+         */
+        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+        break;
+    case em_fc_rx_pause: /* 1 */
+        /* RX Flow control is enabled, and TX Flow control is
+         * disabled, by a software over-ride.
+         */
+        /* Since there really isn't a way to advertise that we are
+         * capable of RX Pause ONLY, we will advertise that we
+         * support both symmetric and asymmetric RX PAUSE.  Later
+         * (in em_config_fc_after_link_up) we will disable the
+         *hw's ability to send PAUSE frames.
+         */
+        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+        break;
+    case em_fc_tx_pause: /* 2 */
+        /* TX Flow control is enabled, and RX Flow control is
+         * disabled, by a software over-ride.
+         */
+        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
+        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
+        break;
+    case em_fc_full: /* 3 */
+        /* Flow control (both RX and TX) is enabled by a software
+         * over-ride.
+         */
+        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+        break;
+    default:
+        DEBUGOUT("Flow control param set incorrectly\n");
+        return -E1000_ERR_CONFIG;
+    }
+
+    if(em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
+
+    if(em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+    return 0;
+}
+
+/******************************************************************************
+* Force PHY speed and duplex settings to hw->forced_speed_duplex
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+em_phy_force_speed_duplex(struct em_hw *hw)
+{
+    uint32_t ctrl;
+    int32_t ret_val;
+    uint16_t mii_ctrl_reg;
+    uint16_t mii_status_reg;
+    uint16_t phy_data;
+    uint16_t i;
+
+    DEBUGFUNC("em_phy_force_speed_duplex");
+
+    /* Turn off Flow control if we are forcing speed and duplex. */
+    hw->fc = em_fc_none;
+
+    DEBUGOUT1("hw->fc = %d\n", hw->fc);
+
+    /* Read the Device Control Register. */
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
+    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+    ctrl &= ~(DEVICE_SPEED_MASK);
+
+    /* Clear the Auto Speed Detect Enable bit. */
+    ctrl &= ~E1000_CTRL_ASDE;
+
+    /* Read the MII Control Register. */
+    if(em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    /* We need to disable autoneg in order to force link and duplex. */
+
+    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
+
+    /* Are we forcing Full or Half Duplex? */
+    if(hw->forced_speed_duplex == em_100_full ||
+       hw->forced_speed_duplex == em_10_full) {
+        /* We want to force full duplex so we SET the full duplex bits in the
+         * Device and MII Control Registers.
+         */
+        ctrl |= E1000_CTRL_FD;
+        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
+        DEBUGOUT("Full Duplex\n");
+    } else {
+        /* We want to force half duplex so we CLEAR the full duplex bits in
+         * the Device and MII Control Registers.
+         */
+        ctrl &= ~E1000_CTRL_FD;
+        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
+        DEBUGOUT("Half Duplex\n");
+    }
+
+    /* Are we forcing 100Mbps??? */
+    if(hw->forced_speed_duplex == em_100_full ||
+       hw->forced_speed_duplex == em_100_half) {
+        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
+        ctrl |= E1000_CTRL_SPD_100;
+        mii_ctrl_reg |= MII_CR_SPEED_100;
+        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
+        DEBUGOUT("Forcing 100mb ");
+    } else {
+        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
+        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+        mii_ctrl_reg |= MII_CR_SPEED_10;
+        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
+        DEBUGOUT("Forcing 10mb ");
+    }
+
+    em_config_collision_dist(hw);
+
+    /* Write the configured values back to the Device Control Reg. */
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+
+    /* Write the MII Control Register with the new PHY configuration. */
+    if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
+     * forced whenever speed are duplex are forced.
+     */
+    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+    if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+    DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
+    
+    /* Need to reset the PHY or these changes will be ignored */
+    mii_ctrl_reg |= MII_CR_RESET;
+    if(em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+    usec_delay(1);
+
+    /* The wait_autoneg_complete flag may be a little misleading here.
+     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
+     * But we do want to delay for a period while forcing only so we
+     * don't generate false No Link messages.  So we will wait here
+     * only if the user has set wait_autoneg_complete to 1, which is
+     * the default.
+     */
+    if(hw->wait_autoneg_complete) {
+        /* We will wait for autoneg to complete. */
+        DEBUGOUT("Waiting for forced speed/duplex link.\n");
+        mii_status_reg = 0;
+
+        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+        for(i = PHY_FORCE_TIME; i > 0; i--) {
+            /* Read the MII Status Register and wait for Auto-Neg Complete bit
+             * to be set.
+             */
+            if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
+                DEBUGOUT("PHY Read Error\n");
+                return -E1000_ERR_PHY;
+            }
+            if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
+                DEBUGOUT("PHY Read Error\n");
+                return -E1000_ERR_PHY;
+            }
+            if(mii_status_reg & MII_SR_LINK_STATUS) break;
+            msec_delay(100);
+        }
+        if(i == 0) { /* We didn't get link */
+            /* Reset the DSP and wait again for link. */
+            
+            ret_val = em_phy_reset_dsp(hw);
+            if(ret_val < 0) {
+                DEBUGOUT("Error Resetting PHY DSP\n");
+                return ret_val;
+            }
+        }
+        /* This loop will early-out if the link condition has been met.  */
+        for(i = PHY_FORCE_TIME; i > 0; i--) {
+            if(mii_status_reg & MII_SR_LINK_STATUS) break;
+            msec_delay(100);
+            /* Read the MII Status Register and wait for Auto-Neg Complete bit
+             * to be set.
+             */
+            if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
+                DEBUGOUT("PHY Read Error\n");
+                return -E1000_ERR_PHY;
+            }
+            if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
+                DEBUGOUT("PHY Read Error\n");
+                return -E1000_ERR_PHY;
+            }
+        }
+    }
+    
+    /* Because we reset the PHY above, we need to re-force TX_CLK in the
+     * Extended PHY Specific Control Register to 25MHz clock.  This value
+     * defaults back to a 2.5MHz clock when the PHY is reset.
+     */
+    if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    phy_data |= M88E1000_EPSCR_TX_CLK_25;
+    if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+
+    /* In addition, because of the s/w reset above, we need to enable CRS on
+     * TX.  This must be set for both full and half duplex operation.
+     */
+    if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+    if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+    return 0;
+}
+
+/******************************************************************************
+* Sets the collision distance in the Transmit Control register
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Link should have been established previously. Reads the speed and duplex
+* information from the Device Status register.
+******************************************************************************/
+void
+em_config_collision_dist(struct em_hw *hw)
+{
+    uint32_t tctl;
+
+    tctl = E1000_READ_REG(hw, TCTL);
+
+    tctl &= ~E1000_TCTL_COLD;
+    tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
+
+    E1000_WRITE_REG(hw, TCTL, tctl);
+}
+
+/******************************************************************************
+* Sets MAC speed and duplex settings to reflect the those in the PHY
+*
+* hw - Struct containing variables accessed by shared code
+* mii_reg - data to write to the MII control register
+*
+* The contents of the PHY register containing the needed information need to
+* be passed in.
+******************************************************************************/
+static int32_t
+em_config_mac_to_phy(struct em_hw *hw)
+{
+    uint32_t ctrl;
+    uint16_t phy_data;
+
+    DEBUGFUNC("em_config_mac_to_phy");
+
+    /* Read the Device Control Register and set the bits to Force Speed
+     * and Duplex.
+     */
+    ctrl = E1000_READ_REG(hw, CTRL);
+    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
+
+    /* Set up duplex in the Device Control and Transmit Control
+     * registers depending on negotiated values.
+     */
+    if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
+    else ctrl &= ~E1000_CTRL_FD;
+
+    em_config_collision_dist(hw);
+
+    /* Set up speed in the Device Control register depending on
+     * negotiated values.
+     */
+    if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
+        ctrl |= E1000_CTRL_SPD_1000;
+    else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
+        ctrl |= E1000_CTRL_SPD_100;
+    /* Write the configured values back to the Device Control Reg. */
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+    return 0;
+}
+
+/******************************************************************************
+ * Forces the MAC's flow control settings.
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Sets the TFCE and RFCE bits in the device control register to reflect
+ * the adapter settings. TFCE and RFCE need to be explicitly set by
+ * software when a Copper PHY is used because autonegotiation is managed
+ * by the PHY rather than the MAC. Software must also configure these
+ * bits when link is forced on a fiber connection.
+ *****************************************************************************/
+static int32_t
+em_force_mac_fc(struct em_hw *hw)
+{
+    uint32_t ctrl;
+
+    DEBUGFUNC("em_force_mac_fc");
+
+    /* Get the current configuration of the Device Control Register */
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Because we didn't get link via the internal auto-negotiation
+     * mechanism (we either forced link or we got link via PHY
+     * auto-neg), we have to manually enable/disable transmit an
+     * receive flow control.
+     *
+     * The "Case" statement below enables/disable flow control
+     * according to the "hw->fc" parameter.
+     *
+     * The possible values of the "fc" parameter are:
+     *      0:  Flow control is completely disabled
+     *      1:  Rx flow control is enabled (we can receive pause
+     *          frames but not send pause frames).
+     *      2:  Tx flow control is enabled (we can send pause frames
+     *          frames but we do not receive pause frames).
+     *      3:  Both Rx and TX flow control (symmetric) is enabled.
+     *  other:  No other values should be possible at this point.
+     */
+
+    switch (hw->fc) {
+    case em_fc_none:
+        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
+        break;
+    case em_fc_rx_pause:
+        ctrl &= (~E1000_CTRL_TFCE);
+        ctrl |= E1000_CTRL_RFCE;
+        break;
+    case em_fc_tx_pause:
+        ctrl &= (~E1000_CTRL_RFCE);
+        ctrl |= E1000_CTRL_TFCE;
+        break;
+    case em_fc_full:
+        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
+        break;
+    default:
+        DEBUGOUT("Flow control param set incorrectly\n");
+        return -E1000_ERR_CONFIG;
+    }
+
+    /* Disable TX Flow Control for 82542 (rev 2.0) */
+    if(hw->mac_type == em_82542_rev2_0)
+        ctrl &= (~E1000_CTRL_TFCE);
+
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+    return 0;
+}
+
+/******************************************************************************
+ * Configures flow control settings after link is established
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Should be called immediately after a valid link has been established.
+ * Forces MAC flow control settings if link was forced. When in MII/GMII mode
+ * and autonegotiation is enabled, the MAC flow control settings will be set
+ * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
+ * and RFCE bits will be automaticaly set to the negotiated flow control mode.
+ *****************************************************************************/
+int32_t
+em_config_fc_after_link_up(struct em_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t mii_status_reg;
+    uint16_t mii_nway_adv_reg;
+    uint16_t mii_nway_lp_ability_reg;
+    uint16_t speed;
+    uint16_t duplex;
+
+    DEBUGFUNC("em_config_fc_after_link_up");
+
+    /* Check for the case where we have fiber media and auto-neg failed
+     * so we had to force link.  In this case, we need to force the
+     * configuration of the MAC to match the "fc" parameter.
+     */
+    if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
+       ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
+        ret_val = em_force_mac_fc(hw);
+        if(ret_val < 0) {
+            DEBUGOUT("Error forcing flow control settings\n");
+            return ret_val;
+        }
+    }
+
+    /* Check for the case where we have copper media and auto-neg is
+     * enabled.  In this case, we need to check and see if Auto-Neg
+     * has completed, and if so, how the PHY and link partner has
+     * flow control configured.
+     */
+    if((hw->media_type == em_media_type_copper) && hw->autoneg) {
+        /* Read the MII Status Register and check to see if AutoNeg
+         * has completed.  We read this twice because this reg has
+         * some "sticky" (latched) bits.
+         */
+        if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
+            DEBUGOUT("PHY Read Error \n");
+            return -E1000_ERR_PHY;
+        }
+        if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
+            DEBUGOUT("PHY Read Error \n");
+            return -E1000_ERR_PHY;
+        }
+
+        if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
+            /* The AutoNeg process has completed, so we now need to
+             * read both the Auto Negotiation Advertisement Register
+             * (Address 4) and the Auto_Negotiation Base Page Ability
+             * Register (Address 5) to determine how flow control was
+             * negotiated.
+             */
+            if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
+                DEBUGOUT("PHY Read Error\n");
+                return -E1000_ERR_PHY;
+            }
+            if(em_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
+                DEBUGOUT("PHY Read Error\n");
+                return -E1000_ERR_PHY;
+            }
+
+            /* Two bits in the Auto Negotiation Advertisement Register
+             * (Address 4) and two bits in the Auto Negotiation Base
+             * Page Ability Register (Address 5) determine flow control
+             * for both the PHY and the link partner.  The following
+             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
+             * 1999, describes these PAUSE resolution bits and how flow
+             * control is determined based upon these settings.
+             * NOTE:  DC = Don't Care
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
+             *-------|---------|-------|---------|--------------------
+             *   0   |    0    |  DC   |   DC    | em_fc_none
+             *   0   |    1    |   0   |   DC    | em_fc_none
+             *   0   |    1    |   1   |    0    | em_fc_none
+             *   0   |    1    |   1   |    1    | em_fc_tx_pause
+             *   1   |    0    |   0   |   DC    | em_fc_none
+             *   1   |   DC    |   1   |   DC    | em_fc_full
+             *   1   |    1    |   0   |    0    | em_fc_none
+             *   1   |    1    |   0   |    1    | em_fc_rx_pause
+             *
+             */
+            /* Are both PAUSE bits set to 1?  If so, this implies
+             * Symmetric Flow Control is enabled at both ends.  The
+             * ASM_DIR bits are irrelevant per the spec.
+             *
+             * For Symmetric Flow Control:
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+             *-------|---------|-------|---------|--------------------
+             *   1   |   DC    |   1   |   DC    | em_fc_full
+             *
+             */
+            if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+               (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
+                /* Now we need to check if the user selected RX ONLY
+                 * of pause frames.  In this case, we had to advertise
+                 * FULL flow control because we could not advertise RX
+                 * ONLY. Hence, we must now check to see if we need to
+                 * turn OFF  the TRANSMISSION of PAUSE frames.
+                 */
+                if(hw->original_fc == em_fc_full) {
+                    hw->fc = em_fc_full;
+                    DEBUGOUT("Flow Control = FULL.\r\n");
+                } else {
+                    hw->fc = em_fc_rx_pause;
+                    DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
+                }
+            }
+            /* For receiving PAUSE frames ONLY.
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+             *-------|---------|-------|---------|--------------------
+             *   0   |    1    |   1   |    1    | em_fc_tx_pause
+             *
+             */
+            else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+                hw->fc = em_fc_tx_pause;
+                DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
+            }
+            /* For transmitting PAUSE frames ONLY.
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+             *-------|---------|-------|---------|--------------------
+             *   1   |    1    |   0   |    1    | em_fc_rx_pause
+             *
+             */
+            else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                    !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+                hw->fc = em_fc_rx_pause;
+                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
+            }
+            /* Per the IEEE spec, at this point flow control should be
+             * disabled.  However, we want to consider that we could
+             * be connected to a legacy switch that doesn't advertise
+             * desired flow control, but can be forced on the link
+             * partner.  So if we advertised no flow control, that is
+             * what we will resolve to.  If we advertised some kind of
+             * receive capability (Rx Pause Only or Full Flow Control)
+             * and the link partner advertised none, we will configure
+             * ourselves to enable Rx Flow Control only.  We can do
+             * this safely for two reasons:  If the link partner really
+             * didn't want flow control enabled, and we enable Rx, no
+             * harm done since we won't be receiving any PAUSE frames
+             * anyway.  If the intent on the link partner was to have
+             * flow control enabled, then by us enabling RX only, we
+             * can at least receive pause frames and process them.
+             * This is a good idea because in most cases, since we are
+             * predominantly a server NIC, more times than not we will
+             * be asked to delay transmission of packets than asking
+             * our link partner to pause transmission of frames.
+             */
+            else if(hw->original_fc == em_fc_none ||
+                    hw->original_fc == em_fc_tx_pause) {
+                hw->fc = em_fc_none;
+                DEBUGOUT("Flow Control = NONE.\r\n");
+            } else {
+                hw->fc = em_fc_rx_pause;
+                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
+            }
+
+            /* Now we need to do one last check...  If we auto-
+             * negotiated to HALF DUPLEX, flow control should not be
+             * enabled per IEEE 802.3 spec.
+             */
+            em_get_speed_and_duplex(hw, &speed, &duplex);
+
+            if(duplex == HALF_DUPLEX)
+                hw->fc = em_fc_none;
+
+            /* Now we call a subroutine to actually force the MAC
+             * controller to use the correct flow control settings.
+             */
+            ret_val = em_force_mac_fc(hw);
+            if(ret_val < 0) {
+                DEBUGOUT("Error forcing flow control settings\n");
+                return ret_val;
+             }
+        } else {
+            DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
+        }
+    }
+    return 0;
+}
+
+/******************************************************************************
+ * Checks to see if the link status of the hardware has changed.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Called by any function that needs to check the link status of the adapter.
+ *****************************************************************************/
+int32_t
+em_check_for_link(struct em_hw *hw)
+{
+    uint32_t rxcw;
+    uint32_t ctrl;
+    uint32_t status;
+    uint32_t rctl;
+    uint32_t signal;
+    int32_t ret_val;
+    uint16_t phy_data;
+    uint16_t lp_capability;
+
+    DEBUGFUNC("em_check_for_link");
+    
+    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
+     * set when the optics detect a signal. On older adapters, it will be 
+     * cleared when there is a signal
+     */
+    if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
+    else signal = 0;
+
+    ctrl = E1000_READ_REG(hw, CTRL);
+    status = E1000_READ_REG(hw, STATUS);
+    rxcw = E1000_READ_REG(hw, RXCW);
+
+    /* If we have a copper PHY then we only want to go out to the PHY
+     * registers to see if Auto-Neg has completed and/or if our link
+     * status has changed.  The get_link_status flag will be set if we
+     * receive a Link Status Change interrupt or we have Rx Sequence
+     * Errors.
+     */
+    if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
+        /* First we want to see if the MII Status Register reports
+         * link.  If so, then we want to get the current speed/duplex
+         * of the PHY.
+         * Read the register twice since the link bit is sticky.
+         */
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
+            DEBUGOUT("PHY Read Error\n");
+            return -E1000_ERR_PHY;
+        }
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
+            DEBUGOUT("PHY Read Error\n");
+            return -E1000_ERR_PHY;
+        }
+
+        if(phy_data & MII_SR_LINK_STATUS) {
+            hw->get_link_status = FALSE;
+        } else {
+            /* No link detected */
+            return 0;
+        }
+
+        /* If we are forcing speed/duplex, then we simply return since
+         * we have already determined whether we have link or not.
+         */
+        if(!hw->autoneg) return -E1000_ERR_CONFIG;
+
+        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
+         * have Si on board that is 82544 or newer, Auto
+         * Speed Detection takes care of MAC speed/duplex
+         * configuration.  So we only need to configure Collision
+         * Distance in the MAC.  Otherwise, we need to force
+         * speed/duplex on the MAC to the current PHY speed/duplex
+         * settings.
+         */
+        if(hw->mac_type >= em_82544)
+            em_config_collision_dist(hw);
+        else {
+            ret_val = em_config_mac_to_phy(hw);
+            if(ret_val < 0) {
+                DEBUGOUT("Error configuring MAC to PHY settings\n");
+                return ret_val;
+            }
+        }
+
+        /* Configure Flow Control now that Auto-Neg has completed. First, we 
+         * need to restore the desired flow control settings because we may
+         * have had to re-autoneg with a different link partner.
+         */
+        ret_val = em_config_fc_after_link_up(hw);
+        if(ret_val < 0) {
+            DEBUGOUT("Error configuring flow control\n");
+            return ret_val;
+        }
+
+        /* At this point we know that we are on copper and we have
+         * auto-negotiated link.  These are conditions for checking the link
+         * parter capability register.  We use the link partner capability to
+         * determine if TBI Compatibility needs to be turned on or off.  If
+         * the link partner advertises any speed in addition to Gigabit, then
+         * we assume that they are GMII-based, and TBI compatibility is not
+         * needed. If no other speeds are advertised, we assume the link
+         * partner is TBI-based, and we turn on TBI Compatibility.
+         */
+        if(hw->tbi_compatibility_en) {
+            if(em_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
+                DEBUGOUT("PHY Read Error\n");
+                return -E1000_ERR_PHY;
+            }
+            if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
+                                NWAY_LPAR_10T_FD_CAPS |
+                                NWAY_LPAR_100TX_HD_CAPS |
+                                NWAY_LPAR_100TX_FD_CAPS |
+                                NWAY_LPAR_100T4_CAPS)) {
+                /* If our link partner advertises anything in addition to 
+                 * gigabit, we do not need to enable TBI compatibility.
+                 */
+                if(hw->tbi_compatibility_on) {
+                    /* If we previously were in the mode, turn it off. */
+                    rctl = E1000_READ_REG(hw, RCTL);
+                    rctl &= ~E1000_RCTL_SBP;
+                    E1000_WRITE_REG(hw, RCTL, rctl);
+                    hw->tbi_compatibility_on = FALSE;
+                }
+            } else {
+                /* If TBI compatibility is was previously off, turn it on. For
+                 * compatibility with a TBI link partner, we will store bad
+                 * packets. Some frames have an additional byte on the end and
+                 * will look like CRC errors to to the hardware.
+                 */
+                if(!hw->tbi_compatibility_on) {
+                    hw->tbi_compatibility_on = TRUE;
+                    rctl = E1000_READ_REG(hw, RCTL);
+                    rctl |= E1000_RCTL_SBP;
+                    E1000_WRITE_REG(hw, RCTL, rctl);
+                }
+            }
+        }
+    }
+    /* If we don't have link (auto-negotiation failed or link partner cannot
+     * auto-negotiate), the cable is plugged in (we have signal), and our
+     * link partner is not trying to auto-negotiate with us (we are receiving
+     * idles or data), we need to force link up. We also need to give
+     * auto-negotiation time to complete, in case the cable was just plugged
+     * in. The autoneg_failed flag does this.
+     */
+    else if((hw->media_type == em_media_type_fiber) &&
+            (!(status & E1000_STATUS_LU)) &&
+            ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
+            (!(rxcw & E1000_RXCW_C))) {
+        if(hw->autoneg_failed == 0) {
+            hw->autoneg_failed = 1;
+            return 0;
+        }
+        DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
+
+        /* Disable auto-negotiation in the TXCW register */
+        E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
+
+        /* Force link-up and also force full-duplex. */
+        ctrl = E1000_READ_REG(hw, CTRL);
+        ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+
+        /* Configure Flow Control after forcing link up. */
+        ret_val = em_config_fc_after_link_up(hw);
+        if(ret_val < 0) {
+            DEBUGOUT("Error configuring flow control\n");
+            return ret_val;
+        }
+    }
+    /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
+     * auto-negotiation in the TXCW register and disable forced link in the
+     * Device Control register in an attempt to auto-negotiate with our link
+     * partner.
+     */
+    else if((hw->media_type == em_media_type_fiber) &&
+              (ctrl & E1000_CTRL_SLU) &&
+              (rxcw & E1000_RXCW_C)) {
+        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
+        E1000_WRITE_REG(hw, TXCW, hw->txcw);
+        E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
+    }
+    return 0;
+}
+
+/******************************************************************************
+ * Detects the current speed and duplex settings of the hardware.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * speed - Speed of the connection
+ * duplex - Duplex setting of the connection
+ *****************************************************************************/
+void
+em_get_speed_and_duplex(struct em_hw *hw,
+                           uint16_t *speed,
+                           uint16_t *duplex)
+{
+    uint32_t status;
+
+    DEBUGFUNC("em_get_speed_and_duplex");
+
+    if(hw->mac_type >= em_82543) {
+        status = E1000_READ_REG(hw, STATUS);
+        if(status & E1000_STATUS_SPEED_1000) {
+            *speed = SPEED_1000;
+            DEBUGOUT("1000 Mbs, ");
+        } else if(status & E1000_STATUS_SPEED_100) {
+            *speed = SPEED_100;
+            DEBUGOUT("100 Mbs, ");
+        } else {
+            *speed = SPEED_10;
+            DEBUGOUT("10 Mbs, ");
+        }
+
+        if(status & E1000_STATUS_FD) {
+            *duplex = FULL_DUPLEX;
+            DEBUGOUT("Full Duplex\r\n");
+        } else {
+            *duplex = HALF_DUPLEX;
+            DEBUGOUT(" Half Duplex\r\n");
+        }
+    } else {
+        DEBUGOUT("1000 Mbs, Full Duplex\r\n");
+        *speed = SPEED_1000;
+        *duplex = FULL_DUPLEX;
+    }
+}
+
+/******************************************************************************
+* Blocks until autoneg completes or times out (~4.5 seconds)
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+int32_t
+em_wait_autoneg(struct em_hw *hw)
+{
+    uint16_t i;
+    uint16_t phy_data;
+
+    DEBUGFUNC("em_wait_autoneg");
+    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
+
+    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+    for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
+        /* Read the MII Status Register and wait for Auto-Neg
+         * Complete bit to be set.
+         */
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
+            DEBUGOUT("PHY Read Error\n");
+            return -E1000_ERR_PHY;
+        }
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
+            DEBUGOUT("PHY Read Error\n");
+            return -E1000_ERR_PHY;
+        }
+        if(phy_data & MII_SR_AUTONEG_COMPLETE) {
+            return 0;
+        }
+        msec_delay(100);
+    }
+    return 0;
+}
+
+/******************************************************************************
+* Raises the Management Data Clock
+*
+* hw - Struct containing variables accessed by shared code
+* ctrl - Device control register's current value
+******************************************************************************/
+static void
+em_raise_mdi_clk(struct em_hw *hw,
+                    uint32_t *ctrl)
+{
+    /* Raise the clock input to the Management Data Clock (by setting the MDC
+     * bit), and then delay 2 microseconds.
+     */
+    E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
+    usec_delay(2);
+}
+
+/******************************************************************************
+* Lowers the Management Data Clock
+*
+* hw - Struct containing variables accessed by shared code
+* ctrl - Device control register's current value
+******************************************************************************/
+static void
+em_lower_mdi_clk(struct em_hw *hw,
+                    uint32_t *ctrl)
+{
+    /* Lower the clock input to the Management Data Clock (by clearing the MDC
+     * bit), and then delay 2 microseconds.
+     */
+    E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
+    usec_delay(2);
+}
+
+/******************************************************************************
+* Shifts data bits out to the PHY
+*
+* hw - Struct containing variables accessed by shared code
+* data - Data to send out to the PHY
+* count - Number of bits to shift out
+*
+* Bits are shifted out in MSB to LSB order.
+******************************************************************************/
+static void
+em_shift_out_mdi_bits(struct em_hw *hw,
+                         uint32_t data,
+                         uint16_t count)
+{
+    uint32_t ctrl;
+    uint32_t mask;
+
+    /* We need to shift "count" number of bits out to the PHY. So, the value
+     * in the "data" parameter will be shifted out to the PHY one bit at a 
+     * time. In order to do this, "data" must be broken down into bits.
+     */
+    mask = 0x01;
+    mask <<= (count - 1);
+
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
+    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
+
+    while(mask) {
+        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
+         * then raising and lowering the Management Data Clock. A "0" is
+         * shifted out to the PHY by setting the MDIO bit to "0" and then
+         * raising and lowering the clock.
+         */
+        if(data & mask) ctrl |= E1000_CTRL_MDIO;
+        else ctrl &= ~E1000_CTRL_MDIO;
+
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+
+        usec_delay(2);
+
+        em_raise_mdi_clk(hw, &ctrl);
+        em_lower_mdi_clk(hw, &ctrl);
+
+        mask = mask >> 1;
+    }
+
+    /* Clear the data bit just before leaving this routine. */
+    ctrl &= ~E1000_CTRL_MDIO;
+}
+
+/******************************************************************************
+* Shifts data bits in from the PHY
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Bits are shifted in in MSB to LSB order. 
+******************************************************************************/
+static uint16_t
+em_shift_in_mdi_bits(struct em_hw *hw)
+{
+    uint32_t ctrl;
+    uint16_t data = 0;
+    uint8_t i;
+
+    /* In order to read a register from the PHY, we need to shift in a total
+     * of 18 bits from the PHY. The first two bit (turnaround) times are used
+     * to avoid contention on the MDIO pin when a read operation is performed.
+     * These two bits are ignored by us and thrown away. Bits are "shifted in"
+     * by raising the input to the Management Data Clock (setting the MDC bit),
+     * and then reading the value of the MDIO bit.
+     */ 
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
+    ctrl &= ~E1000_CTRL_MDIO_DIR;
+    ctrl &= ~E1000_CTRL_MDIO;
+
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+
+    /* Raise and Lower the clock before reading in the data. This accounts for
+     * the turnaround bits. The first clock occurred when we clocked out the
+     * last bit of the Register Address.
+     */
+    em_raise_mdi_clk(hw, &ctrl);
+    em_lower_mdi_clk(hw, &ctrl);
+
+    for(data = 0, i = 0; i < 16; i++) {
+        data = data << 1;
+        em_raise_mdi_clk(hw, &ctrl);
+        ctrl = E1000_READ_REG(hw, CTRL);
+        /* Check to see if we shifted in a "1". */
+        if(ctrl & E1000_CTRL_MDIO) data |= 1;
+        em_lower_mdi_clk(hw, &ctrl);
+    }
+
+    em_raise_mdi_clk(hw, &ctrl);
+    em_lower_mdi_clk(hw, &ctrl);
+
+    /* Clear the MDIO bit just before leaving this routine. */
+    ctrl &= ~E1000_CTRL_MDIO;
+
+    return data;
+}
+
+/*****************************************************************************
+* Reads the value from a PHY register
+*
+* hw - Struct containing variables accessed by shared code
+* reg_addr - address of the PHY register to read
+******************************************************************************/
+int32_t
+em_read_phy_reg(struct em_hw *hw,
+                   uint32_t reg_addr,
+                   uint16_t *phy_data)
+{
+    uint32_t i;
+    uint32_t mdic = 0;
+    const uint32_t phy_addr = 1;
+
+    DEBUGFUNC("em_read_phy_reg");
+
+    if(reg_addr > MAX_PHY_REG_ADDRESS) {
+        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+        return -E1000_ERR_PARAM;
+    }
+
+    if(hw->mac_type > em_82543) {
+        /* Set up Op-code, Phy Address, and register address in the MDI
+         * Control register.  The MAC will take care of interfacing with the
+         * PHY to retrieve the desired data.
+         */
+        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
+                (E1000_MDIC_OP_READ));
+
+        E1000_WRITE_REG(hw, MDIC, mdic);
+
+        /* Poll the ready bit to see if the MDI read completed */
+        for(i = 0; i < 64; i++) {
+            usec_delay(10);
+            mdic = E1000_READ_REG(hw, MDIC);
+            if(mdic & E1000_MDIC_READY) break;
+        }
+        if(!(mdic & E1000_MDIC_READY)) {
+            DEBUGOUT("MDI Read did not complete\n");
+            return -E1000_ERR_PHY;
+        }
+        if(mdic & E1000_MDIC_ERROR) {
+            DEBUGOUT("MDI Error\n");
+            return -E1000_ERR_PHY;
+        }
+        *phy_data = (uint16_t) mdic;
+    } else {
+        /* We must first send a preamble through the MDIO pin to signal the
+         * beginning of an MII instruction.  This is done by sending 32
+         * consecutive "1" bits.
+         */
+        em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+        /* Now combine the next few fields that are required for a read
+         * operation.  We use this method instead of calling the
+         * em_shift_out_mdi_bits routine five different times. The format of
+         * a MII read instruction consists of a shift out of 14 bits and is
+         * defined as follows:
+         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
+         * followed by a shift in of 18 bits.  This first two bits shifted in
+         * are TurnAround bits used to avoid contention on the MDIO pin when a
+         * READ operation is performed.  These two bits are thrown away
+         * followed by a shift in of 16 bits which contains the desired data.
+         */
+        mdic = ((reg_addr) | (phy_addr << 5) | 
+                (PHY_OP_READ << 10) | (PHY_SOF << 12));
+
+        em_shift_out_mdi_bits(hw, mdic, 14);
+
+        /* Now that we've shifted out the read command to the MII, we need to
+         * "shift in" the 16-bit value (18 total bits) of the requested PHY
+         * register address.
+         */
+        *phy_data = em_shift_in_mdi_bits(hw);
+    }
+    return 0;
+}
+
+/******************************************************************************
+* Writes a value to a PHY register
+*
+* hw - Struct containing variables accessed by shared code
+* reg_addr - address of the PHY register to write
+* data - data to write to the PHY
+******************************************************************************/
+int32_t
+em_write_phy_reg(struct em_hw *hw,
+                    uint32_t reg_addr,
+                    uint16_t phy_data)
+{
+    uint32_t i;
+    uint32_t mdic = 0;
+    const uint32_t phy_addr = 1;
+
+    DEBUGFUNC("em_write_phy_reg");
+
+    if(reg_addr > MAX_PHY_REG_ADDRESS) {
+        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+        return -E1000_ERR_PARAM;
+    }
+
+    if(hw->mac_type > em_82543) {
+        /* Set up Op-code, Phy Address, register address, and data intended
+         * for the PHY register in the MDI Control register.  The MAC will take
+         * care of interfacing with the PHY to send the desired data.
+         */
+        mdic = (((uint32_t) phy_data) |
+                (reg_addr << E1000_MDIC_REG_SHIFT) |
+                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
+                (E1000_MDIC_OP_WRITE));
+
+        E1000_WRITE_REG(hw, MDIC, mdic);
+
+        /* Poll the ready bit to see if the MDI read completed */
+        for(i = 0; i < 64; i++) {
+            usec_delay(10);
+            mdic = E1000_READ_REG(hw, MDIC);
+            if(mdic & E1000_MDIC_READY) break;
+        }
+        if(!(mdic & E1000_MDIC_READY)) {
+            DEBUGOUT("MDI Write did not complete\n");
+            return -E1000_ERR_PHY;
+        }
+    } else {
+        /* We'll need to use the SW defined pins to shift the write command
+         * out to the PHY. We first send a preamble to the PHY to signal the
+         * beginning of the MII instruction.  This is done by sending 32 
+         * consecutive "1" bits.
+         */
+        em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+        /* Now combine the remaining required fields that will indicate a 
+         * write operation. We use this method instead of calling the
+         * em_shift_out_mdi_bits routine for each field in the command. The
+         * format of a MII write instruction is as follows:
+         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
+         */
+        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
+                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
+        mdic <<= 16;
+        mdic |= (uint32_t) phy_data;
+
+        em_shift_out_mdi_bits(hw, mdic, 32);
+    }
+    return 0;
+}
+
+/******************************************************************************
+* Returns the PHY to the power-on reset state
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+void
+em_phy_hw_reset(struct em_hw *hw)
+{
+    uint32_t ctrl;
+    uint32_t ctrl_ext;
+
+    DEBUGFUNC("em_phy_hw_reset");
+
+    DEBUGOUT("Resetting Phy...\n");
+
+    if(hw->mac_type > em_82543) {
+        /* Read the device control register and assert the E1000_CTRL_PHY_RST
+         * bit. Then, take it out of reset.
+         */
+        ctrl = E1000_READ_REG(hw, CTRL);
+        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
+        msec_delay(10);
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+    } else {
+        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
+         * bit to put the PHY into reset. Then, take it out of reset.
+         */
+        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
+        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+        msec_delay(10);
+        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+    }
+    usec_delay(150);
+}
+
+/******************************************************************************
+* Resets the PHY
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Sets bit 15 of the MII Control regiser
+******************************************************************************/
+int32_t
+em_phy_reset(struct em_hw *hw)
+{
+    uint16_t phy_data;
+
+    DEBUGFUNC("em_phy_reset");
+
+    if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    phy_data |= MII_CR_RESET;
+    if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
+        DEBUGOUT("PHY Write Error\n");
+        return -E1000_ERR_PHY;
+    }
+    usec_delay(1);
+    return 0;
+}
+
+/******************************************************************************
+* Probes the expected PHY address for known PHY IDs
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+int32_t
+em_detect_gig_phy(struct em_hw *hw)
+{
+    uint16_t phy_id_high, phy_id_low;
+    boolean_t match = FALSE;
+
+    DEBUGFUNC("em_detect_gig_phy");
+
+    /* Read the PHY ID Registers to identify which PHY is onboard. */
+    if(em_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    hw->phy_id = (uint32_t) (phy_id_high << 16);
+    usec_delay(2);
+    if(em_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
+        DEBUGOUT("PHY Read Error\n");
+        return -E1000_ERR_PHY;
+    }
+    hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
+    
+    switch(hw->mac_type) {
+    case em_82543:
+        if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
+        break;
+    case em_82544:
+        if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
+        break;
+    case em_82540:
+    case em_82545:
+    case em_82546:
+        if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
+        break;
+    default:
+        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
+        return -E1000_ERR_CONFIG;
+    }
+    if(match) {
+        DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
+        return 0;
+    }
+    DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
+    return -E1000_ERR_PHY;
+}
+
+/******************************************************************************
+* Resets the PHY's DSP
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+em_phy_reset_dsp(struct em_hw *hw)
+{
+    int32_t ret_val = -E1000_ERR_PHY;
+    DEBUGFUNC("em_phy_reset_dsp");
+    
+    do {
+        if(em_write_phy_reg(hw, 29, 0x001d) < 0) break;
+        if(em_write_phy_reg(hw, 30, 0x00c1) < 0) break;
+        if(em_write_phy_reg(hw, 30, 0x0000) < 0) break;
+        ret_val = 0;
+    } while(0);
+
+    if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
+    return ret_val;
+}
+
+/******************************************************************************
+* Get PHY information from various PHY registers
+*
+* hw - Struct containing variables accessed by shared code
+* phy_info - PHY information structure
+******************************************************************************/
+int32_t
+em_phy_get_info(struct em_hw *hw,
+                   struct em_phy_info *phy_info)
+{
+    int32_t ret_val = -E1000_ERR_PHY;
+    uint16_t phy_data;
+
+    DEBUGFUNC("em_phy_get_info");
+
+    phy_info->cable_length = em_cable_length_undefined;
+    phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
+    phy_info->cable_polarity = em_rev_polarity_undefined;
+    phy_info->polarity_correction = em_polarity_reversal_undefined;
+    phy_info->mdix_mode = em_auto_x_mode_undefined;
+    phy_info->local_rx = em_1000t_rx_status_undefined;
+    phy_info->remote_rx = em_1000t_rx_status_undefined;
+
+    if(hw->media_type != em_media_type_copper) {
+        DEBUGOUT("PHY info is only valid for copper media\n");
+        return -E1000_ERR_CONFIG;
+    }
+
+    do {
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
+        if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
+        if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
+            DEBUGOUT("PHY info is only valid if link is up\n");
+            return -E1000_ERR_CONFIG;
+        }
+
+        if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
+            break;
+        phy_info->extended_10bt_distance =
+            (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
+            M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
+        phy_info->polarity_correction =
+            (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
+            M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
+
+        if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
+            break;
+        phy_info->cable_polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
+            M88E1000_PSSR_REV_POLARITY_SHIFT;
+        phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
+            M88E1000_PSSR_MDIX_SHIFT;
+        if(phy_data & M88E1000_PSSR_1000MBS) {
+            /* Cable Length Estimation and Local/Remote Receiver Informatoion
+             * are only valid at 1000 Mbps
+             */
+            phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
+                                      M88E1000_PSSR_CABLE_LENGTH_SHIFT);
+            if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0) 
+                break;
+            phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
+                SR_1000T_LOCAL_RX_STATUS_SHIFT;
+            phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
+                SR_1000T_REMOTE_RX_STATUS_SHIFT;
+        }
+        ret_val = 0;
+    } while(0);
+
+    if(ret_val < 0) DEBUGOUT("PHY Read Error\n");
+    return ret_val;
+}
+
+int32_t
+em_validate_mdi_setting(struct em_hw *hw)
+{
+    DEBUGFUNC("em_validate_mdi_settings");
+
+    if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
+        DEBUGOUT("Invalid MDI setting detected\n");
+        hw->mdix = 1;
+        return -E1000_ERR_CONFIG;
+    }
+    return 0;
+}
+
+/******************************************************************************
+ * Raises the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * eecd - EECD's current value
+ *****************************************************************************/
+static void
+em_raise_ee_clk(struct em_hw *hw,
+                   uint32_t *eecd)
+{
+    /* Raise the clock input to the EEPROM (by setting the SK bit), and then
+     * wait 50 microseconds.
+     */
+    *eecd = *eecd | E1000_EECD_SK;
+    E1000_WRITE_REG(hw, EECD, *eecd);
+    usec_delay(50);
+}
+
+/******************************************************************************
+ * Lowers the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code 
+ * eecd - EECD's current value
+ *****************************************************************************/
+static void
+em_lower_ee_clk(struct em_hw *hw,
+                   uint32_t *eecd)
+{
+    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
+     * wait 50 microseconds. 
+     */
+    *eecd = *eecd & ~E1000_EECD_SK;
+    E1000_WRITE_REG(hw, EECD, *eecd);
+    usec_delay(50);
+}
+
+/******************************************************************************
+ * Shift data bits out to the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * data - data to send to the EEPROM
+ * count - number of bits to shift out
+ *****************************************************************************/
+static void
+em_shift_out_ee_bits(struct em_hw *hw,
+                        uint16_t data,
+                        uint16_t count)
+{
+    uint32_t eecd;
+    uint32_t mask;
+
+    /* We need to shift "count" bits out to the EEPROM. So, value in the
+     * "data" parameter will be shifted out to the EEPROM one bit at a time.
+     * In order to do this, "data" must be broken down into bits. 
+     */
+    mask = 0x01 << (count - 1);
+    eecd = E1000_READ_REG(hw, EECD);
+    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
+    do {
+        /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
+         * and then raising and then lowering the clock (the SK bit controls
+         * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
+         * by setting "DI" to "0" and then raising and then lowering the clock.
+         */
+        eecd &= ~E1000_EECD_DI;
+
+        if(data & mask)
+            eecd |= E1000_EECD_DI;
+
+        E1000_WRITE_REG(hw, EECD, eecd);
+
+        usec_delay(50);
+
+        em_raise_ee_clk(hw, &eecd);
+        em_lower_ee_clk(hw, &eecd);
+
+        mask = mask >> 1;
+
+    } while(mask);
+
+    /* We leave the "DI" bit set to "0" when we leave this routine. */
+    eecd &= ~E1000_EECD_DI;
+    E1000_WRITE_REG(hw, EECD, eecd);
+}
+
+/******************************************************************************
+ * Shift data bits in from the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static uint16_t
+em_shift_in_ee_bits(struct em_hw *hw)
+{
+    uint32_t eecd;
+    uint32_t i;
+    uint16_t data;
+
+    /* In order to read a register from the EEPROM, we need to shift 16 bits 
+     * in from the EEPROM. Bits are "shifted in" by raising the clock input to
+     * the EEPROM (setting the SK bit), and then reading the value of the "DO"
+     * bit.  During this "shifting in" process the "DI" bit should always be 
+     * clear..
+     */
+
+    eecd = E1000_READ_REG(hw, EECD);
+
+    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
+    data = 0;
+
+    for(i = 0; i < 16; i++) {
+        data = data << 1;
+        em_raise_ee_clk(hw, &eecd);
+
+        eecd = E1000_READ_REG(hw, EECD);
+
+        eecd &= ~(E1000_EECD_DI);
+        if(eecd & E1000_EECD_DO)
+            data |= 1;
+
+        em_lower_ee_clk(hw, &eecd);
+    }
+
+    return data;
+}
+
+/******************************************************************************
+ * Prepares EEPROM for access
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
+ * function should be called before issuing a command to the EEPROM.
+ *****************************************************************************/
+static void
+em_setup_eeprom(struct em_hw *hw)
+{
+    uint32_t eecd;
+
+    eecd = E1000_READ_REG(hw, EECD);
+
+    /* Clear SK and DI */
+    eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
+    E1000_WRITE_REG(hw, EECD, eecd);
+
+    /* Set CS */
+    eecd |= E1000_EECD_CS;
+    E1000_WRITE_REG(hw, EECD, eecd);
+}
+
+/******************************************************************************
+ * Returns EEPROM to a "standby" state
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+em_standby_eeprom(struct em_hw *hw)
+{
+    uint32_t eecd;
+
+    eecd = E1000_READ_REG(hw, EECD);
+
+    /* Deselct EEPROM */
+    eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+    E1000_WRITE_REG(hw, EECD, eecd);
+    usec_delay(50);
+
+    /* Clock high */
+    eecd |= E1000_EECD_SK;
+    E1000_WRITE_REG(hw, EECD, eecd);
+    usec_delay(50);
+
+    /* Select EEPROM */
+    eecd |= E1000_EECD_CS;
+    E1000_WRITE_REG(hw, EECD, eecd);
+    usec_delay(50);
+
+    /* Clock low */
+    eecd &= ~E1000_EECD_SK;
+    E1000_WRITE_REG(hw, EECD, eecd);
+    usec_delay(50);
+}
+
+
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - offset of  word in the EEPROM to read
+ * data - word read from the EEPROM 
+ *****************************************************************************/
+int32_t
+em_read_eeprom(struct em_hw *hw,
+                  uint16_t offset,
+                  uint16_t *data)
+{
+    uint32_t eecd;
+    uint32_t i = 0;
+    boolean_t large_eeprom = FALSE;
+
+    DEBUGFUNC("em_read_eeprom");
+
+    /* Request EEPROM Access */
+    if(hw->mac_type > em_82544) {
+        eecd = E1000_READ_REG(hw, EECD);
+        if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
+        eecd |= E1000_EECD_REQ;
+        E1000_WRITE_REG(hw, EECD, eecd);
+        eecd = E1000_READ_REG(hw, EECD);
+        while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
+            i++;
+            usec_delay(5);
+            eecd = E1000_READ_REG(hw, EECD);
+        }
+        if(!(eecd & E1000_EECD_GNT)) {
+            eecd &= ~E1000_EECD_REQ;
+            E1000_WRITE_REG(hw, EECD, eecd);
+            DEBUGOUT("Could not acquire EEPROM grant\n");
+            return -E1000_ERR_EEPROM;
+        }
+    }
+
+    /*  Prepare the EEPROM for reading  */
+    em_setup_eeprom(hw);
+
+    /*  Send the READ command (opcode + addr)  */
+    em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
+    if(large_eeprom) {
+        /* If we have a 256 word EEPROM, there are 8 address bits */
+        em_shift_out_ee_bits(hw, offset, 8);
+    } else {
+        /* If we have a 64 word EEPROM, there are 6 address bits */
+        em_shift_out_ee_bits(hw, offset, 6);
+    }
+
+    /* Read the data */
+    *data = em_shift_in_ee_bits(hw);
+
+    /* End this read operation */
+    em_standby_eeprom(hw);
+
+    /* Stop requesting EEPROM access */
+    if(hw->mac_type > em_82544) {
+        eecd = E1000_READ_REG(hw, EECD);
+        eecd &= ~E1000_EECD_REQ;
+        E1000_WRITE_REG(hw, EECD, eecd);
+    }
+
+    return 0;
+}
+
+/******************************************************************************
+ * Verifies that the EEPROM has a valid checksum
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Reads the first 64 16 bit words of the EEPROM and sums the values read.
+ * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
+ * valid.
+ *****************************************************************************/
+int32_t
+em_validate_eeprom_checksum(struct em_hw *hw)
+{
+    uint16_t checksum = 0;
+    uint16_t i, eeprom_data;
+
+    DEBUGFUNC("em_validate_eeprom_checksum");
+
+    for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
+        if(em_read_eeprom(hw, i, &eeprom_data) < 0) {
+            DEBUGOUT("EEPROM Read Error\n");
+            return -E1000_ERR_EEPROM;
+        }
+        checksum += eeprom_data;
+    }
+
+    if(checksum == (uint16_t) EEPROM_SUM) {
+        return 0;
+    } else {
+        DEBUGOUT("EEPROM Checksum Invalid\n");    
+        return -E1000_ERR_EEPROM;
+    }
+}
+
+/******************************************************************************
+ * Reads the adapter's part number from the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ * part_num - Adapter's part number
+ *****************************************************************************/
+int32_t
+em_read_part_num(struct em_hw *hw,
+                    uint32_t *part_num)
+{
+    uint16_t offset = EEPROM_PBA_BYTE_1;
+    uint16_t eeprom_data;
+
+    DEBUGFUNC("em_read_part_num");
+
+    /* Get word 0 from EEPROM */
+    if(em_read_eeprom(hw, offset, &eeprom_data) < 0) {
+        DEBUGOUT("EEPROM Read Error\n");
+        return -E1000_ERR_EEPROM;
+    }
+    /* Save word 0 in upper half of part_num */
+    *part_num = (uint32_t) (eeprom_data << 16);
+
+    /* Get word 1 from EEPROM */
+    if(em_read_eeprom(hw, ++offset, &eeprom_data) < 0) {
+        DEBUGOUT("EEPROM Read Error\n");
+        return -E1000_ERR_EEPROM;
+    }
+    /* Save word 1 in lower half of part_num */
+    *part_num |= eeprom_data;
+
+    return 0;
+}
+
+/******************************************************************************
+ * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
+ * second function of dual function devices
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+int32_t
+em_read_mac_addr(struct em_hw * hw)
+{
+    uint16_t offset;
+    uint16_t eeprom_data, i;
+
+    DEBUGFUNC("em_read_mac_addr");
+
+    for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
+        offset = i >> 1;
+        if(em_read_eeprom(hw, offset, &eeprom_data) < 0) {
+            DEBUGOUT("EEPROM Read Error\n");
+            return -E1000_ERR_EEPROM;
+        }
+        hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
+        hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
+    }
+    if((hw->mac_type == em_82546) &&
+       (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+        if(hw->perm_mac_addr[5] & 0x01)
+            hw->perm_mac_addr[5] &= ~(0x01);
+        else
+            hw->perm_mac_addr[5] |= 0x01;
+    }
+    for(i = 0; i < NODE_ADDRESS_SIZE; i++)
+        hw->mac_addr[i] = hw->perm_mac_addr[i];
+    return 0;
+}
+
+/******************************************************************************
+ * Initializes receive address filters.
+ *
+ * hw - Struct containing variables accessed by shared code 
+ *
+ * Places the MAC address in receive address register 0 and clears the rest
+ * of the receive addresss registers. Clears the multicast table. Assumes
+ * the receiver is in reset when the routine is called.
+ *****************************************************************************/
+void
+em_init_rx_addrs(struct em_hw *hw)
+{
+    uint32_t i;
+    uint32_t addr_low;
+    uint32_t addr_high;
+
+    DEBUGFUNC("em_init_rx_addrs");
+
+    /* Setup the receive address. */
+    DEBUGOUT("Programming MAC Address into RAR[0]\n");
+    addr_low = (hw->mac_addr[0] |
+                (hw->mac_addr[1] << 8) |
+                (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
+
+    addr_high = (hw->mac_addr[4] |
+                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
+
+    E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
+    E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
+
+    /* Zero out the other 15 receive addresses. */
+    DEBUGOUT("Clearing RAR[1-15]\n");
+    for(i = 1; i < E1000_RAR_ENTRIES; i++) {
+        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+    }
+}
+
+/******************************************************************************
+ * Updates the MAC's list of multicast addresses.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * mc_addr_list - the list of new multicast addresses
+ * mc_addr_count - number of addresses
+ * pad - number of bytes between addresses in the list
+ *
+ * The given list replaces any existing list. Clears the last 15 receive
+ * address registers and the multicast table. Uses receive address registers
+ * for the first 15 multicast addresses, and hashes the rest into the 
+ * multicast table.
+ *****************************************************************************/
+void
+em_mc_addr_list_update(struct em_hw *hw,
+                          uint8_t *mc_addr_list,
+                          uint32_t mc_addr_count,
+                          uint32_t pad)
+{
+    uint32_t hash_value;
+    uint32_t i;
+    uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
+
+    DEBUGFUNC("em_mc_addr_list_update");
+
+    /* Set the new number of MC addresses that we are being requested to use. */
+    hw->num_mc_addrs = mc_addr_count;
+
+    /* Clear RAR[1-15] */
+    DEBUGOUT(" Clearing RAR[1-15]\n");
+    for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
+        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+    }
+
+    /* Clear the MTA */
+    DEBUGOUT(" Clearing MTA\n");
+    for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
+        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
+    }
+
+    /* Add the new addresses */
+    for(i = 0; i < mc_addr_count; i++) {
+        DEBUGOUT(" Adding the multicast addresses:\n");
+        DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
+                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
+                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
+                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
+                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
+                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
+                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
+
+        hash_value = em_hash_mc_addr(hw,
+                                        mc_addr_list +
+                                        (i * (ETH_LENGTH_OF_ADDRESS + pad)));
+
+        DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
+
+        /* Place this multicast address in the RAR if there is room, *
+         * else put it in the MTA            
+         */
+        if(rar_used_count < E1000_RAR_ENTRIES) {
+            em_rar_set(hw,
+                          mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
+                          rar_used_count);
+            rar_used_count++;
+        } else {
+            em_mta_set(hw, hash_value);
+        }
+    }
+    DEBUGOUT("MC Update Complete\n");
+}
+
+/******************************************************************************
+ * Hashes an address to determine its location in the multicast table
+ *
+ * hw - Struct containing variables accessed by shared code
+ * mc_addr - the multicast address to hash 
+ *****************************************************************************/
+uint32_t
+em_hash_mc_addr(struct em_hw *hw,
+                   uint8_t *mc_addr)
+{
+    uint32_t hash_value = 0;
+
+    /* The portion of the address that is used for the hash table is
+     * determined by the mc_filter_type setting.  
+     */
+    switch (hw->mc_filter_type) {
+    /* [0] [1] [2] [3] [4] [5]
+     * 01  AA  00  12  34  56
+     * LSB                 MSB
+     */
+    case 0:
+        /* [47:36] i.e. 0x563 for above example address */
+        hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
+        break;
+    case 1:
+        /* [46:35] i.e. 0xAC6 for above example address */
+        hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
+        break;
+    case 2:
+        /* [45:34] i.e. 0x5D8 for above example address */
+        hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
+        break;
+    case 3:
+        /* [43:32] i.e. 0x634 for above example address */
+        hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
+        break;
+    }
+
+    hash_value &= 0xFFF;
+    return hash_value;
+}
+
+/******************************************************************************
+ * Sets the bit in the multicast table corresponding to the hash value.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * hash_value - Multicast address hash value
+ *****************************************************************************/
+void
+em_mta_set(struct em_hw *hw,
+              uint32_t hash_value)
+{
+    uint32_t hash_bit, hash_reg;
+    uint32_t mta;
+    uint32_t temp;
+
+    /* The MTA is a register array of 128 32-bit registers.  
+     * It is treated like an array of 4096 bits.  We want to set 
+     * bit BitArray[hash_value]. So we figure out what register
+     * the bit is in, read it, OR in the new bit, then write
+     * back the new value.  The register is determined by the 
+     * upper 7 bits of the hash value and the bit within that 
+     * register are determined by the lower 5 bits of the value.
+     */
+    hash_reg = (hash_value >> 5) & 0x7F;
+    hash_bit = hash_value & 0x1F;
+
+    mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
+
+    mta |= (1 << hash_bit);
+
+    /* If we are on an 82544 and we are trying to write an odd offset
+     * in the MTA, save off the previous entry before writing and
+     * restore the old value after writing.
+     */
+    if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
+        temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
+        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
+        E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
+    } else {
+        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
+    }
+}
+
+/******************************************************************************
+ * Puts an ethernet address into a receive address register.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * addr - Address to put into receive address register
+ * index - Receive address register to write
+ *****************************************************************************/
+void
+em_rar_set(struct em_hw *hw,
+              uint8_t *addr,
+              uint32_t index)
+{
+    uint32_t rar_low, rar_high;
+
+    /* HW expects these in little endian so we reverse the byte order
+     * from network order (big endian) to little endian              
+     */
+    rar_low = ((uint32_t) addr[0] |
+               ((uint32_t) addr[1] << 8) |
+               ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
+
+    rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
+
+    E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
+    E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
+}
+
+/******************************************************************************
+ * Writes a value to the specified offset in the VLAN filter table.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - Offset in VLAN filer table to write
+ * value - Value to write into VLAN filter table
+ *****************************************************************************/
+void
+em_write_vfta(struct em_hw *hw,
+                 uint32_t offset,
+                 uint32_t value)
+{
+    uint32_t temp;
+
+    if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
+        temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
+        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
+        E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
+    } else {
+        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
+    }
+}
+
+/******************************************************************************
+ * Clears the VLAN filer table
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+em_clear_vfta(struct em_hw *hw)
+{
+    uint32_t offset;
+
+    for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
+        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
+}
+
+static int32_t
+em_id_led_init(struct em_hw * hw)
+{
+    uint32_t ledctl;
+    const uint32_t ledctl_mask = 0x000000FF;
+    const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
+    const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
+    uint16_t eeprom_data, i, temp;
+    const uint16_t led_mask = 0x0F;
+	
+    DEBUGFUNC("em_id_led_init");
+    
+    if(hw->mac_type < em_82540) {
+	/* Nothing to do */
+	return 0;
+    }
+    
+    ledctl = E1000_READ_REG(hw, LEDCTL);
+    hw->ledctl_default = ledctl;
+    hw->ledctl_mode1 = hw->ledctl_default;
+    hw->ledctl_mode2 = hw->ledctl_default;
+        
+    if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, &eeprom_data) < 0) {
+        DEBUGOUT("EEPROM Read Error\n");
+        return -E1000_ERR_EEPROM;
+    }
+    if((eeprom_data== ID_LED_RESERVED_0000) || 
+       (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
+    for(i = 0; i < 4; i++) {
+        temp = (eeprom_data >> (i << 2)) & led_mask;
+        switch(temp) {
+	case ID_LED_ON1_DEF2:
+	case ID_LED_ON1_ON2:
+	case ID_LED_ON1_OFF2:
+            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
+            hw->ledctl_mode1 |= ledctl_on << (i << 3);
+            break;
+	case ID_LED_OFF1_DEF2:
+	case ID_LED_OFF1_ON2:
+	case ID_LED_OFF1_OFF2:
+            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
+            hw->ledctl_mode1 |= ledctl_off << (i << 3);
+            break;
+	default:
+	    /* Do nothing */
+	    break;
+	}
+	switch(temp) {
+	case ID_LED_DEF1_ON2:
+	case ID_LED_ON1_ON2:
+	case ID_LED_OFF1_ON2:
+            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
+            hw->ledctl_mode2 |= ledctl_on << (i << 3);
+            break;
+	case ID_LED_DEF1_OFF2:
+	case ID_LED_ON1_OFF2:
+	case ID_LED_OFF1_OFF2:
+            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
+            hw->ledctl_mode2 |= ledctl_off << (i << 3);
+            break;
+	default:
+	    /* Do nothing */
+	    break;
+	}
+    }
+    return 0;
+}
+
+/******************************************************************************
+ * Prepares SW controlable LED for use and saves the current state of the LED.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+int32_t
+em_setup_led(struct em_hw *hw)
+{
+    uint32_t ledctl;
+ 
+    DEBUGFUNC("em_setup_led");
+   
+    switch(hw->device_id) {
+    case E1000_DEV_ID_82542:
+    case E1000_DEV_ID_82543GC_FIBER:
+    case E1000_DEV_ID_82543GC_COPPER:
+    case E1000_DEV_ID_82544EI_COPPER:
+    case E1000_DEV_ID_82544EI_FIBER:
+    case E1000_DEV_ID_82544GC_COPPER:
+    case E1000_DEV_ID_82544GC_LOM:
+        /* No setup necessary */
+        break;
+    case E1000_DEV_ID_82545EM_FIBER:
+    case E1000_DEV_ID_82546EB_FIBER:
+        ledctl = E1000_READ_REG(hw, LEDCTL);
+        /* Save current LEDCTL settings */
+        hw->ledctl_default = ledctl;
+        /* Turn off LED0 */
+        ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
+                    E1000_LEDCTL_LED0_BLINK | 
+                    E1000_LEDCTL_LED0_MODE_MASK);
+        ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
+        E1000_WRITE_REG(hw, LEDCTL, ledctl);
+        break;
+    case E1000_DEV_ID_82540EM:
+    case E1000_DEV_ID_82540EM_LOM:
+    case E1000_DEV_ID_82545EM_COPPER:
+    case E1000_DEV_ID_82546EB_COPPER:
+        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
+        break;
+    default:
+        DEBUGOUT("Invalid device ID\n");
+        return -E1000_ERR_CONFIG;
+    }
+    return 0;
+}
+
+/******************************************************************************
+ * Restores the saved state of the SW controlable LED.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+int32_t
+em_cleanup_led(struct em_hw *hw)
+{
+    DEBUGFUNC("em_cleanup_led");
+
+    switch(hw->device_id) {
+    case E1000_DEV_ID_82542:
+    case E1000_DEV_ID_82543GC_FIBER:
+    case E1000_DEV_ID_82543GC_COPPER:
+    case E1000_DEV_ID_82544EI_COPPER:
+    case E1000_DEV_ID_82544EI_FIBER:
+    case E1000_DEV_ID_82544GC_COPPER:
+    case E1000_DEV_ID_82544GC_LOM:
+        /* No cleanup necessary */
+        break;
+    case E1000_DEV_ID_82540EM:
+    case E1000_DEV_ID_82540EM_LOM:
+    case E1000_DEV_ID_82545EM_COPPER:
+    case E1000_DEV_ID_82545EM_FIBER:
+    case E1000_DEV_ID_82546EB_COPPER:
+    case E1000_DEV_ID_82546EB_FIBER:
+        /* Restore LEDCTL settings */
+        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
+        break;
+    default:
+        DEBUGOUT("Invalid device ID\n");
+        return -E1000_ERR_CONFIG;
+    }
+    return 0;
+}
+    
+/******************************************************************************
+ * Turns on the software controllable LED
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+int32_t
+em_led_on(struct em_hw *hw)
+{
+    uint32_t ctrl;
+
+    DEBUGFUNC("em_led_on");
+
+    switch(hw->device_id) {
+    case E1000_DEV_ID_82542:
+    case E1000_DEV_ID_82543GC_FIBER:
+    case E1000_DEV_ID_82543GC_COPPER:
+    case E1000_DEV_ID_82544EI_FIBER:
+        ctrl = E1000_READ_REG(hw, CTRL);
+        /* Set SW Defineable Pin 0 to turn on the LED */
+        ctrl |= E1000_CTRL_SWDPIN0;
+        ctrl |= E1000_CTRL_SWDPIO0;
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        break;
+    case E1000_DEV_ID_82544EI_COPPER:
+    case E1000_DEV_ID_82544GC_COPPER:
+    case E1000_DEV_ID_82544GC_LOM:
+    case E1000_DEV_ID_82545EM_FIBER:
+    case E1000_DEV_ID_82546EB_FIBER:
+        ctrl = E1000_READ_REG(hw, CTRL);
+        /* Clear SW Defineable Pin 0 to turn on the LED */
+        ctrl &= ~E1000_CTRL_SWDPIN0;
+        ctrl |= E1000_CTRL_SWDPIO0;
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        break;
+    case E1000_DEV_ID_82540EM:
+    case E1000_DEV_ID_82540EM_LOM:
+    case E1000_DEV_ID_82545EM_COPPER:
+    case E1000_DEV_ID_82546EB_COPPER:
+        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
+        break;
+    default:
+        DEBUGOUT("Invalid device ID\n");
+        return -E1000_ERR_CONFIG;
+    }
+    return 0;
+}
+
+/******************************************************************************
+ * Turns off the software controllable LED
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+int32_t
+em_led_off(struct em_hw *hw)
+{
+    uint32_t ctrl;
+
+    DEBUGFUNC("em_led_off");
+
+    switch(hw->device_id) {
+    case E1000_DEV_ID_82542:
+    case E1000_DEV_ID_82543GC_FIBER:
+    case E1000_DEV_ID_82543GC_COPPER:
+    case E1000_DEV_ID_82544EI_FIBER:
+        ctrl = E1000_READ_REG(hw, CTRL);
+        /* Clear SW Defineable Pin 0 to turn off the LED */
+        ctrl &= ~E1000_CTRL_SWDPIN0;
+        ctrl |= E1000_CTRL_SWDPIO0;
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        break;
+    case E1000_DEV_ID_82544EI_COPPER:
+    case E1000_DEV_ID_82544GC_COPPER:
+    case E1000_DEV_ID_82544GC_LOM:
+    case E1000_DEV_ID_82545EM_FIBER:
+    case E1000_DEV_ID_82546EB_FIBER:
+        ctrl = E1000_READ_REG(hw, CTRL);
+        /* Set SW Defineable Pin 0 to turn off the LED */
+        ctrl |= E1000_CTRL_SWDPIN0;
+        ctrl |= E1000_CTRL_SWDPIO0;
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        break;
+    case E1000_DEV_ID_82540EM:
+    case E1000_DEV_ID_82540EM_LOM:
+    case E1000_DEV_ID_82545EM_COPPER:
+    case E1000_DEV_ID_82546EB_COPPER:
+        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
+        break;
+    default:
+        DEBUGOUT("Invalid device ID\n");
+        return -E1000_ERR_CONFIG;
+    }
+    return 0;
+}
+
+/******************************************************************************
+ * Clears all hardware statistics counters. 
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+em_clear_hw_cntrs(struct em_hw *hw)
+{
+    volatile uint32_t temp;
+
+    temp = E1000_READ_REG(hw, CRCERRS);
+    temp = E1000_READ_REG(hw, SYMERRS);
+    temp = E1000_READ_REG(hw, MPC);
+    temp = E1000_READ_REG(hw, SCC);
+    temp = E1000_READ_REG(hw, ECOL);
+    temp = E1000_READ_REG(hw, MCC);
+    temp = E1000_READ_REG(hw, LATECOL);
+    temp = E1000_READ_REG(hw, COLC);
+    temp = E1000_READ_REG(hw, DC);
+    temp = E1000_READ_REG(hw, SEC);
+    temp = E1000_READ_REG(hw, RLEC);
+    temp = E1000_READ_REG(hw, XONRXC);
+    temp = E1000_READ_REG(hw, XONTXC);
+    temp = E1000_READ_REG(hw, XOFFRXC);
+    temp = E1000_READ_REG(hw, XOFFTXC);
+    temp = E1000_READ_REG(hw, FCRUC);
+    temp = E1000_READ_REG(hw, PRC64);
+    temp = E1000_READ_REG(hw, PRC127);
+    temp = E1000_READ_REG(hw, PRC255);
+    temp = E1000_READ_REG(hw, PRC511);
+    temp = E1000_READ_REG(hw, PRC1023);
+    temp = E1000_READ_REG(hw, PRC1522);
+    temp = E1000_READ_REG(hw, GPRC);
+    temp = E1000_READ_REG(hw, BPRC);
+    temp = E1000_READ_REG(hw, MPRC);
+    temp = E1000_READ_REG(hw, GPTC);
+    temp = E1000_READ_REG(hw, GORCL);
+    temp = E1000_READ_REG(hw, GORCH);
+    temp = E1000_READ_REG(hw, GOTCL);
+    temp = E1000_READ_REG(hw, GOTCH);
+    temp = E1000_READ_REG(hw, RNBC);
+    temp = E1000_READ_REG(hw, RUC);
+    temp = E1000_READ_REG(hw, RFC);
+    temp = E1000_READ_REG(hw, ROC);
+    temp = E1000_READ_REG(hw, RJC);
+    temp = E1000_READ_REG(hw, TORL);
+    temp = E1000_READ_REG(hw, TORH);
+    temp = E1000_READ_REG(hw, TOTL);
+    temp = E1000_READ_REG(hw, TOTH);
+    temp = E1000_READ_REG(hw, TPR);
+    temp = E1000_READ_REG(hw, TPT);
+    temp = E1000_READ_REG(hw, PTC64);
+    temp = E1000_READ_REG(hw, PTC127);
+    temp = E1000_READ_REG(hw, PTC255);
+    temp = E1000_READ_REG(hw, PTC511);
+    temp = E1000_READ_REG(hw, PTC1023);
+    temp = E1000_READ_REG(hw, PTC1522);
+    temp = E1000_READ_REG(hw, MPTC);
+    temp = E1000_READ_REG(hw, BPTC);
+
+    if(hw->mac_type < em_82543) return;
+
+    temp = E1000_READ_REG(hw, ALGNERRC);
+    temp = E1000_READ_REG(hw, RXERRC);
+    temp = E1000_READ_REG(hw, TNCRS);
+    temp = E1000_READ_REG(hw, CEXTERR);
+    temp = E1000_READ_REG(hw, TSCTC);
+    temp = E1000_READ_REG(hw, TSCTFC);
+
+    if(hw->mac_type <= em_82544) return;
+
+    temp = E1000_READ_REG(hw, MGTPRC);
+    temp = E1000_READ_REG(hw, MGTPDC);
+    temp = E1000_READ_REG(hw, MGTPTC);
+}
+
+/******************************************************************************
+ * Resets Adaptive IFS to its default state.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Call this after em_init_hw. You may override the IFS defaults by setting
+ * hw->ifs_params_forced to TRUE. However, you must initialize hw->
+ * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
+ * before calling this function.
+ *****************************************************************************/
+void
+em_reset_adaptive(struct em_hw *hw)
+{
+    DEBUGFUNC("em_reset_adaptive");
+
+    if(hw->adaptive_ifs) {
+        if(!hw->ifs_params_forced) {
+            hw->current_ifs_val = 0;
+            hw->ifs_min_val = IFS_MIN;
+            hw->ifs_max_val = IFS_MAX;
+            hw->ifs_step_size = IFS_STEP;
+            hw->ifs_ratio = IFS_RATIO;
+        }
+        hw->in_ifs_mode = FALSE;
+        E1000_WRITE_REG(hw, AIT, 0);
+    } else {
+        DEBUGOUT("Not in Adaptive IFS mode!\n");
+    }
+}
+
+/******************************************************************************
+ * Called during the callback/watchdog routine to update IFS value based on
+ * the ratio of transmits to collisions.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * tx_packets - Number of transmits since last callback
+ * total_collisions - Number of collisions since last callback
+ *****************************************************************************/
+void
+em_update_adaptive(struct em_hw *hw)
+{
+    DEBUGFUNC("em_update_adaptive");
+
+    if(hw->adaptive_ifs) {
+        if((hw->collision_delta * hw->ifs_ratio) > 
+           hw->tx_packet_delta) {
+            if(hw->tx_packet_delta > MIN_NUM_XMITS) {
+                hw->in_ifs_mode = TRUE;
+                if(hw->current_ifs_val < hw->ifs_max_val) {
+                    if(hw->current_ifs_val == 0)
+                        hw->current_ifs_val = hw->ifs_min_val;
+                    else
+                        hw->current_ifs_val += hw->ifs_step_size;
+                    E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
+                }
+            }
+        } else {
+            if((hw->in_ifs_mode == TRUE) && 
+               (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
+                hw->current_ifs_val = 0;
+                hw->in_ifs_mode = FALSE;
+                E1000_WRITE_REG(hw, AIT, 0);
+            }
+        }
+    } else {
+        DEBUGOUT("Not in Adaptive IFS mode!\n");
+    }
+}
+
+/******************************************************************************
+ * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
+ * 
+ * hw - Struct containing variables accessed by shared code
+ * frame_len - The length of the frame in question
+ * mac_addr - The Ethernet destination address of the frame in question
+ *****************************************************************************/
+void
+em_tbi_adjust_stats(struct em_hw *hw,
+                       struct em_hw_stats *stats,
+                       uint32_t frame_len,
+                       uint8_t *mac_addr)
+{
+    uint64_t carry_bit;
+
+    /* First adjust the frame length. */
+    frame_len--;
+    /* We need to adjust the statistics counters, since the hardware
+     * counters overcount this packet as a CRC error and undercount
+     * the packet as a good packet
+     */
+    /* This packet should not be counted as a CRC error.    */
+    stats->crcerrs--;
+    /* This packet does count as a Good Packet Received.    */
+    stats->gprc++;
+
+    /* Adjust the Good Octets received counters             */
+    carry_bit = 0x80000000 & stats->gorcl;
+    stats->gorcl += frame_len;
+    /* If the high bit of Gorcl (the low 32 bits of the Good Octets
+     * Received Count) was one before the addition, 
+     * AND it is zero after, then we lost the carry out, 
+     * need to add one to Gorch (Good Octets Received Count High).
+     * This could be simplified if all environments supported 
+     * 64-bit integers.
+     */
+    if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
+        stats->gorch++;
+    /* Is this a broadcast or multicast?  Check broadcast first,
+     * since the test for a multicast frame will test positive on 
+     * a broadcast frame.
+     */
+    if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
+        /* Broadcast packet */
+        stats->bprc++;
+    else if(*mac_addr & 0x01)
+        /* Multicast packet */
+        stats->mprc++;
+
+    if(frame_len == hw->max_frame_size) {
+        /* In this case, the hardware has overcounted the number of
+         * oversize frames.
+         */
+        if(stats->roc > 0)
+            stats->roc--;
+    }
+
+    /* Adjust the bin counters when the extra byte put the frame in the
+     * wrong bin. Remember that the frame_len was adjusted above.
+     */
+    if(frame_len == 64) {
+        stats->prc64++;
+        stats->prc127--;
+    } else if(frame_len == 127) {
+        stats->prc127++;
+        stats->prc255--;
+    } else if(frame_len == 255) {
+        stats->prc255++;
+        stats->prc511--;
+    } else if(frame_len == 511) {
+        stats->prc511++;
+        stats->prc1023--;
+    } else if(frame_len == 1023) {
+        stats->prc1023++;
+        stats->prc1522--;
+    } else if(frame_len == 1522) {
+        stats->prc1522++;
+    }
+}
+
+/******************************************************************************
+ * Gets the current PCI bus type, speed, and width of the hardware
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+void
+em_get_bus_info(struct em_hw *hw)
+{
+    uint32_t status;
+
+    if(hw->mac_type < em_82543) {
+        hw->bus_type = em_bus_type_unknown;
+        hw->bus_speed = em_bus_speed_unknown;
+        hw->bus_width = em_bus_width_unknown;
+        return;
+    }
+
+    status = E1000_READ_REG(hw, STATUS);
+    hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
+                   em_bus_type_pcix : em_bus_type_pci;
+    if(hw->bus_type == em_bus_type_pci) {
+        hw->bus_speed = (status & E1000_STATUS_PCI66) ?
+                        em_bus_speed_66 : em_bus_speed_33;
+    } else {
+        switch (status & E1000_STATUS_PCIX_SPEED) {
+        case E1000_STATUS_PCIX_SPEED_66:
+            hw->bus_speed = em_bus_speed_66;
+            break;
+        case E1000_STATUS_PCIX_SPEED_100:
+            hw->bus_speed = em_bus_speed_100;
+            break;
+        case E1000_STATUS_PCIX_SPEED_133:
+            hw->bus_speed = em_bus_speed_133;
+            break;
+        default:
+            hw->bus_speed = em_bus_speed_reserved;
+            break;
+        }
+    }
+    hw->bus_width = (status & E1000_STATUS_BUS64) ?
+                    em_bus_width_64 : em_bus_width_32;
+}
+
diff --git a/sys/dev/em/if_em_hw.h b/sys/dev/em/if_em_hw.h
new file mode 100644
index 0000000..2daca23
--- /dev/null
+++ b/sys/dev/em/if_em_hw.h
@@ -0,0 +1,1756 @@
+/*******************************************************************************
+
+  Copyright (c) 2001-2002 Intel Corporation 
+  All rights reserved. 
+  
+  Redistribution and use in source and binary forms of the Software, with or 
+  without modification, are permitted provided that the following conditions 
+  are met: 
+  
+   1. Redistributions of source code of the Software may retain the above 
+      copyright notice, this list of conditions and the following disclaimer.
+   
+   2. Redistributions in binary form of the Software may reproduce the above 
+      copyright notice, this list of conditions and the following disclaimer 
+      in the documentation and/or other materials provided with the 
+      distribution. 
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors shall be used to endorse or promote products derived from 
+      this Software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS CONTRIBUTORS BE LIABLE 
+  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
+  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+  SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*$FreeBSD$*/
+/* if_em_hw.h
+ * Structures, enums, and macros for the MAC
+ */
+
+#ifndef _EM_HW_H_
+#define _EM_HW_H_
+
+#include <dev/em/if_em_osdep.h>
+
+/* Forward declarations of structures used by the shared code */
+struct em_hw;
+struct em_hw_stats;
+
+/* Enumerated types specific to the e1000 hardware */
+/* Media Access Controlers */
+typedef enum {
+    em_82542_rev2_0 = 0,
+    em_82542_rev2_1,
+    em_82543,
+    em_82544,
+    em_82540,
+    em_82545,
+    em_82546,
+    em_num_macs
+} em_mac_type;
+
+/* Media Types */
+typedef enum {
+    em_media_type_copper = 0,
+    em_media_type_fiber = 1,
+    em_num_media_types
+} em_media_type;
+
+typedef enum {
+    em_10_half = 0,
+    em_10_full = 1,
+    em_100_half = 2,
+    em_100_full = 3
+} em_speed_duplex_type;
+
+/* Flow Control Settings */
+typedef enum {
+    em_fc_none = 0,
+    em_fc_rx_pause = 1,
+    em_fc_tx_pause = 2,
+    em_fc_full = 3,
+    em_fc_default = 0xFF
+} em_fc_type;
+
+/* PCI bus types */
+typedef enum {
+    em_bus_type_unknown = 0,
+    em_bus_type_pci,
+    em_bus_type_pcix
+} em_bus_type;
+
+/* PCI bus speeds */
+typedef enum {
+    em_bus_speed_unknown = 0,
+    em_bus_speed_33,
+    em_bus_speed_66,
+    em_bus_speed_100,
+    em_bus_speed_133,
+    em_bus_speed_reserved
+} em_bus_speed;
+
+/* PCI bus widths */
+typedef enum {
+    em_bus_width_unknown = 0,
+    em_bus_width_32,
+    em_bus_width_64
+} em_bus_width;
+
+/* PHY status info structure and supporting enums */
+typedef enum {
+    em_cable_length_50 = 0,
+    em_cable_length_50_80,
+    em_cable_length_80_110,
+    em_cable_length_110_140,
+    em_cable_length_140,
+    em_cable_length_undefined = 0xFF
+} em_cable_length;
+
+typedef enum {
+    em_10bt_ext_dist_enable_normal = 0,
+    em_10bt_ext_dist_enable_lower,
+    em_10bt_ext_dist_enable_undefined = 0xFF
+} em_10bt_ext_dist_enable;
+
+typedef enum {
+    em_rev_polarity_normal = 0,
+    em_rev_polarity_reversed,
+    em_rev_polarity_undefined = 0xFF
+} em_rev_polarity;
+
+typedef enum {
+    em_polarity_reversal_enabled = 0,
+    em_polarity_reversal_disabled,
+    em_polarity_reversal_undefined = 0xFF
+} em_polarity_reversal;
+
+typedef enum {
+    em_auto_x_mode_manual_mdi = 0,
+    em_auto_x_mode_manual_mdix,
+    em_auto_x_mode_auto1,
+    em_auto_x_mode_auto2,
+    em_auto_x_mode_undefined = 0xFF
+} em_auto_x_mode;
+
+typedef enum {
+    em_1000t_rx_status_not_ok = 0,
+    em_1000t_rx_status_ok,
+    em_1000t_rx_status_undefined = 0xFF
+} em_1000t_rx_status;
+
+struct em_phy_info {
+    em_cable_length cable_length;
+    em_10bt_ext_dist_enable extended_10bt_distance;
+    em_rev_polarity cable_polarity;
+    em_polarity_reversal polarity_correction;
+    em_auto_x_mode mdix_mode;
+    em_1000t_rx_status local_rx;
+    em_1000t_rx_status remote_rx;
+};
+
+struct em_phy_stats {
+    uint32_t idle_errors;
+    uint32_t receive_errors;
+};
+
+
+
+/* Error Codes */
+#define E1000_SUCCESS    0
+#define E1000_ERR_EEPROM 1
+#define E1000_ERR_PHY    2
+#define E1000_ERR_CONFIG 3
+#define E1000_ERR_PARAM  4
+
+/* Function prototypes */
+/* Initialization */
+void em_reset_hw(struct em_hw *hw);
+int32_t em_init_hw(struct em_hw *hw);
+
+/* Link Configuration */
+int32_t em_setup_link(struct em_hw *hw);
+int32_t em_phy_setup_autoneg(struct em_hw *hw);
+void em_config_collision_dist(struct em_hw *hw);
+int32_t em_config_fc_after_link_up(struct em_hw *hw);
+int32_t em_check_for_link(struct em_hw *hw);
+void em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex);
+int32_t em_wait_autoneg(struct em_hw *hw);
+
+/* PHY */
+int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
+int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
+void em_phy_hw_reset(struct em_hw *hw);
+int32_t em_phy_reset(struct em_hw *hw);
+int32_t em_detect_gig_phy(struct em_hw *hw);
+int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
+int32_t em_validate_mdi_setting(struct em_hw *hw);
+
+/* EEPROM Functions */
+int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t *data);
+int32_t em_validate_eeprom_checksum(struct em_hw *hw);
+int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);
+int32_t em_read_mac_addr(struct em_hw * hw);
+
+/* Filters (multicast, vlan, receive) */
+void em_init_rx_addrs(struct em_hw *hw);
+void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad);
+uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr);
+void em_mta_set(struct em_hw *hw, uint32_t hash_value);
+void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
+void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value);
+void em_clear_vfta(struct em_hw *hw);
+
+/* LED functions */
+int32_t em_setup_led(struct em_hw *hw);
+int32_t em_cleanup_led(struct em_hw *hw);
+int32_t em_led_on(struct em_hw *hw);
+int32_t em_led_off(struct em_hw *hw);
+
+/* Adaptive IFS Functions */
+
+/* Everything else */
+void em_clear_hw_cntrs(struct em_hw *hw);
+void em_reset_adaptive(struct em_hw *hw);
+void em_update_adaptive(struct em_hw *hw);
+void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
+void em_get_bus_info(struct em_hw *hw);
+void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
+
+/* PCI Device IDs */
+#define E1000_DEV_ID_82542          0x1000
+#define E1000_DEV_ID_82543GC_FIBER  0x1001
+#define E1000_DEV_ID_82543GC_COPPER 0x1004
+#define E1000_DEV_ID_82544EI_COPPER 0x1008
+#define E1000_DEV_ID_82544EI_FIBER  0x1009
+#define E1000_DEV_ID_82544GC_COPPER 0x100C
+#define E1000_DEV_ID_82544GC_LOM    0x100D
+#define E1000_DEV_ID_82540EM        0x100E
+#define E1000_DEV_ID_82540EM_LOM    0x1015
+#define E1000_DEV_ID_82545EM_COPPER 0x100F
+#define E1000_DEV_ID_82545EM_FIBER  0x1011
+#define E1000_DEV_ID_82546EB_COPPER 0x1010
+#define E1000_DEV_ID_82546EB_FIBER  0x1012
+#define NUM_DEV_IDS 13
+
+#define NODE_ADDRESS_SIZE 6
+#define ETH_LENGTH_OF_ADDRESS 6
+
+/* MAC decode size is 128K - This is the size of BAR0 */
+#define MAC_DECODE_SIZE (128 * 1024)
+
+#define E1000_82542_2_0_REV_ID 2
+#define E1000_82542_2_1_REV_ID 3
+
+#define SPEED_10    10
+#define SPEED_100   100
+#define SPEED_1000  1000
+#define HALF_DUPLEX 1
+#define FULL_DUPLEX 2
+
+/* The sizes (in bytes) of a ethernet packet */
+#define ENET_HEADER_SIZE             14
+#define MAXIMUM_ETHERNET_FRAME_SIZE  1518 /* With FCS */
+#define MINIMUM_ETHERNET_FRAME_SIZE  64   /* With FCS */
+#define ETHERNET_FCS_SIZE            4
+#define MAXIMUM_ETHERNET_PACKET_SIZE \
+    (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
+#define MINIMUM_ETHERNET_PACKET_SIZE \
+    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
+#define CRC_LENGTH                   ETHERNET_FCS_SIZE
+#define MAX_JUMBO_FRAME_SIZE         0x3F00
+
+
+/* 802.1q VLAN Packet Sizes */
+#define VLAN_TAG_SIZE                     4     /* 802.3ac tag (not DMAed) */
+
+/* Ethertype field values */
+#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
+#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
+#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
+
+/* Packet Header defines */
+#define IP_PROTOCOL_TCP    6
+#define IP_PROTOCOL_UDP    0x11
+
+/* This defines the bits that are set in the Interrupt Mask
+ * Set/Read Register.  Each bit is documented below:
+ *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
+ *   o RXSEQ  = Receive Sequence Error 
+ */
+#define POLL_IMS_ENABLE_MASK ( \
+    E1000_IMS_RXDMT0 |         \
+    E1000_IMS_RXSEQ)
+
+/* This defines the bits that are set in the Interrupt Mask
+ * Set/Read Register.  Each bit is documented below:
+ *   o RXT0   = Receiver Timer Interrupt (ring 0)
+ *   o TXDW   = Transmit Descriptor Written Back
+ *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
+ *   o RXSEQ  = Receive Sequence Error
+ *   o LSC    = Link Status Change
+ */
+#define IMS_ENABLE_MASK ( \
+    E1000_IMS_RXT0   |    \
+    E1000_IMS_TXDW   |    \
+    E1000_IMS_RXDMT0 |    \
+    E1000_IMS_RXSEQ  |    \
+    E1000_IMS_LSC)
+
+/* The number of high/low register pairs in the RAR. The RAR (Receive Address
+ * Registers) holds the directed and multicast addresses that we monitor. We
+ * reserve one of these spots for our directed address, allowing us room for
+ * E1000_RAR_ENTRIES - 1 multicast addresses. 
+ */
+#define E1000_RAR_ENTRIES 16
+
+#define MIN_NUMBER_OF_DESCRIPTORS 8
+#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
+
+/* Receive Descriptor */
+struct em_rx_desc {
+    uint64_t buffer_addr; /* Address of the descriptor's data buffer */
+    uint16_t length;     /* Length of data DMAed into data buffer */
+    uint16_t csum;       /* Packet checksum */
+    uint8_t status;      /* Descriptor status */
+    uint8_t errors;      /* Descriptor Errors */
+    uint16_t special;
+};
+
+/* Receive Decriptor bit definitions */
+#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
+#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
+#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
+#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
+#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
+#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
+#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
+#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
+#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
+#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
+#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
+#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
+#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
+#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
+#define E1000_RXD_SPC_PRI_SHIFT 0x000D  /* Priority is in upper 3 of 16 */
+#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
+#define E1000_RXD_SPC_CFI_SHIFT 0x000C  /* CFI is bit 12 */
+
+/* mask to determine if packets should be dropped due to frame errors */
+#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
+    E1000_RXD_ERR_CE  |                \
+    E1000_RXD_ERR_SE  |                \
+    E1000_RXD_ERR_SEQ |                \
+    E1000_RXD_ERR_CXE |                \
+    E1000_RXD_ERR_RXE)
+
+/* Transmit Descriptor */
+struct em_tx_desc {
+    uint64_t buffer_addr;       /* Address of the descriptor's data buffer */
+    union {
+        uint32_t data;
+        struct {
+            uint16_t length;    /* Data buffer length */
+            uint8_t cso;        /* Checksum offset */
+            uint8_t cmd;        /* Descriptor control */
+        } flags;
+    } lower;
+    union {
+        uint32_t data;
+        struct {
+            uint8_t status;     /* Descriptor status */
+            uint8_t css;        /* Checksum start */
+            uint16_t special;
+        } fields;
+    } upper;
+};
+
+/* Transmit Descriptor bit definitions */
+#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
+#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
+#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
+#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
+#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
+#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
+#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
+#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
+#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
+#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
+#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
+#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
+#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
+#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+
+/* Offload Context Descriptor */
+struct em_context_desc {
+    union {
+        uint32_t ip_config;
+        struct {
+            uint8_t ipcss;      /* IP checksum start */
+            uint8_t ipcso;      /* IP checksum offset */
+            uint16_t ipcse;     /* IP checksum end */
+        } ip_fields;
+    } lower_setup;
+    union {
+        uint32_t tcp_config;
+        struct {
+            uint8_t tucss;      /* TCP checksum start */
+            uint8_t tucso;      /* TCP checksum offset */
+            uint16_t tucse;     /* TCP checksum end */
+        } tcp_fields;
+    } upper_setup;
+    uint32_t cmd_and_length;    /* */
+    union {
+        uint32_t data;
+        struct {
+            uint8_t status;     /* Descriptor status */
+            uint8_t hdr_len;    /* Header length */
+            uint16_t mss;       /* Maximum segment size */
+        } fields;
+    } tcp_seg_setup;
+};
+
+/* Offload data descriptor */
+struct em_data_desc {
+    uint64_t buffer_addr;       /* Address of the descriptor's buffer address */
+    union {
+        uint32_t data;
+        struct {
+            uint16_t length;    /* Data buffer length */
+            uint8_t typ_len_ext;        /* */
+            uint8_t cmd;        /* */
+        } flags;
+    } lower;
+    union {
+        uint32_t data;
+        struct {
+            uint8_t status;     /* Descriptor status */
+            uint8_t popts;      /* Packet Options */
+            uint16_t special;   /* */
+        } fields;
+    } upper;
+};
+
+/* Filters */
+#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
+#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
+#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
+
+
+/* Receive Address Register */
+struct em_rar {
+    volatile uint32_t low;      /* receive address low */
+    volatile uint32_t high;     /* receive address high */
+};
+
+/* The number of entries in the Multicast Table Array (MTA). */
+#define E1000_NUM_MTA_REGISTERS 128
+
+/* IPv4 Address Table Entry */
+struct em_ipv4_at_entry {
+    volatile uint32_t ipv4_addr;        /* IP Address (RW) */
+    volatile uint32_t reserved;
+};
+
+/* Four wakeup IP addresses are supported */
+#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
+#define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
+#define E1000_IP6AT_SIZE                  1
+
+/* IPv6 Address Table Entry */
+struct em_ipv6_at_entry {
+    volatile uint8_t ipv6_addr[16];
+};
+
+/* Flexible Filter Length Table Entry */
+struct em_fflt_entry {
+    volatile uint32_t length;   /* Flexible Filter Length (RW) */
+    volatile uint32_t reserved;
+};
+
+/* Flexible Filter Mask Table Entry */
+struct em_ffmt_entry {
+    volatile uint32_t mask;     /* Flexible Filter Mask (RW) */
+    volatile uint32_t reserved;
+};
+
+/* Flexible Filter Value Table Entry */
+struct em_ffvt_entry {
+    volatile uint32_t value;    /* Flexible Filter Value (RW) */
+    volatile uint32_t reserved;
+};
+
+/* Four Flexible Filters are supported */
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
+
+/* Each Flexible Filter is at most 128 (0x80) bytes in length */
+#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
+
+#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
+#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+
+/* Register Set. (82543, 82544)
+ *
+ * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
+ * These registers are physically located on the NIC, but are mapped into the 
+ * host memory address space.
+ *
+ * RW - register is both readable and writable
+ * RO - register is read only
+ * WO - register is write only
+ * R/clr - register is read only and is cleared when read
+ * A - register array
+ */
+#define E1000_CTRL     0x00000  /* Device Control - RW */
+#define E1000_STATUS   0x00008  /* Device Status - RO */
+#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
+#define E1000_EERD     0x00014  /* EEPROM Read - RW */
+#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
+#define E1000_MDIC     0x00020  /* MDI Control - RW */
+#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
+#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
+#define E1000_FCT      0x00030  /* Flow Control Type - RW */
+#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
+#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
+#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
+#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
+#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
+#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
+#define E1000_RCTL     0x00100  /* RX Control - RW */
+#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
+#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
+#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
+#define E1000_TCTL     0x00400  /* TX Control - RW */
+#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
+#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
+#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
+#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
+#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
+#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
+#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
+#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
+#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
+#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
+#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
+#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
+#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
+#define E1000_RXDCTL   0x02828  /* RX Descriptor Control - RW */
+#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
+#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
+#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
+#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
+#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
+#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
+#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
+#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
+#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
+#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
+#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
+#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
+#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
+#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
+#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
+#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
+#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
+#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
+#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
+#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
+#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
+#define E1000_COLC     0x04028  /* Collision Count - R/clr */
+#define E1000_DC       0x04030  /* Defer Count - R/clr */
+#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
+#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
+#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
+#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
+#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
+#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
+#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
+#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
+#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
+#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
+#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
+#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
+#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
+#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
+#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
+#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
+#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
+#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
+#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
+#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
+#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
+#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
+#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
+#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
+#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
+#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
+#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
+#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
+#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
+#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
+#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
+#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
+#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
+#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
+#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
+#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
+#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
+#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
+#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
+#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
+#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
+#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
+#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
+#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
+#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
+#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
+#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
+#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
+#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
+#define E1000_RA       0x05400  /* Receive Address - RW Array */
+#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
+#define E1000_WUC      0x05800  /* Wakeup Control - RW */
+#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
+#define E1000_WUS      0x05810  /* Wakeup Status - RO */
+#define E1000_MANC     0x05820  /* Management Control - RW */
+#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
+#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
+#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
+#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
+#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
+#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
+#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
+#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
+
+/* Register Set (82542)
+ *
+ * Some of the 82542 registers are located at different offsets than they are
+ * in more current versions of the 8254x. Despite the difference in location,
+ * the registers function in the same manner.
+ */
+#define E1000_82542_CTRL     E1000_CTRL
+#define E1000_82542_STATUS   E1000_STATUS
+#define E1000_82542_EECD     E1000_EECD
+#define E1000_82542_EERD     E1000_EERD
+#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
+#define E1000_82542_MDIC     E1000_MDIC
+#define E1000_82542_FCAL     E1000_FCAL
+#define E1000_82542_FCAH     E1000_FCAH
+#define E1000_82542_FCT      E1000_FCT
+#define E1000_82542_VET      E1000_VET
+#define E1000_82542_RA       0x00040
+#define E1000_82542_ICR      E1000_ICR
+#define E1000_82542_ITR      E1000_ITR
+#define E1000_82542_ICS      E1000_ICS
+#define E1000_82542_IMS      E1000_IMS
+#define E1000_82542_IMC      E1000_IMC
+#define E1000_82542_RCTL     E1000_RCTL
+#define E1000_82542_RDTR     0x00108
+#define E1000_82542_RDBAL    0x00110
+#define E1000_82542_RDBAH    0x00114
+#define E1000_82542_RDLEN    0x00118
+#define E1000_82542_RDH      0x00120
+#define E1000_82542_RDT      0x00128
+#define E1000_82542_FCRTH    0x00160
+#define E1000_82542_FCRTL    0x00168
+#define E1000_82542_FCTTV    E1000_FCTTV
+#define E1000_82542_TXCW     E1000_TXCW
+#define E1000_82542_RXCW     E1000_RXCW
+#define E1000_82542_MTA      0x00200
+#define E1000_82542_TCTL     E1000_TCTL
+#define E1000_82542_TIPG     E1000_TIPG
+#define E1000_82542_TDBAL    0x00420
+#define E1000_82542_TDBAH    0x00424
+#define E1000_82542_TDLEN    0x00428
+#define E1000_82542_TDH      0x00430
+#define E1000_82542_TDT      0x00438
+#define E1000_82542_TIDV     0x00440
+#define E1000_82542_TBT      E1000_TBT
+#define E1000_82542_AIT      E1000_AIT
+#define E1000_82542_VFTA     0x00600
+#define E1000_82542_LEDCTL   E1000_LEDCTL
+#define E1000_82542_PBA      E1000_PBA
+#define E1000_82542_RXDCTL   E1000_RXDCTL
+#define E1000_82542_RADV     E1000_RADV
+#define E1000_82542_RSRPD    E1000_RSRPD
+#define E1000_82542_TXDMAC   E1000_TXDMAC
+#define E1000_82542_TXDCTL   E1000_TXDCTL
+#define E1000_82542_TADV     E1000_TADV
+#define E1000_82542_TSPMT    E1000_TSPMT
+#define E1000_82542_CRCERRS  E1000_CRCERRS
+#define E1000_82542_ALGNERRC E1000_ALGNERRC
+#define E1000_82542_SYMERRS  E1000_SYMERRS
+#define E1000_82542_RXERRC   E1000_RXERRC
+#define E1000_82542_MPC      E1000_MPC
+#define E1000_82542_SCC      E1000_SCC
+#define E1000_82542_ECOL     E1000_ECOL
+#define E1000_82542_MCC      E1000_MCC
+#define E1000_82542_LATECOL  E1000_LATECOL
+#define E1000_82542_COLC     E1000_COLC
+#define E1000_82542_DC       E1000_DC
+#define E1000_82542_TNCRS    E1000_TNCRS
+#define E1000_82542_SEC      E1000_SEC
+#define E1000_82542_CEXTERR  E1000_CEXTERR
+#define E1000_82542_RLEC     E1000_RLEC
+#define E1000_82542_XONRXC   E1000_XONRXC
+#define E1000_82542_XONTXC   E1000_XONTXC
+#define E1000_82542_XOFFRXC  E1000_XOFFRXC
+#define E1000_82542_XOFFTXC  E1000_XOFFTXC
+#define E1000_82542_FCRUC    E1000_FCRUC
+#define E1000_82542_PRC64    E1000_PRC64
+#define E1000_82542_PRC127   E1000_PRC127
+#define E1000_82542_PRC255   E1000_PRC255
+#define E1000_82542_PRC511   E1000_PRC511
+#define E1000_82542_PRC1023  E1000_PRC1023
+#define E1000_82542_PRC1522  E1000_PRC1522
+#define E1000_82542_GPRC     E1000_GPRC
+#define E1000_82542_BPRC     E1000_BPRC
+#define E1000_82542_MPRC     E1000_MPRC
+#define E1000_82542_GPTC     E1000_GPTC
+#define E1000_82542_GORCL    E1000_GORCL
+#define E1000_82542_GORCH    E1000_GORCH
+#define E1000_82542_GOTCL    E1000_GOTCL
+#define E1000_82542_GOTCH    E1000_GOTCH
+#define E1000_82542_RNBC     E1000_RNBC
+#define E1000_82542_RUC      E1000_RUC
+#define E1000_82542_RFC      E1000_RFC
+#define E1000_82542_ROC      E1000_ROC
+#define E1000_82542_RJC      E1000_RJC
+#define E1000_82542_MGTPRC   E1000_MGTPRC
+#define E1000_82542_MGTPDC   E1000_MGTPDC
+#define E1000_82542_MGTPTC   E1000_MGTPTC
+#define E1000_82542_TORL     E1000_TORL
+#define E1000_82542_TORH     E1000_TORH
+#define E1000_82542_TOTL     E1000_TOTL
+#define E1000_82542_TOTH     E1000_TOTH
+#define E1000_82542_TPR      E1000_TPR
+#define E1000_82542_TPT      E1000_TPT
+#define E1000_82542_PTC64    E1000_PTC64
+#define E1000_82542_PTC127   E1000_PTC127
+#define E1000_82542_PTC255   E1000_PTC255
+#define E1000_82542_PTC511   E1000_PTC511
+#define E1000_82542_PTC1023  E1000_PTC1023
+#define E1000_82542_PTC1522  E1000_PTC1522
+#define E1000_82542_MPTC     E1000_MPTC
+#define E1000_82542_BPTC     E1000_BPTC
+#define E1000_82542_TSCTC    E1000_TSCTC
+#define E1000_82542_TSCTFC   E1000_TSCTFC
+#define E1000_82542_RXCSUM   E1000_RXCSUM
+#define E1000_82542_WUC      E1000_WUC
+#define E1000_82542_WUFC     E1000_WUFC
+#define E1000_82542_WUS      E1000_WUS
+#define E1000_82542_MANC     E1000_MANC
+#define E1000_82542_IPAV     E1000_IPAV
+#define E1000_82542_IP4AT    E1000_IP4AT
+#define E1000_82542_IP6AT    E1000_IP6AT
+#define E1000_82542_WUPL     E1000_WUPL
+#define E1000_82542_WUPM     E1000_WUPM
+#define E1000_82542_FFLT     E1000_FFLT
+#define E1000_82542_FFMT     E1000_FFMT
+#define E1000_82542_FFVT     E1000_FFVT
+
+/* Statistics counters collected by the MAC */
+struct em_hw_stats {
+    uint64_t crcerrs;
+    uint64_t algnerrc;
+    uint64_t symerrs;
+    uint64_t rxerrc;
+    uint64_t mpc;
+    uint64_t scc;
+    uint64_t ecol;
+    uint64_t mcc;
+    uint64_t latecol;
+    uint64_t colc;
+    uint64_t dc;
+    uint64_t tncrs;
+    uint64_t sec;
+    uint64_t cexterr;
+    uint64_t rlec;
+    uint64_t xonrxc;
+    uint64_t xontxc;
+    uint64_t xoffrxc;
+    uint64_t xofftxc;
+    uint64_t fcruc;
+    uint64_t prc64;
+    uint64_t prc127;
+    uint64_t prc255;
+    uint64_t prc511;
+    uint64_t prc1023;
+    uint64_t prc1522;
+    uint64_t gprc;
+    uint64_t bprc;
+    uint64_t mprc;
+    uint64_t gptc;
+    uint64_t gorcl;
+    uint64_t gorch;
+    uint64_t gotcl;
+    uint64_t gotch;
+    uint64_t rnbc;
+    uint64_t ruc;
+    uint64_t rfc;
+    uint64_t roc;
+    uint64_t rjc;
+    uint64_t mgprc;
+    uint64_t mgpdc;
+    uint64_t mgptc;
+    uint64_t torl;
+    uint64_t torh;
+    uint64_t totl;
+    uint64_t toth;
+    uint64_t tpr;
+    uint64_t tpt;
+    uint64_t ptc64;
+    uint64_t ptc127;
+    uint64_t ptc255;
+    uint64_t ptc511;
+    uint64_t ptc1023;
+    uint64_t ptc1522;
+    uint64_t mptc;
+    uint64_t bptc;
+    uint64_t tsctc;
+    uint64_t tsctfc;
+};
+
+/* Structure containing variables used by the shared code (em_hw.c) */
+struct em_hw {
+    uint8_t *hw_addr;
+    em_mac_type mac_type;
+    em_media_type media_type;
+    void *back;
+    em_fc_type fc;
+    em_bus_speed bus_speed;
+    em_bus_width bus_width;
+    em_bus_type bus_type;
+    uint32_t phy_id;
+    uint32_t phy_addr;
+    uint32_t original_fc;
+    uint32_t txcw;
+    uint32_t autoneg_failed;
+    uint32_t max_frame_size;
+    uint32_t min_frame_size;
+    uint32_t mc_filter_type;
+    uint32_t num_mc_addrs;
+    uint32_t collision_delta;
+    uint32_t tx_packet_delta;
+    uint32_t ledctl_default;
+    uint32_t ledctl_mode1;
+    uint32_t ledctl_mode2;
+    uint16_t autoneg_advertised;
+    uint16_t pci_cmd_word;
+    uint16_t fc_high_water;
+    uint16_t fc_low_water;
+    uint16_t fc_pause_time;
+    uint16_t current_ifs_val;
+    uint16_t ifs_min_val;
+    uint16_t ifs_max_val;
+    uint16_t ifs_step_size;
+    uint16_t ifs_ratio;
+    uint16_t device_id;
+    uint16_t vendor_id;
+    uint16_t subsystem_id;
+    uint16_t subsystem_vendor_id;
+    uint8_t revision_id;
+    uint8_t autoneg;
+    uint8_t mdix;
+    uint8_t forced_speed_duplex;
+    uint8_t wait_autoneg_complete;
+    uint8_t dma_fairness;
+    uint8_t mac_addr[NODE_ADDRESS_SIZE];
+    uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
+    boolean_t disable_polarity_correction;
+    boolean_t get_link_status;
+    boolean_t tbi_compatibility_en;
+    boolean_t tbi_compatibility_on;
+    boolean_t fc_send_xon;
+    boolean_t report_tx_early;
+    boolean_t adaptive_ifs;
+    boolean_t ifs_params_forced;
+    boolean_t in_ifs_mode;
+};
+
+
+#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
+#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
+
+/* Register Bit Masks */
+/* Device Control */
+#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
+#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
+#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
+#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
+#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
+#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
+#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
+#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
+#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
+#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
+#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
+#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
+#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
+#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
+#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
+#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
+#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
+#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
+#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
+#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
+#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
+#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
+#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
+#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
+#define E1000_CTRL_RST      0x04000000  /* Global reset */
+#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
+#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
+#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
+#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
+#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
+
+/* Device Status */
+#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
+#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
+#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
+#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
+#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
+#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
+#define E1000_STATUS_SPEED_MASK 0x000000C0
+#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
+#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
+#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
+#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
+#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
+#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
+#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
+
+/* Constants used to intrepret the masked PCI-X bus speed. */
+#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
+#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
+#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
+
+/* EEPROM/Flash Control */
+#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
+#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
+#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
+#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
+#define E1000_EECD_FWE_MASK  0x00000030 
+#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
+#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
+#define E1000_EECD_FWE_SHIFT 4
+#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
+#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
+#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
+#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
+
+/* EEPROM Read */
+#define E1000_EERD_START      0x00000001 /* Start Read */
+#define E1000_EERD_DONE       0x00000010 /* Read Done */
+#define E1000_EERD_ADDR_SHIFT 8
+#define E1000_EERD_ADDR_MASK  0x0000FF00 /* Read Address */
+#define E1000_EERD_DATA_SHIFT 16
+#define E1000_EERD_DATA_MASK  0xFFFF0000 /* Read Data */
+
+/* Extended Device Control */
+#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */ 
+#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
+#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
+#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
+#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
+#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
+#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
+#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
+#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
+#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
+#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
+#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
+#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
+#define E1000_CTRL_EXT_SDP7_DIR  0x00000800 /* Direction of SDP7 0=in 1=out */
+#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
+#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
+#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
+#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
+#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
+#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
+#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
+#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
+#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
+
+/* MDI Control */
+#define E1000_MDIC_DATA_MASK 0x0000FFFF
+#define E1000_MDIC_REG_MASK  0x001F0000
+#define E1000_MDIC_REG_SHIFT 16
+#define E1000_MDIC_PHY_MASK  0x03E00000
+#define E1000_MDIC_PHY_SHIFT 21
+#define E1000_MDIC_OP_WRITE  0x04000000
+#define E1000_MDIC_OP_READ   0x08000000
+#define E1000_MDIC_READY     0x10000000
+#define E1000_MDIC_INT_EN    0x20000000
+#define E1000_MDIC_ERROR     0x40000000
+
+/* LED Control */
+#define E1000_LEDCTL_LED0_MODE_MASK  0x0000000F
+#define E1000_LEDCTL_LED0_MODE_SHIFT 0
+#define E1000_LEDCTL_LED0_IVRT       0x00000040
+#define E1000_LEDCTL_LED0_BLINK      0x00000080
+#define E1000_LEDCTL_LED1_MODE_MASK  0x00000F00
+#define E1000_LEDCTL_LED1_MODE_SHIFT 8
+#define E1000_LEDCTL_LED1_IVRT       0x00004000
+#define E1000_LEDCTL_LED1_BLINK      0x00008000
+#define E1000_LEDCTL_LED2_MODE_MASK  0x000F0000
+#define E1000_LEDCTL_LED2_MODE_SHIFT 16
+#define E1000_LEDCTL_LED2_IVRT       0x00400000
+#define E1000_LEDCTL_LED2_BLINK      0x00800000
+#define E1000_LEDCTL_LED3_MODE_MASK  0x0F000000
+#define E1000_LEDCTL_LED3_MODE_SHIFT 24
+#define E1000_LEDCTL_LED3_IVRT       0x40000000
+#define E1000_LEDCTL_LED3_BLINK      0x80000000
+
+#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
+#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
+#define E1000_LEDCTL_MODE_LINK_UP       0x2
+#define E1000_LEDCTL_MODE_ACTIVITY      0x3
+#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
+#define E1000_LEDCTL_MODE_LINK_10       0x5
+#define E1000_LEDCTL_MODE_LINK_100      0x6
+#define E1000_LEDCTL_MODE_LINK_1000     0x7
+#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
+#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
+#define E1000_LEDCTL_MODE_COLLISION     0xA
+#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
+#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
+#define E1000_LEDCTL_MODE_PAUSED        0xD
+#define E1000_LEDCTL_MODE_LED_ON        0xE
+#define E1000_LEDCTL_MODE_LED_OFF       0xF
+
+/* Receive Address */
+#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
+
+/* Interrupt Cause Read */
+#define E1000_ICR_TXDW    0x00000001    /* Transmit desc written back */
+#define E1000_ICR_TXQE    0x00000002    /* Transmit Queue empty */
+#define E1000_ICR_LSC     0x00000004    /* Link Status Change */
+#define E1000_ICR_RXSEQ   0x00000008    /* rx sequence error */
+#define E1000_ICR_RXDMT0  0x00000010    /* rx desc min. threshold (0) */
+#define E1000_ICR_RXO     0x00000040    /* rx overrun */
+#define E1000_ICR_RXT0    0x00000080    /* rx timer intr (ring 0) */
+#define E1000_ICR_MDAC    0x00000200    /* MDIO access complete */
+#define E1000_ICR_RXCFG   0x00000400    /* RX /c/ ordered set */
+#define E1000_ICR_GPI_EN0 0x00000800    /* GP Int 0 */
+#define E1000_ICR_GPI_EN1 0x00001000    /* GP Int 1 */
+#define E1000_ICR_GPI_EN2 0x00002000    /* GP Int 2 */
+#define E1000_ICR_GPI_EN3 0x00004000    /* GP Int 3 */
+#define E1000_ICR_TXD_LOW 0x00008000
+#define E1000_ICR_SRPD    0x00010000
+
+/* Interrupt Cause Set */
+#define E1000_ICS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
+#define E1000_ICS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
+#define E1000_ICS_LSC     E1000_ICR_LSC         /* Link Status Change */
+#define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
+#define E1000_ICS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
+#define E1000_ICS_RXO     E1000_ICR_RXO         /* rx overrun */
+#define E1000_ICS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
+#define E1000_ICS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
+#define E1000_ICS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
+#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
+#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
+#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
+#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
+#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
+#define E1000_ICS_SRPD    E1000_ICR_SRPD
+
+/* Interrupt Mask Set */
+#define E1000_IMS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
+#define E1000_IMS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
+#define E1000_IMS_LSC     E1000_ICR_LSC         /* Link Status Change */
+#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
+#define E1000_IMS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
+#define E1000_IMS_RXO     E1000_ICR_RXO         /* rx overrun */
+#define E1000_IMS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
+#define E1000_IMS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
+#define E1000_IMS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
+#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
+#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
+#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
+#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
+#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
+#define E1000_IMS_SRPD    E1000_ICR_SRPD
+
+/* Interrupt Mask Clear */
+#define E1000_IMC_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
+#define E1000_IMC_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
+#define E1000_IMC_LSC     E1000_ICR_LSC         /* Link Status Change */
+#define E1000_IMC_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
+#define E1000_IMC_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
+#define E1000_IMC_RXO     E1000_ICR_RXO         /* rx overrun */
+#define E1000_IMC_RXT0    E1000_ICR_RXT0        /* rx timer intr */
+#define E1000_IMC_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
+#define E1000_IMC_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
+#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
+#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
+#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
+#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
+#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
+#define E1000_IMC_SRPD    E1000_ICR_SRPD
+
+/* Receive Control */
+#define E1000_RCTL_RST          0x00000001      /* Software reset */
+#define E1000_RCTL_EN           0x00000002      /* enable */
+#define E1000_RCTL_SBP          0x00000004      /* store bad packet */
+#define E1000_RCTL_UPE          0x00000008      /* unicast promiscuous enable */
+#define E1000_RCTL_MPE          0x00000010      /* multicast promiscuous enab */
+#define E1000_RCTL_LPE          0x00000020      /* long packet enable */
+#define E1000_RCTL_LBM_NO       0x00000000      /* no loopback mode */
+#define E1000_RCTL_LBM_MAC      0x00000040      /* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP      0x00000080      /* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR     0x000000C0      /* tcvr loopback mode */
+#define E1000_RCTL_RDMTS_HALF   0x00000000      /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_QUAT   0x00000100      /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_EIGTH  0x00000200      /* rx desc min threshold size */
+#define E1000_RCTL_MO_SHIFT     12              /* multicast offset shift */
+#define E1000_RCTL_MO_0         0x00000000      /* multicast offset 11:0 */
+#define E1000_RCTL_MO_1         0x00001000      /* multicast offset 12:1 */
+#define E1000_RCTL_MO_2         0x00002000      /* multicast offset 13:2 */
+#define E1000_RCTL_MO_3         0x00003000      /* multicast offset 15:4 */
+#define E1000_RCTL_MDR          0x00004000      /* multicast desc ring 0 */
+#define E1000_RCTL_BAM          0x00008000      /* broadcast enable */
+/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
+#define E1000_RCTL_SZ_2048      0x00000000      /* rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024      0x00010000      /* rx buffer size 1024 */
+#define E1000_RCTL_SZ_512       0x00020000      /* rx buffer size 512 */
+#define E1000_RCTL_SZ_256       0x00030000      /* rx buffer size 256 */
+/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
+#define E1000_RCTL_SZ_16384     0x00010000      /* rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192      0x00020000      /* rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096      0x00030000      /* rx buffer size 4096 */
+#define E1000_RCTL_VFE          0x00040000      /* vlan filter enable */
+#define E1000_RCTL_CFIEN        0x00080000      /* canonical form enable */
+#define E1000_RCTL_CFI          0x00100000      /* canonical form indicator */
+#define E1000_RCTL_DPF          0x00400000      /* discard pause frames */
+#define E1000_RCTL_PMCF         0x00800000      /* pass MAC control frames */
+#define E1000_RCTL_BSEX         0x02000000      /* Buffer size extension */
+
+/* Receive Descriptor */
+#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
+#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
+#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
+#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
+#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
+
+/* Flow Control */
+#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
+#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
+#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
+#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
+
+/* Receive Descriptor Control */
+#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
+#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
+#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
+#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
+
+/* Transmit Descriptor Control */
+#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
+#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
+#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
+
+/* Transmit Configuration Word */
+#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
+#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
+#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
+#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
+#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
+#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
+#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
+#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
+#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
+
+/* Receive Configuration Word */
+#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
+#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
+#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
+#define E1000_RXCW_CC    0x10000000     /* Receive config change */
+#define E1000_RXCW_C     0x20000000     /* Receive config */
+#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
+#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
+
+/* Transmit Control */
+#define E1000_TCTL_RST    0x00000001    /* software reset */
+#define E1000_TCTL_EN     0x00000002    /* enable tx */
+#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
+#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
+#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
+#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
+#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
+#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
+#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
+#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
+
+/* Receive Checksum Control */
+#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
+#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
+#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
+
+/* Definitions for power management and wakeup registers */
+/* Wake Up Control */
+#define E1000_WUC_APME       0x00000001 /* APM Enable */
+#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
+#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
+#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
+
+/* Wake Up Filter Control */
+#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
+#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
+#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
+#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
+#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
+#define E1000_WUFC_FLX_OFFSET 16       /* Offset to the Flexible Filters bits */
+#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
+
+/* Wake Up Status */
+#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
+#define E1000_WUS_MAG  0x00000002 /* Magic Packet Received */
+#define E1000_WUS_EX   0x00000004 /* Directed Exact Received */
+#define E1000_WUS_MC   0x00000008 /* Directed Multicast Received */
+#define E1000_WUS_BC   0x00000010 /* Broadcast Received */
+#define E1000_WUS_ARP  0x00000020 /* ARP Request Packet Received */
+#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
+#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
+#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
+#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
+#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
+#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
+#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
+
+/* Management Control */
+#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
+#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
+#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
+#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
+#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
+#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
+#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
+#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
+#define E1000_MANC_NEIGHBOR_EN   0x00004000 /* Enable Neighbor Discovery 
+                                             * Filtering */
+#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
+#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
+#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
+#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
+#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
+#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
+#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
+#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
+#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
+
+#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
+#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
+
+/* Wake Up Packet Length */
+#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
+
+#define E1000_MDALIGN          4096
+
+/* EEPROM Commands */
+#define EEPROM_READ_OPCODE  0x6  /* EERPOM read opcode */
+#define EEPROM_WRITE_OPCODE 0x5  /* EERPOM write opcode */
+#define EEPROM_ERASE_OPCODE 0x7  /* EERPOM erase opcode */
+#define EEPROM_EWEN_OPCODE  0x13 /* EERPOM erase/write enable */
+#define EEPROM_EWDS_OPCODE  0x10 /* EERPOM erast/write disable */
+
+/* EEPROM Word Offsets */
+#define EEPROM_ID_LED_SETTINGS     0x0004
+#define EEPROM_INIT_CONTROL1_REG   0x000A
+#define EEPROM_INIT_CONTROL2_REG   0x000F
+#define EEPROM_FLASH_VERSION       0x0032
+#define EEPROM_CHECKSUM_REG        0x003F
+
+/* Word definitions for ID LED Settings */
+#define ID_LED_RESERVED_0000 0x0000
+#define ID_LED_RESERVED_FFFF 0xFFFF
+#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
+		              (ID_LED_OFF1_OFF2 << 8) | \
+		              (ID_LED_DEF1_DEF2 << 4) | \
+			      (ID_LED_DEF1_DEF2))
+#define ID_LED_DEF1_DEF2     0x1
+#define ID_LED_DEF1_ON2      0x2
+#define ID_LED_DEF1_OFF2     0x3
+#define ID_LED_ON1_DEF2      0x4
+#define ID_LED_ON1_ON2       0x5
+#define ID_LED_ON1_OFF2      0x6
+#define ID_LED_OFF1_DEF2     0x7
+#define ID_LED_OFF1_ON2      0x8
+#define ID_LED_OFF1_OFF2     0x9
+
+/* Mask bits for fields in Word 0x0a of the EEPROM */
+#define EEPROM_WORD0A_ILOS   0x0010
+#define EEPROM_WORD0A_SWDPIO 0x01E0
+#define EEPROM_WORD0A_LRST   0x0200
+#define EEPROM_WORD0A_FD     0x0400
+#define EEPROM_WORD0A_66MHZ  0x0800
+
+/* Mask bits for fields in Word 0x0f of the EEPROM */
+#define EEPROM_WORD0F_PAUSE_MASK 0x3000
+#define EEPROM_WORD0F_PAUSE      0x1000
+#define EEPROM_WORD0F_ASM_DIR    0x2000
+#define EEPROM_WORD0F_ANE        0x0800
+#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
+
+/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
+#define EEPROM_SUM 0xBABA
+
+/* EEPROM Map defines (WORD OFFSETS)*/
+#define EEPROM_NODE_ADDRESS_BYTE_0 0
+#define EEPROM_PBA_BYTE_1          8
+
+/* EEPROM Map Sizes (Byte Counts) */
+#define PBA_SIZE 4
+
+/* Collision related configuration parameters */
+#define E1000_COLLISION_THRESHOLD       16
+#define E1000_CT_SHIFT                  4
+#define E1000_COLLISION_DISTANCE        64
+#define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
+#define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
+#define E1000_GB_HDX_COLLISION_DISTANCE 512
+#define E1000_COLD_SHIFT                12
+
+/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
+#define REQ_TX_DESCRIPTOR_MULTIPLE  8
+#define REQ_RX_DESCRIPTOR_MULTIPLE  8
+
+/* Default values for the transmit IPG register */
+#define DEFAULT_82542_TIPG_IPGT        10
+#define DEFAULT_82543_TIPG_IPGT_FIBER  9
+#define DEFAULT_82543_TIPG_IPGT_COPPER 8
+
+#define E1000_TIPG_IPGT_MASK  0x000003FF
+#define E1000_TIPG_IPGR1_MASK 0x000FFC00
+#define E1000_TIPG_IPGR2_MASK 0x3FF00000
+
+#define DEFAULT_82542_TIPG_IPGR1 2
+#define DEFAULT_82543_TIPG_IPGR1 8
+#define E1000_TIPG_IPGR1_SHIFT  10
+
+#define DEFAULT_82542_TIPG_IPGR2 10
+#define DEFAULT_82543_TIPG_IPGR2 6
+#define E1000_TIPG_IPGR2_SHIFT  20
+
+#define E1000_TXDMAC_DPP 0x00000001
+
+/* Adaptive IFS defines */
+#define TX_THRESHOLD_START     8
+#define TX_THRESHOLD_INCREMENT 10
+#define TX_THRESHOLD_DECREMENT 1
+#define TX_THRESHOLD_STOP      190
+#define TX_THRESHOLD_DISABLE   0
+#define TX_THRESHOLD_TIMER_MS  10000
+#define MIN_NUM_XMITS          1000
+#define IFS_MAX                80
+#define IFS_STEP               10
+#define IFS_MIN                40
+#define IFS_RATIO              4
+
+/* PBA constants */
+#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
+#define E1000_PBA_24K 0x0018
+#define E1000_PBA_40K 0x0028
+#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
+
+/* Flow Control Constants */
+#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
+#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
+#define FLOW_CONTROL_TYPE         0x8808
+
+/* The historical defaults for the flow control values are given below. */
+#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
+#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
+#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
+
+
+/* The number of bits that we need to shift right to move the "pause"
+ * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
+ * in the TXCW register 
+ */
+#define PAUSE_SHIFT 5
+
+/* The number of bits that we need to shift left to move the "SWDPIO"
+ * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
+ * in the CTRL register 
+ */
+#define SWDPIO_SHIFT 17
+
+/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
+ * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
+ * Extended CTRL register.
+ * in the CTRL register 
+ */
+#define SWDPIO__EXT_SHIFT 4
+
+/* The number of bits that we need to shift left to move the "ILOS"
+ * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
+ * in the CTRL register 
+ */
+#define ILOS_SHIFT  3
+
+
+#define RECEIVE_BUFFER_ALIGN_SIZE  (256)
+
+/* The number of milliseconds we wait for auto-negotiation to complete */
+#define LINK_UP_TIMEOUT             500
+
+#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
+
+/* The carrier extension symbol, as received by the NIC. */
+#define CARRIER_EXTENSION   0x0F
+
+/* TBI_ACCEPT macro definition:
+ *
+ * This macro requires:
+ *      adapter = a pointer to struct em_hw 
+ *      status = the 8 bit status field of the RX descriptor with EOP set
+ *      error = the 8 bit error field of the RX descriptor with EOP set
+ *      length = the sum of all the length fields of the RX descriptors that
+ *               make up the current frame
+ *      last_byte = the last byte of the frame DMAed by the hardware
+ *      max_frame_length = the maximum frame length we want to accept.
+ *      min_frame_length = the minimum frame length we want to accept.
+ *
+ * This macro is a conditional that should be used in the interrupt 
+ * handler's Rx processing routine when RxErrors have been detected.
+ *
+ * Typical use:
+ *  ...
+ *  if (TBI_ACCEPT) {
+ *      accept_frame = TRUE;
+ *      em_tbi_adjust_stats(adapter, MacAddress);
+ *      frame_length--;
+ *  } else {
+ *      accept_frame = FALSE;
+ *  }
+ *  ...
+ */
+
+#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
+    ((adapter)->tbi_compatibility_on && \
+     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
+     ((last_byte) == CARRIER_EXTENSION) && \
+     (((status) & E1000_RXD_STAT_VP) ? \
+          (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
+           ((length) <= ((adapter)->max_frame_size + 1))) : \
+          (((length) > (adapter)->min_frame_size) && \
+           ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
+
+
+/* Structures, enums, and macros for the PHY */
+
+/* Bit definitions for the Management Data IO (MDIO) and Management Data
+ * Clock (MDC) pins in the Device Control Register.
+ */
+#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
+#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
+#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
+#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
+#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
+#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
+#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
+#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
+
+/* PHY 1000 MII Register/Bit Definitions */
+/* PHY Registers defined by IEEE */
+#define PHY_CTRL         0x00 /* Control Register */
+#define PHY_STATUS       0x01 /* Status Regiser */
+#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
+#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
+#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
+#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
+#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
+#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
+
+/* M88E1000 Specific Registers */
+#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
+#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
+#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
+#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
+#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
+#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
+
+#define MAX_PHY_REG_ADDRESS 0x1F        /* 5 bit address bus (0-0x1F) */
+
+/* PHY Control Register */
+#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
+#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
+#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN       0x0800  /* Power down */
+#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
+
+/* PHY Status Register */
+#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
+#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
+
+/* Autoneg Advertisement Register */
+#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
+#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
+#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
+#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
+#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
+#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
+#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
+
+/* Link Partner Ability Register (Base Page) */
+#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
+#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
+#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
+#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
+#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
+#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
+#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
+#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
+#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
+#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
+
+/* Autoneg Expansion Register */
+#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
+#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
+#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
+#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
+#define NWAY_ER_PAR_DETECT_FAULT  0x0100 /* LP is 100TX Full Duplex Capable */
+
+/* Next Page TX Register */
+#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
+#define NPTX_TOGGLE         0x0800 /* Toggles between exchanges
+                                    * of different NP
+                                    */
+#define NPTX_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
+                                    * 0 = cannot comply with msg
+                                    */
+#define NPTX_MSG_PAGE       0x2000 /* formatted(1)/unformatted(0) pg */
+#define NPTX_NEXT_PAGE      0x8000 /* 1 = addition NP will follow 
+                                    * 0 = sending last NP
+                                    */
+
+/* Link Partner Next Page Register */
+#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
+#define LP_RNPR_TOGGLE         0x0800 /* Toggles between exchanges
+                                       * of different NP
+                                       */
+#define LP_RNPR_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg 
+                                       * 0 = cannot comply with msg
+                                       */
+#define LP_RNPR_MSG_PAGE       0x2000  /* formatted(1)/unformatted(0) pg */
+#define LP_RNPR_ACKNOWLDGE     0x4000  /* 1 = ACK / 0 = NO ACK */
+#define LP_RNPR_NEXT_PAGE      0x8000  /* 1 = addition NP will follow
+                                        * 0 = sending last NP 
+                                        */
+
+/* 1000BASE-T Control Register */
+#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
+#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
+#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
+                                        /* 0=DTE device */
+#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
+                                        /* 0=Configure PHY as Slave */
+#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
+                                        /* 0=Automatic Master/Slave config */
+#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
+#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
+#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
+#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
+#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
+
+/* 1000BASE-T Status Register */
+#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
+#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
+#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
+#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
+#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
+#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local TX is Master, 0=Slave */
+#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
+#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
+#define SR_1000T_LOCAL_RX_STATUS_SHIFT  13
+
+/* Extended Status Register */
+#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
+#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
+#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
+#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
+
+#define PHY_TX_POLARITY_MASK   0x0100 /* register 10h bit 8 (polarity bit) */
+#define PHY_TX_NORMAL_POLARITY 0      /* register 10h bit 8 (normal polarity) */
+
+#define AUTO_POLARITY_DISABLE  0x0010 /* register 11h bit 4 */
+                                      /* (0=enable, 1=disable) */
+
+/* M88E1000 PHY Specific Control Register */
+#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
+#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
+#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
+#define M88E1000_PSCR_CLK125_DISABLE    0x0010 /* 1=CLK125 low, 
+                                                * 0=CLK125 toggling
+                                                */
+#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
+                                               /* Manual MDI configuration */
+#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
+#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,
+                                                *  100BASE-TX/10BASE-T: 
+                                                *  MDI Mode
+                                                */
+#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled 
+                                                * all speeds. 
+                                                */
+#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 
+                                        /* 1=Enable Extended 10BASE-T distance
+                                         * (Lower 10BASE-T RX Threshold)
+                                         * 0=Normal 10BASE-T RX Threshold */
+#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
+                                        /* 1=5-Bit interface in 100BASE-TX
+                                         * 0=MII interface in 100BASE-TX */
+#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
+#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
+
+#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
+#define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
+#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
+
+/* M88E1000 PHY Specific Status Register */
+#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
+#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
+#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
+#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
+                                            * 3=110-140M;4=>140M */
+#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
+#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
+#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
+#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
+#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
+#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
+#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
+#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
+
+#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
+#define M88E1000_PSSR_MDIX_SHIFT         6
+#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
+
+/* M88E1000 Extended PHY Specific Control Register */
+#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
+#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000 /* 1=Lost lock detect enabled.
+                                              * Will assert lost lock and bring
+                                              * link down if idle not seen
+                                              * within 1ms in 1000BASE-T 
+                                              */
+/* Number of times we will attempt to autonegotiate before downshifting if we
+ * are the master */
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000    
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
+/* Number of times we will attempt to autonegotiate before downshifting if we
+ * are the slave */
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
+#define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
+
+/* Bit definitions for valid PHY IDs. */
+#define M88E1000_E_PHY_ID  0x01410C50
+#define M88E1000_I_PHY_ID  0x01410C30
+#define M88E1011_I_PHY_ID  0x01410C20
+#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
+#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
+
+/* Miscellaneous PHY bit definitions. */
+#define PHY_PREAMBLE        0xFFFFFFFF
+#define PHY_SOF             0x01
+#define PHY_OP_READ         0x02
+#define PHY_OP_WRITE        0x01
+#define PHY_TURNAROUND      0x02
+#define PHY_PREAMBLE_SIZE   32
+#define MII_CR_SPEED_1000   0x0040
+#define MII_CR_SPEED_100    0x2000
+#define MII_CR_SPEED_10     0x0000
+#define E1000_PHY_ADDRESS   0x01
+#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
+#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
+#define PHY_REVISION_MASK   0xFFFFFFF0
+#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
+#define REG4_SPEED_MASK     0x01E0
+#define REG9_SPEED_MASK     0x0300
+#define ADVERTISE_10_HALF   0x0001
+#define ADVERTISE_10_FULL   0x0002
+#define ADVERTISE_100_HALF  0x0004
+#define ADVERTISE_100_FULL  0x0008
+#define ADVERTISE_1000_HALF 0x0010
+#define ADVERTISE_1000_FULL 0x0020
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
+
+#endif /* _EM_HW_H_ */
diff --git a/sys/dev/em/if_em_osdep.h b/sys/dev/em/if_em_osdep.h
index 55c6da1..e106e04 100644
--- a/sys/dev/em/if_em_osdep.h
+++ b/sys/dev/em/if_em_osdep.h
@@ -66,17 +66,17 @@ SUCH DAMAGE.
 #define MSGOUT(S, A, B)     printf(S "\n", A, B)
 #define DEBUGFUNC(F)        DEBUGOUT(F);
 #if DBG
-    #define DEBUGOUT(S)         printf(S "\n")
-    #define DEBUGOUT1(S,A)      printf(S "\n",A)
-    #define DEBUGOUT2(S,A,B)    printf(S "\n",A,B)
-    #define DEBUGOUT3(S,A,B,C)  printf(S "\n",A,B,C)
-    #define DEBUGOUT7(S,A,B,C,D,E,F,G)  printf(S "\n",A,B,C,D,E,F,G)
+	#define DEBUGOUT(S)         printf(S "\n")
+	#define DEBUGOUT1(S,A)      printf(S "\n",A)
+	#define DEBUGOUT2(S,A,B)    printf(S "\n",A,B)
+	#define DEBUGOUT3(S,A,B,C)  printf(S "\n",A,B,C)
+	#define DEBUGOUT7(S,A,B,C,D,E,F,G)  printf(S "\n",A,B,C,D,E,F,G)
 #else
-    #define DEBUGOUT(S)
-    #define DEBUGOUT1(S,A)
-    #define DEBUGOUT2(S,A,B)
-    #define DEBUGOUT3(S,A,B,C)
-    #define DEBUGOUT7(S,A,B,C,D,E,F,G)
+	#define DEBUGOUT(S)
+	#define DEBUGOUT1(S,A)
+	#define DEBUGOUT2(S,A,B)
+	#define DEBUGOUT3(S,A,B,C)
+	#define DEBUGOUT7(S,A,B,C,D,E,F,G)
 #endif
 
 #define FALSE               0
@@ -86,9 +86,9 @@ SUCH DAMAGE.
 
 struct em_osdep
 {
-   bus_space_tag_t bus_space_tag;
-   bus_space_handle_t bus_space_handle;
-   struct device   *dev;
+	bus_space_tag_t bus_space_tag;
+	bus_space_handle_t bus_space_handle;
+	struct device   *dev;
 };
 
 #define E1000_READ_REG(a, reg) (\
diff --git a/sys/modules/em/Makefile b/sys/modules/em/Makefile
index 4a89fba..df17b2f 100644
--- a/sys/modules/em/Makefile
+++ b/sys/modules/em/Makefile
@@ -1,9 +1,8 @@
-# $FreeBSD$
-
-.PATH:	${.CURDIR}/../../dev/em
-KMOD	= if_em
-SRCS	= device_if.h bus_if.h pci_if.h opt_bdg.h
-SRCS    += if_em.c if_em_fxhw.c if_em_phy.c
+#$FreeBSD$
+.PATH:  ${.CURDIR}/../../dev/em
+KMOD    = if_em
+SRCS    = device_if.h bus_if.h pci_if.h opt_bdg.h
+SRCS    += if_em.c if_em_hw.c
 
 clean:
 	rm -f opt_bdg.h device_if.h bus_if.h pci_if.h setdef*