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author | jhb <jhb@FreeBSD.org> | 2003-01-08 01:15:26 +0000 |
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committer | jhb <jhb@FreeBSD.org> | 2003-01-08 01:15:26 +0000 |
commit | 601a1149602be9890a49f5bdaaf28c73b34c2d42 (patch) | |
tree | 5472a3271e9734cef89667d72dec35d496a66694 | |
parent | aacf88c6168a5237ea9d8f6dc8712c9b2fc066fa (diff) | |
download | FreeBSD-src-601a1149602be9890a49f5bdaaf28c73b34c2d42.zip FreeBSD-src-601a1149602be9890a49f5bdaaf28c73b34c2d42.tar.gz |
- Fix the name of the hyperthreading cpuid feature flag to be HTT instead
of HHT.
- Document fields returned in %ebx by a cpuid with %eax of 1.
-rw-r--r-- | sys/amd64/include/specialreg.h | 10 | ||||
-rw-r--r-- | sys/i386/include/specialreg.h | 10 |
2 files changed, 18 insertions, 2 deletions
diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 99f9f3c..4c29084 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -106,12 +106,20 @@ #define CPUID_XMM 0x02000000 #define CPUID_SSE2 0x04000000 #define CPUID_SS 0x08000000 -#define CPUID_HHT 0x10000000 +#define CPUID_HTT 0x10000000 #define CPUID_TM 0x20000000 #define CPUID_B30 0x40000000 #define CPUID_PBE 0x80000000 /* + *CPUID instruction 1 ebx info + */ +#define CPUID_BRAND_INDEX 0x000000ff +#define CPUID_CLFUSH_SIZE 0x0000ff00 +#define CPUID_HTT_CORES 0x00ff0000 +#define CPUID_LOCAL_APIC_ID 0xff000000 + +/* * Model-specific registers for the i386 family */ #define MSR_P5_MC_ADDR 0x000 diff --git a/sys/i386/include/specialreg.h b/sys/i386/include/specialreg.h index 99f9f3c..4c29084 100644 --- a/sys/i386/include/specialreg.h +++ b/sys/i386/include/specialreg.h @@ -106,12 +106,20 @@ #define CPUID_XMM 0x02000000 #define CPUID_SSE2 0x04000000 #define CPUID_SS 0x08000000 -#define CPUID_HHT 0x10000000 +#define CPUID_HTT 0x10000000 #define CPUID_TM 0x20000000 #define CPUID_B30 0x40000000 #define CPUID_PBE 0x80000000 /* + *CPUID instruction 1 ebx info + */ +#define CPUID_BRAND_INDEX 0x000000ff +#define CPUID_CLFUSH_SIZE 0x0000ff00 +#define CPUID_HTT_CORES 0x00ff0000 +#define CPUID_LOCAL_APIC_ID 0xff000000 + +/* * Model-specific registers for the i386 family */ #define MSR_P5_MC_ADDR 0x000 |