Add some (totally untested!) code to correctly set the RF half/quarter

mode configuration registers. This is apparently required for correct
behaviour, but also requires the chip to actually officially support it.

Sponsored by:	Hobnob, Inc.

1 files changed, 14 insertions, 0 deletions

diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
index 598a2d3..86a3f92 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
@@ -724,6 +724,20 @@ ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan)
 		rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ?
 			AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
 	}
+
+	/*
+	 * Set half/quarter mode flags if required.
+	 *
+	 * This doesn't change the IFS timings at all; that needs to
+	 * be done as part of the MAC setup.  Similarly, the PLL
+	 * configuration also needs some changes for the half/quarter
+	 * rate clock.
+	 */
+	if (IEEE80211_IS_CHAN_HALF(chan))
+		rfMode |= AR_PHY_MODE_HALF;
+	else if (IEEE80211_IS_CHAN_QUARTER(chan))
+		rfMode |= AR_PHY_MODE_QUARTER;
+
 	OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
 }