Adds JC's cleanup patches that fix it so

we call an platform dependant topo function as
well as clean up all the XLR specific ifdefs around
smp platform init.

Obtained from:	JC

5 files changed, 30 insertions, 19 deletions

diff --git a/sys/mips/include/hwfunc.h b/sys/mips/include/hwfunc.h
index bbf3086..fd89953 100644
--- a/sys/mips/include/hwfunc.h
+++ b/sys/mips/include/hwfunc.h
@@ -93,5 +93,11 @@ extern int platform_processor_id(void);
  */
 extern int platform_num_processors(void);
 
+/*
+ * Return the topology of processors on this platform
+ */
+struct cpu_group *platform_smp_topo(void);
+
+
 #endif	/* SMP */
 #endif /* !_MACHINE_HWFUNC_H_ */
diff --git a/sys/mips/mips/mp_machdep.c b/sys/mips/mips/mp_machdep.c
index 3278d73..7428719 100644
--- a/sys/mips/mips/mp_machdep.c
+++ b/sys/mips/mips/mp_machdep.c
@@ -196,8 +196,7 @@ cpu_mp_announce(void)
 struct cpu_group *
 cpu_topo(void)
 {
-
-	return (smp_topo_none());
+	return (platform_smp_topo());
 }
 
 int
@@ -238,10 +237,6 @@ cpu_mp_start(void)
 void
 smp_init_secondary(u_int32_t cpuid)
 {
-#ifndef TARGET_XLR_XLS
-	int ipi_int_mask, clock_int_mask;
-#endif
-
 	/* TLB */
 	Mips_SetWIRED(0);
 	Mips_TLBFlush(num_tlbentries);
@@ -294,17 +289,6 @@ smp_init_secondary(u_int32_t cpuid)
 	while (smp_started == 0)
 		; /* nothing */
 
-#ifndef TARGET_XLR_XLS
-	/*
-	 * Unmask the clock and ipi interrupts.
-	 */
-	clock_int_mask = hard_int_mask(5);
-	ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
-	set_intr_mask(ALL_INT_MASK & ~(ipi_int_mask | clock_int_mask));
-#else
-	platform_init_ap(cpuid);
-#endif
-
 	/*
 	 * Bootstrap the compare register.
 	 */
diff --git a/sys/mips/mips/mpboot.S b/sys/mips/mips/mpboot.S
index 89a1dd3..1329d45 100644
--- a/sys/mips/mips/mpboot.S
+++ b/sys/mips/mips/mpboot.S
@@ -76,10 +76,8 @@ GLOBAL(mpentry)
 
 	PTR_LA	gp, _C_LABEL(_gp)
 
-#ifndef TARGET_XLR_XLS
 	jal	platform_init_ap
 	move	a0, s0
-#endif
 	jal	smp_init_secondary
 	move	a0, s0
 
diff --git a/sys/mips/rmi/xlr_machdep.c b/sys/mips/rmi/xlr_machdep.c
index a01d1de0..dc22faa 100644
--- a/sys/mips/rmi/xlr_machdep.c
+++ b/sys/mips/rmi/xlr_machdep.c
@@ -534,6 +534,8 @@ void platform_init_ap(int processor_id)
 
 	/* Setup interrupts for secondary CPUs here */
 	stat = mips_rd_status();
+	KASSERT((stat & MIPS_SR_INT_IE) == 0,
+	    ("Interrupts enabled in %s!", __func__));
 	stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
 	mips_wr_status(stat);
 
@@ -570,4 +572,11 @@ int platform_num_processors(void)
 {
 	return fls(xlr_boot1_info.cpu_online_map);
 }
+
+struct cpu_group *
+platform_smp_topo()
+{
+	return (smp_topo_2level(CG_SHARE_L2, platform_num_processors() / 4,
+	    CG_SHARE_L1, 4, CG_FLAG_THREAD));
+}
 #endif
diff --git a/sys/mips/sibyte/sb_machdep.c b/sys/mips/sibyte/sb_machdep.c
index 559bf74..9841ced 100644
--- a/sys/mips/sibyte/sb_machdep.c
+++ b/sys/mips/sibyte/sb_machdep.c
@@ -344,9 +344,16 @@ platform_ipi_intrnum(void)
 	return (4);
 }
 
+struct cpu_group *
+platform_smp_topo(void)
+{
+	return (smp_topo_none());
+}
+
 void
 platform_init_ap(int cpuid)
 {
+	int ipi_int_mask, clock_int_mask;
 
 	KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
 
@@ -356,6 +363,13 @@ platform_init_ap(int cpuid)
 	kseg0_map_coherent();
 
 	sb_intr_init(cpuid);
+
+	/*
+	 * Unmask the clock and ipi interrupts.
+	 */
+	clock_int_mask = hard_int_mask(5);
+	ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+	set_intr_mask(ALL_INT_MASK & ~(ipi_int_mask | clock_int_mask));
 }
 
 int