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authorlinimon <linimon@FreeBSD.org>2003-10-27 10:02:34 +0000
committerlinimon <linimon@FreeBSD.org>2003-10-27 10:02:34 +0000
commit06df298d74bb092f2daa2ee35e1fb9bd4f6e646d (patch)
tree61137cfcbb94c473e7507599be2635c4f7f0895c /cad/iverilog
parentb8030896e237587602fd8250cd1d0a8027697042 (diff)
downloadFreeBSD-ports-06df298d74bb092f2daa2ee35e1fb9bd4f6e646d.zip
FreeBSD-ports-06df298d74bb092f2daa2ee35e1fb9bd4f6e646d.tar.gz
Maintainer Update to latest snapshot. Changes: add AMD64 support
(experimental); time 0 race resolution; identation cleanup; manpage update. PR: ports/58320
Diffstat (limited to 'cad/iverilog')
-rw-r--r--cad/iverilog/Makefile6
-rw-r--r--cad/iverilog/distinfo2
-rw-r--r--cad/iverilog/pkg-plist1
3 files changed, 4 insertions, 5 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index e0ce997..ca06116 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,12 +7,10 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.7.20030722
+PORTVERSION= 0.7.20031009
CATEGORIES= cad
-#MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
-#DISTNAME= verilog-${PORTVERSION}
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
-DISTNAME= verilog-20030722
+DISTNAME= verilog-20031009
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index d334394..e885603 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1 +1 @@
-MD5 (verilog-20030722.tar.gz) = b435baa100fb368a9cfc12f510af9c6e
+MD5 (verilog-20031009.tar.gz) = d4d78212b4f7dde22555cdac5a52b468
diff --git a/cad/iverilog/pkg-plist b/cad/iverilog/pkg-plist
index 30e97c5..dd107f3 100644
--- a/cad/iverilog/pkg-plist
+++ b/cad/iverilog/pkg-plist
@@ -5,6 +5,7 @@ include/acc_user.h
include/ivl_target.h
include/veriuser.h
include/vpi_user.h
+lib/ivl/cadpli.vpl
lib/ivl/fpga.tgt
lib/ivl/iverilog.conf
lib/ivl/ivl
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